rt61pci.c 75 KB

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  1. /*
  2. Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt61pci
  19. Abstract: rt61pci device specific routines.
  20. Supported chipsets: RT2561, RT2561s, RT2661.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/eeprom_93cx6.h>
  29. #include "rt2x00.h"
  30. #include "rt2x00pci.h"
  31. #include "rt61pci.h"
  32. /*
  33. * Register access.
  34. * BBP and RF register require indirect register access,
  35. * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  36. * These indirect registers work with busy bits,
  37. * and we will try maximal REGISTER_BUSY_COUNT times to access
  38. * the register while taking a REGISTER_BUSY_DELAY us delay
  39. * between each attampt. When the busy bit is still set at that time,
  40. * the access attempt is considered to have failed,
  41. * and we will print an error.
  42. */
  43. static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  44. {
  45. u32 reg;
  46. unsigned int i;
  47. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  48. rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  49. if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  50. break;
  51. udelay(REGISTER_BUSY_DELAY);
  52. }
  53. return reg;
  54. }
  55. static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  56. const unsigned int word, const u8 value)
  57. {
  58. u32 reg;
  59. /*
  60. * Wait until the BBP becomes ready.
  61. */
  62. reg = rt61pci_bbp_check(rt2x00dev);
  63. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  64. ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  65. return;
  66. }
  67. /*
  68. * Write the data into the BBP.
  69. */
  70. reg = 0;
  71. rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  72. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  73. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  74. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  75. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  76. }
  77. static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  78. const unsigned int word, u8 *value)
  79. {
  80. u32 reg;
  81. /*
  82. * Wait until the BBP becomes ready.
  83. */
  84. reg = rt61pci_bbp_check(rt2x00dev);
  85. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  86. ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
  87. return;
  88. }
  89. /*
  90. * Write the request into the BBP.
  91. */
  92. reg = 0;
  93. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  94. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  95. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
  96. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  97. /*
  98. * Wait until the BBP becomes ready.
  99. */
  100. reg = rt61pci_bbp_check(rt2x00dev);
  101. if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  102. ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
  103. *value = 0xff;
  104. return;
  105. }
  106. *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
  107. }
  108. static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
  109. const unsigned int word, const u32 value)
  110. {
  111. u32 reg;
  112. unsigned int i;
  113. if (!word)
  114. return;
  115. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  116. rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
  117. if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
  118. goto rf_write;
  119. udelay(REGISTER_BUSY_DELAY);
  120. }
  121. ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
  122. return;
  123. rf_write:
  124. reg = 0;
  125. rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
  126. rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
  127. rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
  128. rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
  129. rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
  130. rt2x00_rf_write(rt2x00dev, word, value);
  131. }
  132. static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
  133. const u8 command, const u8 token,
  134. const u8 arg0, const u8 arg1)
  135. {
  136. u32 reg;
  137. rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
  138. if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
  139. ERROR(rt2x00dev, "mcu request error. "
  140. "Request 0x%02x failed for token 0x%02x.\n",
  141. command, token);
  142. return;
  143. }
  144. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  145. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  146. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  147. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  148. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
  149. rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
  150. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  151. rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
  152. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
  153. }
  154. static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  155. {
  156. struct rt2x00_dev *rt2x00dev = eeprom->data;
  157. u32 reg;
  158. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  159. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  160. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  161. eeprom->reg_data_clock =
  162. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  163. eeprom->reg_chip_select =
  164. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  165. }
  166. static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  167. {
  168. struct rt2x00_dev *rt2x00dev = eeprom->data;
  169. u32 reg = 0;
  170. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  171. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  172. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  173. !!eeprom->reg_data_clock);
  174. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  175. !!eeprom->reg_chip_select);
  176. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  177. }
  178. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  179. #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
  180. static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
  181. const unsigned int word, u32 *data)
  182. {
  183. rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
  184. }
  185. static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
  186. const unsigned int word, u32 data)
  187. {
  188. rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
  189. }
  190. static const struct rt2x00debug rt61pci_rt2x00debug = {
  191. .owner = THIS_MODULE,
  192. .csr = {
  193. .read = rt61pci_read_csr,
  194. .write = rt61pci_write_csr,
  195. .word_size = sizeof(u32),
  196. .word_count = CSR_REG_SIZE / sizeof(u32),
  197. },
  198. .eeprom = {
  199. .read = rt2x00_eeprom_read,
  200. .write = rt2x00_eeprom_write,
  201. .word_size = sizeof(u16),
  202. .word_count = EEPROM_SIZE / sizeof(u16),
  203. },
  204. .bbp = {
  205. .read = rt61pci_bbp_read,
  206. .write = rt61pci_bbp_write,
  207. .word_size = sizeof(u8),
  208. .word_count = BBP_SIZE / sizeof(u8),
  209. },
  210. .rf = {
  211. .read = rt2x00_rf_read,
  212. .write = rt61pci_rf_write,
  213. .word_size = sizeof(u32),
  214. .word_count = RF_SIZE / sizeof(u32),
  215. },
  216. };
  217. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  218. #ifdef CONFIG_RT61PCI_RFKILL
  219. static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  220. {
  221. u32 reg;
  222. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  223. return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
  224. }
  225. #else
  226. #define rt61pci_rfkill_poll NULL
  227. #endif /* CONFIG_RT61PCI_RFKILL */
  228. /*
  229. * Configuration handlers.
  230. */
  231. static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
  232. {
  233. u32 tmp;
  234. tmp = le32_to_cpu(mac[1]);
  235. rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
  236. mac[1] = cpu_to_le32(tmp);
  237. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
  238. (2 * sizeof(__le32)));
  239. }
  240. static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
  241. {
  242. u32 tmp;
  243. tmp = le32_to_cpu(bssid[1]);
  244. rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
  245. bssid[1] = cpu_to_le32(tmp);
  246. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
  247. (2 * sizeof(__le32)));
  248. }
  249. static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
  250. const int tsf_sync)
  251. {
  252. u32 reg;
  253. /*
  254. * Clear current synchronisation setup.
  255. * For the Beacon base registers we only need to clear
  256. * the first byte since that byte contains the VALID and OWNER
  257. * bits which (when set to 0) will invalidate the entire beacon.
  258. */
  259. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  260. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  261. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  262. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  263. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  264. /*
  265. * Enable synchronisation.
  266. */
  267. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  268. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  269. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  270. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  271. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, tsf_sync);
  272. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  273. }
  274. static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
  275. const int short_preamble,
  276. const int ack_timeout,
  277. const int ack_consume_time)
  278. {
  279. u32 reg;
  280. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  281. rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
  282. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  283. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  284. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
  285. !!short_preamble);
  286. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  287. }
  288. static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
  289. const int basic_rate_mask)
  290. {
  291. rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
  292. }
  293. static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
  294. struct rf_channel *rf, const int txpower)
  295. {
  296. u8 r3;
  297. u8 r94;
  298. u8 smart;
  299. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  300. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  301. smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  302. rt2x00_rf(&rt2x00dev->chip, RF2527));
  303. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  304. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
  305. rt61pci_bbp_write(rt2x00dev, 3, r3);
  306. r94 = 6;
  307. if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
  308. r94 += txpower - MAX_TXPOWER;
  309. else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
  310. r94 += txpower;
  311. rt61pci_bbp_write(rt2x00dev, 94, r94);
  312. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  313. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  314. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  315. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  316. udelay(200);
  317. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  318. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  319. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  320. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  321. udelay(200);
  322. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  323. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  324. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  325. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  326. msleep(1);
  327. }
  328. static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  329. const int txpower)
  330. {
  331. struct rf_channel rf;
  332. rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
  333. rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
  334. rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
  335. rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
  336. rt61pci_config_channel(rt2x00dev, &rf, txpower);
  337. }
  338. static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
  339. struct antenna_setup *ant)
  340. {
  341. u8 r3;
  342. u8 r4;
  343. u8 r77;
  344. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  345. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  346. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  347. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  348. rt2x00_rf(&rt2x00dev->chip, RF5325));
  349. /*
  350. * Configure the RX antenna.
  351. */
  352. switch (ant->rx) {
  353. case ANTENNA_HW_DIVERSITY:
  354. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  355. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  356. (rt2x00dev->curr_hwmode != HWMODE_A));
  357. break;
  358. case ANTENNA_A:
  359. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  360. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  361. if (rt2x00dev->curr_hwmode == HWMODE_A)
  362. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  363. else
  364. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  365. break;
  366. case ANTENNA_SW_DIVERSITY:
  367. /*
  368. * NOTE: We should never come here because rt2x00lib is
  369. * supposed to catch this and send us the correct antenna
  370. * explicitely. However we are nog going to bug about this.
  371. * Instead, just default to antenna B.
  372. */
  373. case ANTENNA_B:
  374. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  375. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  376. if (rt2x00dev->curr_hwmode == HWMODE_A)
  377. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  378. else
  379. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  380. break;
  381. }
  382. rt61pci_bbp_write(rt2x00dev, 77, r77);
  383. rt61pci_bbp_write(rt2x00dev, 3, r3);
  384. rt61pci_bbp_write(rt2x00dev, 4, r4);
  385. }
  386. static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
  387. struct antenna_setup *ant)
  388. {
  389. u8 r3;
  390. u8 r4;
  391. u8 r77;
  392. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  393. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  394. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  395. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
  396. rt2x00_rf(&rt2x00dev->chip, RF2529));
  397. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  398. !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
  399. /*
  400. * Configure the RX antenna.
  401. */
  402. switch (ant->rx) {
  403. case ANTENNA_HW_DIVERSITY:
  404. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  405. break;
  406. case ANTENNA_A:
  407. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  408. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  409. break;
  410. case ANTENNA_SW_DIVERSITY:
  411. /*
  412. * NOTE: We should never come here because rt2x00lib is
  413. * supposed to catch this and send us the correct antenna
  414. * explicitely. However we are nog going to bug about this.
  415. * Instead, just default to antenna B.
  416. */
  417. case ANTENNA_B:
  418. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  419. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  420. break;
  421. }
  422. rt61pci_bbp_write(rt2x00dev, 77, r77);
  423. rt61pci_bbp_write(rt2x00dev, 3, r3);
  424. rt61pci_bbp_write(rt2x00dev, 4, r4);
  425. }
  426. static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
  427. const int p1, const int p2)
  428. {
  429. u32 reg;
  430. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  431. rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
  432. rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
  433. rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
  434. rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
  435. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
  436. }
  437. static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
  438. struct antenna_setup *ant)
  439. {
  440. u8 r3;
  441. u8 r4;
  442. u8 r77;
  443. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  444. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  445. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  446. /* FIXME: Antenna selection for the rf 2529 is very confusing in the
  447. * legacy driver. The code below should be ok for non-diversity setups.
  448. */
  449. /*
  450. * Configure the RX antenna.
  451. */
  452. switch (ant->rx) {
  453. case ANTENNA_A:
  454. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  455. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  456. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
  457. break;
  458. case ANTENNA_SW_DIVERSITY:
  459. case ANTENNA_HW_DIVERSITY:
  460. /*
  461. * NOTE: We should never come here because rt2x00lib is
  462. * supposed to catch this and send us the correct antenna
  463. * explicitely. However we are nog going to bug about this.
  464. * Instead, just default to antenna B.
  465. */
  466. case ANTENNA_B:
  467. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  468. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  469. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  470. break;
  471. }
  472. rt61pci_bbp_write(rt2x00dev, 77, r77);
  473. rt61pci_bbp_write(rt2x00dev, 3, r3);
  474. rt61pci_bbp_write(rt2x00dev, 4, r4);
  475. }
  476. struct antenna_sel {
  477. u8 word;
  478. /*
  479. * value[0] -> non-LNA
  480. * value[1] -> LNA
  481. */
  482. u8 value[2];
  483. };
  484. static const struct antenna_sel antenna_sel_a[] = {
  485. { 96, { 0x58, 0x78 } },
  486. { 104, { 0x38, 0x48 } },
  487. { 75, { 0xfe, 0x80 } },
  488. { 86, { 0xfe, 0x80 } },
  489. { 88, { 0xfe, 0x80 } },
  490. { 35, { 0x60, 0x60 } },
  491. { 97, { 0x58, 0x58 } },
  492. { 98, { 0x58, 0x58 } },
  493. };
  494. static const struct antenna_sel antenna_sel_bg[] = {
  495. { 96, { 0x48, 0x68 } },
  496. { 104, { 0x2c, 0x3c } },
  497. { 75, { 0xfe, 0x80 } },
  498. { 86, { 0xfe, 0x80 } },
  499. { 88, { 0xfe, 0x80 } },
  500. { 35, { 0x50, 0x50 } },
  501. { 97, { 0x48, 0x48 } },
  502. { 98, { 0x48, 0x48 } },
  503. };
  504. static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
  505. struct antenna_setup *ant)
  506. {
  507. const struct antenna_sel *sel;
  508. unsigned int lna;
  509. unsigned int i;
  510. u32 reg;
  511. if (rt2x00dev->curr_hwmode == HWMODE_A) {
  512. sel = antenna_sel_a;
  513. lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  514. } else {
  515. sel = antenna_sel_bg;
  516. lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  517. }
  518. for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
  519. rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
  520. rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
  521. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
  522. (rt2x00dev->curr_hwmode == HWMODE_B ||
  523. rt2x00dev->curr_hwmode == HWMODE_G));
  524. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
  525. (rt2x00dev->curr_hwmode == HWMODE_A));
  526. rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
  527. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  528. rt2x00_rf(&rt2x00dev->chip, RF5325))
  529. rt61pci_config_antenna_5x(rt2x00dev, ant);
  530. else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
  531. rt61pci_config_antenna_2x(rt2x00dev, ant);
  532. else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  533. if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
  534. rt61pci_config_antenna_2x(rt2x00dev, ant);
  535. else
  536. rt61pci_config_antenna_2529(rt2x00dev, ant);
  537. }
  538. }
  539. static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
  540. struct rt2x00lib_conf *libconf)
  541. {
  542. u32 reg;
  543. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  544. rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
  545. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  546. rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
  547. rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
  548. rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
  549. rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
  550. rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
  551. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  552. rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
  553. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  554. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  555. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
  556. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  557. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  558. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
  559. libconf->conf->beacon_int * 16);
  560. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  561. }
  562. static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
  563. const unsigned int flags,
  564. struct rt2x00lib_conf *libconf)
  565. {
  566. if (flags & CONFIG_UPDATE_PHYMODE)
  567. rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
  568. if (flags & CONFIG_UPDATE_CHANNEL)
  569. rt61pci_config_channel(rt2x00dev, &libconf->rf,
  570. libconf->conf->power_level);
  571. if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
  572. rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
  573. if (flags & CONFIG_UPDATE_ANTENNA)
  574. rt61pci_config_antenna(rt2x00dev, &libconf->ant);
  575. if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
  576. rt61pci_config_duration(rt2x00dev, libconf);
  577. }
  578. /*
  579. * LED functions.
  580. */
  581. static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
  582. {
  583. u32 reg;
  584. u8 arg0;
  585. u8 arg1;
  586. rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
  587. rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
  588. rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
  589. rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
  590. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
  591. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
  592. (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
  593. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
  594. (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
  595. arg0 = rt2x00dev->led_reg & 0xff;
  596. arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
  597. rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
  598. }
  599. static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
  600. {
  601. u16 led_reg;
  602. u8 arg0;
  603. u8 arg1;
  604. led_reg = rt2x00dev->led_reg;
  605. rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
  606. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
  607. rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
  608. arg0 = led_reg & 0xff;
  609. arg1 = (led_reg >> 8) & 0xff;
  610. rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
  611. }
  612. static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
  613. {
  614. u8 led;
  615. if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
  616. return;
  617. /*
  618. * Led handling requires a positive value for the rssi,
  619. * to do that correctly we need to add the correction.
  620. */
  621. rssi += rt2x00dev->rssi_offset;
  622. if (rssi <= 30)
  623. led = 0;
  624. else if (rssi <= 39)
  625. led = 1;
  626. else if (rssi <= 49)
  627. led = 2;
  628. else if (rssi <= 53)
  629. led = 3;
  630. else if (rssi <= 63)
  631. led = 4;
  632. else
  633. led = 5;
  634. rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
  635. }
  636. /*
  637. * Link tuning
  638. */
  639. static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
  640. struct link_qual *qual)
  641. {
  642. u32 reg;
  643. /*
  644. * Update FCS error count from register.
  645. */
  646. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  647. qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
  648. /*
  649. * Update False CCA count from register.
  650. */
  651. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  652. qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
  653. }
  654. static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
  655. {
  656. rt61pci_bbp_write(rt2x00dev, 17, 0x20);
  657. rt2x00dev->link.vgc_level = 0x20;
  658. }
  659. static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
  660. {
  661. int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
  662. u8 r17;
  663. u8 up_bound;
  664. u8 low_bound;
  665. /*
  666. * Update Led strength
  667. */
  668. rt61pci_activity_led(rt2x00dev, rssi);
  669. rt61pci_bbp_read(rt2x00dev, 17, &r17);
  670. /*
  671. * Determine r17 bounds.
  672. */
  673. if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
  674. low_bound = 0x28;
  675. up_bound = 0x48;
  676. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
  677. low_bound += 0x10;
  678. up_bound += 0x10;
  679. }
  680. } else {
  681. low_bound = 0x20;
  682. up_bound = 0x40;
  683. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  684. low_bound += 0x10;
  685. up_bound += 0x10;
  686. }
  687. }
  688. /*
  689. * Special big-R17 for very short distance
  690. */
  691. if (rssi >= -35) {
  692. if (r17 != 0x60)
  693. rt61pci_bbp_write(rt2x00dev, 17, 0x60);
  694. return;
  695. }
  696. /*
  697. * Special big-R17 for short distance
  698. */
  699. if (rssi >= -58) {
  700. if (r17 != up_bound)
  701. rt61pci_bbp_write(rt2x00dev, 17, up_bound);
  702. return;
  703. }
  704. /*
  705. * Special big-R17 for middle-short distance
  706. */
  707. if (rssi >= -66) {
  708. low_bound += 0x10;
  709. if (r17 != low_bound)
  710. rt61pci_bbp_write(rt2x00dev, 17, low_bound);
  711. return;
  712. }
  713. /*
  714. * Special mid-R17 for middle distance
  715. */
  716. if (rssi >= -74) {
  717. low_bound += 0x08;
  718. if (r17 != low_bound)
  719. rt61pci_bbp_write(rt2x00dev, 17, low_bound);
  720. return;
  721. }
  722. /*
  723. * Special case: Change up_bound based on the rssi.
  724. * Lower up_bound when rssi is weaker then -74 dBm.
  725. */
  726. up_bound -= 2 * (-74 - rssi);
  727. if (low_bound > up_bound)
  728. up_bound = low_bound;
  729. if (r17 > up_bound) {
  730. rt61pci_bbp_write(rt2x00dev, 17, up_bound);
  731. return;
  732. }
  733. /*
  734. * r17 does not yet exceed upper limit, continue and base
  735. * the r17 tuning on the false CCA count.
  736. */
  737. if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
  738. if (++r17 > up_bound)
  739. r17 = up_bound;
  740. rt61pci_bbp_write(rt2x00dev, 17, r17);
  741. } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
  742. if (--r17 < low_bound)
  743. r17 = low_bound;
  744. rt61pci_bbp_write(rt2x00dev, 17, r17);
  745. }
  746. }
  747. /*
  748. * Firmware name function.
  749. */
  750. static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  751. {
  752. char *fw_name;
  753. switch (rt2x00dev->chip.rt) {
  754. case RT2561:
  755. fw_name = FIRMWARE_RT2561;
  756. break;
  757. case RT2561s:
  758. fw_name = FIRMWARE_RT2561s;
  759. break;
  760. case RT2661:
  761. fw_name = FIRMWARE_RT2661;
  762. break;
  763. default:
  764. fw_name = NULL;
  765. break;
  766. }
  767. return fw_name;
  768. }
  769. /*
  770. * Initialization functions.
  771. */
  772. static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
  773. const size_t len)
  774. {
  775. int i;
  776. u32 reg;
  777. /*
  778. * Wait for stable hardware.
  779. */
  780. for (i = 0; i < 100; i++) {
  781. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  782. if (reg)
  783. break;
  784. msleep(1);
  785. }
  786. if (!reg) {
  787. ERROR(rt2x00dev, "Unstable hardware.\n");
  788. return -EBUSY;
  789. }
  790. /*
  791. * Prepare MCU and mailbox for firmware loading.
  792. */
  793. reg = 0;
  794. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  795. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  796. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  797. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  798. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
  799. /*
  800. * Write firmware to device.
  801. */
  802. reg = 0;
  803. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  804. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
  805. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  806. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  807. data, len);
  808. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
  809. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  810. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
  811. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  812. for (i = 0; i < 100; i++) {
  813. rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
  814. if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
  815. break;
  816. msleep(1);
  817. }
  818. if (i == 100) {
  819. ERROR(rt2x00dev, "MCU Control register not ready.\n");
  820. return -EBUSY;
  821. }
  822. /*
  823. * Reset MAC and BBP registers.
  824. */
  825. reg = 0;
  826. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  827. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  828. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  829. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  830. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  831. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  832. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  833. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  834. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  835. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  836. return 0;
  837. }
  838. static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
  839. {
  840. struct data_ring *ring = rt2x00dev->rx;
  841. __le32 *rxd;
  842. unsigned int i;
  843. u32 word;
  844. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  845. for (i = 0; i < ring->stats.limit; i++) {
  846. rxd = ring->entry[i].priv;
  847. rt2x00_desc_read(rxd, 5, &word);
  848. rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
  849. ring->entry[i].data_dma);
  850. rt2x00_desc_write(rxd, 5, word);
  851. rt2x00_desc_read(rxd, 0, &word);
  852. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  853. rt2x00_desc_write(rxd, 0, word);
  854. }
  855. rt2x00_ring_index_clear(rt2x00dev->rx);
  856. }
  857. static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
  858. {
  859. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  860. __le32 *txd;
  861. unsigned int i;
  862. u32 word;
  863. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  864. for (i = 0; i < ring->stats.limit; i++) {
  865. txd = ring->entry[i].priv;
  866. rt2x00_desc_read(txd, 1, &word);
  867. rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
  868. rt2x00_desc_write(txd, 1, word);
  869. rt2x00_desc_read(txd, 5, &word);
  870. rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
  871. rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
  872. rt2x00_desc_write(txd, 5, word);
  873. rt2x00_desc_read(txd, 6, &word);
  874. rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
  875. ring->entry[i].data_dma);
  876. rt2x00_desc_write(txd, 6, word);
  877. rt2x00_desc_read(txd, 0, &word);
  878. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  879. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  880. rt2x00_desc_write(txd, 0, word);
  881. }
  882. rt2x00_ring_index_clear(ring);
  883. }
  884. static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
  885. {
  886. u32 reg;
  887. /*
  888. * Initialize rings.
  889. */
  890. rt61pci_init_rxring(rt2x00dev);
  891. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  892. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  893. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
  894. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
  895. rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
  896. /*
  897. * Initialize registers.
  898. */
  899. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
  900. rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
  901. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
  902. rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
  903. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
  904. rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
  905. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
  906. rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
  907. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
  908. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
  909. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
  910. rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
  911. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
  912. rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
  913. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
  914. 4);
  915. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
  916. rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
  917. rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
  918. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
  919. rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
  920. rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
  921. rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
  922. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
  923. rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
  924. rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
  925. rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
  926. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
  927. rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
  928. rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
  929. rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
  930. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
  931. rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
  932. rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
  933. rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
  934. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
  935. rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
  936. rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
  937. rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE,
  938. rt2x00dev->rx->stats.limit);
  939. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
  940. rt2x00dev->rx->desc_size / 4);
  941. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
  942. rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
  943. rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
  944. rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
  945. rt2x00dev->rx->data_dma);
  946. rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
  947. rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
  948. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
  949. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
  950. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
  951. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
  952. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_MGMT, 0);
  953. rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
  954. rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
  955. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
  956. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
  957. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
  958. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
  959. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
  960. rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
  961. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  962. rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
  963. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  964. return 0;
  965. }
  966. static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
  967. {
  968. u32 reg;
  969. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  970. rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
  971. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
  972. rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
  973. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  974. rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
  975. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
  976. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
  977. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
  978. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
  979. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
  980. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
  981. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
  982. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
  983. rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
  984. /*
  985. * CCK TXD BBP registers
  986. */
  987. rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
  988. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
  989. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
  990. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
  991. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
  992. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
  993. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
  994. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
  995. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
  996. rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
  997. /*
  998. * OFDM TXD BBP registers
  999. */
  1000. rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
  1001. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
  1002. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
  1003. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
  1004. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
  1005. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
  1006. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
  1007. rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
  1008. rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
  1009. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
  1010. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
  1011. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
  1012. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
  1013. rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
  1014. rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
  1015. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
  1016. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
  1017. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
  1018. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
  1019. rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
  1020. rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
  1021. rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
  1022. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  1023. rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
  1024. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  1025. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
  1026. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  1027. return -EBUSY;
  1028. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
  1029. /*
  1030. * Invalidate all Shared Keys (SEC_CSR0),
  1031. * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
  1032. */
  1033. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
  1034. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
  1035. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
  1036. rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
  1037. rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
  1038. rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
  1039. rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
  1040. rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
  1041. rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
  1042. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1043. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
  1044. rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
  1045. rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
  1046. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
  1047. rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
  1048. rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
  1049. rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
  1050. rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
  1051. /*
  1052. * We must clear the error counters.
  1053. * These registers are cleared on read,
  1054. * so we may pass a useless variable to store the value.
  1055. */
  1056. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  1057. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  1058. rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
  1059. /*
  1060. * Reset MAC and BBP registers.
  1061. */
  1062. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1063. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1064. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1065. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1066. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1067. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1068. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1069. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1070. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1071. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1072. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1073. return 0;
  1074. }
  1075. static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  1076. {
  1077. unsigned int i;
  1078. u16 eeprom;
  1079. u8 reg_id;
  1080. u8 value;
  1081. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1082. rt61pci_bbp_read(rt2x00dev, 0, &value);
  1083. if ((value != 0xff) && (value != 0x00))
  1084. goto continue_csr_init;
  1085. NOTICE(rt2x00dev, "Waiting for BBP register.\n");
  1086. udelay(REGISTER_BUSY_DELAY);
  1087. }
  1088. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1089. return -EACCES;
  1090. continue_csr_init:
  1091. rt61pci_bbp_write(rt2x00dev, 3, 0x00);
  1092. rt61pci_bbp_write(rt2x00dev, 15, 0x30);
  1093. rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
  1094. rt61pci_bbp_write(rt2x00dev, 22, 0x38);
  1095. rt61pci_bbp_write(rt2x00dev, 23, 0x06);
  1096. rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
  1097. rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
  1098. rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
  1099. rt61pci_bbp_write(rt2x00dev, 34, 0x12);
  1100. rt61pci_bbp_write(rt2x00dev, 37, 0x07);
  1101. rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
  1102. rt61pci_bbp_write(rt2x00dev, 41, 0x60);
  1103. rt61pci_bbp_write(rt2x00dev, 53, 0x10);
  1104. rt61pci_bbp_write(rt2x00dev, 54, 0x18);
  1105. rt61pci_bbp_write(rt2x00dev, 60, 0x10);
  1106. rt61pci_bbp_write(rt2x00dev, 61, 0x04);
  1107. rt61pci_bbp_write(rt2x00dev, 62, 0x04);
  1108. rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
  1109. rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
  1110. rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
  1111. rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
  1112. rt61pci_bbp_write(rt2x00dev, 99, 0x00);
  1113. rt61pci_bbp_write(rt2x00dev, 102, 0x16);
  1114. rt61pci_bbp_write(rt2x00dev, 107, 0x04);
  1115. DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
  1116. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1117. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1118. if (eeprom != 0xffff && eeprom != 0x0000) {
  1119. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1120. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1121. DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
  1122. reg_id, value);
  1123. rt61pci_bbp_write(rt2x00dev, reg_id, value);
  1124. }
  1125. }
  1126. DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
  1127. return 0;
  1128. }
  1129. /*
  1130. * Device state switch handlers.
  1131. */
  1132. static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  1133. enum dev_state state)
  1134. {
  1135. u32 reg;
  1136. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1137. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
  1138. state == STATE_RADIO_RX_OFF);
  1139. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1140. }
  1141. static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  1142. enum dev_state state)
  1143. {
  1144. int mask = (state == STATE_RADIO_IRQ_OFF);
  1145. u32 reg;
  1146. /*
  1147. * When interrupts are being enabled, the interrupt registers
  1148. * should clear the register to assure a clean state.
  1149. */
  1150. if (state == STATE_RADIO_IRQ_ON) {
  1151. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1152. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1153. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
  1154. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
  1155. }
  1156. /*
  1157. * Only toggle the interrupts bits we are going to use.
  1158. * Non-checked interrupt bits are disabled by default.
  1159. */
  1160. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  1161. rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
  1162. rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
  1163. rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
  1164. rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
  1165. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  1166. rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
  1167. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
  1168. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
  1169. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
  1170. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
  1171. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
  1172. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
  1173. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
  1174. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
  1175. rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
  1176. }
  1177. static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  1178. {
  1179. u32 reg;
  1180. /*
  1181. * Initialize all registers.
  1182. */
  1183. if (rt61pci_init_rings(rt2x00dev) ||
  1184. rt61pci_init_registers(rt2x00dev) ||
  1185. rt61pci_init_bbp(rt2x00dev)) {
  1186. ERROR(rt2x00dev, "Register initialization failed.\n");
  1187. return -EIO;
  1188. }
  1189. /*
  1190. * Enable interrupts.
  1191. */
  1192. rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
  1193. /*
  1194. * Enable RX.
  1195. */
  1196. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1197. rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
  1198. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1199. /*
  1200. * Enable LED
  1201. */
  1202. rt61pci_enable_led(rt2x00dev);
  1203. return 0;
  1204. }
  1205. static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  1206. {
  1207. u32 reg;
  1208. /*
  1209. * Disable LED
  1210. */
  1211. rt61pci_disable_led(rt2x00dev);
  1212. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
  1213. /*
  1214. * Disable synchronisation.
  1215. */
  1216. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  1217. /*
  1218. * Cancel RX and TX.
  1219. */
  1220. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1221. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
  1222. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
  1223. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
  1224. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
  1225. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
  1226. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1227. /*
  1228. * Disable interrupts.
  1229. */
  1230. rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
  1231. }
  1232. static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
  1233. {
  1234. u32 reg;
  1235. unsigned int i;
  1236. char put_to_sleep;
  1237. char current_state;
  1238. put_to_sleep = (state != STATE_AWAKE);
  1239. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1240. rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
  1241. rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
  1242. rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
  1243. /*
  1244. * Device is not guaranteed to be in the requested state yet.
  1245. * We must wait until the register indicates that the
  1246. * device has entered the correct state.
  1247. */
  1248. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1249. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1250. current_state =
  1251. rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
  1252. if (current_state == !put_to_sleep)
  1253. return 0;
  1254. msleep(10);
  1255. }
  1256. NOTICE(rt2x00dev, "Device failed to enter state %d, "
  1257. "current device state %d.\n", !put_to_sleep, current_state);
  1258. return -EBUSY;
  1259. }
  1260. static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  1261. enum dev_state state)
  1262. {
  1263. int retval = 0;
  1264. switch (state) {
  1265. case STATE_RADIO_ON:
  1266. retval = rt61pci_enable_radio(rt2x00dev);
  1267. break;
  1268. case STATE_RADIO_OFF:
  1269. rt61pci_disable_radio(rt2x00dev);
  1270. break;
  1271. case STATE_RADIO_RX_ON:
  1272. case STATE_RADIO_RX_OFF:
  1273. rt61pci_toggle_rx(rt2x00dev, state);
  1274. break;
  1275. case STATE_DEEP_SLEEP:
  1276. case STATE_SLEEP:
  1277. case STATE_STANDBY:
  1278. case STATE_AWAKE:
  1279. retval = rt61pci_set_state(rt2x00dev, state);
  1280. break;
  1281. default:
  1282. retval = -ENOTSUPP;
  1283. break;
  1284. }
  1285. return retval;
  1286. }
  1287. /*
  1288. * TX descriptor initialization
  1289. */
  1290. static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  1291. __le32 *txd,
  1292. struct txdata_entry_desc *desc,
  1293. struct ieee80211_hdr *ieee80211hdr,
  1294. unsigned int length,
  1295. struct ieee80211_tx_control *control)
  1296. {
  1297. u32 word;
  1298. /*
  1299. * Start writing the descriptor words.
  1300. */
  1301. rt2x00_desc_read(txd, 1, &word);
  1302. rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
  1303. rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
  1304. rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
  1305. rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
  1306. rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
  1307. rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
  1308. rt2x00_desc_write(txd, 1, word);
  1309. rt2x00_desc_read(txd, 2, &word);
  1310. rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
  1311. rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
  1312. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
  1313. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
  1314. rt2x00_desc_write(txd, 2, word);
  1315. rt2x00_desc_read(txd, 5, &word);
  1316. rt2x00_set_field32(&word, TXD_W5_TX_POWER,
  1317. TXPOWER_TO_DEV(control->power_level));
  1318. rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
  1319. rt2x00_desc_write(txd, 5, word);
  1320. rt2x00_desc_read(txd, 11, &word);
  1321. rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
  1322. rt2x00_desc_write(txd, 11, word);
  1323. rt2x00_desc_read(txd, 0, &word);
  1324. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1325. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1326. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1327. test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
  1328. rt2x00_set_field32(&word, TXD_W0_ACK,
  1329. test_bit(ENTRY_TXD_ACK, &desc->flags));
  1330. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1331. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
  1332. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1333. test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
  1334. rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
  1335. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1336. !!(control->flags &
  1337. IEEE80211_TXCTL_LONG_RETRY_LIMIT));
  1338. rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
  1339. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
  1340. rt2x00_set_field32(&word, TXD_W0_BURST,
  1341. test_bit(ENTRY_TXD_BURST, &desc->flags));
  1342. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
  1343. rt2x00_desc_write(txd, 0, word);
  1344. }
  1345. /*
  1346. * TX data initialization
  1347. */
  1348. static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1349. unsigned int queue)
  1350. {
  1351. u32 reg;
  1352. if (queue == IEEE80211_TX_QUEUE_BEACON) {
  1353. /*
  1354. * For Wi-Fi faily generated beacons between participating
  1355. * stations. Set TBTT phase adaptive adjustment step to 8us.
  1356. */
  1357. rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
  1358. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1359. if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
  1360. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
  1361. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1362. }
  1363. return;
  1364. }
  1365. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1366. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
  1367. (queue == IEEE80211_TX_QUEUE_DATA0));
  1368. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
  1369. (queue == IEEE80211_TX_QUEUE_DATA1));
  1370. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
  1371. (queue == IEEE80211_TX_QUEUE_DATA2));
  1372. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
  1373. (queue == IEEE80211_TX_QUEUE_DATA3));
  1374. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_MGMT,
  1375. (queue == IEEE80211_TX_QUEUE_DATA4));
  1376. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1377. }
  1378. /*
  1379. * RX control handlers
  1380. */
  1381. static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
  1382. {
  1383. u16 eeprom;
  1384. u8 offset;
  1385. u8 lna;
  1386. lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
  1387. switch (lna) {
  1388. case 3:
  1389. offset = 90;
  1390. break;
  1391. case 2:
  1392. offset = 74;
  1393. break;
  1394. case 1:
  1395. offset = 64;
  1396. break;
  1397. default:
  1398. return 0;
  1399. }
  1400. if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
  1401. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  1402. offset += 14;
  1403. if (lna == 3 || lna == 2)
  1404. offset += 10;
  1405. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
  1406. offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
  1407. } else {
  1408. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
  1409. offset += 14;
  1410. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
  1411. offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
  1412. }
  1413. return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
  1414. }
  1415. static void rt61pci_fill_rxdone(struct data_entry *entry,
  1416. struct rxdata_entry_desc *desc)
  1417. {
  1418. __le32 *rxd = entry->priv;
  1419. u32 word0;
  1420. u32 word1;
  1421. rt2x00_desc_read(rxd, 0, &word0);
  1422. rt2x00_desc_read(rxd, 1, &word1);
  1423. desc->flags = 0;
  1424. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1425. desc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1426. /*
  1427. * Obtain the status about this packet.
  1428. */
  1429. desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
  1430. desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
  1431. desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
  1432. desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1433. return;
  1434. }
  1435. /*
  1436. * Interrupt functions.
  1437. */
  1438. static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
  1439. {
  1440. struct data_ring *ring;
  1441. struct data_entry *entry;
  1442. struct data_entry *entry_done;
  1443. __le32 *txd;
  1444. u32 word;
  1445. u32 reg;
  1446. u32 old_reg;
  1447. int type;
  1448. int index;
  1449. int tx_status;
  1450. int retry;
  1451. /*
  1452. * During each loop we will compare the freshly read
  1453. * STA_CSR4 register value with the value read from
  1454. * the previous loop. If the 2 values are equal then
  1455. * we should stop processing because the chance it
  1456. * quite big that the device has been unplugged and
  1457. * we risk going into an endless loop.
  1458. */
  1459. old_reg = 0;
  1460. while (1) {
  1461. rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
  1462. if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
  1463. break;
  1464. if (old_reg == reg)
  1465. break;
  1466. old_reg = reg;
  1467. /*
  1468. * Skip this entry when it contains an invalid
  1469. * ring identication number.
  1470. */
  1471. type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
  1472. ring = rt2x00lib_get_ring(rt2x00dev, type);
  1473. if (unlikely(!ring))
  1474. continue;
  1475. /*
  1476. * Skip this entry when it contains an invalid
  1477. * index number.
  1478. */
  1479. index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
  1480. if (unlikely(index >= ring->stats.limit))
  1481. continue;
  1482. entry = &ring->entry[index];
  1483. txd = entry->priv;
  1484. rt2x00_desc_read(txd, 0, &word);
  1485. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1486. !rt2x00_get_field32(word, TXD_W0_VALID))
  1487. return;
  1488. entry_done = rt2x00_get_data_entry_done(ring);
  1489. while (entry != entry_done) {
  1490. /* Catch up. Just report any entries we missed as
  1491. * failed. */
  1492. WARNING(rt2x00dev,
  1493. "TX status report missed for entry %p\n",
  1494. entry_done);
  1495. rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
  1496. entry_done = rt2x00_get_data_entry_done(ring);
  1497. }
  1498. /*
  1499. * Obtain the status about this packet.
  1500. */
  1501. tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
  1502. retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
  1503. rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
  1504. }
  1505. }
  1506. static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
  1507. {
  1508. struct rt2x00_dev *rt2x00dev = dev_instance;
  1509. u32 reg_mcu;
  1510. u32 reg;
  1511. /*
  1512. * Get the interrupt sources & saved to local variable.
  1513. * Write register value back to clear pending interrupts.
  1514. */
  1515. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
  1516. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
  1517. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1518. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1519. if (!reg && !reg_mcu)
  1520. return IRQ_NONE;
  1521. if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
  1522. return IRQ_HANDLED;
  1523. /*
  1524. * Handle interrupts, walk through all bits
  1525. * and run the tasks, the bits are checked in order of
  1526. * priority.
  1527. */
  1528. /*
  1529. * 1 - Rx ring done interrupt.
  1530. */
  1531. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
  1532. rt2x00pci_rxdone(rt2x00dev);
  1533. /*
  1534. * 2 - Tx ring done interrupt.
  1535. */
  1536. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
  1537. rt61pci_txdone(rt2x00dev);
  1538. /*
  1539. * 3 - Handle MCU command done.
  1540. */
  1541. if (reg_mcu)
  1542. rt2x00pci_register_write(rt2x00dev,
  1543. M2H_CMD_DONE_CSR, 0xffffffff);
  1544. return IRQ_HANDLED;
  1545. }
  1546. /*
  1547. * Device probe functions.
  1548. */
  1549. static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1550. {
  1551. struct eeprom_93cx6 eeprom;
  1552. u32 reg;
  1553. u16 word;
  1554. u8 *mac;
  1555. s8 value;
  1556. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  1557. eeprom.data = rt2x00dev;
  1558. eeprom.register_read = rt61pci_eepromregister_read;
  1559. eeprom.register_write = rt61pci_eepromregister_write;
  1560. eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
  1561. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1562. eeprom.reg_data_in = 0;
  1563. eeprom.reg_data_out = 0;
  1564. eeprom.reg_data_clock = 0;
  1565. eeprom.reg_chip_select = 0;
  1566. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1567. EEPROM_SIZE / sizeof(u16));
  1568. /*
  1569. * Start validation of the data that has been read.
  1570. */
  1571. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1572. if (!is_valid_ether_addr(mac)) {
  1573. DECLARE_MAC_BUF(macbuf);
  1574. random_ether_addr(mac);
  1575. EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
  1576. }
  1577. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1578. if (word == 0xffff) {
  1579. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1580. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1581. ANTENNA_B);
  1582. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1583. ANTENNA_B);
  1584. rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
  1585. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1586. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1587. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
  1588. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1589. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1590. }
  1591. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1592. if (word == 0xffff) {
  1593. rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
  1594. rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
  1595. rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
  1596. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1597. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1598. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1599. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1600. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1601. }
  1602. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
  1603. if (word == 0xffff) {
  1604. rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
  1605. LED_MODE_DEFAULT);
  1606. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
  1607. EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
  1608. }
  1609. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1610. if (word == 0xffff) {
  1611. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1612. rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
  1613. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1614. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1615. }
  1616. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
  1617. if (word == 0xffff) {
  1618. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1619. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1620. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1621. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1622. } else {
  1623. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
  1624. if (value < -10 || value > 10)
  1625. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1626. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
  1627. if (value < -10 || value > 10)
  1628. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1629. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1630. }
  1631. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
  1632. if (word == 0xffff) {
  1633. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1634. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1635. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1636. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1637. } else {
  1638. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
  1639. if (value < -10 || value > 10)
  1640. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1641. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
  1642. if (value < -10 || value > 10)
  1643. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1644. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1645. }
  1646. return 0;
  1647. }
  1648. static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1649. {
  1650. u32 reg;
  1651. u16 value;
  1652. u16 eeprom;
  1653. u16 device;
  1654. /*
  1655. * Read EEPROM word for configuration.
  1656. */
  1657. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1658. /*
  1659. * Identify RF chipset.
  1660. * To determine the RT chip we have to read the
  1661. * PCI header of the device.
  1662. */
  1663. pci_read_config_word(rt2x00dev_pci(rt2x00dev),
  1664. PCI_CONFIG_HEADER_DEVICE, &device);
  1665. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1666. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1667. rt2x00_set_chip(rt2x00dev, device, value, reg);
  1668. if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
  1669. !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
  1670. !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
  1671. !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
  1672. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1673. return -ENODEV;
  1674. }
  1675. /*
  1676. * Determine number of antenna's.
  1677. */
  1678. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
  1679. __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
  1680. /*
  1681. * Identify default antenna configuration.
  1682. */
  1683. rt2x00dev->default_ant.tx =
  1684. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1685. rt2x00dev->default_ant.rx =
  1686. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1687. /*
  1688. * Read the Frame type.
  1689. */
  1690. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
  1691. __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
  1692. /*
  1693. * Detect if this device has an hardware controlled radio.
  1694. */
  1695. #ifdef CONFIG_RT61PCI_RFKILL
  1696. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1697. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1698. #endif /* CONFIG_RT61PCI_RFKILL */
  1699. /*
  1700. * Read frequency offset and RF programming sequence.
  1701. */
  1702. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1703. if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
  1704. __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
  1705. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  1706. /*
  1707. * Read external LNA informations.
  1708. */
  1709. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1710. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  1711. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  1712. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1713. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  1714. /*
  1715. * When working with a RF2529 chip without double antenna
  1716. * the antenna settings should be gathered from the NIC
  1717. * eeprom word.
  1718. */
  1719. if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
  1720. !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
  1721. switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
  1722. case 0:
  1723. rt2x00dev->default_ant.tx = ANTENNA_B;
  1724. rt2x00dev->default_ant.rx = ANTENNA_A;
  1725. break;
  1726. case 1:
  1727. rt2x00dev->default_ant.tx = ANTENNA_B;
  1728. rt2x00dev->default_ant.rx = ANTENNA_B;
  1729. break;
  1730. case 2:
  1731. rt2x00dev->default_ant.tx = ANTENNA_A;
  1732. rt2x00dev->default_ant.rx = ANTENNA_A;
  1733. break;
  1734. case 3:
  1735. rt2x00dev->default_ant.tx = ANTENNA_A;
  1736. rt2x00dev->default_ant.rx = ANTENNA_B;
  1737. break;
  1738. }
  1739. if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
  1740. rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
  1741. if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
  1742. rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
  1743. }
  1744. /*
  1745. * Store led settings, for correct led behaviour.
  1746. * If the eeprom value is invalid,
  1747. * switch to default led mode.
  1748. */
  1749. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
  1750. rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
  1751. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
  1752. rt2x00dev->led_mode);
  1753. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
  1754. rt2x00_get_field16(eeprom,
  1755. EEPROM_LED_POLARITY_GPIO_0));
  1756. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
  1757. rt2x00_get_field16(eeprom,
  1758. EEPROM_LED_POLARITY_GPIO_1));
  1759. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
  1760. rt2x00_get_field16(eeprom,
  1761. EEPROM_LED_POLARITY_GPIO_2));
  1762. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
  1763. rt2x00_get_field16(eeprom,
  1764. EEPROM_LED_POLARITY_GPIO_3));
  1765. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
  1766. rt2x00_get_field16(eeprom,
  1767. EEPROM_LED_POLARITY_GPIO_4));
  1768. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
  1769. rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
  1770. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
  1771. rt2x00_get_field16(eeprom,
  1772. EEPROM_LED_POLARITY_RDY_G));
  1773. rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
  1774. rt2x00_get_field16(eeprom,
  1775. EEPROM_LED_POLARITY_RDY_A));
  1776. return 0;
  1777. }
  1778. /*
  1779. * RF value list for RF5225 & RF5325
  1780. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
  1781. */
  1782. static const struct rf_channel rf_vals_noseq[] = {
  1783. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  1784. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  1785. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  1786. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  1787. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  1788. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  1789. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  1790. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  1791. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  1792. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  1793. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  1794. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  1795. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  1796. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  1797. /* 802.11 UNI / HyperLan 2 */
  1798. { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
  1799. { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
  1800. { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
  1801. { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
  1802. { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
  1803. { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
  1804. { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
  1805. { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
  1806. /* 802.11 HyperLan 2 */
  1807. { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
  1808. { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
  1809. { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
  1810. { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
  1811. { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
  1812. { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
  1813. { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
  1814. { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
  1815. { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
  1816. { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
  1817. /* 802.11 UNII */
  1818. { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
  1819. { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
  1820. { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
  1821. { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
  1822. { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
  1823. { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
  1824. /* MMAC(Japan)J52 ch 34,38,42,46 */
  1825. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
  1826. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
  1827. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
  1828. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
  1829. };
  1830. /*
  1831. * RF value list for RF5225 & RF5325
  1832. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
  1833. */
  1834. static const struct rf_channel rf_vals_seq[] = {
  1835. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  1836. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  1837. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  1838. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  1839. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  1840. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  1841. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  1842. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  1843. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  1844. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  1845. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  1846. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  1847. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  1848. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  1849. /* 802.11 UNI / HyperLan 2 */
  1850. { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
  1851. { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
  1852. { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
  1853. { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
  1854. { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
  1855. { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
  1856. { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
  1857. { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
  1858. /* 802.11 HyperLan 2 */
  1859. { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
  1860. { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
  1861. { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
  1862. { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
  1863. { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
  1864. { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
  1865. { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
  1866. { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
  1867. { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
  1868. { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
  1869. /* 802.11 UNII */
  1870. { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
  1871. { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
  1872. { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
  1873. { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
  1874. { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
  1875. { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
  1876. /* MMAC(Japan)J52 ch 34,38,42,46 */
  1877. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
  1878. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
  1879. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
  1880. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
  1881. };
  1882. static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1883. {
  1884. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1885. u8 *txpower;
  1886. unsigned int i;
  1887. /*
  1888. * Initialize all hw fields.
  1889. */
  1890. rt2x00dev->hw->flags =
  1891. IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  1892. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  1893. rt2x00dev->hw->extra_tx_headroom = 0;
  1894. rt2x00dev->hw->max_signal = MAX_SIGNAL;
  1895. rt2x00dev->hw->max_rssi = MAX_RX_SSI;
  1896. rt2x00dev->hw->queues = 5;
  1897. SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
  1898. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1899. rt2x00_eeprom_addr(rt2x00dev,
  1900. EEPROM_MAC_ADDR_0));
  1901. /*
  1902. * Convert tx_power array in eeprom.
  1903. */
  1904. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
  1905. for (i = 0; i < 14; i++)
  1906. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1907. /*
  1908. * Initialize hw_mode information.
  1909. */
  1910. spec->num_modes = 2;
  1911. spec->num_rates = 12;
  1912. spec->tx_power_a = NULL;
  1913. spec->tx_power_bg = txpower;
  1914. spec->tx_power_default = DEFAULT_TXPOWER;
  1915. if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
  1916. spec->num_channels = 14;
  1917. spec->channels = rf_vals_noseq;
  1918. } else {
  1919. spec->num_channels = 14;
  1920. spec->channels = rf_vals_seq;
  1921. }
  1922. if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
  1923. rt2x00_rf(&rt2x00dev->chip, RF5325)) {
  1924. spec->num_modes = 3;
  1925. spec->num_channels = ARRAY_SIZE(rf_vals_seq);
  1926. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
  1927. for (i = 0; i < 14; i++)
  1928. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1929. spec->tx_power_a = txpower;
  1930. }
  1931. }
  1932. static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1933. {
  1934. int retval;
  1935. /*
  1936. * Allocate eeprom data.
  1937. */
  1938. retval = rt61pci_validate_eeprom(rt2x00dev);
  1939. if (retval)
  1940. return retval;
  1941. retval = rt61pci_init_eeprom(rt2x00dev);
  1942. if (retval)
  1943. return retval;
  1944. /*
  1945. * Initialize hw specifications.
  1946. */
  1947. rt61pci_probe_hw_mode(rt2x00dev);
  1948. /*
  1949. * This device requires firmware
  1950. */
  1951. __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
  1952. /*
  1953. * Set the rssi offset.
  1954. */
  1955. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1956. return 0;
  1957. }
  1958. /*
  1959. * IEEE80211 stack callback functions.
  1960. */
  1961. static void rt61pci_configure_filter(struct ieee80211_hw *hw,
  1962. unsigned int changed_flags,
  1963. unsigned int *total_flags,
  1964. int mc_count,
  1965. struct dev_addr_list *mc_list)
  1966. {
  1967. struct rt2x00_dev *rt2x00dev = hw->priv;
  1968. struct interface *intf = &rt2x00dev->interface;
  1969. u32 reg;
  1970. /*
  1971. * Mask off any flags we are going to ignore from
  1972. * the total_flags field.
  1973. */
  1974. *total_flags &=
  1975. FIF_ALLMULTI |
  1976. FIF_FCSFAIL |
  1977. FIF_PLCPFAIL |
  1978. FIF_CONTROL |
  1979. FIF_OTHER_BSS |
  1980. FIF_PROMISC_IN_BSS;
  1981. /*
  1982. * Apply some rules to the filters:
  1983. * - Some filters imply different filters to be set.
  1984. * - Some things we can't filter out at all.
  1985. * - Some filters are set based on interface type.
  1986. */
  1987. if (mc_count)
  1988. *total_flags |= FIF_ALLMULTI;
  1989. if (*total_flags & FIF_OTHER_BSS ||
  1990. *total_flags & FIF_PROMISC_IN_BSS)
  1991. *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
  1992. if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
  1993. *total_flags |= FIF_PROMISC_IN_BSS;
  1994. /*
  1995. * Check if there is any work left for us.
  1996. */
  1997. if (intf->filter == *total_flags)
  1998. return;
  1999. intf->filter = *total_flags;
  2000. /*
  2001. * Start configuration steps.
  2002. * Note that the version error will always be dropped
  2003. * and broadcast frames will always be accepted since
  2004. * there is no filter for it at this time.
  2005. */
  2006. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  2007. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
  2008. !(*total_flags & FIF_FCSFAIL));
  2009. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
  2010. !(*total_flags & FIF_PLCPFAIL));
  2011. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
  2012. !(*total_flags & FIF_CONTROL));
  2013. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
  2014. !(*total_flags & FIF_PROMISC_IN_BSS));
  2015. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
  2016. !(*total_flags & FIF_PROMISC_IN_BSS));
  2017. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
  2018. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
  2019. !(*total_flags & FIF_ALLMULTI));
  2020. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BORADCAST, 0);
  2021. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 1);
  2022. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  2023. }
  2024. static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
  2025. u32 short_retry, u32 long_retry)
  2026. {
  2027. struct rt2x00_dev *rt2x00dev = hw->priv;
  2028. u32 reg;
  2029. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  2030. rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
  2031. rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
  2032. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  2033. return 0;
  2034. }
  2035. static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
  2036. {
  2037. struct rt2x00_dev *rt2x00dev = hw->priv;
  2038. u64 tsf;
  2039. u32 reg;
  2040. rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
  2041. tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
  2042. rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
  2043. tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
  2044. return tsf;
  2045. }
  2046. static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
  2047. {
  2048. struct rt2x00_dev *rt2x00dev = hw->priv;
  2049. rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
  2050. rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
  2051. }
  2052. static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  2053. struct ieee80211_tx_control *control)
  2054. {
  2055. struct rt2x00_dev *rt2x00dev = hw->priv;
  2056. struct skb_desc *desc;
  2057. struct data_ring *ring;
  2058. struct data_entry *entry;
  2059. /*
  2060. * Just in case the ieee80211 doesn't set this,
  2061. * but we need this queue set for the descriptor
  2062. * initialization.
  2063. */
  2064. control->queue = IEEE80211_TX_QUEUE_BEACON;
  2065. ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
  2066. entry = rt2x00_get_data_entry(ring);
  2067. /*
  2068. * We need to append the descriptor in front of the
  2069. * beacon frame.
  2070. */
  2071. if (skb_headroom(skb) < TXD_DESC_SIZE) {
  2072. if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
  2073. dev_kfree_skb(skb);
  2074. return -ENOMEM;
  2075. }
  2076. }
  2077. /*
  2078. * Add the descriptor in front of the skb.
  2079. */
  2080. skb_push(skb, ring->desc_size);
  2081. memset(skb->data, 0, ring->desc_size);
  2082. /*
  2083. * Fill in skb descriptor
  2084. */
  2085. desc = get_skb_desc(skb);
  2086. desc->desc_len = ring->desc_size;
  2087. desc->data_len = skb->len - ring->desc_size;
  2088. desc->desc = skb->data;
  2089. desc->data = skb->data + ring->desc_size;
  2090. desc->ring = ring;
  2091. desc->entry = entry;
  2092. rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
  2093. /*
  2094. * Write entire beacon with descriptor to register,
  2095. * and kick the beacon generator.
  2096. */
  2097. rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
  2098. skb->data, skb->len);
  2099. rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
  2100. return 0;
  2101. }
  2102. static const struct ieee80211_ops rt61pci_mac80211_ops = {
  2103. .tx = rt2x00mac_tx,
  2104. .start = rt2x00mac_start,
  2105. .stop = rt2x00mac_stop,
  2106. .add_interface = rt2x00mac_add_interface,
  2107. .remove_interface = rt2x00mac_remove_interface,
  2108. .config = rt2x00mac_config,
  2109. .config_interface = rt2x00mac_config_interface,
  2110. .configure_filter = rt61pci_configure_filter,
  2111. .get_stats = rt2x00mac_get_stats,
  2112. .set_retry_limit = rt61pci_set_retry_limit,
  2113. .erp_ie_changed = rt2x00mac_erp_ie_changed,
  2114. .conf_tx = rt2x00mac_conf_tx,
  2115. .get_tx_stats = rt2x00mac_get_tx_stats,
  2116. .get_tsf = rt61pci_get_tsf,
  2117. .reset_tsf = rt61pci_reset_tsf,
  2118. .beacon_update = rt61pci_beacon_update,
  2119. };
  2120. static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
  2121. .irq_handler = rt61pci_interrupt,
  2122. .probe_hw = rt61pci_probe_hw,
  2123. .get_firmware_name = rt61pci_get_firmware_name,
  2124. .load_firmware = rt61pci_load_firmware,
  2125. .initialize = rt2x00pci_initialize,
  2126. .uninitialize = rt2x00pci_uninitialize,
  2127. .set_device_state = rt61pci_set_device_state,
  2128. .rfkill_poll = rt61pci_rfkill_poll,
  2129. .link_stats = rt61pci_link_stats,
  2130. .reset_tuner = rt61pci_reset_tuner,
  2131. .link_tuner = rt61pci_link_tuner,
  2132. .write_tx_desc = rt61pci_write_tx_desc,
  2133. .write_tx_data = rt2x00pci_write_tx_data,
  2134. .kick_tx_queue = rt61pci_kick_tx_queue,
  2135. .fill_rxdone = rt61pci_fill_rxdone,
  2136. .config_mac_addr = rt61pci_config_mac_addr,
  2137. .config_bssid = rt61pci_config_bssid,
  2138. .config_type = rt61pci_config_type,
  2139. .config_preamble = rt61pci_config_preamble,
  2140. .config = rt61pci_config,
  2141. };
  2142. static const struct rt2x00_ops rt61pci_ops = {
  2143. .name = KBUILD_MODNAME,
  2144. .rxd_size = RXD_DESC_SIZE,
  2145. .txd_size = TXD_DESC_SIZE,
  2146. .eeprom_size = EEPROM_SIZE,
  2147. .rf_size = RF_SIZE,
  2148. .lib = &rt61pci_rt2x00_ops,
  2149. .hw = &rt61pci_mac80211_ops,
  2150. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  2151. .debugfs = &rt61pci_rt2x00debug,
  2152. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  2153. };
  2154. /*
  2155. * RT61pci module information.
  2156. */
  2157. static struct pci_device_id rt61pci_device_table[] = {
  2158. /* RT2561s */
  2159. { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
  2160. /* RT2561 v2 */
  2161. { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
  2162. /* RT2661 */
  2163. { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
  2164. { 0, }
  2165. };
  2166. MODULE_AUTHOR(DRV_PROJECT);
  2167. MODULE_VERSION(DRV_VERSION);
  2168. MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
  2169. MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
  2170. "PCI & PCMCIA chipset based cards");
  2171. MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
  2172. MODULE_FIRMWARE(FIRMWARE_RT2561);
  2173. MODULE_FIRMWARE(FIRMWARE_RT2561s);
  2174. MODULE_FIRMWARE(FIRMWARE_RT2661);
  2175. MODULE_LICENSE("GPL");
  2176. static struct pci_driver rt61pci_driver = {
  2177. .name = KBUILD_MODNAME,
  2178. .id_table = rt61pci_device_table,
  2179. .probe = rt2x00pci_probe,
  2180. .remove = __devexit_p(rt2x00pci_remove),
  2181. .suspend = rt2x00pci_suspend,
  2182. .resume = rt2x00pci_resume,
  2183. };
  2184. static int __init rt61pci_init(void)
  2185. {
  2186. return pci_register_driver(&rt61pci_driver);
  2187. }
  2188. static void __exit rt61pci_exit(void)
  2189. {
  2190. pci_unregister_driver(&rt61pci_driver);
  2191. }
  2192. module_init(rt61pci_init);
  2193. module_exit(rt61pci_exit);