rt2500pci.c 58 KB

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  1. /*
  2. Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2500pci
  19. Abstract: rt2500pci device specific routines.
  20. Supported chipsets: RT2560.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/eeprom_93cx6.h>
  29. #include "rt2x00.h"
  30. #include "rt2x00pci.h"
  31. #include "rt2500pci.h"
  32. /*
  33. * Register access.
  34. * All access to the CSR registers will go through the methods
  35. * rt2x00pci_register_read and rt2x00pci_register_write.
  36. * BBP and RF register require indirect register access,
  37. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  38. * These indirect registers work with busy bits,
  39. * and we will try maximal REGISTER_BUSY_COUNT times to access
  40. * the register while taking a REGISTER_BUSY_DELAY us delay
  41. * between each attampt. When the busy bit is still set at that time,
  42. * the access attempt is considered to have failed,
  43. * and we will print an error.
  44. */
  45. static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  46. {
  47. u32 reg;
  48. unsigned int i;
  49. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  50. rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  51. if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  52. break;
  53. udelay(REGISTER_BUSY_DELAY);
  54. }
  55. return reg;
  56. }
  57. static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58. const unsigned int word, const u8 value)
  59. {
  60. u32 reg;
  61. /*
  62. * Wait until the BBP becomes ready.
  63. */
  64. reg = rt2500pci_bbp_check(rt2x00dev);
  65. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  66. ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  67. return;
  68. }
  69. /*
  70. * Write the data into the BBP.
  71. */
  72. reg = 0;
  73. rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  74. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  75. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  76. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  77. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  78. }
  79. static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  80. const unsigned int word, u8 *value)
  81. {
  82. u32 reg;
  83. /*
  84. * Wait until the BBP becomes ready.
  85. */
  86. reg = rt2500pci_bbp_check(rt2x00dev);
  87. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  88. ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
  89. return;
  90. }
  91. /*
  92. * Write the request into the BBP.
  93. */
  94. reg = 0;
  95. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  96. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  97. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  98. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  99. /*
  100. * Wait until the BBP becomes ready.
  101. */
  102. reg = rt2500pci_bbp_check(rt2x00dev);
  103. if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  104. ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
  105. *value = 0xff;
  106. return;
  107. }
  108. *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  109. }
  110. static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
  111. const unsigned int word, const u32 value)
  112. {
  113. u32 reg;
  114. unsigned int i;
  115. if (!word)
  116. return;
  117. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  118. rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
  119. if (!rt2x00_get_field32(reg, RFCSR_BUSY))
  120. goto rf_write;
  121. udelay(REGISTER_BUSY_DELAY);
  122. }
  123. ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
  124. return;
  125. rf_write:
  126. reg = 0;
  127. rt2x00_set_field32(&reg, RFCSR_VALUE, value);
  128. rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
  129. rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
  130. rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
  131. rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
  132. rt2x00_rf_write(rt2x00dev, word, value);
  133. }
  134. static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  135. {
  136. struct rt2x00_dev *rt2x00dev = eeprom->data;
  137. u32 reg;
  138. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  139. eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
  140. eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
  141. eeprom->reg_data_clock =
  142. !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
  143. eeprom->reg_chip_select =
  144. !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
  145. }
  146. static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  147. {
  148. struct rt2x00_dev *rt2x00dev = eeprom->data;
  149. u32 reg = 0;
  150. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
  151. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
  152. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
  153. !!eeprom->reg_data_clock);
  154. rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
  155. !!eeprom->reg_chip_select);
  156. rt2x00pci_register_write(rt2x00dev, CSR21, reg);
  157. }
  158. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  159. #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
  160. static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
  161. const unsigned int word, u32 *data)
  162. {
  163. rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
  164. }
  165. static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
  166. const unsigned int word, u32 data)
  167. {
  168. rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
  169. }
  170. static const struct rt2x00debug rt2500pci_rt2x00debug = {
  171. .owner = THIS_MODULE,
  172. .csr = {
  173. .read = rt2500pci_read_csr,
  174. .write = rt2500pci_write_csr,
  175. .word_size = sizeof(u32),
  176. .word_count = CSR_REG_SIZE / sizeof(u32),
  177. },
  178. .eeprom = {
  179. .read = rt2x00_eeprom_read,
  180. .write = rt2x00_eeprom_write,
  181. .word_size = sizeof(u16),
  182. .word_count = EEPROM_SIZE / sizeof(u16),
  183. },
  184. .bbp = {
  185. .read = rt2500pci_bbp_read,
  186. .write = rt2500pci_bbp_write,
  187. .word_size = sizeof(u8),
  188. .word_count = BBP_SIZE / sizeof(u8),
  189. },
  190. .rf = {
  191. .read = rt2x00_rf_read,
  192. .write = rt2500pci_rf_write,
  193. .word_size = sizeof(u32),
  194. .word_count = RF_SIZE / sizeof(u32),
  195. },
  196. };
  197. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  198. #ifdef CONFIG_RT2500PCI_RFKILL
  199. static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  200. {
  201. u32 reg;
  202. rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
  203. return rt2x00_get_field32(reg, GPIOCSR_BIT0);
  204. }
  205. #else
  206. #define rt2500pci_rfkill_poll NULL
  207. #endif /* CONFIG_RT2500PCI_RFKILL */
  208. /*
  209. * Configuration handlers.
  210. */
  211. static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
  212. __le32 *mac)
  213. {
  214. rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
  215. (2 * sizeof(__le32)));
  216. }
  217. static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
  218. __le32 *bssid)
  219. {
  220. rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
  221. (2 * sizeof(__le32)));
  222. }
  223. static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
  224. const int tsf_sync)
  225. {
  226. u32 reg;
  227. rt2x00pci_register_write(rt2x00dev, CSR14, 0);
  228. /*
  229. * Enable beacon config
  230. */
  231. rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
  232. rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
  233. PREAMBLE + get_duration(IEEE80211_HEADER, 20));
  234. rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
  235. rt2x00lib_get_ring(rt2x00dev,
  236. IEEE80211_TX_QUEUE_BEACON)
  237. ->tx_params.cw_min);
  238. rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
  239. /*
  240. * Enable synchronisation.
  241. */
  242. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  243. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  244. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  245. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  246. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
  247. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  248. }
  249. static void rt2500pci_config_preamble(struct rt2x00_dev *rt2x00dev,
  250. const int short_preamble,
  251. const int ack_timeout,
  252. const int ack_consume_time)
  253. {
  254. int preamble_mask;
  255. u32 reg;
  256. /*
  257. * When short preamble is enabled, we should set bit 0x08
  258. */
  259. preamble_mask = short_preamble << 3;
  260. rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
  261. rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
  262. rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
  263. rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
  264. rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
  265. rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
  266. rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
  267. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
  268. rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
  269. rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
  270. rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
  271. rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
  272. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
  273. rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
  274. rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
  275. rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
  276. rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
  277. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
  278. rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
  279. rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
  280. rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
  281. rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
  282. rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
  283. rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
  284. }
  285. static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
  286. const int basic_rate_mask)
  287. {
  288. rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
  289. }
  290. static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
  291. struct rf_channel *rf, const int txpower)
  292. {
  293. u8 r70;
  294. /*
  295. * Set TXpower.
  296. */
  297. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  298. /*
  299. * Switch on tuning bits.
  300. * For RT2523 devices we do not need to update the R1 register.
  301. */
  302. if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
  303. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
  304. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
  305. /*
  306. * For RT2525 we should first set the channel to half band higher.
  307. */
  308. if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
  309. static const u32 vals[] = {
  310. 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
  311. 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
  312. 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
  313. 0x00080d2e, 0x00080d3a
  314. };
  315. rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
  316. rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
  317. rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
  318. if (rf->rf4)
  319. rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
  320. }
  321. rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
  322. rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
  323. rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
  324. if (rf->rf4)
  325. rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
  326. /*
  327. * Channel 14 requires the Japan filter bit to be set.
  328. */
  329. r70 = 0x46;
  330. rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
  331. rt2500pci_bbp_write(rt2x00dev, 70, r70);
  332. msleep(1);
  333. /*
  334. * Switch off tuning bits.
  335. * For RT2523 devices we do not need to update the R1 register.
  336. */
  337. if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
  338. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
  339. rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
  340. }
  341. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
  342. rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
  343. /*
  344. * Clear false CRC during channel switch.
  345. */
  346. rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
  347. }
  348. static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  349. const int txpower)
  350. {
  351. u32 rf3;
  352. rt2x00_rf_read(rt2x00dev, 3, &rf3);
  353. rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  354. rt2500pci_rf_write(rt2x00dev, 3, rf3);
  355. }
  356. static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
  357. struct antenna_setup *ant)
  358. {
  359. u32 reg;
  360. u8 r14;
  361. u8 r2;
  362. rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
  363. rt2500pci_bbp_read(rt2x00dev, 14, &r14);
  364. rt2500pci_bbp_read(rt2x00dev, 2, &r2);
  365. /*
  366. * Configure the TX antenna.
  367. */
  368. switch (ant->tx) {
  369. case ANTENNA_A:
  370. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
  371. rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
  372. rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
  373. break;
  374. case ANTENNA_HW_DIVERSITY:
  375. case ANTENNA_SW_DIVERSITY:
  376. /*
  377. * NOTE: We should never come here because rt2x00lib is
  378. * supposed to catch this and send us the correct antenna
  379. * explicitely. However we are nog going to bug about this.
  380. * Instead, just default to antenna B.
  381. */
  382. case ANTENNA_B:
  383. rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
  384. rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
  385. rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
  386. break;
  387. }
  388. /*
  389. * Configure the RX antenna.
  390. */
  391. switch (ant->rx) {
  392. case ANTENNA_A:
  393. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
  394. break;
  395. case ANTENNA_HW_DIVERSITY:
  396. case ANTENNA_SW_DIVERSITY:
  397. /*
  398. * NOTE: We should never come here because rt2x00lib is
  399. * supposed to catch this and send us the correct antenna
  400. * explicitely. However we are nog going to bug about this.
  401. * Instead, just default to antenna B.
  402. */
  403. case ANTENNA_B:
  404. rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
  405. break;
  406. }
  407. /*
  408. * RT2525E and RT5222 need to flip TX I/Q
  409. */
  410. if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
  411. rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  412. rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
  413. rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
  414. rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
  415. /*
  416. * RT2525E does not need RX I/Q Flip.
  417. */
  418. if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
  419. rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
  420. } else {
  421. rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
  422. rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
  423. }
  424. rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
  425. rt2500pci_bbp_write(rt2x00dev, 14, r14);
  426. rt2500pci_bbp_write(rt2x00dev, 2, r2);
  427. }
  428. static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
  429. struct rt2x00lib_conf *libconf)
  430. {
  431. u32 reg;
  432. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  433. rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
  434. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  435. rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
  436. rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
  437. rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
  438. rt2x00pci_register_write(rt2x00dev, CSR18, reg);
  439. rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
  440. rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
  441. rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
  442. rt2x00pci_register_write(rt2x00dev, CSR19, reg);
  443. rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
  444. rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
  445. rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
  446. rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
  447. rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
  448. rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
  449. libconf->conf->beacon_int * 16);
  450. rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
  451. libconf->conf->beacon_int * 16);
  452. rt2x00pci_register_write(rt2x00dev, CSR12, reg);
  453. }
  454. static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
  455. const unsigned int flags,
  456. struct rt2x00lib_conf *libconf)
  457. {
  458. if (flags & CONFIG_UPDATE_PHYMODE)
  459. rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
  460. if (flags & CONFIG_UPDATE_CHANNEL)
  461. rt2500pci_config_channel(rt2x00dev, &libconf->rf,
  462. libconf->conf->power_level);
  463. if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
  464. rt2500pci_config_txpower(rt2x00dev,
  465. libconf->conf->power_level);
  466. if (flags & CONFIG_UPDATE_ANTENNA)
  467. rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
  468. if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
  469. rt2500pci_config_duration(rt2x00dev, libconf);
  470. }
  471. /*
  472. * LED functions.
  473. */
  474. static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
  475. {
  476. u32 reg;
  477. rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
  478. rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
  479. rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
  480. rt2x00_set_field32(&reg, LEDCSR_LINK,
  481. (rt2x00dev->led_mode != LED_MODE_ASUS));
  482. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
  483. (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
  484. rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
  485. }
  486. static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
  487. {
  488. u32 reg;
  489. rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
  490. rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
  491. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
  492. rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
  493. }
  494. /*
  495. * Link tuning
  496. */
  497. static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
  498. struct link_qual *qual)
  499. {
  500. u32 reg;
  501. /*
  502. * Update FCS error count from register.
  503. */
  504. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  505. qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
  506. /*
  507. * Update False CCA count from register.
  508. */
  509. rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
  510. qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
  511. }
  512. static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
  513. {
  514. rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
  515. rt2x00dev->link.vgc_level = 0x48;
  516. }
  517. static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
  518. {
  519. int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
  520. u8 r17;
  521. /*
  522. * To prevent collisions with MAC ASIC on chipsets
  523. * up to version C the link tuning should halt after 20
  524. * seconds.
  525. */
  526. if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
  527. rt2x00dev->link.count > 20)
  528. return;
  529. rt2500pci_bbp_read(rt2x00dev, 17, &r17);
  530. /*
  531. * Chipset versions C and lower should directly continue
  532. * to the dynamic CCA tuning.
  533. */
  534. if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
  535. goto dynamic_cca_tune;
  536. /*
  537. * A too low RSSI will cause too much false CCA which will
  538. * then corrupt the R17 tuning. To remidy this the tuning should
  539. * be stopped (While making sure the R17 value will not exceed limits)
  540. */
  541. if (rssi < -80 && rt2x00dev->link.count > 20) {
  542. if (r17 >= 0x41) {
  543. r17 = rt2x00dev->link.vgc_level;
  544. rt2500pci_bbp_write(rt2x00dev, 17, r17);
  545. }
  546. return;
  547. }
  548. /*
  549. * Special big-R17 for short distance
  550. */
  551. if (rssi >= -58) {
  552. if (r17 != 0x50)
  553. rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
  554. return;
  555. }
  556. /*
  557. * Special mid-R17 for middle distance
  558. */
  559. if (rssi >= -74) {
  560. if (r17 != 0x41)
  561. rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
  562. return;
  563. }
  564. /*
  565. * Leave short or middle distance condition, restore r17
  566. * to the dynamic tuning range.
  567. */
  568. if (r17 >= 0x41) {
  569. rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
  570. return;
  571. }
  572. dynamic_cca_tune:
  573. /*
  574. * R17 is inside the dynamic tuning range,
  575. * start tuning the link based on the false cca counter.
  576. */
  577. if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
  578. rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
  579. rt2x00dev->link.vgc_level = r17;
  580. } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
  581. rt2500pci_bbp_write(rt2x00dev, 17, --r17);
  582. rt2x00dev->link.vgc_level = r17;
  583. }
  584. }
  585. /*
  586. * Initialization functions.
  587. */
  588. static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
  589. {
  590. struct data_ring *ring = rt2x00dev->rx;
  591. __le32 *rxd;
  592. unsigned int i;
  593. u32 word;
  594. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  595. for (i = 0; i < ring->stats.limit; i++) {
  596. rxd = ring->entry[i].priv;
  597. rt2x00_desc_read(rxd, 1, &word);
  598. rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
  599. ring->entry[i].data_dma);
  600. rt2x00_desc_write(rxd, 1, word);
  601. rt2x00_desc_read(rxd, 0, &word);
  602. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  603. rt2x00_desc_write(rxd, 0, word);
  604. }
  605. rt2x00_ring_index_clear(rt2x00dev->rx);
  606. }
  607. static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
  608. {
  609. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  610. __le32 *txd;
  611. unsigned int i;
  612. u32 word;
  613. memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
  614. for (i = 0; i < ring->stats.limit; i++) {
  615. txd = ring->entry[i].priv;
  616. rt2x00_desc_read(txd, 1, &word);
  617. rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
  618. ring->entry[i].data_dma);
  619. rt2x00_desc_write(txd, 1, word);
  620. rt2x00_desc_read(txd, 0, &word);
  621. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  622. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  623. rt2x00_desc_write(txd, 0, word);
  624. }
  625. rt2x00_ring_index_clear(ring);
  626. }
  627. static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
  628. {
  629. u32 reg;
  630. /*
  631. * Initialize rings.
  632. */
  633. rt2500pci_init_rxring(rt2x00dev);
  634. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  635. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  636. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
  637. rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
  638. /*
  639. * Initialize registers.
  640. */
  641. rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
  642. rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
  643. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
  644. rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
  645. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
  646. rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
  647. rt2x00dev->bcn[1].stats.limit);
  648. rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
  649. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
  650. rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
  651. rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
  652. rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
  653. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
  654. rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
  655. rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
  656. rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
  657. rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
  658. rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
  659. rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
  660. rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
  661. rt2x00dev->bcn[1].data_dma);
  662. rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
  663. rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
  664. rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
  665. rt2x00dev->bcn[0].data_dma);
  666. rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
  667. rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
  668. rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
  669. rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
  670. rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
  671. rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
  672. rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
  673. rt2x00dev->rx->data_dma);
  674. rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
  675. return 0;
  676. }
  677. static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
  678. {
  679. u32 reg;
  680. rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
  681. rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
  682. rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
  683. rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
  684. rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
  685. rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
  686. rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
  687. rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
  688. rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
  689. rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
  690. rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
  691. rt2x00dev->rx->data_size / 128);
  692. rt2x00pci_register_write(rt2x00dev, CSR9, reg);
  693. /*
  694. * Always use CWmin and CWmax set in descriptor.
  695. */
  696. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  697. rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
  698. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  699. rt2x00pci_register_write(rt2x00dev, CNT3, 0);
  700. rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
  701. rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
  702. rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
  703. rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
  704. rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
  705. rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
  706. rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
  707. rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
  708. rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
  709. rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
  710. rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
  711. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
  712. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
  713. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
  714. rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
  715. rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
  716. rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
  717. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
  718. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
  719. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
  720. rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
  721. rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
  722. rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
  723. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
  724. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
  725. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
  726. rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
  727. rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
  728. rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
  729. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
  730. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
  731. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
  732. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
  733. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
  734. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
  735. rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
  736. rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
  737. rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
  738. rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
  739. rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
  740. rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
  741. rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
  742. rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
  743. rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
  744. rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
  745. rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
  746. rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
  747. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
  748. rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
  749. rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
  750. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  751. return -EBUSY;
  752. rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
  753. rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
  754. rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
  755. rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
  756. rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
  757. rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
  758. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
  759. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
  760. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
  761. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
  762. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
  763. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
  764. rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
  765. rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
  766. rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
  767. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  768. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
  769. rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
  770. rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
  771. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  772. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  773. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
  774. rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
  775. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  776. /*
  777. * We must clear the FCS and FIFO error count.
  778. * These registers are cleared on read,
  779. * so we may pass a useless variable to store the value.
  780. */
  781. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  782. rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
  783. return 0;
  784. }
  785. static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  786. {
  787. unsigned int i;
  788. u16 eeprom;
  789. u8 reg_id;
  790. u8 value;
  791. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  792. rt2500pci_bbp_read(rt2x00dev, 0, &value);
  793. if ((value != 0xff) && (value != 0x00))
  794. goto continue_csr_init;
  795. NOTICE(rt2x00dev, "Waiting for BBP register.\n");
  796. udelay(REGISTER_BUSY_DELAY);
  797. }
  798. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  799. return -EACCES;
  800. continue_csr_init:
  801. rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
  802. rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
  803. rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
  804. rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
  805. rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
  806. rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
  807. rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
  808. rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
  809. rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
  810. rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
  811. rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
  812. rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
  813. rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
  814. rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
  815. rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
  816. rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
  817. rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
  818. rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
  819. rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
  820. rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
  821. rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
  822. rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
  823. rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
  824. rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
  825. rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
  826. rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
  827. rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
  828. rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
  829. rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
  830. rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
  831. DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
  832. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  833. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  834. if (eeprom != 0xffff && eeprom != 0x0000) {
  835. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  836. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  837. DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
  838. reg_id, value);
  839. rt2500pci_bbp_write(rt2x00dev, reg_id, value);
  840. }
  841. }
  842. DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
  843. return 0;
  844. }
  845. /*
  846. * Device state switch handlers.
  847. */
  848. static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  849. enum dev_state state)
  850. {
  851. u32 reg;
  852. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  853. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
  854. state == STATE_RADIO_RX_OFF);
  855. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  856. }
  857. static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  858. enum dev_state state)
  859. {
  860. int mask = (state == STATE_RADIO_IRQ_OFF);
  861. u32 reg;
  862. /*
  863. * When interrupts are being enabled, the interrupt registers
  864. * should clear the register to assure a clean state.
  865. */
  866. if (state == STATE_RADIO_IRQ_ON) {
  867. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  868. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  869. }
  870. /*
  871. * Only toggle the interrupts bits we are going to use.
  872. * Non-checked interrupt bits are disabled by default.
  873. */
  874. rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
  875. rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
  876. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
  877. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
  878. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
  879. rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
  880. rt2x00pci_register_write(rt2x00dev, CSR8, reg);
  881. }
  882. static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  883. {
  884. /*
  885. * Initialize all registers.
  886. */
  887. if (rt2500pci_init_rings(rt2x00dev) ||
  888. rt2500pci_init_registers(rt2x00dev) ||
  889. rt2500pci_init_bbp(rt2x00dev)) {
  890. ERROR(rt2x00dev, "Register initialization failed.\n");
  891. return -EIO;
  892. }
  893. /*
  894. * Enable interrupts.
  895. */
  896. rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
  897. /*
  898. * Enable LED
  899. */
  900. rt2500pci_enable_led(rt2x00dev);
  901. return 0;
  902. }
  903. static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  904. {
  905. u32 reg;
  906. /*
  907. * Disable LED
  908. */
  909. rt2500pci_disable_led(rt2x00dev);
  910. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
  911. /*
  912. * Disable synchronisation.
  913. */
  914. rt2x00pci_register_write(rt2x00dev, CSR14, 0);
  915. /*
  916. * Cancel RX and TX.
  917. */
  918. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  919. rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
  920. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  921. /*
  922. * Disable interrupts.
  923. */
  924. rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
  925. }
  926. static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
  927. enum dev_state state)
  928. {
  929. u32 reg;
  930. unsigned int i;
  931. char put_to_sleep;
  932. char bbp_state;
  933. char rf_state;
  934. put_to_sleep = (state != STATE_AWAKE);
  935. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
  936. rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
  937. rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
  938. rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
  939. rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
  940. rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
  941. /*
  942. * Device is not guaranteed to be in the requested state yet.
  943. * We must wait until the register indicates that the
  944. * device has entered the correct state.
  945. */
  946. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  947. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
  948. bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
  949. rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
  950. if (bbp_state == state && rf_state == state)
  951. return 0;
  952. msleep(10);
  953. }
  954. NOTICE(rt2x00dev, "Device failed to enter state %d, "
  955. "current device state: bbp %d and rf %d.\n",
  956. state, bbp_state, rf_state);
  957. return -EBUSY;
  958. }
  959. static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  960. enum dev_state state)
  961. {
  962. int retval = 0;
  963. switch (state) {
  964. case STATE_RADIO_ON:
  965. retval = rt2500pci_enable_radio(rt2x00dev);
  966. break;
  967. case STATE_RADIO_OFF:
  968. rt2500pci_disable_radio(rt2x00dev);
  969. break;
  970. case STATE_RADIO_RX_ON:
  971. case STATE_RADIO_RX_OFF:
  972. rt2500pci_toggle_rx(rt2x00dev, state);
  973. break;
  974. case STATE_DEEP_SLEEP:
  975. case STATE_SLEEP:
  976. case STATE_STANDBY:
  977. case STATE_AWAKE:
  978. retval = rt2500pci_set_state(rt2x00dev, state);
  979. break;
  980. default:
  981. retval = -ENOTSUPP;
  982. break;
  983. }
  984. return retval;
  985. }
  986. /*
  987. * TX descriptor initialization
  988. */
  989. static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  990. __le32 *txd,
  991. struct txdata_entry_desc *desc,
  992. struct ieee80211_hdr *ieee80211hdr,
  993. unsigned int length,
  994. struct ieee80211_tx_control *control)
  995. {
  996. u32 word;
  997. /*
  998. * Start writing the descriptor words.
  999. */
  1000. rt2x00_desc_read(txd, 2, &word);
  1001. rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
  1002. rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
  1003. rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
  1004. rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
  1005. rt2x00_desc_write(txd, 2, word);
  1006. rt2x00_desc_read(txd, 3, &word);
  1007. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
  1008. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
  1009. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
  1010. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
  1011. rt2x00_desc_write(txd, 3, word);
  1012. rt2x00_desc_read(txd, 10, &word);
  1013. rt2x00_set_field32(&word, TXD_W10_RTS,
  1014. test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
  1015. rt2x00_desc_write(txd, 10, word);
  1016. rt2x00_desc_read(txd, 0, &word);
  1017. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1018. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1019. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1020. test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
  1021. rt2x00_set_field32(&word, TXD_W0_ACK,
  1022. test_bit(ENTRY_TXD_ACK, &desc->flags));
  1023. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1024. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
  1025. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1026. test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
  1027. rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
  1028. rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
  1029. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1030. !!(control->flags &
  1031. IEEE80211_TXCTL_LONG_RETRY_LIMIT));
  1032. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
  1033. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
  1034. rt2x00_desc_write(txd, 0, word);
  1035. }
  1036. /*
  1037. * TX data initialization
  1038. */
  1039. static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1040. unsigned int queue)
  1041. {
  1042. u32 reg;
  1043. if (queue == IEEE80211_TX_QUEUE_BEACON) {
  1044. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  1045. if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
  1046. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  1047. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  1048. }
  1049. return;
  1050. }
  1051. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  1052. rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
  1053. (queue == IEEE80211_TX_QUEUE_DATA0));
  1054. rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
  1055. (queue == IEEE80211_TX_QUEUE_DATA1));
  1056. rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
  1057. (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
  1058. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  1059. }
  1060. /*
  1061. * RX control handlers
  1062. */
  1063. static void rt2500pci_fill_rxdone(struct data_entry *entry,
  1064. struct rxdata_entry_desc *desc)
  1065. {
  1066. __le32 *rxd = entry->priv;
  1067. u32 word0;
  1068. u32 word2;
  1069. rt2x00_desc_read(rxd, 0, &word0);
  1070. rt2x00_desc_read(rxd, 2, &word2);
  1071. desc->flags = 0;
  1072. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1073. desc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1074. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  1075. desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  1076. desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
  1077. desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
  1078. entry->ring->rt2x00dev->rssi_offset;
  1079. desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
  1080. desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1081. }
  1082. /*
  1083. * Interrupt functions.
  1084. */
  1085. static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
  1086. {
  1087. struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
  1088. struct data_entry *entry;
  1089. __le32 *txd;
  1090. u32 word;
  1091. int tx_status;
  1092. int retry;
  1093. while (!rt2x00_ring_empty(ring)) {
  1094. entry = rt2x00_get_data_entry_done(ring);
  1095. txd = entry->priv;
  1096. rt2x00_desc_read(txd, 0, &word);
  1097. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1098. !rt2x00_get_field32(word, TXD_W0_VALID))
  1099. break;
  1100. /*
  1101. * Obtain the status about this packet.
  1102. */
  1103. tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
  1104. retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
  1105. rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
  1106. }
  1107. }
  1108. static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
  1109. {
  1110. struct rt2x00_dev *rt2x00dev = dev_instance;
  1111. u32 reg;
  1112. /*
  1113. * Get the interrupt sources & saved to local variable.
  1114. * Write register value back to clear pending interrupts.
  1115. */
  1116. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  1117. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  1118. if (!reg)
  1119. return IRQ_NONE;
  1120. if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
  1121. return IRQ_HANDLED;
  1122. /*
  1123. * Handle interrupts, walk through all bits
  1124. * and run the tasks, the bits are checked in order of
  1125. * priority.
  1126. */
  1127. /*
  1128. * 1 - Beacon timer expired interrupt.
  1129. */
  1130. if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
  1131. rt2x00lib_beacondone(rt2x00dev);
  1132. /*
  1133. * 2 - Rx ring done interrupt.
  1134. */
  1135. if (rt2x00_get_field32(reg, CSR7_RXDONE))
  1136. rt2x00pci_rxdone(rt2x00dev);
  1137. /*
  1138. * 3 - Atim ring transmit done interrupt.
  1139. */
  1140. if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
  1141. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
  1142. /*
  1143. * 4 - Priority ring transmit done interrupt.
  1144. */
  1145. if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
  1146. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
  1147. /*
  1148. * 5 - Tx ring transmit done interrupt.
  1149. */
  1150. if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
  1151. rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
  1152. return IRQ_HANDLED;
  1153. }
  1154. /*
  1155. * Device probe functions.
  1156. */
  1157. static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1158. {
  1159. struct eeprom_93cx6 eeprom;
  1160. u32 reg;
  1161. u16 word;
  1162. u8 *mac;
  1163. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  1164. eeprom.data = rt2x00dev;
  1165. eeprom.register_read = rt2500pci_eepromregister_read;
  1166. eeprom.register_write = rt2500pci_eepromregister_write;
  1167. eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
  1168. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1169. eeprom.reg_data_in = 0;
  1170. eeprom.reg_data_out = 0;
  1171. eeprom.reg_data_clock = 0;
  1172. eeprom.reg_chip_select = 0;
  1173. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1174. EEPROM_SIZE / sizeof(u16));
  1175. /*
  1176. * Start validation of the data that has been read.
  1177. */
  1178. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1179. if (!is_valid_ether_addr(mac)) {
  1180. DECLARE_MAC_BUF(macbuf);
  1181. random_ether_addr(mac);
  1182. EEPROM(rt2x00dev, "MAC: %s\n",
  1183. print_mac(macbuf, mac));
  1184. }
  1185. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1186. if (word == 0xffff) {
  1187. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1188. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1189. ANTENNA_SW_DIVERSITY);
  1190. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1191. ANTENNA_SW_DIVERSITY);
  1192. rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
  1193. LED_MODE_DEFAULT);
  1194. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1195. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1196. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
  1197. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1198. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1199. }
  1200. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1201. if (word == 0xffff) {
  1202. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1203. rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
  1204. rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
  1205. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1206. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1207. }
  1208. rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
  1209. if (word == 0xffff) {
  1210. rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
  1211. DEFAULT_RSSI_OFFSET);
  1212. rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
  1213. EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
  1214. }
  1215. return 0;
  1216. }
  1217. static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1218. {
  1219. u32 reg;
  1220. u16 value;
  1221. u16 eeprom;
  1222. /*
  1223. * Read EEPROM word for configuration.
  1224. */
  1225. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1226. /*
  1227. * Identify RF chipset.
  1228. */
  1229. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1230. rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
  1231. rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
  1232. if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
  1233. !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
  1234. !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
  1235. !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
  1236. !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
  1237. !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  1238. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1239. return -ENODEV;
  1240. }
  1241. /*
  1242. * Identify default antenna configuration.
  1243. */
  1244. rt2x00dev->default_ant.tx =
  1245. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1246. rt2x00dev->default_ant.rx =
  1247. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1248. /*
  1249. * Store led mode, for correct led behaviour.
  1250. */
  1251. rt2x00dev->led_mode =
  1252. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1253. /*
  1254. * Detect if this device has an hardware controlled radio.
  1255. */
  1256. #ifdef CONFIG_RT2500PCI_RFKILL
  1257. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1258. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1259. #endif /* CONFIG_RT2500PCI_RFKILL */
  1260. /*
  1261. * Check if the BBP tuning should be enabled.
  1262. */
  1263. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1264. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
  1265. __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
  1266. /*
  1267. * Read the RSSI <-> dBm offset information.
  1268. */
  1269. rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
  1270. rt2x00dev->rssi_offset =
  1271. rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
  1272. return 0;
  1273. }
  1274. /*
  1275. * RF value list for RF2522
  1276. * Supports: 2.4 GHz
  1277. */
  1278. static const struct rf_channel rf_vals_bg_2522[] = {
  1279. { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
  1280. { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
  1281. { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
  1282. { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
  1283. { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
  1284. { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
  1285. { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
  1286. { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
  1287. { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
  1288. { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
  1289. { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
  1290. { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
  1291. { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
  1292. { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
  1293. };
  1294. /*
  1295. * RF value list for RF2523
  1296. * Supports: 2.4 GHz
  1297. */
  1298. static const struct rf_channel rf_vals_bg_2523[] = {
  1299. { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
  1300. { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
  1301. { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
  1302. { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
  1303. { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
  1304. { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
  1305. { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
  1306. { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
  1307. { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
  1308. { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
  1309. { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
  1310. { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
  1311. { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
  1312. { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
  1313. };
  1314. /*
  1315. * RF value list for RF2524
  1316. * Supports: 2.4 GHz
  1317. */
  1318. static const struct rf_channel rf_vals_bg_2524[] = {
  1319. { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
  1320. { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
  1321. { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
  1322. { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
  1323. { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
  1324. { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
  1325. { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
  1326. { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
  1327. { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
  1328. { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
  1329. { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
  1330. { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
  1331. { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
  1332. { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
  1333. };
  1334. /*
  1335. * RF value list for RF2525
  1336. * Supports: 2.4 GHz
  1337. */
  1338. static const struct rf_channel rf_vals_bg_2525[] = {
  1339. { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
  1340. { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
  1341. { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
  1342. { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
  1343. { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
  1344. { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
  1345. { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
  1346. { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
  1347. { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
  1348. { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
  1349. { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
  1350. { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
  1351. { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
  1352. { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
  1353. };
  1354. /*
  1355. * RF value list for RF2525e
  1356. * Supports: 2.4 GHz
  1357. */
  1358. static const struct rf_channel rf_vals_bg_2525e[] = {
  1359. { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
  1360. { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
  1361. { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
  1362. { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
  1363. { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
  1364. { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
  1365. { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
  1366. { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
  1367. { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
  1368. { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
  1369. { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
  1370. { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
  1371. { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
  1372. { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
  1373. };
  1374. /*
  1375. * RF value list for RF5222
  1376. * Supports: 2.4 GHz & 5.2 GHz
  1377. */
  1378. static const struct rf_channel rf_vals_5222[] = {
  1379. { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
  1380. { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
  1381. { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
  1382. { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
  1383. { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
  1384. { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
  1385. { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
  1386. { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
  1387. { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
  1388. { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
  1389. { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
  1390. { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
  1391. { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
  1392. { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
  1393. /* 802.11 UNI / HyperLan 2 */
  1394. { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
  1395. { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
  1396. { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
  1397. { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
  1398. { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
  1399. { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
  1400. { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
  1401. { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
  1402. /* 802.11 HyperLan 2 */
  1403. { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
  1404. { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
  1405. { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
  1406. { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
  1407. { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
  1408. { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
  1409. { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
  1410. { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
  1411. { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
  1412. { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
  1413. /* 802.11 UNII */
  1414. { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
  1415. { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
  1416. { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
  1417. { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
  1418. { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
  1419. };
  1420. static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1421. {
  1422. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1423. u8 *txpower;
  1424. unsigned int i;
  1425. /*
  1426. * Initialize all hw fields.
  1427. */
  1428. rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
  1429. rt2x00dev->hw->extra_tx_headroom = 0;
  1430. rt2x00dev->hw->max_signal = MAX_SIGNAL;
  1431. rt2x00dev->hw->max_rssi = MAX_RX_SSI;
  1432. rt2x00dev->hw->queues = 2;
  1433. SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
  1434. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1435. rt2x00_eeprom_addr(rt2x00dev,
  1436. EEPROM_MAC_ADDR_0));
  1437. /*
  1438. * Convert tx_power array in eeprom.
  1439. */
  1440. txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1441. for (i = 0; i < 14; i++)
  1442. txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
  1443. /*
  1444. * Initialize hw_mode information.
  1445. */
  1446. spec->num_modes = 2;
  1447. spec->num_rates = 12;
  1448. spec->tx_power_a = NULL;
  1449. spec->tx_power_bg = txpower;
  1450. spec->tx_power_default = DEFAULT_TXPOWER;
  1451. if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
  1452. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
  1453. spec->channels = rf_vals_bg_2522;
  1454. } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
  1455. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
  1456. spec->channels = rf_vals_bg_2523;
  1457. } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
  1458. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
  1459. spec->channels = rf_vals_bg_2524;
  1460. } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
  1461. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
  1462. spec->channels = rf_vals_bg_2525;
  1463. } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
  1464. spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
  1465. spec->channels = rf_vals_bg_2525e;
  1466. } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
  1467. spec->num_channels = ARRAY_SIZE(rf_vals_5222);
  1468. spec->channels = rf_vals_5222;
  1469. spec->num_modes = 3;
  1470. }
  1471. }
  1472. static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1473. {
  1474. int retval;
  1475. /*
  1476. * Allocate eeprom data.
  1477. */
  1478. retval = rt2500pci_validate_eeprom(rt2x00dev);
  1479. if (retval)
  1480. return retval;
  1481. retval = rt2500pci_init_eeprom(rt2x00dev);
  1482. if (retval)
  1483. return retval;
  1484. /*
  1485. * Initialize hw specifications.
  1486. */
  1487. rt2500pci_probe_hw_mode(rt2x00dev);
  1488. /*
  1489. * This device requires the beacon ring
  1490. */
  1491. __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
  1492. /*
  1493. * Set the rssi offset.
  1494. */
  1495. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1496. return 0;
  1497. }
  1498. /*
  1499. * IEEE80211 stack callback functions.
  1500. */
  1501. static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
  1502. unsigned int changed_flags,
  1503. unsigned int *total_flags,
  1504. int mc_count,
  1505. struct dev_addr_list *mc_list)
  1506. {
  1507. struct rt2x00_dev *rt2x00dev = hw->priv;
  1508. struct interface *intf = &rt2x00dev->interface;
  1509. u32 reg;
  1510. /*
  1511. * Mask off any flags we are going to ignore from
  1512. * the total_flags field.
  1513. */
  1514. *total_flags &=
  1515. FIF_ALLMULTI |
  1516. FIF_FCSFAIL |
  1517. FIF_PLCPFAIL |
  1518. FIF_CONTROL |
  1519. FIF_OTHER_BSS |
  1520. FIF_PROMISC_IN_BSS;
  1521. /*
  1522. * Apply some rules to the filters:
  1523. * - Some filters imply different filters to be set.
  1524. * - Some things we can't filter out at all.
  1525. * - Some filters are set based on interface type.
  1526. */
  1527. if (mc_count)
  1528. *total_flags |= FIF_ALLMULTI;
  1529. if (*total_flags & FIF_OTHER_BSS ||
  1530. *total_flags & FIF_PROMISC_IN_BSS)
  1531. *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
  1532. if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
  1533. *total_flags |= FIF_PROMISC_IN_BSS;
  1534. /*
  1535. * Check if there is any work left for us.
  1536. */
  1537. if (intf->filter == *total_flags)
  1538. return;
  1539. intf->filter = *total_flags;
  1540. /*
  1541. * Start configuration steps.
  1542. * Note that the version error will always be dropped
  1543. * and broadcast frames will always be accepted since
  1544. * there is no filter for it at this time.
  1545. */
  1546. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  1547. rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
  1548. !(*total_flags & FIF_FCSFAIL));
  1549. rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
  1550. !(*total_flags & FIF_PLCPFAIL));
  1551. rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
  1552. !(*total_flags & FIF_CONTROL));
  1553. rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
  1554. !(*total_flags & FIF_PROMISC_IN_BSS));
  1555. rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
  1556. !(*total_flags & FIF_PROMISC_IN_BSS));
  1557. rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
  1558. rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
  1559. !(*total_flags & FIF_ALLMULTI));
  1560. rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
  1561. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  1562. }
  1563. static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
  1564. u32 short_retry, u32 long_retry)
  1565. {
  1566. struct rt2x00_dev *rt2x00dev = hw->priv;
  1567. u32 reg;
  1568. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  1569. rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
  1570. rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
  1571. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  1572. return 0;
  1573. }
  1574. static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
  1575. {
  1576. struct rt2x00_dev *rt2x00dev = hw->priv;
  1577. u64 tsf;
  1578. u32 reg;
  1579. rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
  1580. tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
  1581. rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
  1582. tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
  1583. return tsf;
  1584. }
  1585. static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
  1586. {
  1587. struct rt2x00_dev *rt2x00dev = hw->priv;
  1588. rt2x00pci_register_write(rt2x00dev, CSR16, 0);
  1589. rt2x00pci_register_write(rt2x00dev, CSR17, 0);
  1590. }
  1591. static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
  1592. {
  1593. struct rt2x00_dev *rt2x00dev = hw->priv;
  1594. u32 reg;
  1595. rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
  1596. return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
  1597. }
  1598. static const struct ieee80211_ops rt2500pci_mac80211_ops = {
  1599. .tx = rt2x00mac_tx,
  1600. .start = rt2x00mac_start,
  1601. .stop = rt2x00mac_stop,
  1602. .add_interface = rt2x00mac_add_interface,
  1603. .remove_interface = rt2x00mac_remove_interface,
  1604. .config = rt2x00mac_config,
  1605. .config_interface = rt2x00mac_config_interface,
  1606. .configure_filter = rt2500pci_configure_filter,
  1607. .get_stats = rt2x00mac_get_stats,
  1608. .set_retry_limit = rt2500pci_set_retry_limit,
  1609. .erp_ie_changed = rt2x00mac_erp_ie_changed,
  1610. .conf_tx = rt2x00mac_conf_tx,
  1611. .get_tx_stats = rt2x00mac_get_tx_stats,
  1612. .get_tsf = rt2500pci_get_tsf,
  1613. .reset_tsf = rt2500pci_reset_tsf,
  1614. .beacon_update = rt2x00pci_beacon_update,
  1615. .tx_last_beacon = rt2500pci_tx_last_beacon,
  1616. };
  1617. static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
  1618. .irq_handler = rt2500pci_interrupt,
  1619. .probe_hw = rt2500pci_probe_hw,
  1620. .initialize = rt2x00pci_initialize,
  1621. .uninitialize = rt2x00pci_uninitialize,
  1622. .set_device_state = rt2500pci_set_device_state,
  1623. .rfkill_poll = rt2500pci_rfkill_poll,
  1624. .link_stats = rt2500pci_link_stats,
  1625. .reset_tuner = rt2500pci_reset_tuner,
  1626. .link_tuner = rt2500pci_link_tuner,
  1627. .write_tx_desc = rt2500pci_write_tx_desc,
  1628. .write_tx_data = rt2x00pci_write_tx_data,
  1629. .kick_tx_queue = rt2500pci_kick_tx_queue,
  1630. .fill_rxdone = rt2500pci_fill_rxdone,
  1631. .config_mac_addr = rt2500pci_config_mac_addr,
  1632. .config_bssid = rt2500pci_config_bssid,
  1633. .config_type = rt2500pci_config_type,
  1634. .config_preamble = rt2500pci_config_preamble,
  1635. .config = rt2500pci_config,
  1636. };
  1637. static const struct rt2x00_ops rt2500pci_ops = {
  1638. .name = KBUILD_MODNAME,
  1639. .rxd_size = RXD_DESC_SIZE,
  1640. .txd_size = TXD_DESC_SIZE,
  1641. .eeprom_size = EEPROM_SIZE,
  1642. .rf_size = RF_SIZE,
  1643. .lib = &rt2500pci_rt2x00_ops,
  1644. .hw = &rt2500pci_mac80211_ops,
  1645. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1646. .debugfs = &rt2500pci_rt2x00debug,
  1647. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1648. };
  1649. /*
  1650. * RT2500pci module information.
  1651. */
  1652. static struct pci_device_id rt2500pci_device_table[] = {
  1653. { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
  1654. { 0, }
  1655. };
  1656. MODULE_AUTHOR(DRV_PROJECT);
  1657. MODULE_VERSION(DRV_VERSION);
  1658. MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
  1659. MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
  1660. MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
  1661. MODULE_LICENSE("GPL");
  1662. static struct pci_driver rt2500pci_driver = {
  1663. .name = KBUILD_MODNAME,
  1664. .id_table = rt2500pci_device_table,
  1665. .probe = rt2x00pci_probe,
  1666. .remove = __devexit_p(rt2x00pci_remove),
  1667. .suspend = rt2x00pci_suspend,
  1668. .resume = rt2x00pci_resume,
  1669. };
  1670. static int __init rt2500pci_init(void)
  1671. {
  1672. return pci_register_driver(&rt2500pci_driver);
  1673. }
  1674. static void __exit rt2500pci_exit(void)
  1675. {
  1676. pci_unregister_driver(&rt2500pci_driver);
  1677. }
  1678. module_init(rt2500pci_init);
  1679. module_exit(rt2500pci_exit);