wa.c 20 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. PHY workarounds.
  4. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; see the file COPYING. If not, write to
  16. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  17. Boston, MA 02110-1301, USA.
  18. */
  19. #include "b43.h"
  20. #include "main.h"
  21. #include "tables.h"
  22. #include "phy.h"
  23. #include "wa.h"
  24. static void b43_wa_papd(struct b43_wldev *dev)
  25. {
  26. u16 backup;
  27. backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
  28. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
  29. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
  30. b43_dummy_transmission(dev);
  31. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
  32. }
  33. static void b43_wa_auxclipthr(struct b43_wldev *dev)
  34. {
  35. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
  36. }
  37. static void b43_wa_afcdac(struct b43_wldev *dev)
  38. {
  39. b43_phy_write(dev, 0x0035, 0x03FF);
  40. b43_phy_write(dev, 0x0036, 0x0400);
  41. }
  42. static void b43_wa_txdc_offset(struct b43_wldev *dev)
  43. {
  44. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
  45. }
  46. void b43_wa_initgains(struct b43_wldev *dev)
  47. {
  48. struct b43_phy *phy = &dev->phy;
  49. b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
  50. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  51. b43_phy_read(dev, B43_PHY_LPFGAINCTL) & 0xFF0F);
  52. if (phy->rev <= 2)
  53. b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
  54. b43_radio_write16(dev, 0x0002, 0x1FBF);
  55. b43_phy_write(dev, 0x0024, 0x4680);
  56. b43_phy_write(dev, 0x0020, 0x0003);
  57. b43_phy_write(dev, 0x001D, 0x0F40);
  58. b43_phy_write(dev, 0x001F, 0x1C00);
  59. if (phy->rev <= 3)
  60. b43_phy_write(dev, 0x002A,
  61. (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x0400);
  62. else if (phy->rev == 5) {
  63. b43_phy_write(dev, 0x002A,
  64. (b43_phy_read(dev, 0x002A) & 0x00FF) | 0x1A00);
  65. b43_phy_write(dev, 0x00CC, 0x2121);
  66. }
  67. if (phy->rev >= 3)
  68. b43_phy_write(dev, 0x00BA, 0x3ED5);
  69. }
  70. static void b43_wa_divider(struct b43_wldev *dev)
  71. {
  72. b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B) & ~0x0100);
  73. b43_phy_write(dev, 0x008E, 0x58C1);
  74. }
  75. static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
  76. {
  77. if (dev->phy.rev <= 2) {
  78. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
  79. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
  80. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
  81. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
  82. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
  83. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  84. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  85. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  86. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  87. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  88. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  89. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  90. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
  91. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
  92. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
  93. } else {
  94. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  95. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  96. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  97. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  98. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  99. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  100. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  101. }
  102. }
  103. static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
  104. {
  105. int i;
  106. if (0 /* FIXME: For APHY.rev=2 this might be needed */) {
  107. for (i = 0; i < 8; i++)
  108. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
  109. for (i = 8; i < 16; i++)
  110. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
  111. } else {
  112. for (i = 0; i < 64; i++)
  113. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i);
  114. }
  115. }
  116. static void b43_wa_analog(struct b43_wldev *dev)
  117. {
  118. struct b43_phy *phy = &dev->phy;
  119. u16 ofdmrev;
  120. ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
  121. if (ofdmrev > 2) {
  122. if (phy->type == B43_PHYTYPE_A)
  123. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
  124. else
  125. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
  126. } else {
  127. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
  128. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
  129. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
  130. }
  131. }
  132. static void b43_wa_dac(struct b43_wldev *dev)
  133. {
  134. if (dev->phy.analog == 1)
  135. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  136. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
  137. else
  138. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  139. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
  140. }
  141. static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
  142. {
  143. int i;
  144. if (dev->phy.type == B43_PHYTYPE_A)
  145. for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
  146. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
  147. else
  148. for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
  149. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
  150. }
  151. static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
  152. {
  153. struct b43_phy *phy = &dev->phy;
  154. int i;
  155. if (phy->type == B43_PHYTYPE_A) {
  156. if (phy->rev == 2)
  157. for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
  158. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
  159. else
  160. for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
  161. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
  162. } else {
  163. if (phy->rev == 1)
  164. for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
  165. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
  166. else
  167. for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
  168. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
  169. }
  170. }
  171. static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
  172. {
  173. int i;
  174. for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
  175. b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
  176. }
  177. static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
  178. {
  179. struct b43_phy *phy = &dev->phy;
  180. int i;
  181. if (phy->type == B43_PHYTYPE_A) {
  182. if (phy->rev <= 1)
  183. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  184. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  185. i, 0);
  186. else if (phy->rev == 2)
  187. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  188. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  189. i, b43_tab_noisescalea2[i]);
  190. else if (phy->rev == 3)
  191. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  192. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  193. i, b43_tab_noisescalea3[i]);
  194. else
  195. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  196. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  197. i, b43_tab_noisescaleg3[i]);
  198. } else {
  199. if (phy->rev >= 6) {
  200. if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
  201. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  202. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  203. i, b43_tab_noisescaleg3[i]);
  204. else
  205. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  206. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  207. i, b43_tab_noisescaleg2[i]);
  208. } else {
  209. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  210. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE,
  211. i, b43_tab_noisescaleg1[i]);
  212. }
  213. }
  214. }
  215. static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
  216. {
  217. int i;
  218. for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
  219. b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
  220. i, b43_tab_retard[i]);
  221. }
  222. static void b43_wa_txlna_gain(struct b43_wldev *dev)
  223. {
  224. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
  225. }
  226. static void b43_wa_crs_reset(struct b43_wldev *dev)
  227. {
  228. b43_phy_write(dev, 0x002C, 0x0064);
  229. }
  230. static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
  231. {
  232. b43_hf_write(dev, b43_hf_read(dev) |
  233. B43_HF_2060W);
  234. }
  235. static void b43_wa_lms(struct b43_wldev *dev)
  236. {
  237. b43_phy_write(dev, 0x0055,
  238. (b43_phy_read(dev, 0x0055) & 0xFFC0) | 0x0004);
  239. }
  240. static void b43_wa_mixedsignal(struct b43_wldev *dev)
  241. {
  242. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
  243. }
  244. static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
  245. {
  246. struct b43_phy *phy = &dev->phy;
  247. int i;
  248. const u16 *tab;
  249. if (phy->type == B43_PHYTYPE_A) {
  250. tab = b43_tab_sigmasqr1;
  251. } else if (phy->type == B43_PHYTYPE_G) {
  252. tab = b43_tab_sigmasqr2;
  253. } else {
  254. B43_WARN_ON(1);
  255. return;
  256. }
  257. for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
  258. b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
  259. i, tab[i]);
  260. }
  261. }
  262. static void b43_wa_iqadc(struct b43_wldev *dev)
  263. {
  264. if (dev->phy.analog == 4)
  265. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
  266. b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
  267. }
  268. static void b43_wa_crs_ed(struct b43_wldev *dev)
  269. {
  270. struct b43_phy *phy = &dev->phy;
  271. if (phy->rev == 1) {
  272. b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);
  273. } else if (phy->rev == 2) {
  274. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);
  275. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);
  276. b43_phy_write(dev, B43_PHY_ANTDWELL,
  277. b43_phy_read(dev, B43_PHY_ANTDWELL)
  278. | 0x0800);
  279. } else {
  280. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);
  281. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);
  282. b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
  283. b43_phy_write(dev, B43_PHY_ANTDWELL,
  284. b43_phy_read(dev, B43_PHY_ANTDWELL)
  285. | 0x0800);
  286. }
  287. }
  288. static void b43_wa_crs_thr(struct b43_wldev *dev)
  289. {
  290. b43_phy_write(dev, B43_PHY_CRS0,
  291. (b43_phy_read(dev, B43_PHY_CRS0) & ~0x03C0) | 0xD000);
  292. }
  293. static void b43_wa_crs_blank(struct b43_wldev *dev)
  294. {
  295. b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
  296. }
  297. static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
  298. {
  299. b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
  300. }
  301. static void b43_wa_wrssi_offset(struct b43_wldev *dev)
  302. {
  303. int i;
  304. if (dev->phy.rev == 1) {
  305. for (i = 0; i < 16; i++) {
  306. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
  307. i, 0x0020);
  308. }
  309. } else {
  310. for (i = 0; i < 32; i++) {
  311. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
  312. i, 0x0820);
  313. }
  314. }
  315. }
  316. static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
  317. {
  318. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
  319. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
  320. }
  321. static void b43_wa_altagc(struct b43_wldev *dev)
  322. {
  323. struct b43_phy *phy = &dev->phy;
  324. if (phy->rev == 1) {
  325. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
  326. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
  327. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
  328. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
  329. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
  330. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
  331. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
  332. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
  333. b43_phy_write(dev, B43_PHY_LMS, 4);
  334. } else {
  335. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
  336. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
  337. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
  338. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
  339. }
  340. b43_phy_write(dev, B43_PHY_CCKSHIFTBITS_WA,
  341. (b43_phy_read(dev, B43_PHY_CCKSHIFTBITS_WA) & ~0xFF00) | 0x5700);
  342. b43_phy_write(dev, B43_PHY_OFDM(0x1A),
  343. (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x007F) | 0x000F);
  344. b43_phy_write(dev, B43_PHY_OFDM(0x1A),
  345. (b43_phy_read(dev, B43_PHY_OFDM(0x1A)) & ~0x3F80) | 0x2B80);
  346. b43_phy_write(dev, B43_PHY_ANTWRSETT,
  347. (b43_phy_read(dev, B43_PHY_ANTWRSETT) & 0xF0FF) | 0x0300);
  348. b43_radio_write16(dev, 0x7A,
  349. b43_radio_read16(dev, 0x7A) | 0x0008);
  350. b43_phy_write(dev, B43_PHY_N1P1GAIN,
  351. (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x000F) | 0x0008);
  352. b43_phy_write(dev, B43_PHY_P1P2GAIN,
  353. (b43_phy_read(dev, B43_PHY_P1P2GAIN) & ~0x0F00) | 0x0600);
  354. b43_phy_write(dev, B43_PHY_N1N2GAIN,
  355. (b43_phy_read(dev, B43_PHY_N1N2GAIN) & ~0x0F00) | 0x0700);
  356. b43_phy_write(dev, B43_PHY_N1P1GAIN,
  357. (b43_phy_read(dev, B43_PHY_N1P1GAIN) & ~0x0F00) | 0x0100);
  358. if (phy->rev == 1) {
  359. b43_phy_write(dev, B43_PHY_N1N2GAIN,
  360. (b43_phy_read(dev, B43_PHY_N1N2GAIN)
  361. & ~0x000F) | 0x0007);
  362. }
  363. b43_phy_write(dev, B43_PHY_OFDM(0x88),
  364. (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x00FF) | 0x001C);
  365. b43_phy_write(dev, B43_PHY_OFDM(0x88),
  366. (b43_phy_read(dev, B43_PHY_OFDM(0x88)) & ~0x3F00) | 0x0200);
  367. b43_phy_write(dev, B43_PHY_OFDM(0x96),
  368. (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0x00FF) | 0x001C);
  369. b43_phy_write(dev, B43_PHY_OFDM(0x89),
  370. (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x00FF) | 0x0020);
  371. b43_phy_write(dev, B43_PHY_OFDM(0x89),
  372. (b43_phy_read(dev, B43_PHY_OFDM(0x89)) & ~0x3F00) | 0x0200);
  373. b43_phy_write(dev, B43_PHY_OFDM(0x82),
  374. (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & ~0x00FF) | 0x002E);
  375. b43_phy_write(dev, B43_PHY_OFDM(0x96),
  376. (b43_phy_read(dev, B43_PHY_OFDM(0x96)) & ~0xFF00) | 0x1A00);
  377. b43_phy_write(dev, B43_PHY_OFDM(0x81),
  378. (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0x00FF) | 0x0028);
  379. b43_phy_write(dev, B43_PHY_OFDM(0x81),
  380. (b43_phy_read(dev, B43_PHY_OFDM(0x81)) & ~0xFF00) | 0x2C00);
  381. if (phy->rev == 1) {
  382. b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
  383. b43_phy_write(dev, B43_PHY_OFDM(0x1B),
  384. (b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E) | 0x0002);
  385. } else {
  386. b43_phy_write(dev, B43_PHY_OFDM(0x1B),
  387. b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x001E);
  388. b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
  389. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  390. (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0x000F) | 0x0004);
  391. if (phy->rev >= 6) {
  392. b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
  393. b43_phy_write(dev, B43_PHY_LPFGAINCTL,
  394. (b43_phy_read(dev, B43_PHY_LPFGAINCTL) & ~0xF000) | 0x3000);
  395. }
  396. }
  397. b43_phy_write(dev, B43_PHY_DIVSRCHIDX,
  398. (b43_phy_read(dev, B43_PHY_DIVSRCHIDX) & 0x8080) | 0x7874);
  399. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
  400. if (phy->rev == 1) {
  401. b43_phy_write(dev, B43_PHY_DIVP1P2GAIN,
  402. (b43_phy_read(dev, B43_PHY_DIVP1P2GAIN) & ~0x0F00) | 0x0600);
  403. b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
  404. b43_phy_write(dev, B43_PHY_ANTWRSETT,
  405. (b43_phy_read(dev, B43_PHY_ANTWRSETT) & ~0x00FF) | 0x001E);
  406. b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
  407. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
  408. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
  409. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
  410. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
  411. } else {
  412. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
  413. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
  414. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
  415. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
  416. }
  417. if (phy->rev >= 6) {
  418. b43_phy_write(dev, B43_PHY_OFDM(0x26),
  419. b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x0003);
  420. b43_phy_write(dev, B43_PHY_OFDM(0x26),
  421. b43_phy_read(dev, B43_PHY_OFDM(0x26)) & ~0x1000);
  422. }
  423. b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */
  424. }
  425. static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
  426. {
  427. b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0xC480);
  428. }
  429. static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
  430. {
  431. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
  432. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
  433. }
  434. static void b43_wa_rssi_adc(struct b43_wldev *dev)
  435. {
  436. if (dev->phy.analog == 4)
  437. b43_phy_write(dev, 0x00DC, 0x7454);
  438. }
  439. static void b43_wa_boards_a(struct b43_wldev *dev)
  440. {
  441. struct ssb_bus *bus = dev->dev->bus;
  442. if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
  443. bus->boardinfo.type == SSB_BOARD_BU4306 &&
  444. bus->boardinfo.rev < 0x30) {
  445. b43_phy_write(dev, 0x0010, 0xE000);
  446. b43_phy_write(dev, 0x0013, 0x0140);
  447. b43_phy_write(dev, 0x0014, 0x0280);
  448. } else {
  449. if (bus->boardinfo.type == SSB_BOARD_MP4318 &&
  450. bus->boardinfo.rev < 0x20) {
  451. b43_phy_write(dev, 0x0013, 0x0210);
  452. b43_phy_write(dev, 0x0014, 0x0840);
  453. } else {
  454. b43_phy_write(dev, 0x0013, 0x0140);
  455. b43_phy_write(dev, 0x0014, 0x0280);
  456. }
  457. if (dev->phy.rev <= 4)
  458. b43_phy_write(dev, 0x0010, 0xE000);
  459. else
  460. b43_phy_write(dev, 0x0010, 0x2000);
  461. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
  462. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
  463. }
  464. }
  465. static void b43_wa_boards_g(struct b43_wldev *dev)
  466. {
  467. struct ssb_bus *bus = dev->dev->bus;
  468. struct b43_phy *phy = &dev->phy;
  469. if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM ||
  470. bus->boardinfo.type != SSB_BOARD_BU4306 ||
  471. bus->boardinfo.rev != 0x17) {
  472. if (phy->rev < 2) {
  473. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
  474. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
  475. } else {
  476. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
  477. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
  478. if ((bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
  479. (phy->rev >= 7)) {
  480. b43_phy_write(dev, B43_PHY_EXTG(0x11),
  481. b43_phy_read(dev, B43_PHY_EXTG(0x11)) & 0xF7FF);
  482. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
  483. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
  484. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
  485. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
  486. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
  487. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
  488. }
  489. }
  490. }
  491. if (bus->sprom.boardflags_lo & B43_BFL_FEM) {
  492. b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
  493. b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
  494. }
  495. }
  496. void b43_wa_all(struct b43_wldev *dev)
  497. {
  498. struct b43_phy *phy = &dev->phy;
  499. if (phy->type == B43_PHYTYPE_A) {
  500. switch (phy->rev) {
  501. case 2:
  502. b43_wa_papd(dev);
  503. b43_wa_auxclipthr(dev);
  504. b43_wa_afcdac(dev);
  505. b43_wa_txdc_offset(dev);
  506. b43_wa_initgains(dev);
  507. b43_wa_divider(dev);
  508. b43_wa_gt(dev);
  509. b43_wa_rssi_lt(dev);
  510. b43_wa_analog(dev);
  511. b43_wa_dac(dev);
  512. b43_wa_fft(dev);
  513. b43_wa_nft(dev);
  514. b43_wa_rt(dev);
  515. b43_wa_nst(dev);
  516. b43_wa_art(dev);
  517. b43_wa_txlna_gain(dev);
  518. b43_wa_crs_reset(dev);
  519. b43_wa_2060txlna_gain(dev);
  520. b43_wa_lms(dev);
  521. break;
  522. case 3:
  523. b43_wa_papd(dev);
  524. b43_wa_mixedsignal(dev);
  525. b43_wa_rssi_lt(dev);
  526. b43_wa_txdc_offset(dev);
  527. b43_wa_initgains(dev);
  528. b43_wa_dac(dev);
  529. b43_wa_nft(dev);
  530. b43_wa_nst(dev);
  531. b43_wa_msst(dev);
  532. b43_wa_analog(dev);
  533. b43_wa_gt(dev);
  534. b43_wa_txpuoff_rxpuon(dev);
  535. b43_wa_txlna_gain(dev);
  536. break;
  537. case 5:
  538. b43_wa_iqadc(dev);
  539. case 6:
  540. b43_wa_papd(dev);
  541. b43_wa_rssi_lt(dev);
  542. b43_wa_txdc_offset(dev);
  543. b43_wa_initgains(dev);
  544. b43_wa_dac(dev);
  545. b43_wa_nft(dev);
  546. b43_wa_nst(dev);
  547. b43_wa_msst(dev);
  548. b43_wa_analog(dev);
  549. b43_wa_gt(dev);
  550. b43_wa_txpuoff_rxpuon(dev);
  551. b43_wa_txlna_gain(dev);
  552. break;
  553. case 7:
  554. b43_wa_iqadc(dev);
  555. b43_wa_papd(dev);
  556. b43_wa_rssi_lt(dev);
  557. b43_wa_txdc_offset(dev);
  558. b43_wa_initgains(dev);
  559. b43_wa_dac(dev);
  560. b43_wa_nft(dev);
  561. b43_wa_nst(dev);
  562. b43_wa_msst(dev);
  563. b43_wa_analog(dev);
  564. b43_wa_gt(dev);
  565. b43_wa_txpuoff_rxpuon(dev);
  566. b43_wa_txlna_gain(dev);
  567. b43_wa_rssi_adc(dev);
  568. default:
  569. B43_WARN_ON(1);
  570. }
  571. b43_wa_boards_a(dev);
  572. } else if (phy->type == B43_PHYTYPE_G) {
  573. switch (phy->rev) {
  574. case 1://XXX review rev1
  575. b43_wa_crs_ed(dev);
  576. b43_wa_crs_thr(dev);
  577. b43_wa_crs_blank(dev);
  578. b43_wa_cck_shiftbits(dev);
  579. b43_wa_fft(dev);
  580. b43_wa_nft(dev);
  581. b43_wa_rt(dev);
  582. b43_wa_nst(dev);
  583. b43_wa_art(dev);
  584. b43_wa_wrssi_offset(dev);
  585. b43_wa_altagc(dev);
  586. break;
  587. case 2:
  588. case 6:
  589. case 7:
  590. case 8:
  591. case 9:
  592. b43_wa_tr_ltov(dev);
  593. b43_wa_crs_ed(dev);
  594. b43_wa_rssi_lt(dev);
  595. b43_wa_nft(dev);
  596. b43_wa_nst(dev);
  597. b43_wa_msst(dev);
  598. b43_wa_wrssi_offset(dev);
  599. b43_wa_altagc(dev);
  600. b43_wa_analog(dev);
  601. b43_wa_txpuoff_rxpuon(dev);
  602. break;
  603. default:
  604. B43_WARN_ON(1);
  605. }
  606. b43_wa_boards_g(dev);
  607. } else { /* No N PHY support so far */
  608. B43_WARN_ON(1);
  609. }
  610. b43_wa_cpll_nonpilot(dev);
  611. }