cx23885-dvb.c 26 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "tda10048.h"
  39. #include "tuner-xc2028.h"
  40. #include "tuner-simple.h"
  41. #include "dib7000p.h"
  42. #include "dibx000_common.h"
  43. #include "zl10353.h"
  44. #include "stv0900.h"
  45. #include "stv0900_reg.h"
  46. #include "stv6110.h"
  47. #include "lnbh24.h"
  48. #include "cx24116.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. static unsigned int debug;
  55. #define dprintk(level, fmt, arg...)\
  56. do { if (debug >= level)\
  57. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  58. } while (0)
  59. /* ------------------------------------------------------------------ */
  60. static unsigned int alt_tuner;
  61. module_param(alt_tuner, int, 0644);
  62. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  63. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  64. /* ------------------------------------------------------------------ */
  65. static int dvb_buf_setup(struct videobuf_queue *q,
  66. unsigned int *count, unsigned int *size)
  67. {
  68. struct cx23885_tsport *port = q->priv_data;
  69. port->ts_packet_size = 188 * 4;
  70. port->ts_packet_count = 32;
  71. *size = port->ts_packet_size * port->ts_packet_count;
  72. *count = 32;
  73. return 0;
  74. }
  75. static int dvb_buf_prepare(struct videobuf_queue *q,
  76. struct videobuf_buffer *vb, enum v4l2_field field)
  77. {
  78. struct cx23885_tsport *port = q->priv_data;
  79. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  80. }
  81. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  82. {
  83. struct cx23885_tsport *port = q->priv_data;
  84. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  85. }
  86. static void dvb_buf_release(struct videobuf_queue *q,
  87. struct videobuf_buffer *vb)
  88. {
  89. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  90. }
  91. static struct videobuf_queue_ops dvb_qops = {
  92. .buf_setup = dvb_buf_setup,
  93. .buf_prepare = dvb_buf_prepare,
  94. .buf_queue = dvb_buf_queue,
  95. .buf_release = dvb_buf_release,
  96. };
  97. static struct s5h1409_config hauppauge_generic_config = {
  98. .demod_address = 0x32 >> 1,
  99. .output_mode = S5H1409_SERIAL_OUTPUT,
  100. .gpio = S5H1409_GPIO_ON,
  101. .qam_if = 44000,
  102. .inversion = S5H1409_INVERSION_OFF,
  103. .status_mode = S5H1409_DEMODLOCKING,
  104. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  105. };
  106. static struct tda10048_config hauppauge_hvr1200_config = {
  107. .demod_address = 0x10 >> 1,
  108. .output_mode = TDA10048_SERIAL_OUTPUT,
  109. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  110. .inversion = TDA10048_INVERSION_ON,
  111. .dtv6_if_freq_khz = TDA10048_IF_3300,
  112. .dtv7_if_freq_khz = TDA10048_IF_3800,
  113. .dtv8_if_freq_khz = TDA10048_IF_4300,
  114. .clk_freq_khz = TDA10048_CLK_16000,
  115. };
  116. static struct tda10048_config hauppauge_hvr1210_config = {
  117. .demod_address = 0x10 >> 1,
  118. .output_mode = TDA10048_SERIAL_OUTPUT,
  119. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  120. .inversion = TDA10048_INVERSION_ON,
  121. .dtv6_if_freq_khz = TDA10048_IF_3300,
  122. .dtv7_if_freq_khz = TDA10048_IF_3500,
  123. .dtv8_if_freq_khz = TDA10048_IF_4000,
  124. .clk_freq_khz = TDA10048_CLK_16000,
  125. };
  126. static struct s5h1409_config hauppauge_ezqam_config = {
  127. .demod_address = 0x32 >> 1,
  128. .output_mode = S5H1409_SERIAL_OUTPUT,
  129. .gpio = S5H1409_GPIO_OFF,
  130. .qam_if = 4000,
  131. .inversion = S5H1409_INVERSION_ON,
  132. .status_mode = S5H1409_DEMODLOCKING,
  133. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  134. };
  135. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  136. .demod_address = 0x32 >> 1,
  137. .output_mode = S5H1409_SERIAL_OUTPUT,
  138. .gpio = S5H1409_GPIO_OFF,
  139. .qam_if = 44000,
  140. .inversion = S5H1409_INVERSION_OFF,
  141. .status_mode = S5H1409_DEMODLOCKING,
  142. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  143. };
  144. static struct s5h1409_config hauppauge_hvr1500_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .inversion = S5H1409_INVERSION_OFF,
  149. .status_mode = S5H1409_DEMODLOCKING,
  150. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  151. };
  152. static struct mt2131_config hauppauge_generic_tunerconfig = {
  153. 0x61
  154. };
  155. static struct lgdt330x_config fusionhdtv_5_express = {
  156. .demod_address = 0x0e,
  157. .demod_chip = LGDT3303,
  158. .serial_mpeg = 0x40,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1500q_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_ON,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config dvico_s5h1409_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_ON,
  173. .qam_if = 44000,
  174. .inversion = S5H1409_INVERSION_OFF,
  175. .status_mode = S5H1409_DEMODLOCKING,
  176. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  177. };
  178. static struct s5h1411_config dvico_s5h1411_config = {
  179. .output_mode = S5H1411_SERIAL_OUTPUT,
  180. .gpio = S5H1411_GPIO_ON,
  181. .qam_if = S5H1411_IF_44000,
  182. .vsb_if = S5H1411_IF_44000,
  183. .inversion = S5H1411_INVERSION_OFF,
  184. .status_mode = S5H1411_DEMODLOCKING,
  185. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1411_config hcw_s5h1411_config = {
  188. .output_mode = S5H1411_SERIAL_OUTPUT,
  189. .gpio = S5H1411_GPIO_OFF,
  190. .vsb_if = S5H1411_IF_44000,
  191. .qam_if = S5H1411_IF_4000,
  192. .inversion = S5H1411_INVERSION_ON,
  193. .status_mode = S5H1411_DEMODLOCKING,
  194. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  197. .i2c_address = 0x61,
  198. .if_khz = 5380,
  199. };
  200. static struct xc5000_config dvico_xc5000_tunerconfig = {
  201. .i2c_address = 0x64,
  202. .if_khz = 5380,
  203. };
  204. static struct tda829x_config tda829x_no_probe = {
  205. .probe_tuner = TDA829X_DONT_PROBE,
  206. };
  207. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  208. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  209. .if_lvl = 6, .rfagc_top = 0x37 },
  210. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  211. .if_lvl = 6, .rfagc_top = 0x37 },
  212. };
  213. static struct tda18271_config hauppauge_tda18271_config = {
  214. .std_map = &hauppauge_tda18271_std_map,
  215. .gate = TDA18271_GATE_ANALOG,
  216. };
  217. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  218. .gate = TDA18271_GATE_ANALOG,
  219. };
  220. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  221. .gate = TDA18271_GATE_DIGITAL,
  222. };
  223. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  224. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  225. .if_lvl = 1, .rfagc_top = 0x58 },
  226. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  227. .if_lvl = 1, .rfagc_top = 0x58 },
  228. };
  229. static struct tda18271_config hauppauge_hvr127x_config = {
  230. .std_map = &hauppauge_hvr127x_std_map,
  231. };
  232. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  233. .i2c_addr = 0x0e,
  234. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  235. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  236. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  237. .deny_i2c_rptr = 1,
  238. .spectral_inversion = 1,
  239. .qam_if_khz = 4000,
  240. .vsb_if_khz = 3250,
  241. };
  242. static struct dibx000_agc_config xc3028_agc_config = {
  243. BAND_VHF | BAND_UHF, /* band_caps */
  244. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  245. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  246. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  247. * P_agc_nb_est=2, P_agc_write=0
  248. */
  249. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  250. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  251. 712, /* inv_gain */
  252. 21, /* time_stabiliz */
  253. 0, /* alpha_level */
  254. 118, /* thlock */
  255. 0, /* wbd_inv */
  256. 2867, /* wbd_ref */
  257. 0, /* wbd_sel */
  258. 2, /* wbd_alpha */
  259. 0, /* agc1_max */
  260. 0, /* agc1_min */
  261. 39718, /* agc2_max */
  262. 9930, /* agc2_min */
  263. 0, /* agc1_pt1 */
  264. 0, /* agc1_pt2 */
  265. 0, /* agc1_pt3 */
  266. 0, /* agc1_slope1 */
  267. 0, /* agc1_slope2 */
  268. 0, /* agc2_pt1 */
  269. 128, /* agc2_pt2 */
  270. 29, /* agc2_slope1 */
  271. 29, /* agc2_slope2 */
  272. 17, /* alpha_mant */
  273. 27, /* alpha_exp */
  274. 23, /* beta_mant */
  275. 51, /* beta_exp */
  276. 1, /* perform_agc_softsplit */
  277. };
  278. /* PLL Configuration for COFDM BW_MHz = 8.000000
  279. * With external clock = 30.000000 */
  280. static struct dibx000_bandwidth_config xc3028_bw_config = {
  281. 60000, /* internal */
  282. 30000, /* sampling */
  283. 1, /* pll_cfg: prediv */
  284. 8, /* pll_cfg: ratio */
  285. 3, /* pll_cfg: range */
  286. 1, /* pll_cfg: reset */
  287. 0, /* pll_cfg: bypass */
  288. 0, /* misc: refdiv */
  289. 0, /* misc: bypclk_div */
  290. 1, /* misc: IO_CLK_en_core */
  291. 1, /* misc: ADClkSrc */
  292. 0, /* misc: modulo */
  293. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  294. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  295. 20452225, /* timf */
  296. 30000000 /* xtal_hz */
  297. };
  298. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  299. .output_mpeg2_in_188_bytes = 1,
  300. .hostbus_diversity = 1,
  301. .tuner_is_baseband = 0,
  302. .update_lna = NULL,
  303. .agc_config_count = 1,
  304. .agc = &xc3028_agc_config,
  305. .bw = &xc3028_bw_config,
  306. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  307. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  308. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  309. .pwm_freq_div = 0,
  310. .agc_control = NULL,
  311. .spur_protect = 0,
  312. .output_mode = OUTMODE_MPEG2_SERIAL,
  313. };
  314. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  315. .demod_address = 0x0f,
  316. .if2 = 45600,
  317. .no_tuner = 1,
  318. .disable_i2c_gate_ctrl = 1,
  319. };
  320. static struct stv0900_reg stv0900_ts_regs[] = {
  321. { R0900_TSGENERAL, 0x00 },
  322. { R0900_P1_TSSPEED, 0x40 },
  323. { R0900_P2_TSSPEED, 0x40 },
  324. { R0900_P1_TSCFGM, 0xc0 },
  325. { R0900_P2_TSCFGM, 0xc0 },
  326. { R0900_P1_TSCFGH, 0xe0 },
  327. { R0900_P2_TSCFGH, 0xe0 },
  328. { R0900_P1_TSCFGL, 0x20 },
  329. { R0900_P2_TSCFGL, 0x20 },
  330. { 0xffff, 0xff }, /* terminate */
  331. };
  332. static struct stv0900_config netup_stv0900_config = {
  333. .demod_address = 0x68,
  334. .xtal = 27000000,
  335. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  336. .diseqc_mode = 2,/* 2/3 PWM */
  337. .ts_config_regs = stv0900_ts_regs,
  338. .tun1_maddress = 0,/* 0x60 */
  339. .tun2_maddress = 3,/* 0x63 */
  340. .tun1_adc = 1,/* 1 Vpp */
  341. .tun2_adc = 1,/* 1 Vpp */
  342. };
  343. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  344. .i2c_address = 0x60,
  345. .mclk = 27000000,
  346. .iq_wiring = 0,
  347. };
  348. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  349. .i2c_address = 0x63,
  350. .mclk = 27000000,
  351. .iq_wiring = 1,
  352. };
  353. static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  354. {
  355. struct cx23885_tsport *port = fe->dvb->priv;
  356. struct cx23885_dev *dev = port->dev;
  357. if (voltage == SEC_VOLTAGE_18)
  358. cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
  359. else if (voltage == SEC_VOLTAGE_13)
  360. cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
  361. else
  362. cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
  363. return 0;
  364. }
  365. static struct cx24116_config tbs_cx24116_config = {
  366. .demod_address = 0x05,
  367. };
  368. static struct cx24116_config tevii_cx24116_config = {
  369. .demod_address = 0x55,
  370. };
  371. static struct cx24116_config dvbworld_cx24116_config = {
  372. .demod_address = 0x05,
  373. };
  374. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  375. .prod = LGS8GXX_PROD_LGS8GL5,
  376. .demod_address = 0x19,
  377. .serial_ts = 0,
  378. .ts_clk_pol = 1,
  379. .ts_clk_gated = 1,
  380. .if_clk_freq = 30400, /* 30.4 MHz */
  381. .if_freq = 5380, /* 5.38 MHz */
  382. .if_neg_center = 1,
  383. .ext_adc = 0,
  384. .adc_signed = 0,
  385. .if_neg_edge = 0,
  386. };
  387. static struct xc5000_config mygica_x8506_xc5000_config = {
  388. .i2c_address = 0x61,
  389. .if_khz = 5380,
  390. };
  391. static int dvb_register(struct cx23885_tsport *port)
  392. {
  393. struct cx23885_dev *dev = port->dev;
  394. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  395. struct videobuf_dvb_frontend *fe0;
  396. int ret;
  397. /* Get the first frontend */
  398. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  399. if (!fe0)
  400. return -EINVAL;
  401. /* init struct videobuf_dvb */
  402. fe0->dvb.name = dev->name;
  403. /* init frontend */
  404. switch (dev->board) {
  405. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  406. i2c_bus = &dev->i2c_bus[0];
  407. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  408. &hauppauge_generic_config,
  409. &i2c_bus->i2c_adap);
  410. if (fe0->dvb.frontend != NULL) {
  411. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  412. &i2c_bus->i2c_adap,
  413. &hauppauge_generic_tunerconfig, 0);
  414. }
  415. break;
  416. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  417. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  418. i2c_bus = &dev->i2c_bus[0];
  419. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  420. &hauppauge_lgdt3305_config,
  421. &i2c_bus->i2c_adap);
  422. if (fe0->dvb.frontend != NULL) {
  423. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  424. 0x60, &dev->i2c_bus[1].i2c_adap,
  425. &hauppauge_hvr127x_config);
  426. }
  427. break;
  428. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  429. i2c_bus = &dev->i2c_bus[0];
  430. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  431. &hcw_s5h1411_config,
  432. &i2c_bus->i2c_adap);
  433. if (fe0->dvb.frontend != NULL) {
  434. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  435. 0x60, &dev->i2c_bus[1].i2c_adap,
  436. &hauppauge_tda18271_config);
  437. }
  438. break;
  439. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  440. i2c_bus = &dev->i2c_bus[0];
  441. switch (alt_tuner) {
  442. case 1:
  443. fe0->dvb.frontend =
  444. dvb_attach(s5h1409_attach,
  445. &hauppauge_ezqam_config,
  446. &i2c_bus->i2c_adap);
  447. if (fe0->dvb.frontend != NULL) {
  448. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  449. &dev->i2c_bus[1].i2c_adap, 0x42,
  450. &tda829x_no_probe);
  451. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  452. 0x60, &dev->i2c_bus[1].i2c_adap,
  453. &hauppauge_tda18271_config);
  454. }
  455. break;
  456. case 0:
  457. default:
  458. fe0->dvb.frontend =
  459. dvb_attach(s5h1409_attach,
  460. &hauppauge_generic_config,
  461. &i2c_bus->i2c_adap);
  462. if (fe0->dvb.frontend != NULL)
  463. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  464. &i2c_bus->i2c_adap,
  465. &hauppauge_generic_tunerconfig, 0);
  466. break;
  467. }
  468. break;
  469. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  470. i2c_bus = &dev->i2c_bus[0];
  471. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  472. &hauppauge_hvr1800lp_config,
  473. &i2c_bus->i2c_adap);
  474. if (fe0->dvb.frontend != NULL) {
  475. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  476. &i2c_bus->i2c_adap,
  477. &hauppauge_generic_tunerconfig, 0);
  478. }
  479. break;
  480. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  481. i2c_bus = &dev->i2c_bus[0];
  482. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  483. &fusionhdtv_5_express,
  484. &i2c_bus->i2c_adap);
  485. if (fe0->dvb.frontend != NULL) {
  486. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  487. &i2c_bus->i2c_adap, 0x61,
  488. TUNER_LG_TDVS_H06XF);
  489. }
  490. break;
  491. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  492. i2c_bus = &dev->i2c_bus[1];
  493. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  494. &hauppauge_hvr1500q_config,
  495. &dev->i2c_bus[0].i2c_adap);
  496. if (fe0->dvb.frontend != NULL)
  497. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  498. &i2c_bus->i2c_adap,
  499. &hauppauge_hvr1500q_tunerconfig);
  500. break;
  501. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  502. i2c_bus = &dev->i2c_bus[1];
  503. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  504. &hauppauge_hvr1500_config,
  505. &dev->i2c_bus[0].i2c_adap);
  506. if (fe0->dvb.frontend != NULL) {
  507. struct dvb_frontend *fe;
  508. struct xc2028_config cfg = {
  509. .i2c_adap = &i2c_bus->i2c_adap,
  510. .i2c_addr = 0x61,
  511. };
  512. static struct xc2028_ctrl ctl = {
  513. .fname = XC2028_DEFAULT_FIRMWARE,
  514. .max_len = 64,
  515. .demod = XC3028_FE_OREN538,
  516. };
  517. fe = dvb_attach(xc2028_attach,
  518. fe0->dvb.frontend, &cfg);
  519. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  520. fe->ops.tuner_ops.set_config(fe, &ctl);
  521. }
  522. break;
  523. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  524. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  525. i2c_bus = &dev->i2c_bus[0];
  526. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  527. &hauppauge_hvr1200_config,
  528. &i2c_bus->i2c_adap);
  529. if (fe0->dvb.frontend != NULL) {
  530. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  531. &dev->i2c_bus[1].i2c_adap, 0x42,
  532. &tda829x_no_probe);
  533. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  534. 0x60, &dev->i2c_bus[1].i2c_adap,
  535. &hauppauge_hvr1200_tuner_config);
  536. }
  537. break;
  538. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  539. i2c_bus = &dev->i2c_bus[0];
  540. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  541. &hauppauge_hvr1210_config,
  542. &i2c_bus->i2c_adap);
  543. if (fe0->dvb.frontend != NULL) {
  544. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  545. 0x60, &dev->i2c_bus[1].i2c_adap,
  546. &hauppauge_hvr1210_tuner_config);
  547. }
  548. break;
  549. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  550. i2c_bus = &dev->i2c_bus[0];
  551. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  552. &i2c_bus->i2c_adap,
  553. 0x12, &hauppauge_hvr1400_dib7000_config);
  554. if (fe0->dvb.frontend != NULL) {
  555. struct dvb_frontend *fe;
  556. struct xc2028_config cfg = {
  557. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  558. .i2c_addr = 0x64,
  559. };
  560. static struct xc2028_ctrl ctl = {
  561. .fname = XC3028L_DEFAULT_FIRMWARE,
  562. .max_len = 64,
  563. .demod = 5000,
  564. /* This is true for all demods with
  565. v36 firmware? */
  566. .type = XC2028_D2633,
  567. };
  568. fe = dvb_attach(xc2028_attach,
  569. fe0->dvb.frontend, &cfg);
  570. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  571. fe->ops.tuner_ops.set_config(fe, &ctl);
  572. }
  573. break;
  574. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  575. i2c_bus = &dev->i2c_bus[port->nr - 1];
  576. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  577. &dvico_s5h1409_config,
  578. &i2c_bus->i2c_adap);
  579. if (fe0->dvb.frontend == NULL)
  580. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  581. &dvico_s5h1411_config,
  582. &i2c_bus->i2c_adap);
  583. if (fe0->dvb.frontend != NULL)
  584. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  585. &i2c_bus->i2c_adap,
  586. &dvico_xc5000_tunerconfig);
  587. break;
  588. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  589. i2c_bus = &dev->i2c_bus[port->nr - 1];
  590. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  591. &dvico_fusionhdtv_xc3028,
  592. &i2c_bus->i2c_adap);
  593. if (fe0->dvb.frontend != NULL) {
  594. struct dvb_frontend *fe;
  595. struct xc2028_config cfg = {
  596. .i2c_adap = &i2c_bus->i2c_adap,
  597. .i2c_addr = 0x61,
  598. };
  599. static struct xc2028_ctrl ctl = {
  600. .fname = XC2028_DEFAULT_FIRMWARE,
  601. .max_len = 64,
  602. .demod = XC3028_FE_ZARLINK456,
  603. };
  604. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  605. &cfg);
  606. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  607. fe->ops.tuner_ops.set_config(fe, &ctl);
  608. }
  609. break;
  610. }
  611. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  612. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  613. i2c_bus = &dev->i2c_bus[0];
  614. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  615. &dvico_fusionhdtv_xc3028,
  616. &i2c_bus->i2c_adap);
  617. if (fe0->dvb.frontend != NULL) {
  618. struct dvb_frontend *fe;
  619. struct xc2028_config cfg = {
  620. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  621. .i2c_addr = 0x61,
  622. };
  623. static struct xc2028_ctrl ctl = {
  624. .fname = XC2028_DEFAULT_FIRMWARE,
  625. .max_len = 64,
  626. .demod = XC3028_FE_ZARLINK456,
  627. };
  628. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  629. &cfg);
  630. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  631. fe->ops.tuner_ops.set_config(fe, &ctl);
  632. }
  633. break;
  634. case CX23885_BOARD_TBS_6920:
  635. i2c_bus = &dev->i2c_bus[0];
  636. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  637. &tbs_cx24116_config,
  638. &i2c_bus->i2c_adap);
  639. if (fe0->dvb.frontend != NULL)
  640. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  641. break;
  642. case CX23885_BOARD_TEVII_S470:
  643. i2c_bus = &dev->i2c_bus[1];
  644. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  645. &tevii_cx24116_config,
  646. &i2c_bus->i2c_adap);
  647. if (fe0->dvb.frontend != NULL)
  648. fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
  649. break;
  650. case CX23885_BOARD_DVBWORLD_2005:
  651. i2c_bus = &dev->i2c_bus[1];
  652. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  653. &dvbworld_cx24116_config,
  654. &i2c_bus->i2c_adap);
  655. break;
  656. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  657. i2c_bus = &dev->i2c_bus[0];
  658. switch (port->nr) {
  659. /* port B */
  660. case 1:
  661. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  662. &netup_stv0900_config,
  663. &i2c_bus->i2c_adap, 0);
  664. if (fe0->dvb.frontend != NULL) {
  665. if (dvb_attach(stv6110_attach,
  666. fe0->dvb.frontend,
  667. &netup_stv6110_tunerconfig_a,
  668. &i2c_bus->i2c_adap)) {
  669. if (!dvb_attach(lnbh24_attach,
  670. fe0->dvb.frontend,
  671. &i2c_bus->i2c_adap,
  672. LNBH24_PCL,
  673. LNBH24_TTX, 0x09))
  674. printk(KERN_ERR
  675. "No LNBH24 found!\n");
  676. }
  677. }
  678. break;
  679. /* port C */
  680. case 2:
  681. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  682. &netup_stv0900_config,
  683. &i2c_bus->i2c_adap, 1);
  684. if (fe0->dvb.frontend != NULL) {
  685. if (dvb_attach(stv6110_attach,
  686. fe0->dvb.frontend,
  687. &netup_stv6110_tunerconfig_b,
  688. &i2c_bus->i2c_adap)) {
  689. if (!dvb_attach(lnbh24_attach,
  690. fe0->dvb.frontend,
  691. &i2c_bus->i2c_adap,
  692. LNBH24_PCL,
  693. LNBH24_TTX, 0x0a))
  694. printk(KERN_ERR
  695. "No LNBH24 found!\n");
  696. }
  697. }
  698. break;
  699. }
  700. break;
  701. case CX23885_BOARD_MYGICA_X8506:
  702. i2c_bus = &dev->i2c_bus[0];
  703. i2c_bus2 = &dev->i2c_bus[1];
  704. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  705. &mygica_x8506_lgs8gl5_config,
  706. &i2c_bus->i2c_adap);
  707. if (fe0->dvb.frontend != NULL) {
  708. dvb_attach(xc5000_attach,
  709. fe0->dvb.frontend,
  710. &i2c_bus2->i2c_adap,
  711. &mygica_x8506_xc5000_config);
  712. }
  713. break;
  714. default:
  715. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  716. " isn't supported yet\n",
  717. dev->name);
  718. break;
  719. }
  720. if (NULL == fe0->dvb.frontend) {
  721. printk(KERN_ERR "%s: frontend initialization failed\n",
  722. dev->name);
  723. return -1;
  724. }
  725. /* define general-purpose callback pointer */
  726. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  727. /* Put the analog decoder in standby to keep it quiet */
  728. call_all(dev, tuner, s_standby);
  729. if (fe0->dvb.frontend->ops.analog_ops.standby)
  730. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  731. /* register everything */
  732. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  733. &dev->pci->dev, adapter_nr, 0);
  734. /* init CI & MAC */
  735. switch (dev->board) {
  736. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  737. static struct netup_card_info cinfo;
  738. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  739. memcpy(port->frontends.adapter.proposed_mac,
  740. cinfo.port[port->nr - 1].mac, 6);
  741. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
  742. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  743. port->nr,
  744. port->frontends.adapter.proposed_mac[0],
  745. port->frontends.adapter.proposed_mac[1],
  746. port->frontends.adapter.proposed_mac[2],
  747. port->frontends.adapter.proposed_mac[3],
  748. port->frontends.adapter.proposed_mac[4],
  749. port->frontends.adapter.proposed_mac[5]);
  750. netup_ci_init(port);
  751. break;
  752. }
  753. }
  754. return ret;
  755. }
  756. int cx23885_dvb_register(struct cx23885_tsport *port)
  757. {
  758. struct videobuf_dvb_frontend *fe0;
  759. struct cx23885_dev *dev = port->dev;
  760. int err, i;
  761. /* Here we need to allocate the correct number of frontends,
  762. * as reflected in the cards struct. The reality is that currrently
  763. * no cx23885 boards support this - yet. But, if we don't modify this
  764. * code then the second frontend would never be allocated (later)
  765. * and fail with error before the attach in dvb_register().
  766. * Without these changes we risk an OOPS later. The changes here
  767. * are for safety, and should provide a good foundation for the
  768. * future addition of any multi-frontend cx23885 based boards.
  769. */
  770. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  771. port->num_frontends);
  772. for (i = 1; i <= port->num_frontends; i++) {
  773. if (videobuf_dvb_alloc_frontend(
  774. &port->frontends, i) == NULL) {
  775. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  776. return -ENOMEM;
  777. }
  778. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  779. if (!fe0)
  780. err = -EINVAL;
  781. dprintk(1, "%s\n", __func__);
  782. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  783. dev->board,
  784. dev->name,
  785. dev->pci_bus,
  786. dev->pci_slot);
  787. err = -ENODEV;
  788. /* dvb stuff */
  789. /* We have to init the queue for each frontend on a port. */
  790. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  791. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  792. &dev->pci->dev, &port->slock,
  793. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  794. sizeof(struct cx23885_buffer), port);
  795. }
  796. err = dvb_register(port);
  797. if (err != 0)
  798. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  799. __func__, err);
  800. return err;
  801. }
  802. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  803. {
  804. struct videobuf_dvb_frontend *fe0;
  805. /* FIXME: in an error condition where the we have
  806. * an expected number of frontends (attach problem)
  807. * then this might not clean up correctly, if 1
  808. * is invalid.
  809. * This comment only applies to future boards IF they
  810. * implement MFE support.
  811. */
  812. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  813. if (fe0->dvb.frontend)
  814. videobuf_dvb_unregister_bus(&port->frontends);
  815. switch (port->dev->board) {
  816. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  817. netup_ci_exit(port);
  818. break;
  819. }
  820. return 0;
  821. }