intc-simr.c 2.0 KB

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  1. /*
  2. * intc-simr.c
  3. *
  4. * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
  5. *
  6. * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file COPYING in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irq.h>
  17. #include <linux/io.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/traps.h>
  21. static void intc_irq_mask(struct irq_data *d)
  22. {
  23. unsigned int irq = d->irq;
  24. if (irq >= MCFINT_VECBASE) {
  25. if (irq < MCFINT_VECBASE + 64)
  26. __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
  27. else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
  28. __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
  29. }
  30. }
  31. static void intc_irq_unmask(struct irq_data *d)
  32. {
  33. unsigned int irq = d->irq;
  34. if (irq >= MCFINT_VECBASE) {
  35. if (irq < MCFINT_VECBASE + 64)
  36. __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
  37. else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
  38. __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
  39. }
  40. }
  41. static int intc_irq_set_type(struct irq_data *d, unsigned int type)
  42. {
  43. unsigned int irq = d->irq;
  44. if (irq >= MCFINT_VECBASE) {
  45. if (irq < MCFINT_VECBASE + 64)
  46. __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
  47. else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
  48. __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
  49. }
  50. return 0;
  51. }
  52. static struct irq_chip intc_irq_chip = {
  53. .name = "CF-INTC",
  54. .irq_mask = intc_irq_mask,
  55. .irq_unmask = intc_irq_unmask,
  56. .irq_set_type = intc_irq_set_type,
  57. };
  58. void __init init_IRQ(void)
  59. {
  60. int irq;
  61. init_vectors();
  62. /* Mask all interrupt sources */
  63. __raw_writeb(0xff, MCFINTC0_SIMR);
  64. if (MCFINTC1_SIMR)
  65. __raw_writeb(0xff, MCFINTC1_SIMR);
  66. for (irq = 0; (irq < NR_IRQS); irq++) {
  67. set_irq_chip(irq, &intc_irq_chip);
  68. set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
  69. set_irq_handler(irq, handle_level_irq);
  70. }
  71. }