emu10k1_main.c 28 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Creative Labs, Inc.
  4. * Routines for control of EMU10K1 chips
  5. *
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
  7. * Added support for Audigy 2 Value.
  8. *
  9. *
  10. * BUGS:
  11. * --
  12. *
  13. * TODO:
  14. * --
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  29. *
  30. */
  31. #include <sound/driver.h>
  32. #include <linux/delay.h>
  33. #include <linux/init.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/pci.h>
  36. #include <linux/slab.h>
  37. #include <linux/vmalloc.h>
  38. #include <sound/core.h>
  39. #include <sound/emu10k1.h>
  40. #include "p16v.h"
  41. #if 0
  42. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Creative Labs, Inc.");
  43. MODULE_DESCRIPTION("Routines for control of EMU10K1 chips");
  44. MODULE_LICENSE("GPL");
  45. #endif
  46. /*************************************************************************
  47. * EMU10K1 init / done
  48. *************************************************************************/
  49. void snd_emu10k1_voice_init(emu10k1_t * emu, int ch)
  50. {
  51. snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
  52. snd_emu10k1_ptr_write(emu, IP, ch, 0);
  53. snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
  54. snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
  55. snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
  56. snd_emu10k1_ptr_write(emu, CPF, ch, 0);
  57. snd_emu10k1_ptr_write(emu, CCR, ch, 0);
  58. snd_emu10k1_ptr_write(emu, PSST, ch, 0);
  59. snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
  60. snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
  61. snd_emu10k1_ptr_write(emu, Z1, ch, 0);
  62. snd_emu10k1_ptr_write(emu, Z2, ch, 0);
  63. snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
  64. snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
  65. snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
  66. snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
  67. snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
  68. snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
  69. snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
  70. snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
  71. snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
  72. /*** these are last so OFF prevents writing ***/
  73. snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
  74. snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
  75. snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
  76. snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
  77. snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
  78. /* Audigy extra stuffs */
  79. if (emu->audigy) {
  80. snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
  81. snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
  82. snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
  83. snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
  84. snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
  85. snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
  86. snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
  87. }
  88. }
  89. static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
  90. {
  91. int ch, idx, err;
  92. unsigned int silent_page;
  93. emu->fx8010.itram_size = (16 * 1024)/2;
  94. emu->fx8010.etram_pages.area = NULL;
  95. emu->fx8010.etram_pages.bytes = 0;
  96. /* disable audio and lock cache */
  97. outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
  98. /* reset recording buffers */
  99. snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
  100. snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
  101. snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
  102. snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
  103. snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
  104. snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
  105. /* disable channel interrupt */
  106. outl(0, emu->port + INTE);
  107. snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
  108. snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
  109. snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
  110. snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
  111. if (emu->audigy){
  112. /* set SPDIF bypass mode */
  113. snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
  114. /* enable rear left + rear right AC97 slots */
  115. snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | AC97SLOT_REAR_LEFT);
  116. }
  117. /* init envelope engine */
  118. for (ch = 0; ch < NUM_G; ch++) {
  119. emu->voices[ch].emu = emu;
  120. emu->voices[ch].number = ch;
  121. snd_emu10k1_voice_init(emu, ch);
  122. }
  123. /*
  124. * Init to 0x02109204 :
  125. * Clock accuracy = 0 (1000ppm)
  126. * Sample Rate = 2 (48kHz)
  127. * Audio Channel = 1 (Left of 2)
  128. * Source Number = 0 (Unspecified)
  129. * Generation Status = 1 (Original for Cat Code 12)
  130. * Cat Code = 12 (Digital Signal Mixer)
  131. * Mode = 0 (Mode 0)
  132. * Emphasis = 0 (None)
  133. * CP = 1 (Copyright unasserted)
  134. * AN = 0 (Audio data)
  135. * P = 0 (Consumer)
  136. */
  137. snd_emu10k1_ptr_write(emu, SPCS0, 0,
  138. emu->spdif_bits[0] =
  139. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  140. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  141. SPCS_GENERATIONSTATUS | 0x00001200 |
  142. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  143. snd_emu10k1_ptr_write(emu, SPCS1, 0,
  144. emu->spdif_bits[1] =
  145. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  146. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  147. SPCS_GENERATIONSTATUS | 0x00001200 |
  148. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  149. snd_emu10k1_ptr_write(emu, SPCS2, 0,
  150. emu->spdif_bits[2] =
  151. SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
  152. SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
  153. SPCS_GENERATIONSTATUS | 0x00001200 |
  154. 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
  155. if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
  156. /* Hacks for Alice3 to work independent of haP16V driver */
  157. u32 tmp;
  158. //Setup SRCMulti_I2S SamplingRate
  159. tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
  160. tmp &= 0xfffff1ff;
  161. tmp |= (0x2<<9);
  162. snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
  163. /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
  164. snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
  165. /* Setup SRCMulti Input Audio Enable */
  166. /* Use 0xFFFFFFFF to enable P16V sounds. */
  167. snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
  168. /* Enabled Phased (8-channel) P16V playback */
  169. outl(0x0201, emu->port + HCFG2);
  170. /* Set playback routing. */
  171. snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
  172. }
  173. if (emu->audigy && (emu->serial == 0x10011102) ) { /* audigy2 Value */
  174. /* Hacks for Alice3 to work independent of haP16V driver */
  175. u32 tmp;
  176. snd_printk(KERN_ERR "Audigy2 value:Special config.\n");
  177. //Setup SRCMulti_I2S SamplingRate
  178. tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
  179. tmp &= 0xfffff1ff;
  180. tmp |= (0x2<<9);
  181. snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
  182. /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
  183. outl(0x600000, emu->port + 0x20);
  184. outl(0x14, emu->port + 0x24);
  185. /* Setup SRCMulti Input Audio Enable */
  186. outl(0x7b0000, emu->port + 0x20);
  187. outl(0xFF000000, emu->port + 0x24);
  188. /* Setup SPDIF Out Audio Enable */
  189. /* The Audigy 2 Value has a separate SPDIF out,
  190. * so no need for a mixer switch
  191. */
  192. outl(0x7a0000, emu->port + 0x20);
  193. outl(0xFF000000, emu->port + 0x24);
  194. tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
  195. outl(tmp, emu->port + A_IOCFG);
  196. }
  197. /*
  198. * Clear page with silence & setup all pointers to this page
  199. */
  200. memset(emu->silent_page.area, 0, PAGE_SIZE);
  201. silent_page = emu->silent_page.addr << 1;
  202. for (idx = 0; idx < MAXPAGES; idx++)
  203. ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
  204. snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
  205. snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
  206. snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
  207. silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
  208. for (ch = 0; ch < NUM_G; ch++) {
  209. snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
  210. snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
  211. }
  212. /*
  213. * Hokay, setup HCFG
  214. * Mute Disable Audio = 0
  215. * Lock Tank Memory = 1
  216. * Lock Sound Memory = 0
  217. * Auto Mute = 1
  218. */
  219. if (emu->audigy) {
  220. if (emu->revision == 4) /* audigy2 */
  221. outl(HCFG_AUDIOENABLE |
  222. HCFG_AC3ENABLE_CDSPDIF |
  223. HCFG_AC3ENABLE_GPSPDIF |
  224. HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
  225. else
  226. outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
  227. } else if (emu->model == 0x20 ||
  228. emu->model == 0xc400 ||
  229. (emu->model == 0x21 && emu->revision < 6))
  230. outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
  231. else
  232. // With on-chip joystick
  233. outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
  234. if (enable_ir) { /* enable IR for SB Live */
  235. if (emu->audigy) {
  236. unsigned int reg = inl(emu->port + A_IOCFG);
  237. outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
  238. udelay(500);
  239. outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
  240. udelay(100);
  241. outl(reg, emu->port + A_IOCFG);
  242. } else {
  243. unsigned int reg = inl(emu->port + HCFG);
  244. outl(reg | HCFG_GPOUT2, emu->port + HCFG);
  245. udelay(500);
  246. outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
  247. udelay(100);
  248. outl(reg, emu->port + HCFG);
  249. }
  250. }
  251. if (emu->audigy) { /* enable analog output */
  252. unsigned int reg = inl(emu->port + A_IOCFG);
  253. outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
  254. }
  255. /*
  256. * Initialize the effect engine
  257. */
  258. if ((err = snd_emu10k1_init_efx(emu)) < 0)
  259. return err;
  260. /*
  261. * Enable the audio bit
  262. */
  263. outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
  264. /* Enable analog/digital outs on audigy */
  265. if (emu->audigy) {
  266. outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
  267. if (emu->revision == 4) { /* audigy2 */
  268. /* Unmute Analog now. Set GPO6 to 1 for Apollo.
  269. * This has to be done after init ALice3 I2SOut beyond 48KHz.
  270. * So, sequence is important. */
  271. outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
  272. } else if (emu->serial == 0x10011102) { /* audigy2 value */
  273. /* Unmute Analog now. */
  274. outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
  275. } else {
  276. /* Disable routing from AC97 line out to Front speakers */
  277. outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
  278. }
  279. }
  280. #if 0
  281. {
  282. unsigned int tmp;
  283. /* FIXME: the following routine disables LiveDrive-II !! */
  284. // TOSLink detection
  285. emu->tos_link = 0;
  286. tmp = inl(emu->port + HCFG);
  287. if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
  288. outl(tmp|0x800, emu->port + HCFG);
  289. udelay(50);
  290. if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
  291. emu->tos_link = 1;
  292. outl(tmp, emu->port + HCFG);
  293. }
  294. }
  295. }
  296. #endif
  297. snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
  298. emu->reserved_page = (emu10k1_memblk_t *)snd_emu10k1_synth_alloc(emu, 4096);
  299. if (emu->reserved_page)
  300. emu->reserved_page->map_locked = 1;
  301. return 0;
  302. }
  303. static int snd_emu10k1_done(emu10k1_t * emu)
  304. {
  305. int ch;
  306. outl(0, emu->port + INTE);
  307. /*
  308. * Shutdown the chip
  309. */
  310. for (ch = 0; ch < NUM_G; ch++)
  311. snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
  312. for (ch = 0; ch < NUM_G; ch++) {
  313. snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
  314. snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
  315. snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
  316. snd_emu10k1_ptr_write(emu, CPF, ch, 0);
  317. }
  318. /* reset recording buffers */
  319. snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
  320. snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
  321. snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
  322. snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
  323. snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
  324. snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
  325. snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
  326. snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
  327. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  328. if (emu->audigy)
  329. snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
  330. else
  331. snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
  332. /* disable channel interrupt */
  333. snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
  334. snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
  335. snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
  336. snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
  337. /* remove reserved page */
  338. if (emu->reserved_page != NULL) {
  339. snd_emu10k1_synth_free(emu, (snd_util_memblk_t *)emu->reserved_page);
  340. emu->reserved_page = NULL;
  341. }
  342. /* disable audio and lock cache */
  343. outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
  344. snd_emu10k1_ptr_write(emu, PTB, 0, 0);
  345. snd_emu10k1_free_efx(emu);
  346. return 0;
  347. }
  348. /*************************************************************************
  349. * ECARD functional implementation
  350. *************************************************************************/
  351. /* In A1 Silicon, these bits are in the HC register */
  352. #define HOOKN_BIT (1L << 12)
  353. #define HANDN_BIT (1L << 11)
  354. #define PULSEN_BIT (1L << 10)
  355. #define EC_GDI1 (1 << 13)
  356. #define EC_GDI0 (1 << 14)
  357. #define EC_NUM_CONTROL_BITS 20
  358. #define EC_AC3_DATA_SELN 0x0001L
  359. #define EC_EE_DATA_SEL 0x0002L
  360. #define EC_EE_CNTRL_SELN 0x0004L
  361. #define EC_EECLK 0x0008L
  362. #define EC_EECS 0x0010L
  363. #define EC_EESDO 0x0020L
  364. #define EC_TRIM_CSN 0x0040L
  365. #define EC_TRIM_SCLK 0x0080L
  366. #define EC_TRIM_SDATA 0x0100L
  367. #define EC_TRIM_MUTEN 0x0200L
  368. #define EC_ADCCAL 0x0400L
  369. #define EC_ADCRSTN 0x0800L
  370. #define EC_DACCAL 0x1000L
  371. #define EC_DACMUTEN 0x2000L
  372. #define EC_LEDN 0x4000L
  373. #define EC_SPDIF0_SEL_SHIFT 15
  374. #define EC_SPDIF1_SEL_SHIFT 17
  375. #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
  376. #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
  377. #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
  378. #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
  379. #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
  380. * be incremented any time the EEPROM's
  381. * format is changed. */
  382. #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
  383. /* Addresses for special values stored in to EEPROM */
  384. #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
  385. #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
  386. #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
  387. #define EC_LAST_PROMFILE_ADDR 0x2f
  388. #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
  389. * can be up to 30 characters in length
  390. * and is stored as a NULL-terminated
  391. * ASCII string. Any unused bytes must be
  392. * filled with zeros */
  393. #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
  394. /* Most of this stuff is pretty self-evident. According to the hardware
  395. * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
  396. * offset problem. Weird.
  397. */
  398. #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
  399. EC_TRIM_CSN)
  400. #define EC_DEFAULT_ADC_GAIN 0xC4C4
  401. #define EC_DEFAULT_SPDIF0_SEL 0x0
  402. #define EC_DEFAULT_SPDIF1_SEL 0x4
  403. /**************************************************************************
  404. * @func Clock bits into the Ecard's control latch. The Ecard uses a
  405. * control latch will is loaded bit-serially by toggling the Modem control
  406. * lines from function 2 on the E8010. This function hides these details
  407. * and presents the illusion that we are actually writing to a distinct
  408. * register.
  409. */
  410. static void snd_emu10k1_ecard_write(emu10k1_t * emu, unsigned int value)
  411. {
  412. unsigned short count;
  413. unsigned int data;
  414. unsigned long hc_port;
  415. unsigned int hc_value;
  416. hc_port = emu->port + HCFG;
  417. hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
  418. outl(hc_value, hc_port);
  419. for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
  420. /* Set up the value */
  421. data = ((value & 0x1) ? PULSEN_BIT : 0);
  422. value >>= 1;
  423. outl(hc_value | data, hc_port);
  424. /* Clock the shift register */
  425. outl(hc_value | data | HANDN_BIT, hc_port);
  426. outl(hc_value | data, hc_port);
  427. }
  428. /* Latch the bits */
  429. outl(hc_value | HOOKN_BIT, hc_port);
  430. outl(hc_value, hc_port);
  431. }
  432. /**************************************************************************
  433. * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
  434. * trim value consists of a 16bit value which is composed of two
  435. * 8 bit gain/trim values, one for the left channel and one for the
  436. * right channel. The following table maps from the Gain/Attenuation
  437. * value in decibels into the corresponding bit pattern for a single
  438. * channel.
  439. */
  440. static void snd_emu10k1_ecard_setadcgain(emu10k1_t * emu,
  441. unsigned short gain)
  442. {
  443. unsigned int bit;
  444. /* Enable writing to the TRIM registers */
  445. snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
  446. /* Do it again to insure that we meet hold time requirements */
  447. snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
  448. for (bit = (1 << 15); bit; bit >>= 1) {
  449. unsigned int value;
  450. value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
  451. if (gain & bit)
  452. value |= EC_TRIM_SDATA;
  453. /* Clock the bit */
  454. snd_emu10k1_ecard_write(emu, value);
  455. snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
  456. snd_emu10k1_ecard_write(emu, value);
  457. }
  458. snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
  459. }
  460. static int __devinit snd_emu10k1_ecard_init(emu10k1_t * emu)
  461. {
  462. unsigned int hc_value;
  463. /* Set up the initial settings */
  464. emu->ecard_ctrl = EC_RAW_RUN_MODE |
  465. EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
  466. EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
  467. /* Step 0: Set the codec type in the hardware control register
  468. * and enable audio output */
  469. hc_value = inl(emu->port + HCFG);
  470. outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
  471. inl(emu->port + HCFG);
  472. /* Step 1: Turn off the led and deassert TRIM_CS */
  473. snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
  474. /* Step 2: Calibrate the ADC and DAC */
  475. snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
  476. /* Step 3: Wait for awhile; XXX We can't get away with this
  477. * under a real operating system; we'll need to block and wait that
  478. * way. */
  479. snd_emu10k1_wait(emu, 48000);
  480. /* Step 4: Switch off the DAC and ADC calibration. Note
  481. * That ADC_CAL is actually an inverted signal, so we assert
  482. * it here to stop calibration. */
  483. snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
  484. /* Step 4: Switch into run mode */
  485. snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
  486. /* Step 5: Set the analog input gain */
  487. snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
  488. return 0;
  489. }
  490. /*
  491. * Create the EMU10K1 instance
  492. */
  493. static int snd_emu10k1_free(emu10k1_t *emu)
  494. {
  495. if (emu->port) { /* avoid access to already used hardware */
  496. snd_emu10k1_fx8010_tram_setup(emu, 0);
  497. snd_emu10k1_done(emu);
  498. }
  499. if (emu->memhdr)
  500. snd_util_memhdr_free(emu->memhdr);
  501. if (emu->silent_page.area)
  502. snd_dma_free_pages(&emu->silent_page);
  503. if (emu->ptb_pages.area)
  504. snd_dma_free_pages(&emu->ptb_pages);
  505. vfree(emu->page_ptr_table);
  506. vfree(emu->page_addr_table);
  507. if (emu->irq >= 0)
  508. free_irq(emu->irq, (void *)emu);
  509. if (emu->port)
  510. pci_release_regions(emu->pci);
  511. pci_disable_device(emu->pci);
  512. if (emu->card_capabilities->ca0151_chip) /* P16V */
  513. snd_p16v_free(emu);
  514. kfree(emu);
  515. return 0;
  516. }
  517. static int snd_emu10k1_dev_free(snd_device_t *device)
  518. {
  519. emu10k1_t *emu = device->device_data;
  520. return snd_emu10k1_free(emu);
  521. }
  522. static emu_chip_details_t emu_chip_details[] = {
  523. /* Audigy 2 Value AC3 out does not work yet. Need to find out how to turn off interpolators.*/
  524. {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
  525. .driver = "Audigy2", .name = "Audigy 2 Value [SB0400]",
  526. .id = "Audigy2",
  527. .emu10k2_chip = 1,
  528. .ca0108_chip = 1,
  529. .spk71 = 1,
  530. .ac97_chip = 1} ,
  531. {.vendor = 0x1102, .device = 0x0008,
  532. .driver = "Audigy2", .name = "Audigy 2 Value [Unknown]",
  533. .id = "Audigy2",
  534. .emu10k2_chip = 1,
  535. .ca0108_chip = 1,
  536. .ac97_chip = 1} ,
  537. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
  538. .driver = "Audigy2", .name = "Audigy 4 PRO [SB0380]",
  539. .id = "Audigy2",
  540. .emu10k2_chip = 1,
  541. .ca0102_chip = 1,
  542. .ca0151_chip = 1,
  543. .spk71 = 1,
  544. .spdif_bug = 1,
  545. .ac97_chip = 1} ,
  546. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
  547. .driver = "Audigy2", .name = "Audigy 2 ZS [SB0350]",
  548. .id = "Audigy2",
  549. .emu10k2_chip = 1,
  550. .ca0102_chip = 1,
  551. .ca0151_chip = 1,
  552. .spk71 = 1,
  553. .spdif_bug = 1,
  554. .ac97_chip = 1} ,
  555. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
  556. .driver = "Audigy2", .name = "Audigy 2 ZS [2001]",
  557. .id = "Audigy2",
  558. .emu10k2_chip = 1,
  559. .ca0102_chip = 1,
  560. .ca0151_chip = 1,
  561. .spk71 = 1,
  562. .spdif_bug = 1,
  563. .ac97_chip = 1} ,
  564. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
  565. .driver = "Audigy2", .name = "Audigy 2 [SB0240]",
  566. .id = "Audigy2",
  567. .emu10k2_chip = 1,
  568. .ca0102_chip = 1,
  569. .ca0151_chip = 1,
  570. .spk71 = 1,
  571. .spdif_bug = 1,
  572. .ac97_chip = 1} ,
  573. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
  574. .driver = "Audigy2", .name = "Audigy 2 EX [1005]",
  575. .id = "Audigy2",
  576. .emu10k2_chip = 1,
  577. .ca0102_chip = 1,
  578. .ca0151_chip = 1,
  579. .spdif_bug = 1} ,
  580. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
  581. .driver = "Audigy2", .name = "Audigy 2 Platinum [SB0240P]",
  582. .id = "Audigy2",
  583. .emu10k2_chip = 1,
  584. .ca0102_chip = 1,
  585. .ca0151_chip = 1,
  586. .spk71 = 1,
  587. .spdif_bug = 1,
  588. .ac97_chip = 1} ,
  589. {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
  590. .driver = "Audigy2", .name = "Audigy 2 [Unknown]",
  591. .id = "Audigy2",
  592. .emu10k2_chip = 1,
  593. .ca0102_chip = 1,
  594. .ca0151_chip = 1,
  595. .spdif_bug = 1,
  596. .ac97_chip = 1} ,
  597. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10020052,
  598. .driver = "Audigy", .name = "Audigy 1 ES [SB0160]",
  599. .id = "Audigy",
  600. .emu10k2_chip = 1,
  601. .ca0102_chip = 1,
  602. .spdif_bug = 1,
  603. .ac97_chip = 1} ,
  604. {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
  605. .driver = "Audigy", .name = "Audigy 1 [SB0090]",
  606. .id = "Audigy",
  607. .emu10k2_chip = 1,
  608. .ca0102_chip = 1,
  609. .ac97_chip = 1} ,
  610. {.vendor = 0x1102, .device = 0x0004,
  611. .driver = "Audigy", .name = "Audigy 1 [Unknown]",
  612. .id = "Audigy",
  613. .emu10k2_chip = 1,
  614. .ca0102_chip = 1,
  615. .ac97_chip = 1} ,
  616. {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
  617. .driver = "EMU10K1", .name = "E-mu APS [4001]",
  618. .id = "APS",
  619. .emu10k1_chip = 1,
  620. .ecard = 1} ,
  621. {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
  622. .driver = "EMU10K1", .name = "SBLive! Player 5.1 [SB0060]",
  623. .id = "Live",
  624. .emu10k1_chip = 1,
  625. .ac97_chip = 1,
  626. .sblive51 = 1} ,
  627. {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
  628. .driver = "EMU10K1", .name = "SB Live 5.1",
  629. .id = "Live",
  630. .emu10k1_chip = 1,
  631. .ac97_chip = 1,
  632. .sblive51 = 1} ,
  633. {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
  634. .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]",
  635. .id = "Live",
  636. .emu10k1_chip = 1,
  637. .ac97_chip = 1} ,
  638. {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
  639. .driver = "EMU10K1", .name = "SBLive! Value [CT4832]",
  640. .id = "Live",
  641. .emu10k1_chip = 1,
  642. .ac97_chip = 1,
  643. .sblive51 = 1} ,
  644. {.vendor = 0x1102, .device = 0x0002,
  645. .driver = "EMU10K1", .name = "SB Live [Unknown]",
  646. .id = "Live",
  647. .emu10k1_chip = 1,
  648. .ac97_chip = 1,
  649. .sblive51 = 1} ,
  650. { } /* terminator */
  651. };
  652. int __devinit snd_emu10k1_create(snd_card_t * card,
  653. struct pci_dev * pci,
  654. unsigned short extin_mask,
  655. unsigned short extout_mask,
  656. long max_cache_bytes,
  657. int enable_ir,
  658. emu10k1_t ** remu)
  659. {
  660. emu10k1_t *emu;
  661. int err;
  662. int is_audigy;
  663. unsigned char revision;
  664. const emu_chip_details_t *c;
  665. static snd_device_ops_t ops = {
  666. .dev_free = snd_emu10k1_dev_free,
  667. };
  668. *remu = NULL;
  669. /* enable PCI device */
  670. if ((err = pci_enable_device(pci)) < 0)
  671. return err;
  672. emu = kcalloc(1, sizeof(*emu), GFP_KERNEL);
  673. if (emu == NULL) {
  674. pci_disable_device(pci);
  675. return -ENOMEM;
  676. }
  677. emu->card = card;
  678. spin_lock_init(&emu->reg_lock);
  679. spin_lock_init(&emu->emu_lock);
  680. spin_lock_init(&emu->voice_lock);
  681. spin_lock_init(&emu->synth_lock);
  682. spin_lock_init(&emu->memblk_lock);
  683. init_MUTEX(&emu->ptb_lock);
  684. init_MUTEX(&emu->fx8010.lock);
  685. INIT_LIST_HEAD(&emu->mapped_link_head);
  686. INIT_LIST_HEAD(&emu->mapped_order_link_head);
  687. emu->pci = pci;
  688. emu->irq = -1;
  689. emu->synth = NULL;
  690. emu->get_synth_voice = NULL;
  691. /* read revision & serial */
  692. pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
  693. emu->revision = revision;
  694. pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
  695. pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
  696. snd_printdd("vendor=0x%x, device=0x%x, subsystem_vendor_id=0x%x, subsystem_id=0x%x\n",pci->vendor, pci->device, emu->serial, emu->model);
  697. for (c = emu_chip_details; c->vendor; c++) {
  698. if (c->vendor == pci->vendor && c->device == pci->device) {
  699. if (c->subsystem && c->subsystem != emu->serial)
  700. continue;
  701. if (c->revision && c->revision != emu->revision)
  702. continue;
  703. break;
  704. }
  705. }
  706. if (c->vendor == 0) {
  707. snd_printk(KERN_ERR "emu10k1: Card not recognised\n");
  708. kfree(emu);
  709. pci_disable_device(pci);
  710. return -ENOENT;
  711. }
  712. emu->card_capabilities = c;
  713. if (c->subsystem != 0)
  714. snd_printdd("Sound card name=%s\n", c->name);
  715. else
  716. snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x\n", c->name, pci->vendor, pci->device, emu->serial);
  717. if (!*card->id && c->id) {
  718. int i, n = 0;
  719. strlcpy(card->id, c->id, sizeof(card->id));
  720. for (;;) {
  721. for (i = 0; i < snd_ecards_limit; i++) {
  722. if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
  723. break;
  724. }
  725. if (i >= snd_ecards_limit)
  726. break;
  727. n++;
  728. if (n >= SNDRV_CARDS)
  729. break;
  730. snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
  731. }
  732. }
  733. is_audigy = emu->audigy = c->emu10k2_chip;
  734. /* set the DMA transfer mask */
  735. emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
  736. if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
  737. pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
  738. snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
  739. kfree(emu);
  740. pci_disable_device(pci);
  741. return -ENXIO;
  742. }
  743. if (is_audigy)
  744. emu->gpr_base = A_FXGPREGBASE;
  745. else
  746. emu->gpr_base = FXGPREGBASE;
  747. if ((err = pci_request_regions(pci, "EMU10K1")) < 0) {
  748. kfree(emu);
  749. pci_disable_device(pci);
  750. return err;
  751. }
  752. emu->port = pci_resource_start(pci, 0);
  753. if (request_irq(pci->irq, snd_emu10k1_interrupt, SA_INTERRUPT|SA_SHIRQ, "EMU10K1", (void *)emu)) {
  754. snd_emu10k1_free(emu);
  755. return -EBUSY;
  756. }
  757. emu->irq = pci->irq;
  758. emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
  759. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  760. 32 * 1024, &emu->ptb_pages) < 0) {
  761. snd_emu10k1_free(emu);
  762. return -ENOMEM;
  763. }
  764. emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
  765. emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
  766. if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
  767. snd_emu10k1_free(emu);
  768. return -ENOMEM;
  769. }
  770. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  771. EMUPAGESIZE, &emu->silent_page) < 0) {
  772. snd_emu10k1_free(emu);
  773. return -ENOMEM;
  774. }
  775. emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
  776. if (emu->memhdr == NULL) {
  777. snd_emu10k1_free(emu);
  778. return -ENOMEM;
  779. }
  780. emu->memhdr->block_extra_size = sizeof(emu10k1_memblk_t) - sizeof(snd_util_memblk_t);
  781. pci_set_master(pci);
  782. emu->fx8010.fxbus_mask = 0x303f;
  783. if (extin_mask == 0)
  784. extin_mask = 0x3fcf;
  785. if (extout_mask == 0)
  786. extout_mask = 0x7fff;
  787. emu->fx8010.extin_mask = extin_mask;
  788. emu->fx8010.extout_mask = extout_mask;
  789. if (emu->card_capabilities->ecard) {
  790. if ((err = snd_emu10k1_ecard_init(emu)) < 0) {
  791. snd_emu10k1_free(emu);
  792. return err;
  793. }
  794. } else {
  795. /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
  796. does not support this, it shouldn't do any harm */
  797. snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
  798. }
  799. if ((err = snd_emu10k1_init(emu, enable_ir)) < 0) {
  800. snd_emu10k1_free(emu);
  801. return err;
  802. }
  803. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0) {
  804. snd_emu10k1_free(emu);
  805. return err;
  806. }
  807. snd_emu10k1_proc_init(emu);
  808. snd_card_set_dev(card, &pci->dev);
  809. *remu = emu;
  810. return 0;
  811. }
  812. /* memory.c */
  813. EXPORT_SYMBOL(snd_emu10k1_synth_alloc);
  814. EXPORT_SYMBOL(snd_emu10k1_synth_free);
  815. EXPORT_SYMBOL(snd_emu10k1_synth_bzero);
  816. EXPORT_SYMBOL(snd_emu10k1_synth_copy_from_user);
  817. EXPORT_SYMBOL(snd_emu10k1_memblk_map);
  818. /* voice.c */
  819. EXPORT_SYMBOL(snd_emu10k1_voice_alloc);
  820. EXPORT_SYMBOL(snd_emu10k1_voice_free);
  821. /* io.c */
  822. EXPORT_SYMBOL(snd_emu10k1_ptr_read);
  823. EXPORT_SYMBOL(snd_emu10k1_ptr_write);