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linux-vybrid_pu...
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arch
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powerpc
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kernel
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cpu_setup_power.S

cpu_setup_power.S 2.3 KB
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  1. /*
    2. 

  2.  * This file contains low level CPU setup functions.
    3. 

  3.  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or
    6. 

  6.  * modify it under the terms of the GNU General Public License
    7. 

  7.  * as published by the Free Software Foundation; either version
    8. 

  8.  * 2 of the License, or (at your option) any later version.
    9. 

  9.  *
    10. 

  10.  */
    11. 

  11. 

  12. #include <asm/processor.h>
    13. 

  13. #include <asm/page.h>
    14. 

  14. #include <asm/cputable.h>
    15. 

  15. #include <asm/ppc_asm.h>
    16. 

  16. #include <asm/asm-offsets.h>
    17. 

  17. #include <asm/cache.h>
    18. 

  18. 

  19. /* Entry: r3 = crap, r4 = ptr to cputable entry
    20. 

  20.  *
    21. 

  21.  * Note that we can be called twice for pseudo-PVRs
    22. 

  22.  */
    23. 

  23. _GLOBAL(__setup_cpu_power7)
    24. 

  24. 	mflr	r11
    25. 

  25. 	bl	__init_hvmode_206
    26. 

  26. 	mtlr	r11
    27. 

  27. 	beqlr
    28. 

  28. 	li	r0,0
    29. 

  29. 	mtspr	SPRN_LPID,r0
    30. 

  30. 	mfspr	r3,SPRN_LPCR
    31. 

  31. 	bl	__init_LPCR
    32. 

  32. 	bl	__init_TLB
    33. 

  33. 	mtlr	r11
    34. 

  34. 	blr
    35. 

  35. 

  36. _GLOBAL(__restore_cpu_power7)
    37. 

  37. 	mflr	r11
    38. 

  38. 	mfmsr	r3
    39. 

  39. 	rldicl.	r0,r3,4,63
    40. 

  40. 	beqlr
    41. 

  41. 	li	r0,0
    42. 

  42. 	mtspr	SPRN_LPID,r0
    43. 

  43. 	mfspr	r3,SPRN_LPCR
    44. 

  44. 	bl	__init_LPCR
    45. 

  45. 	bl	__init_TLB
    46. 

  46. 	mtlr	r11
    47. 

  47. 	blr
    48. 

  48. 

  49. _GLOBAL(__setup_cpu_power8)
    50. 

  50. 	mflr	r11
    51. 

  51. 	bl	__init_hvmode_206
    52. 

  52. 	mtlr	r11
    53. 

  53. 	beqlr
    54. 

  54. 	li	r0,0
    55. 

  55. 	mtspr	SPRN_LPID,r0
    56. 

  56. 	mfspr	r3,SPRN_LPCR
    57. 

  57. 	bl	__init_LPCR
    58. 

  58. 	bl	__init_TLB
    59. 

  59. 	mtlr	r11
    60. 

  60. 	blr
    61. 

  61. 

  62. _GLOBAL(__restore_cpu_power8)
    63. 

  63. 	mflr	r11
    64. 

  64. 	mfmsr	r3
    65. 

  65. 	rldicl.	r0,r3,4,63
    66. 

  66. 	beqlr
    67. 

  67. 	li	r0,0
    68. 

  68. 	mtspr	SPRN_LPID,r0
    69. 

  69. 	mfspr   r3,SPRN_LPCR
    70. 

  70. 	bl	__init_LPCR
    71. 

  71. 	bl	__init_TLB
    72. 

  72. 	mtlr	r11
    73. 

  73. 	blr
    74. 

  74. 

  75. __init_hvmode_206:
    76. 

  76. 	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
    77. 

  77. 	mfmsr	r3
    78. 

  78. 	rldicl.	r0,r3,4,63
    79. 

  79. 	bnelr
    80. 

  80. 	ld	r5,CPU_SPEC_FEATURES(r4)
    81. 

  81. 	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
    82. 

  82. 	xor	r5,r5,r6
    83. 

  83. 	std	r5,CPU_SPEC_FEATURES(r4)
    84. 

  84. 	blr
    85. 

  85. 

  86. __init_LPCR:
    87. 

  87. 	/* Setup a sane LPCR:
    88. 

  88. 	 *   Called with initial LPCR in R3
    89. 

  89. 	 *
    90. 

  90. 	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
    91. 

  91. 	 *   PECE = 0b111
    92. 

  92. 	 *   DPFD = 4
    93. 

  93. 	 *   HDICE = 0
    94. 

  94. 	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
    95. 

  95. 	 *   VRMASD = 0b10000 (L=1, LP=00)
    96. 

  96. 	 *
    97. 

  97. 	 * Other bits untouched for now
    98. 

  98. 	 */
    99. 

  99. 	li	r5,1
    100. 

  100. 	rldimi	r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
    101. 

  101. 	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
    102. 

  102. 	li	r5,4
    103. 

  103. 	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
    104. 

  104. 	clrrdi	r3,r3,1		/* clear HDICE */
    105. 

  105. 	li	r5,4
    106. 

  106. 	rldimi	r3,r5, LPCR_VC_SH, 0
    107. 

  107. 	li	r5,0x10
    108. 

  108. 	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
    109. 

  109. 	mtspr	SPRN_LPCR,r3
    110. 

  110. 	isync
    111. 

  111. 	blr
    112. 

  112. 

  113. __init_TLB:
    114. 

  114. 	/* Clear the TLB */
    115. 

  115. 	li	r6,128
    116. 

  116. 	mtctr	r6
    117. 

  117. 	li	r7,0xc00	/* IS field = 0b11 */
    118. 

  118. 	ptesync
    119. 

  119. 2:	tlbiel	r7
    120. 

  120. 	addi	r7,r7,0x1000
    121. 

  121. 	bdnz	2b
    122. 

  122. 	ptesync
    123. 

  123. 1:	blr
    124.