netxen_nic_init.c 38 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. struct crb_addr_pair {
  35. u32 addr;
  36. u32 data;
  37. };
  38. #define NETXEN_MAX_CRB_XFORM 60
  39. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  40. #define NETXEN_ADDR_ERROR (0xffffffff)
  41. #define crb_addr_transform(name) \
  42. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  43. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  44. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  45. static void
  46. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  47. struct nx_host_rds_ring *rds_ring);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  103. {
  104. struct netxen_recv_context *recv_ctx;
  105. struct nx_host_rds_ring *rds_ring;
  106. struct netxen_rx_buffer *rx_buf;
  107. int i, ring;
  108. recv_ctx = &adapter->recv_ctx;
  109. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  110. rds_ring = &recv_ctx->rds_rings[ring];
  111. for (i = 0; i < rds_ring->num_desc; ++i) {
  112. rx_buf = &(rds_ring->rx_buf_arr[i]);
  113. if (rx_buf->state == NETXEN_BUFFER_FREE)
  114. continue;
  115. pci_unmap_single(adapter->pdev,
  116. rx_buf->dma,
  117. rds_ring->dma_size,
  118. PCI_DMA_FROMDEVICE);
  119. if (rx_buf->skb != NULL)
  120. dev_kfree_skb_any(rx_buf->skb);
  121. }
  122. }
  123. }
  124. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  125. {
  126. struct netxen_cmd_buffer *cmd_buf;
  127. struct netxen_skb_frag *buffrag;
  128. int i, j;
  129. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  130. cmd_buf = tx_ring->cmd_buf_arr;
  131. for (i = 0; i < tx_ring->num_desc; i++) {
  132. buffrag = cmd_buf->frag_array;
  133. if (buffrag->dma) {
  134. pci_unmap_single(adapter->pdev, buffrag->dma,
  135. buffrag->length, PCI_DMA_TODEVICE);
  136. buffrag->dma = 0ULL;
  137. }
  138. for (j = 0; j < cmd_buf->frag_count; j++) {
  139. buffrag++;
  140. if (buffrag->dma) {
  141. pci_unmap_page(adapter->pdev, buffrag->dma,
  142. buffrag->length,
  143. PCI_DMA_TODEVICE);
  144. buffrag->dma = 0ULL;
  145. }
  146. }
  147. if (cmd_buf->skb) {
  148. dev_kfree_skb_any(cmd_buf->skb);
  149. cmd_buf->skb = NULL;
  150. }
  151. cmd_buf++;
  152. }
  153. }
  154. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  155. {
  156. struct netxen_recv_context *recv_ctx;
  157. struct nx_host_rds_ring *rds_ring;
  158. struct nx_host_tx_ring *tx_ring;
  159. int ring;
  160. recv_ctx = &adapter->recv_ctx;
  161. if (recv_ctx->rds_rings == NULL)
  162. goto skip_rds;
  163. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  164. rds_ring = &recv_ctx->rds_rings[ring];
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. kfree(recv_ctx->rds_rings);
  169. skip_rds:
  170. if (adapter->tx_ring == NULL)
  171. return;
  172. tx_ring = adapter->tx_ring;
  173. vfree(tx_ring->cmd_buf_arr);
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. return -ENOMEM;
  201. }
  202. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  203. tx_ring->cmd_buf_arr = cmd_buf_arr;
  204. recv_ctx = &adapter->recv_ctx;
  205. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  206. rds_ring = kzalloc(size, GFP_KERNEL);
  207. if (rds_ring == NULL) {
  208. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  209. netdev->name);
  210. return -ENOMEM;
  211. }
  212. recv_ctx->rds_rings = rds_ring;
  213. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  214. rds_ring = &recv_ctx->rds_rings[ring];
  215. switch (ring) {
  216. case RCV_RING_NORMAL:
  217. rds_ring->num_desc = adapter->num_rxd;
  218. if (adapter->ahw.cut_through) {
  219. rds_ring->dma_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. rds_ring->skb_size =
  222. NX_CT_DEFAULT_RX_BUF_LEN;
  223. } else {
  224. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  225. rds_ring->dma_size =
  226. NX_P3_RX_BUF_MAX_LEN;
  227. else
  228. rds_ring->dma_size =
  229. NX_P2_RX_BUF_MAX_LEN;
  230. rds_ring->skb_size =
  231. rds_ring->dma_size + NET_IP_ALIGN;
  232. }
  233. break;
  234. case RCV_RING_JUMBO:
  235. rds_ring->num_desc = adapter->num_jumbo_rxd;
  236. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  237. rds_ring->dma_size =
  238. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  239. else
  240. rds_ring->dma_size =
  241. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  242. if (adapter->capabilities & NX_CAP0_HW_LRO)
  243. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  244. rds_ring->skb_size =
  245. rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. case RCV_RING_LRO:
  248. rds_ring->num_desc = adapter->num_lro_rxd;
  249. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  250. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  251. break;
  252. }
  253. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  254. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  255. if (rds_ring->rx_buf_arr == NULL) {
  256. printk(KERN_ERR "%s: Failed to allocate "
  257. "rx buffer ring %d\n",
  258. netdev->name, ring);
  259. /* free whatever was already allocated */
  260. goto err_out;
  261. }
  262. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  263. INIT_LIST_HEAD(&rds_ring->free_list);
  264. /*
  265. * Now go through all of them, set reference handles
  266. * and put them in the queues.
  267. */
  268. rx_buf = rds_ring->rx_buf_arr;
  269. for (i = 0; i < rds_ring->num_desc; i++) {
  270. list_add_tail(&rx_buf->list,
  271. &rds_ring->free_list);
  272. rx_buf->ref_handle = i;
  273. rx_buf->state = NETXEN_BUFFER_FREE;
  274. rx_buf++;
  275. }
  276. spin_lock_init(&rds_ring->lock);
  277. }
  278. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  279. sds_ring = &recv_ctx->sds_rings[ring];
  280. sds_ring->irq = adapter->msix_entries[ring].vector;
  281. sds_ring->adapter = adapter;
  282. sds_ring->num_desc = adapter->num_rxd;
  283. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  284. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  285. }
  286. return 0;
  287. err_out:
  288. netxen_free_sw_resources(adapter);
  289. return -ENOMEM;
  290. }
  291. /*
  292. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  293. * address to external PCI CRB address.
  294. */
  295. static u32 netxen_decode_crb_addr(u32 addr)
  296. {
  297. int i;
  298. u32 base_addr, offset, pci_base;
  299. crb_addr_transform_setup();
  300. pci_base = NETXEN_ADDR_ERROR;
  301. base_addr = addr & 0xfff00000;
  302. offset = addr & 0x000fffff;
  303. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  304. if (crb_addr_xform[i] == base_addr) {
  305. pci_base = i << 20;
  306. break;
  307. }
  308. }
  309. if (pci_base == NETXEN_ADDR_ERROR)
  310. return pci_base;
  311. else
  312. return (pci_base + offset);
  313. }
  314. #define NETXEN_MAX_ROM_WAIT_USEC 100
  315. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  316. {
  317. long timeout = 0;
  318. long done = 0;
  319. cond_resched();
  320. while (done == 0) {
  321. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  322. done &= 2;
  323. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  324. dev_err(&adapter->pdev->dev,
  325. "Timeout reached waiting for rom done");
  326. return -EIO;
  327. }
  328. udelay(1);
  329. }
  330. return 0;
  331. }
  332. static int do_rom_fast_read(struct netxen_adapter *adapter,
  333. int addr, int *valp)
  334. {
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  336. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  337. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  338. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  339. if (netxen_wait_rom_done(adapter)) {
  340. printk("Error waiting for rom done\n");
  341. return -EIO;
  342. }
  343. /* reset abyte_cnt and dummy_byte_cnt */
  344. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  345. udelay(10);
  346. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  347. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  348. return 0;
  349. }
  350. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  351. u8 *bytes, size_t size)
  352. {
  353. int addridx;
  354. int ret = 0;
  355. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  356. int v;
  357. ret = do_rom_fast_read(adapter, addridx, &v);
  358. if (ret != 0)
  359. break;
  360. *(__le32 *)bytes = cpu_to_le32(v);
  361. bytes += 4;
  362. }
  363. return ret;
  364. }
  365. int
  366. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  367. u8 *bytes, size_t size)
  368. {
  369. int ret;
  370. ret = netxen_rom_lock(adapter);
  371. if (ret < 0)
  372. return ret;
  373. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  374. netxen_rom_unlock(adapter);
  375. return ret;
  376. }
  377. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  378. {
  379. int ret;
  380. if (netxen_rom_lock(adapter) != 0)
  381. return -EIO;
  382. ret = do_rom_fast_read(adapter, addr, valp);
  383. netxen_rom_unlock(adapter);
  384. return ret;
  385. }
  386. #define NETXEN_BOARDTYPE 0x4008
  387. #define NETXEN_BOARDNUM 0x400c
  388. #define NETXEN_CHIPNUM 0x4010
  389. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  390. {
  391. int addr, val;
  392. int i, n, init_delay = 0;
  393. struct crb_addr_pair *buf;
  394. unsigned offset;
  395. u32 off;
  396. /* resetall */
  397. netxen_rom_lock(adapter);
  398. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  399. netxen_rom_unlock(adapter);
  400. if (verbose) {
  401. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  402. printk("P2 ROM board type: 0x%08x\n", val);
  403. else
  404. printk("Could not read board type\n");
  405. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  406. printk("P2 ROM board num: 0x%08x\n", val);
  407. else
  408. printk("Could not read board number\n");
  409. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  410. printk("P2 ROM chip num: 0x%08x\n", val);
  411. else
  412. printk("Could not read chip number\n");
  413. }
  414. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  415. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  416. (n != 0xcafecafe) ||
  417. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  418. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  419. "n: %08x\n", netxen_nic_driver_name, n);
  420. return -EIO;
  421. }
  422. offset = n & 0xffffU;
  423. n = (n >> 16) & 0xffffU;
  424. } else {
  425. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  426. !(n & 0x80000000)) {
  427. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  428. "n: %08x\n", netxen_nic_driver_name, n);
  429. return -EIO;
  430. }
  431. offset = 1;
  432. n &= ~0x80000000;
  433. }
  434. if (n < 1024) {
  435. if (verbose)
  436. printk(KERN_DEBUG "%s: %d CRB init values found"
  437. " in ROM.\n", netxen_nic_driver_name, n);
  438. } else {
  439. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  440. " initialized.\n", __func__, n);
  441. return -EIO;
  442. }
  443. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  444. if (buf == NULL) {
  445. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  446. netxen_nic_driver_name);
  447. return -ENOMEM;
  448. }
  449. for (i = 0; i < n; i++) {
  450. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  451. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  452. kfree(buf);
  453. return -EIO;
  454. }
  455. buf[i].addr = addr;
  456. buf[i].data = val;
  457. if (verbose)
  458. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  459. netxen_nic_driver_name,
  460. (u32)netxen_decode_crb_addr(addr), val);
  461. }
  462. for (i = 0; i < n; i++) {
  463. off = netxen_decode_crb_addr(buf[i].addr);
  464. if (off == NETXEN_ADDR_ERROR) {
  465. printk(KERN_ERR"CRB init value out of range %x\n",
  466. buf[i].addr);
  467. continue;
  468. }
  469. off += NETXEN_PCI_CRBSPACE;
  470. /* skipping cold reboot MAGIC */
  471. if (off == NETXEN_CAM_RAM(0x1fc))
  472. continue;
  473. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  474. /* do not reset PCI */
  475. if (off == (ROMUSB_GLB + 0xbc))
  476. continue;
  477. if (off == (ROMUSB_GLB + 0xa8))
  478. continue;
  479. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  480. continue;
  481. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  482. continue;
  483. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  484. continue;
  485. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  486. buf[i].data = 0x1020;
  487. /* skip the function enable register */
  488. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  489. continue;
  490. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  491. continue;
  492. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  493. continue;
  494. }
  495. if (off == NETXEN_ADDR_ERROR) {
  496. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  497. netxen_nic_driver_name, buf[i].addr);
  498. continue;
  499. }
  500. init_delay = 1;
  501. /* After writing this register, HW needs time for CRB */
  502. /* to quiet down (else crb_window returns 0xffffffff) */
  503. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  504. init_delay = 1000;
  505. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  506. /* hold xdma in reset also */
  507. buf[i].data = NETXEN_NIC_XDMA_RESET;
  508. buf[i].data = 0x8000ff;
  509. }
  510. }
  511. NXWR32(adapter, off, buf[i].data);
  512. msleep(init_delay);
  513. }
  514. kfree(buf);
  515. /* disable_peg_cache_all */
  516. /* unreset_net_cache */
  517. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  518. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  519. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  520. }
  521. /* p2dn replyCount */
  522. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  523. /* disable_peg_cache 0 */
  524. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  525. /* disable_peg_cache 1 */
  526. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  527. /* peg_clr_all */
  528. /* peg_clr 0 */
  529. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  530. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  531. /* peg_clr 1 */
  532. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  533. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  534. /* peg_clr 2 */
  535. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  536. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  537. /* peg_clr 3 */
  538. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  539. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  540. return 0;
  541. }
  542. int
  543. netxen_need_fw_reset(struct netxen_adapter *adapter)
  544. {
  545. u32 count, old_count;
  546. u32 val, version, major, minor, build;
  547. int i, timeout;
  548. u8 fw_type;
  549. /* NX2031 firmware doesn't support heartbit */
  550. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  551. return 1;
  552. /* last attempt had failed */
  553. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  554. return 1;
  555. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  556. for (i = 0; i < 10; i++) {
  557. timeout = msleep_interruptible(200);
  558. if (timeout) {
  559. NXWR32(adapter, CRB_CMDPEG_STATE,
  560. PHAN_INITIALIZE_FAILED);
  561. return -EINTR;
  562. }
  563. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  564. if (count != old_count)
  565. break;
  566. }
  567. /* firmware is dead */
  568. if (count == old_count)
  569. return 1;
  570. /* check if we have got newer or different file firmware */
  571. if (adapter->fw) {
  572. const struct firmware *fw = adapter->fw;
  573. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  574. version = NETXEN_DECODE_VERSION(val);
  575. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  576. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  577. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  578. if (version > NETXEN_VERSION_CODE(major, minor, build))
  579. return 1;
  580. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  581. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  582. fw_type = (val & 0x4) ?
  583. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  584. if (adapter->fw_type != fw_type)
  585. return 1;
  586. }
  587. }
  588. return 0;
  589. }
  590. static char *fw_name[] = {
  591. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  592. };
  593. int
  594. netxen_load_firmware(struct netxen_adapter *adapter)
  595. {
  596. u64 *ptr64;
  597. u32 i, flashaddr, size;
  598. const struct firmware *fw = adapter->fw;
  599. struct pci_dev *pdev = adapter->pdev;
  600. dev_info(&pdev->dev, "loading firmware from %s\n",
  601. fw_name[adapter->fw_type]);
  602. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  603. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  604. if (fw) {
  605. __le64 data;
  606. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  607. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  608. flashaddr = NETXEN_BOOTLD_START;
  609. for (i = 0; i < size; i++) {
  610. data = cpu_to_le64(ptr64[i]);
  611. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  612. flashaddr += 8;
  613. }
  614. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  615. size = (__force u32)cpu_to_le32(size) / 8;
  616. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  617. flashaddr = NETXEN_IMAGE_START;
  618. for (i = 0; i < size; i++) {
  619. data = cpu_to_le64(ptr64[i]);
  620. if (adapter->pci_mem_write(adapter,
  621. flashaddr, &data, 8))
  622. return -EIO;
  623. flashaddr += 8;
  624. }
  625. } else {
  626. u64 data;
  627. u32 hi, lo;
  628. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  629. flashaddr = NETXEN_BOOTLD_START;
  630. for (i = 0; i < size; i++) {
  631. if (netxen_rom_fast_read(adapter,
  632. flashaddr, &lo) != 0)
  633. return -EIO;
  634. if (netxen_rom_fast_read(adapter,
  635. flashaddr + 4, &hi) != 0)
  636. return -EIO;
  637. /* hi, lo are already in host endian byteorder */
  638. data = (((u64)hi << 32) | lo);
  639. if (adapter->pci_mem_write(adapter,
  640. flashaddr, &data, 8))
  641. return -EIO;
  642. flashaddr += 8;
  643. }
  644. }
  645. msleep(1);
  646. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  647. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  648. else {
  649. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  650. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  651. }
  652. return 0;
  653. }
  654. static int
  655. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  656. {
  657. __le32 val;
  658. u32 ver, min_ver, bios;
  659. struct pci_dev *pdev = adapter->pdev;
  660. const struct firmware *fw = adapter->fw;
  661. if (fw->size < NX_FW_MIN_SIZE)
  662. return -EINVAL;
  663. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  664. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  665. return -EINVAL;
  666. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  667. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  668. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  669. else
  670. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  671. ver = NETXEN_DECODE_VERSION(val);
  672. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  673. dev_err(&pdev->dev,
  674. "%s: firmware version %d.%d.%d unsupported\n",
  675. fwname, _major(ver), _minor(ver), _build(ver));
  676. return -EINVAL;
  677. }
  678. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  679. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  680. if ((__force u32)val != bios) {
  681. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  682. fwname);
  683. return -EINVAL;
  684. }
  685. /* check if flashed firmware is newer */
  686. if (netxen_rom_fast_read(adapter,
  687. NX_FW_VERSION_OFFSET, (int *)&val))
  688. return -EIO;
  689. val = NETXEN_DECODE_VERSION(val);
  690. if (val > ver) {
  691. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  692. fwname);
  693. return -EINVAL;
  694. }
  695. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  696. return 0;
  697. }
  698. static int
  699. netxen_p3_has_mn(struct netxen_adapter *adapter)
  700. {
  701. u32 capability, flashed_ver;
  702. capability = 0;
  703. netxen_rom_fast_read(adapter,
  704. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  705. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  706. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  707. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  708. if (capability & NX_PEG_TUNE_MN_PRESENT)
  709. return 1;
  710. }
  711. return 0;
  712. }
  713. void netxen_request_firmware(struct netxen_adapter *adapter)
  714. {
  715. u8 fw_type;
  716. struct pci_dev *pdev = adapter->pdev;
  717. int rc = 0;
  718. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  719. fw_type = NX_P2_MN_ROMIMAGE;
  720. goto request_fw;
  721. }
  722. fw_type = netxen_p3_has_mn(adapter) ?
  723. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  724. request_fw:
  725. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  726. if (rc != 0) {
  727. if (fw_type == NX_P3_MN_ROMIMAGE) {
  728. msleep(1);
  729. fw_type = NX_P3_CT_ROMIMAGE;
  730. goto request_fw;
  731. }
  732. fw_type = NX_FLASH_ROMIMAGE;
  733. adapter->fw = NULL;
  734. goto done;
  735. }
  736. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  737. if (rc != 0) {
  738. release_firmware(adapter->fw);
  739. if (fw_type == NX_P3_MN_ROMIMAGE) {
  740. msleep(1);
  741. fw_type = NX_P3_CT_ROMIMAGE;
  742. goto request_fw;
  743. }
  744. fw_type = NX_FLASH_ROMIMAGE;
  745. adapter->fw = NULL;
  746. goto done;
  747. }
  748. done:
  749. adapter->fw_type = fw_type;
  750. }
  751. void
  752. netxen_release_firmware(struct netxen_adapter *adapter)
  753. {
  754. if (adapter->fw)
  755. release_firmware(adapter->fw);
  756. adapter->fw = NULL;
  757. }
  758. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  759. {
  760. u64 addr;
  761. u32 hi, lo;
  762. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  763. return 0;
  764. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  765. NETXEN_HOST_DUMMY_DMA_SIZE,
  766. &adapter->dummy_dma.phys_addr);
  767. if (adapter->dummy_dma.addr == NULL) {
  768. dev_err(&adapter->pdev->dev,
  769. "ERROR: Could not allocate dummy DMA memory\n");
  770. return -ENOMEM;
  771. }
  772. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  773. hi = (addr >> 32) & 0xffffffff;
  774. lo = addr & 0xffffffff;
  775. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  776. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  777. return 0;
  778. }
  779. /*
  780. * NetXen DMA watchdog control:
  781. *
  782. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  783. * Bit 1 : disable_request => 1 req disable dma watchdog
  784. * Bit 2 : enable_request => 1 req enable dma watchdog
  785. * Bit 3-31 : unused
  786. */
  787. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  788. {
  789. int i = 100;
  790. u32 ctrl;
  791. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  792. return;
  793. if (!adapter->dummy_dma.addr)
  794. return;
  795. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  796. if ((ctrl & 0x1) != 0) {
  797. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  798. while ((ctrl & 0x1) != 0) {
  799. msleep(50);
  800. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  801. if (--i == 0)
  802. break;
  803. };
  804. }
  805. if (i) {
  806. pci_free_consistent(adapter->pdev,
  807. NETXEN_HOST_DUMMY_DMA_SIZE,
  808. adapter->dummy_dma.addr,
  809. adapter->dummy_dma.phys_addr);
  810. adapter->dummy_dma.addr = NULL;
  811. } else
  812. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  813. }
  814. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  815. {
  816. u32 val = 0;
  817. int retries = 60;
  818. if (pegtune_val)
  819. return 0;
  820. do {
  821. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  822. switch (val) {
  823. case PHAN_INITIALIZE_COMPLETE:
  824. case PHAN_INITIALIZE_ACK:
  825. return 0;
  826. case PHAN_INITIALIZE_FAILED:
  827. goto out_err;
  828. default:
  829. break;
  830. }
  831. msleep(500);
  832. } while (--retries);
  833. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  834. out_err:
  835. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  836. return -EIO;
  837. }
  838. static int
  839. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  840. {
  841. u32 val = 0;
  842. int retries = 2000;
  843. do {
  844. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  845. if (val == PHAN_PEG_RCV_INITIALIZED)
  846. return 0;
  847. msleep(10);
  848. } while (--retries);
  849. if (!retries) {
  850. printk(KERN_ERR "Receive Peg initialization not "
  851. "complete, state: 0x%x.\n", val);
  852. return -EIO;
  853. }
  854. return 0;
  855. }
  856. int netxen_init_firmware(struct netxen_adapter *adapter)
  857. {
  858. int err;
  859. err = netxen_receive_peg_ready(adapter);
  860. if (err)
  861. return err;
  862. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  863. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  864. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  865. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  866. return err;
  867. }
  868. static void
  869. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  870. {
  871. u32 cable_OUI;
  872. u16 cable_len;
  873. u16 link_speed;
  874. u8 link_status, module, duplex, autoneg;
  875. struct net_device *netdev = adapter->netdev;
  876. adapter->has_link_events = 1;
  877. cable_OUI = msg->body[1] & 0xffffffff;
  878. cable_len = (msg->body[1] >> 32) & 0xffff;
  879. link_speed = (msg->body[1] >> 48) & 0xffff;
  880. link_status = msg->body[2] & 0xff;
  881. duplex = (msg->body[2] >> 16) & 0xff;
  882. autoneg = (msg->body[2] >> 24) & 0xff;
  883. module = (msg->body[2] >> 8) & 0xff;
  884. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  885. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  886. netdev->name, cable_OUI, cable_len);
  887. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  888. printk(KERN_INFO "%s: unsupported cable length %d\n",
  889. netdev->name, cable_len);
  890. }
  891. netxen_advert_link_change(adapter, link_status);
  892. /* update link parameters */
  893. if (duplex == LINKEVENT_FULL_DUPLEX)
  894. adapter->link_duplex = DUPLEX_FULL;
  895. else
  896. adapter->link_duplex = DUPLEX_HALF;
  897. adapter->module_type = module;
  898. adapter->link_autoneg = autoneg;
  899. adapter->link_speed = link_speed;
  900. }
  901. static void
  902. netxen_handle_fw_message(int desc_cnt, int index,
  903. struct nx_host_sds_ring *sds_ring)
  904. {
  905. nx_fw_msg_t msg;
  906. struct status_desc *desc;
  907. int i = 0, opcode;
  908. while (desc_cnt > 0 && i < 8) {
  909. desc = &sds_ring->desc_head[index];
  910. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  911. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  912. index = get_next_index(index, sds_ring->num_desc);
  913. desc_cnt--;
  914. }
  915. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  916. switch (opcode) {
  917. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  918. netxen_handle_linkevent(sds_ring->adapter, &msg);
  919. break;
  920. default:
  921. break;
  922. }
  923. }
  924. static int
  925. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  926. struct nx_host_rds_ring *rds_ring,
  927. struct netxen_rx_buffer *buffer)
  928. {
  929. struct sk_buff *skb;
  930. dma_addr_t dma;
  931. struct pci_dev *pdev = adapter->pdev;
  932. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  933. if (!buffer->skb)
  934. return 1;
  935. skb = buffer->skb;
  936. if (!adapter->ahw.cut_through)
  937. skb_reserve(skb, 2);
  938. dma = pci_map_single(pdev, skb->data,
  939. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  940. if (pci_dma_mapping_error(pdev, dma)) {
  941. dev_kfree_skb_any(skb);
  942. buffer->skb = NULL;
  943. return 1;
  944. }
  945. buffer->skb = skb;
  946. buffer->dma = dma;
  947. buffer->state = NETXEN_BUFFER_BUSY;
  948. return 0;
  949. }
  950. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  951. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  952. {
  953. struct netxen_rx_buffer *buffer;
  954. struct sk_buff *skb;
  955. buffer = &rds_ring->rx_buf_arr[index];
  956. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  957. PCI_DMA_FROMDEVICE);
  958. skb = buffer->skb;
  959. if (!skb)
  960. goto no_skb;
  961. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  962. adapter->stats.csummed++;
  963. skb->ip_summed = CHECKSUM_UNNECESSARY;
  964. } else
  965. skb->ip_summed = CHECKSUM_NONE;
  966. skb->dev = adapter->netdev;
  967. buffer->skb = NULL;
  968. no_skb:
  969. buffer->state = NETXEN_BUFFER_FREE;
  970. return skb;
  971. }
  972. static struct netxen_rx_buffer *
  973. netxen_process_rcv(struct netxen_adapter *adapter,
  974. struct nx_host_sds_ring *sds_ring,
  975. int ring, u64 sts_data0)
  976. {
  977. struct net_device *netdev = adapter->netdev;
  978. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  979. struct netxen_rx_buffer *buffer;
  980. struct sk_buff *skb;
  981. struct nx_host_rds_ring *rds_ring;
  982. int index, length, cksum, pkt_offset;
  983. if (unlikely(ring >= adapter->max_rds_rings))
  984. return NULL;
  985. rds_ring = &recv_ctx->rds_rings[ring];
  986. index = netxen_get_sts_refhandle(sts_data0);
  987. if (unlikely(index >= rds_ring->num_desc))
  988. return NULL;
  989. buffer = &rds_ring->rx_buf_arr[index];
  990. length = netxen_get_sts_totallength(sts_data0);
  991. cksum = netxen_get_sts_status(sts_data0);
  992. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  993. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  994. if (!skb)
  995. return buffer;
  996. if (length > rds_ring->skb_size)
  997. skb_put(skb, rds_ring->skb_size);
  998. else
  999. skb_put(skb, length);
  1000. if (pkt_offset)
  1001. skb_pull(skb, pkt_offset);
  1002. skb->truesize = skb->len + sizeof(struct sk_buff);
  1003. skb->protocol = eth_type_trans(skb, netdev);
  1004. napi_gro_receive(&sds_ring->napi, skb);
  1005. adapter->stats.rx_pkts++;
  1006. adapter->stats.rxbytes += length;
  1007. return buffer;
  1008. }
  1009. #define TCP_HDR_SIZE 20
  1010. #define TCP_TS_OPTION_SIZE 12
  1011. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1012. static struct netxen_rx_buffer *
  1013. netxen_process_lro(struct netxen_adapter *adapter,
  1014. struct nx_host_sds_ring *sds_ring,
  1015. int ring, u64 sts_data0, u64 sts_data1)
  1016. {
  1017. struct net_device *netdev = adapter->netdev;
  1018. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1019. struct netxen_rx_buffer *buffer;
  1020. struct sk_buff *skb;
  1021. struct nx_host_rds_ring *rds_ring;
  1022. struct iphdr *iph;
  1023. struct tcphdr *th;
  1024. bool push, timestamp;
  1025. int l2_hdr_offset, l4_hdr_offset;
  1026. int index;
  1027. u16 lro_length, length, data_offset;
  1028. u32 seq_number;
  1029. if (unlikely(ring > adapter->max_rds_rings))
  1030. return NULL;
  1031. rds_ring = &recv_ctx->rds_rings[ring];
  1032. index = netxen_get_lro_sts_refhandle(sts_data0);
  1033. if (unlikely(index > rds_ring->num_desc))
  1034. return NULL;
  1035. buffer = &rds_ring->rx_buf_arr[index];
  1036. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1037. lro_length = netxen_get_lro_sts_length(sts_data0);
  1038. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1039. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1040. push = netxen_get_lro_sts_push_flag(sts_data0);
  1041. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1042. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1043. if (!skb)
  1044. return buffer;
  1045. if (timestamp)
  1046. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1047. else
  1048. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1049. skb_put(skb, lro_length + data_offset);
  1050. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1051. skb_pull(skb, l2_hdr_offset);
  1052. skb->protocol = eth_type_trans(skb, netdev);
  1053. iph = (struct iphdr *)skb->data;
  1054. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1055. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1056. iph->tot_len = htons(length);
  1057. iph->check = 0;
  1058. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1059. th->psh = push;
  1060. th->seq = htonl(seq_number);
  1061. length = skb->len;
  1062. netif_receive_skb(skb);
  1063. adapter->stats.lro_pkts++;
  1064. adapter->stats.rxbytes += length;
  1065. return buffer;
  1066. }
  1067. #define netxen_merge_rx_buffers(list, head) \
  1068. do { list_splice_tail_init(list, head); } while (0);
  1069. int
  1070. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1071. {
  1072. struct netxen_adapter *adapter = sds_ring->adapter;
  1073. struct list_head *cur;
  1074. struct status_desc *desc;
  1075. struct netxen_rx_buffer *rxbuf;
  1076. u32 consumer = sds_ring->consumer;
  1077. int count = 0;
  1078. u64 sts_data0, sts_data1;
  1079. int opcode, ring = 0, desc_cnt;
  1080. while (count < max) {
  1081. desc = &sds_ring->desc_head[consumer];
  1082. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1083. if (!(sts_data0 & STATUS_OWNER_HOST))
  1084. break;
  1085. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1086. opcode = netxen_get_sts_opcode(sts_data0);
  1087. switch (opcode) {
  1088. case NETXEN_NIC_RXPKT_DESC:
  1089. case NETXEN_OLD_RXPKT_DESC:
  1090. case NETXEN_NIC_SYN_OFFLOAD:
  1091. ring = netxen_get_sts_type(sts_data0);
  1092. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1093. ring, sts_data0);
  1094. break;
  1095. case NETXEN_NIC_LRO_DESC:
  1096. ring = netxen_get_lro_sts_type(sts_data0);
  1097. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1098. rxbuf = netxen_process_lro(adapter, sds_ring,
  1099. ring, sts_data0, sts_data1);
  1100. break;
  1101. case NETXEN_NIC_RESPONSE_DESC:
  1102. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1103. default:
  1104. goto skip;
  1105. }
  1106. WARN_ON(desc_cnt > 1);
  1107. if (rxbuf)
  1108. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1109. skip:
  1110. for (; desc_cnt > 0; desc_cnt--) {
  1111. desc = &sds_ring->desc_head[consumer];
  1112. desc->status_desc_data[0] =
  1113. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1114. consumer = get_next_index(consumer, sds_ring->num_desc);
  1115. }
  1116. count++;
  1117. }
  1118. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1119. struct nx_host_rds_ring *rds_ring =
  1120. &adapter->recv_ctx.rds_rings[ring];
  1121. if (!list_empty(&sds_ring->free_list[ring])) {
  1122. list_for_each(cur, &sds_ring->free_list[ring]) {
  1123. rxbuf = list_entry(cur,
  1124. struct netxen_rx_buffer, list);
  1125. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1126. }
  1127. spin_lock(&rds_ring->lock);
  1128. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1129. &rds_ring->free_list);
  1130. spin_unlock(&rds_ring->lock);
  1131. }
  1132. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1133. }
  1134. if (count) {
  1135. sds_ring->consumer = consumer;
  1136. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1137. }
  1138. return count;
  1139. }
  1140. /* Process Command status ring */
  1141. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1142. {
  1143. u32 sw_consumer, hw_consumer;
  1144. int count = 0, i;
  1145. struct netxen_cmd_buffer *buffer;
  1146. struct pci_dev *pdev = adapter->pdev;
  1147. struct net_device *netdev = adapter->netdev;
  1148. struct netxen_skb_frag *frag;
  1149. int done = 0;
  1150. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1151. if (!spin_trylock(&adapter->tx_clean_lock))
  1152. return 1;
  1153. sw_consumer = tx_ring->sw_consumer;
  1154. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1155. while (sw_consumer != hw_consumer) {
  1156. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1157. if (buffer->skb) {
  1158. frag = &buffer->frag_array[0];
  1159. pci_unmap_single(pdev, frag->dma, frag->length,
  1160. PCI_DMA_TODEVICE);
  1161. frag->dma = 0ULL;
  1162. for (i = 1; i < buffer->frag_count; i++) {
  1163. frag++; /* Get the next frag */
  1164. pci_unmap_page(pdev, frag->dma, frag->length,
  1165. PCI_DMA_TODEVICE);
  1166. frag->dma = 0ULL;
  1167. }
  1168. adapter->stats.xmitfinished++;
  1169. dev_kfree_skb_any(buffer->skb);
  1170. buffer->skb = NULL;
  1171. }
  1172. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1173. if (++count >= MAX_STATUS_HANDLE)
  1174. break;
  1175. }
  1176. if (count && netif_running(netdev)) {
  1177. tx_ring->sw_consumer = sw_consumer;
  1178. smp_mb();
  1179. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1180. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1181. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1182. netif_wake_queue(netdev);
  1183. __netif_tx_unlock(tx_ring->txq);
  1184. }
  1185. }
  1186. /*
  1187. * If everything is freed up to consumer then check if the ring is full
  1188. * If the ring is full then check if more needs to be freed and
  1189. * schedule the call back again.
  1190. *
  1191. * This happens when there are 2 CPUs. One could be freeing and the
  1192. * other filling it. If the ring is full when we get out of here and
  1193. * the card has already interrupted the host then the host can miss the
  1194. * interrupt.
  1195. *
  1196. * There is still a possible race condition and the host could miss an
  1197. * interrupt. The card has to take care of this.
  1198. */
  1199. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1200. done = (sw_consumer == hw_consumer);
  1201. spin_unlock(&adapter->tx_clean_lock);
  1202. return (done);
  1203. }
  1204. void
  1205. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1206. struct nx_host_rds_ring *rds_ring)
  1207. {
  1208. struct rcv_desc *pdesc;
  1209. struct netxen_rx_buffer *buffer;
  1210. int producer, count = 0;
  1211. netxen_ctx_msg msg = 0;
  1212. struct list_head *head;
  1213. producer = rds_ring->producer;
  1214. spin_lock(&rds_ring->lock);
  1215. head = &rds_ring->free_list;
  1216. while (!list_empty(head)) {
  1217. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1218. if (!buffer->skb) {
  1219. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1220. break;
  1221. }
  1222. count++;
  1223. list_del(&buffer->list);
  1224. /* make a rcv descriptor */
  1225. pdesc = &rds_ring->desc_head[producer];
  1226. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1227. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1228. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1229. producer = get_next_index(producer, rds_ring->num_desc);
  1230. }
  1231. spin_unlock(&rds_ring->lock);
  1232. if (count) {
  1233. rds_ring->producer = producer;
  1234. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1235. (producer-1) & (rds_ring->num_desc-1));
  1236. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1237. /*
  1238. * Write a doorbell msg to tell phanmon of change in
  1239. * receive ring producer
  1240. * Only for firmware version < 4.0.0
  1241. */
  1242. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1243. netxen_set_msg_privid(msg);
  1244. netxen_set_msg_count(msg,
  1245. ((producer - 1) &
  1246. (rds_ring->num_desc - 1)));
  1247. netxen_set_msg_ctxid(msg, adapter->portnum);
  1248. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1249. read_lock(&adapter->adapter_lock);
  1250. writel(msg, DB_NORMALIZE(adapter,
  1251. NETXEN_RCV_PRODUCER_OFFSET));
  1252. read_unlock(&adapter->adapter_lock);
  1253. }
  1254. }
  1255. }
  1256. static void
  1257. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1258. struct nx_host_rds_ring *rds_ring)
  1259. {
  1260. struct rcv_desc *pdesc;
  1261. struct netxen_rx_buffer *buffer;
  1262. int producer, count = 0;
  1263. struct list_head *head;
  1264. producer = rds_ring->producer;
  1265. if (!spin_trylock(&rds_ring->lock))
  1266. return;
  1267. head = &rds_ring->free_list;
  1268. while (!list_empty(head)) {
  1269. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1270. if (!buffer->skb) {
  1271. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1272. break;
  1273. }
  1274. count++;
  1275. list_del(&buffer->list);
  1276. /* make a rcv descriptor */
  1277. pdesc = &rds_ring->desc_head[producer];
  1278. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1279. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1280. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1281. producer = get_next_index(producer, rds_ring->num_desc);
  1282. }
  1283. if (count) {
  1284. rds_ring->producer = producer;
  1285. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1286. (producer - 1) & (rds_ring->num_desc - 1));
  1287. }
  1288. spin_unlock(&rds_ring->lock);
  1289. }
  1290. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1291. {
  1292. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1293. return;
  1294. }