mpc85xx_ads.c 6.1 KB

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  1. /*
  2. * MPC85xx setup and early boot code plus other random bits.
  3. *
  4. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5. *
  6. * Copyright 2005 Freescale Semiconductor Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/stddef.h>
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/kdev_t.h>
  17. #include <linux/delay.h>
  18. #include <linux/seq_file.h>
  19. #include <asm/system.h>
  20. #include <asm/time.h>
  21. #include <asm/machdep.h>
  22. #include <asm/pci-bridge.h>
  23. #include <asm/mpc85xx.h>
  24. #include <asm/prom.h>
  25. #include <asm/mpic.h>
  26. #include <mm/mmu_decl.h>
  27. #include <asm/udbg.h>
  28. #include <sysdev/fsl_soc.h>
  29. #include <sysdev/fsl_pci.h>
  30. #include "mpc85xx.h"
  31. #ifdef CONFIG_CPM2
  32. #include <linux/fs_enet_pd.h>
  33. #include <asm/cpm2.h>
  34. #include <sysdev/cpm2_pic.h>
  35. #include <asm/fs_pd.h>
  36. #endif
  37. #ifdef CONFIG_PCI
  38. static int mpc85xx_exclude_device(struct pci_controller *hose,
  39. u_char bus, u_char devfn)
  40. {
  41. if (bus == 0 && PCI_SLOT(devfn) == 0)
  42. return PCIBIOS_DEVICE_NOT_FOUND;
  43. else
  44. return PCIBIOS_SUCCESSFUL;
  45. }
  46. #endif /* CONFIG_PCI */
  47. #ifdef CONFIG_CPM2
  48. static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
  49. {
  50. int cascade_irq;
  51. while ((cascade_irq = cpm2_get_irq()) >= 0) {
  52. generic_handle_irq(cascade_irq);
  53. }
  54. desc->chip->eoi(irq);
  55. }
  56. #endif /* CONFIG_CPM2 */
  57. static void __init mpc85xx_ads_pic_init(void)
  58. {
  59. struct mpic *mpic;
  60. struct resource r;
  61. struct device_node *np = NULL;
  62. #ifdef CONFIG_CPM2
  63. int irq;
  64. #endif
  65. np = of_find_node_by_type(np, "open-pic");
  66. if (np == NULL) {
  67. printk(KERN_ERR "Could not find open-pic node\n");
  68. return;
  69. }
  70. if(of_address_to_resource(np, 0, &r)) {
  71. printk(KERN_ERR "Could not map mpic register space\n");
  72. of_node_put(np);
  73. return;
  74. }
  75. mpic = mpic_alloc(np, r.start,
  76. MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  77. 0, 256, " OpenPIC ");
  78. BUG_ON(mpic == NULL);
  79. of_node_put(np);
  80. mpic_init(mpic);
  81. #ifdef CONFIG_CPM2
  82. /* Setup CPM2 PIC */
  83. np = of_find_node_by_type(NULL, "cpm-pic");
  84. if (np == NULL) {
  85. printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
  86. return;
  87. }
  88. irq = irq_of_parse_and_map(np, 0);
  89. cpm2_pic_init(np);
  90. set_irq_chained_handler(irq, cpm2_cascade);
  91. #endif
  92. }
  93. /*
  94. * Setup the architecture
  95. */
  96. #ifdef CONFIG_CPM2
  97. void init_fcc_ioports(struct fs_platform_info *fpi)
  98. {
  99. struct io_port *io = cpm2_map(im_ioport);
  100. int fcc_no = fs_get_fcc_index(fpi->fs_no);
  101. int target;
  102. u32 tempval;
  103. switch(fcc_no) {
  104. case 1:
  105. tempval = in_be32(&io->iop_pdirb);
  106. tempval &= ~PB2_DIRB0;
  107. tempval |= PB2_DIRB1;
  108. out_be32(&io->iop_pdirb, tempval);
  109. tempval = in_be32(&io->iop_psorb);
  110. tempval &= ~PB2_PSORB0;
  111. tempval |= PB2_PSORB1;
  112. out_be32(&io->iop_psorb, tempval);
  113. tempval = in_be32(&io->iop_pparb);
  114. tempval |= (PB2_DIRB0 | PB2_DIRB1);
  115. out_be32(&io->iop_pparb, tempval);
  116. target = CPM_CLK_FCC2;
  117. break;
  118. case 2:
  119. tempval = in_be32(&io->iop_pdirb);
  120. tempval &= ~PB3_DIRB0;
  121. tempval |= PB3_DIRB1;
  122. out_be32(&io->iop_pdirb, tempval);
  123. tempval = in_be32(&io->iop_psorb);
  124. tempval &= ~PB3_PSORB0;
  125. tempval |= PB3_PSORB1;
  126. out_be32(&io->iop_psorb, tempval);
  127. tempval = in_be32(&io->iop_pparb);
  128. tempval |= (PB3_DIRB0 | PB3_DIRB1);
  129. out_be32(&io->iop_pparb, tempval);
  130. tempval = in_be32(&io->iop_pdirc);
  131. tempval |= PC3_DIRC1;
  132. out_be32(&io->iop_pdirc, tempval);
  133. tempval = in_be32(&io->iop_pparc);
  134. tempval |= PC3_DIRC1;
  135. out_be32(&io->iop_pparc, tempval);
  136. target = CPM_CLK_FCC3;
  137. break;
  138. default:
  139. printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
  140. return;
  141. }
  142. /* Port C has clocks...... */
  143. tempval = in_be32(&io->iop_psorc);
  144. tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
  145. out_be32(&io->iop_psorc, tempval);
  146. tempval = in_be32(&io->iop_pdirc);
  147. tempval &= ~(PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
  148. out_be32(&io->iop_pdirc, tempval);
  149. tempval = in_be32(&io->iop_pparc);
  150. tempval |= (PC_CLK(fpi->clk_rx - 8) | PC_CLK(fpi->clk_tx - 8));
  151. out_be32(&io->iop_pparc, tempval);
  152. cpm2_unmap(io);
  153. /* Configure Serial Interface clock routing.
  154. * First, clear FCC bits to zero,
  155. * then set the ones we want.
  156. */
  157. cpm2_clk_setup(target, fpi->clk_rx, CPM_CLK_RX);
  158. cpm2_clk_setup(target, fpi->clk_tx, CPM_CLK_TX);
  159. }
  160. #endif
  161. static void __init mpc85xx_ads_setup_arch(void)
  162. {
  163. struct device_node *cpu;
  164. #ifdef CONFIG_PCI
  165. struct device_node *np;
  166. #endif
  167. if (ppc_md.progress)
  168. ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
  169. cpu = of_find_node_by_type(NULL, "cpu");
  170. if (cpu != 0) {
  171. const unsigned int *fp;
  172. fp = of_get_property(cpu, "clock-frequency", NULL);
  173. if (fp != 0)
  174. loops_per_jiffy = *fp / HZ;
  175. else
  176. loops_per_jiffy = 50000000 / HZ;
  177. of_node_put(cpu);
  178. }
  179. #ifdef CONFIG_CPM2
  180. cpm2_reset();
  181. #endif
  182. #ifdef CONFIG_PCI
  183. for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  184. fsl_add_bridge(np, 1);
  185. ppc_md.pci_exclude_device = mpc85xx_exclude_device;
  186. #endif
  187. }
  188. static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
  189. {
  190. uint pvid, svid, phid1;
  191. uint memsize = total_memory;
  192. pvid = mfspr(SPRN_PVR);
  193. svid = mfspr(SPRN_SVR);
  194. seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  195. seq_printf(m, "Machine\t\t: mpc85xx\n");
  196. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  197. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  198. /* Display cpu Pll setting */
  199. phid1 = mfspr(SPRN_HID1);
  200. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  201. /* Display the amount of memory */
  202. seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
  203. }
  204. /*
  205. * Called very early, device-tree isn't unflattened
  206. */
  207. static int __init mpc85xx_ads_probe(void)
  208. {
  209. unsigned long root = of_get_flat_dt_root();
  210. return of_flat_dt_is_compatible(root, "MPC85xxADS");
  211. }
  212. define_machine(mpc85xx_ads) {
  213. .name = "MPC85xx ADS",
  214. .probe = mpc85xx_ads_probe,
  215. .setup_arch = mpc85xx_ads_setup_arch,
  216. .init_IRQ = mpc85xx_ads_pic_init,
  217. .show_cpuinfo = mpc85xx_ads_show_cpuinfo,
  218. .get_irq = mpic_get_irq,
  219. .restart = mpc85xx_restart,
  220. .calibrate_decr = generic_calibrate_decr,
  221. .progress = udbg_progress,
  222. };