cacheinit.c 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566
  1. /*
  2. * Copyright 2004-2007 Analog Devices Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, see the file COPYING, or write
  16. * to the Free Software Foundation, Inc.,
  17. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18. */
  19. #include <linux/cpu.h>
  20. #include <asm/cacheflush.h>
  21. #include <asm/blackfin.h>
  22. #include <asm/cplbinit.h>
  23. #if defined(CONFIG_BLKFIN_CACHE)
  24. void bfin_icache_init(void)
  25. {
  26. unsigned long *table = icplb_table;
  27. unsigned long ctrl;
  28. int i;
  29. for (i = 0; i < MAX_CPLBS; i++) {
  30. unsigned long addr = *table++;
  31. unsigned long data = *table++;
  32. if (addr == (unsigned long)-1)
  33. break;
  34. bfin_write32(ICPLB_ADDR0 + i * 4, addr);
  35. bfin_write32(ICPLB_DATA0 + i * 4, data);
  36. }
  37. ctrl = bfin_read_IMEM_CONTROL();
  38. ctrl |= IMC | ENICPLB;
  39. bfin_write_IMEM_CONTROL(ctrl);
  40. }
  41. #endif
  42. #if defined(CONFIG_BLKFIN_DCACHE)
  43. void bfin_dcache_init(void)
  44. {
  45. unsigned long *table = dcplb_table;
  46. unsigned long ctrl;
  47. int i;
  48. for (i = 0; i < MAX_CPLBS; i++) {
  49. unsigned long addr = *table++;
  50. unsigned long data = *table++;
  51. if (addr == (unsigned long)-1)
  52. break;
  53. bfin_write32(DCPLB_ADDR0 + i * 4, addr);
  54. bfin_write32(DCPLB_DATA0 + i * 4, data);
  55. }
  56. ctrl = bfin_read_DMEM_CONTROL();
  57. ctrl |= DMEM_CNTR;
  58. bfin_write_DMEM_CONTROL(ctrl);
  59. }
  60. #endif