rt2800lib.c 76 KB

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  1. /*
  2. Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  3. Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
  4. Based on the original rt2800pci.c and rt2800usb.c.
  5. Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
  6. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  7. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  8. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  9. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  10. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  11. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  12. <http://rt2x00.serialmonkey.com>
  13. This program is free software; you can redistribute it and/or modify
  14. it under the terms of the GNU General Public License as published by
  15. the Free Software Foundation; either version 2 of the License, or
  16. (at your option) any later version.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. You should have received a copy of the GNU General Public License
  22. along with this program; if not, write to the
  23. Free Software Foundation, Inc.,
  24. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25. */
  26. /*
  27. Module: rt2800lib
  28. Abstract: rt2800 generic device routines.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include "rt2x00.h"
  33. #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  34. #include "rt2x00usb.h"
  35. #endif
  36. #include "rt2800lib.h"
  37. #include "rt2800.h"
  38. #include "rt2800usb.h"
  39. MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  40. MODULE_DESCRIPTION("rt2800 library");
  41. MODULE_LICENSE("GPL");
  42. /*
  43. * Register access.
  44. * All access to the CSR registers will go through the methods
  45. * rt2800_register_read and rt2800_register_write.
  46. * BBP and RF register require indirect register access,
  47. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  48. * These indirect registers work with busy bits,
  49. * and we will try maximal REGISTER_BUSY_COUNT times to access
  50. * the register while taking a REGISTER_BUSY_DELAY us delay
  51. * between each attampt. When the busy bit is still set at that time,
  52. * the access attempt is considered to have failed,
  53. * and we will print an error.
  54. * The _lock versions must be used if you already hold the csr_mutex
  55. */
  56. #define WAIT_FOR_BBP(__dev, __reg) \
  57. rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  58. #define WAIT_FOR_RFCSR(__dev, __reg) \
  59. rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  60. #define WAIT_FOR_RF(__dev, __reg) \
  61. rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  62. #define WAIT_FOR_MCU(__dev, __reg) \
  63. rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  64. H2M_MAILBOX_CSR_OWNER, (__reg))
  65. static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  66. const unsigned int word, const u8 value)
  67. {
  68. u32 reg;
  69. mutex_lock(&rt2x00dev->csr_mutex);
  70. /*
  71. * Wait until the BBP becomes available, afterwards we
  72. * can safely write the new data into the register.
  73. */
  74. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  75. reg = 0;
  76. rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  77. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  78. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  79. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  80. if (rt2x00_intf_is_pci(rt2x00dev))
  81. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  82. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  83. }
  84. mutex_unlock(&rt2x00dev->csr_mutex);
  85. }
  86. static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
  87. const unsigned int word, u8 *value)
  88. {
  89. u32 reg;
  90. mutex_lock(&rt2x00dev->csr_mutex);
  91. /*
  92. * Wait until the BBP becomes available, afterwards we
  93. * can safely write the read request into the register.
  94. * After the data has been written, we wait until hardware
  95. * returns the correct value, if at any time the register
  96. * doesn't become available in time, reg will be 0xffffffff
  97. * which means we return 0xff to the caller.
  98. */
  99. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  100. reg = 0;
  101. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  102. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  103. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
  104. if (rt2x00_intf_is_pci(rt2x00dev))
  105. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  106. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  107. WAIT_FOR_BBP(rt2x00dev, &reg);
  108. }
  109. *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
  110. mutex_unlock(&rt2x00dev->csr_mutex);
  111. }
  112. static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  113. const unsigned int word, const u8 value)
  114. {
  115. u32 reg;
  116. mutex_lock(&rt2x00dev->csr_mutex);
  117. /*
  118. * Wait until the RFCSR becomes available, afterwards we
  119. * can safely write the new data into the register.
  120. */
  121. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  122. reg = 0;
  123. rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  124. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  125. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  126. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  127. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  128. }
  129. mutex_unlock(&rt2x00dev->csr_mutex);
  130. }
  131. static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  132. const unsigned int word, u8 *value)
  133. {
  134. u32 reg;
  135. mutex_lock(&rt2x00dev->csr_mutex);
  136. /*
  137. * Wait until the RFCSR becomes available, afterwards we
  138. * can safely write the read request into the register.
  139. * After the data has been written, we wait until hardware
  140. * returns the correct value, if at any time the register
  141. * doesn't become available in time, reg will be 0xffffffff
  142. * which means we return 0xff to the caller.
  143. */
  144. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  145. reg = 0;
  146. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  147. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  148. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  149. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  150. WAIT_FOR_RFCSR(rt2x00dev, &reg);
  151. }
  152. *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  153. mutex_unlock(&rt2x00dev->csr_mutex);
  154. }
  155. static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  156. const unsigned int word, const u32 value)
  157. {
  158. u32 reg;
  159. mutex_lock(&rt2x00dev->csr_mutex);
  160. /*
  161. * Wait until the RF becomes available, afterwards we
  162. * can safely write the new data into the register.
  163. */
  164. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  165. reg = 0;
  166. rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
  167. rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
  168. rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
  169. rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
  170. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
  171. rt2x00_rf_write(rt2x00dev, word, value);
  172. }
  173. mutex_unlock(&rt2x00dev->csr_mutex);
  174. }
  175. void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
  176. const u8 command, const u8 token,
  177. const u8 arg0, const u8 arg1)
  178. {
  179. u32 reg;
  180. /*
  181. * RT2880 and RT3052 don't support MCU requests.
  182. */
  183. if (rt2x00_rt(rt2x00dev, RT2880) || rt2x00_rt(rt2x00dev, RT3052))
  184. return;
  185. mutex_lock(&rt2x00dev->csr_mutex);
  186. /*
  187. * Wait until the MCU becomes available, afterwards we
  188. * can safely write the new data into the register.
  189. */
  190. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  191. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  192. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  193. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  194. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  195. rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
  196. reg = 0;
  197. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  198. rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
  199. }
  200. mutex_unlock(&rt2x00dev->csr_mutex);
  201. }
  202. EXPORT_SYMBOL_GPL(rt2800_mcu_request);
  203. int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
  204. {
  205. unsigned int i;
  206. u32 reg;
  207. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  208. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  209. if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
  210. !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
  211. return 0;
  212. msleep(1);
  213. }
  214. ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
  215. return -EACCES;
  216. }
  217. EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
  218. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  219. const struct rt2x00debug rt2800_rt2x00debug = {
  220. .owner = THIS_MODULE,
  221. .csr = {
  222. .read = rt2800_register_read,
  223. .write = rt2800_register_write,
  224. .flags = RT2X00DEBUGFS_OFFSET,
  225. .word_base = CSR_REG_BASE,
  226. .word_size = sizeof(u32),
  227. .word_count = CSR_REG_SIZE / sizeof(u32),
  228. },
  229. .eeprom = {
  230. .read = rt2x00_eeprom_read,
  231. .write = rt2x00_eeprom_write,
  232. .word_base = EEPROM_BASE,
  233. .word_size = sizeof(u16),
  234. .word_count = EEPROM_SIZE / sizeof(u16),
  235. },
  236. .bbp = {
  237. .read = rt2800_bbp_read,
  238. .write = rt2800_bbp_write,
  239. .word_base = BBP_BASE,
  240. .word_size = sizeof(u8),
  241. .word_count = BBP_SIZE / sizeof(u8),
  242. },
  243. .rf = {
  244. .read = rt2x00_rf_read,
  245. .write = rt2800_rf_write,
  246. .word_base = RF_BASE,
  247. .word_size = sizeof(u32),
  248. .word_count = RF_SIZE / sizeof(u32),
  249. },
  250. };
  251. EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
  252. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  253. int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  254. {
  255. u32 reg;
  256. rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
  257. return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
  258. }
  259. EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
  260. #ifdef CONFIG_RT2X00_LIB_LEDS
  261. static void rt2800_brightness_set(struct led_classdev *led_cdev,
  262. enum led_brightness brightness)
  263. {
  264. struct rt2x00_led *led =
  265. container_of(led_cdev, struct rt2x00_led, led_dev);
  266. unsigned int enabled = brightness != LED_OFF;
  267. unsigned int bg_mode =
  268. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  269. unsigned int polarity =
  270. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  271. EEPROM_FREQ_LED_POLARITY);
  272. unsigned int ledmode =
  273. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  274. EEPROM_FREQ_LED_MODE);
  275. if (led->type == LED_TYPE_RADIO) {
  276. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  277. enabled ? 0x20 : 0);
  278. } else if (led->type == LED_TYPE_ASSOC) {
  279. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  280. enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
  281. } else if (led->type == LED_TYPE_QUALITY) {
  282. /*
  283. * The brightness is divided into 6 levels (0 - 5),
  284. * The specs tell us the following levels:
  285. * 0, 1 ,3, 7, 15, 31
  286. * to determine the level in a simple way we can simply
  287. * work with bitshifting:
  288. * (1 << level) - 1
  289. */
  290. rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  291. (1 << brightness / (LED_FULL / 6)) - 1,
  292. polarity);
  293. }
  294. }
  295. static int rt2800_blink_set(struct led_classdev *led_cdev,
  296. unsigned long *delay_on, unsigned long *delay_off)
  297. {
  298. struct rt2x00_led *led =
  299. container_of(led_cdev, struct rt2x00_led, led_dev);
  300. u32 reg;
  301. rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
  302. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
  303. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
  304. rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
  305. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
  306. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
  307. rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
  308. rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
  309. rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
  310. return 0;
  311. }
  312. static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
  313. struct rt2x00_led *led, enum led_type type)
  314. {
  315. led->rt2x00dev = rt2x00dev;
  316. led->type = type;
  317. led->led_dev.brightness_set = rt2800_brightness_set;
  318. led->led_dev.blink_set = rt2800_blink_set;
  319. led->flags = LED_INITIALIZED;
  320. }
  321. #endif /* CONFIG_RT2X00_LIB_LEDS */
  322. /*
  323. * Configuration handlers.
  324. */
  325. static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
  326. struct rt2x00lib_crypto *crypto,
  327. struct ieee80211_key_conf *key)
  328. {
  329. struct mac_wcid_entry wcid_entry;
  330. struct mac_iveiv_entry iveiv_entry;
  331. u32 offset;
  332. u32 reg;
  333. offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
  334. rt2800_register_read(rt2x00dev, offset, &reg);
  335. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
  336. !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
  337. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
  338. (crypto->cmd == SET_KEY) * crypto->cipher);
  339. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
  340. (crypto->cmd == SET_KEY) * crypto->bssidx);
  341. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
  342. rt2800_register_write(rt2x00dev, offset, reg);
  343. offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
  344. memset(&iveiv_entry, 0, sizeof(iveiv_entry));
  345. if ((crypto->cipher == CIPHER_TKIP) ||
  346. (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
  347. (crypto->cipher == CIPHER_AES))
  348. iveiv_entry.iv[3] |= 0x20;
  349. iveiv_entry.iv[3] |= key->keyidx << 6;
  350. rt2800_register_multiwrite(rt2x00dev, offset,
  351. &iveiv_entry, sizeof(iveiv_entry));
  352. offset = MAC_WCID_ENTRY(key->hw_key_idx);
  353. memset(&wcid_entry, 0, sizeof(wcid_entry));
  354. if (crypto->cmd == SET_KEY)
  355. memcpy(&wcid_entry, crypto->address, ETH_ALEN);
  356. rt2800_register_multiwrite(rt2x00dev, offset,
  357. &wcid_entry, sizeof(wcid_entry));
  358. }
  359. int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
  360. struct rt2x00lib_crypto *crypto,
  361. struct ieee80211_key_conf *key)
  362. {
  363. struct hw_key_entry key_entry;
  364. struct rt2x00_field32 field;
  365. u32 offset;
  366. u32 reg;
  367. if (crypto->cmd == SET_KEY) {
  368. key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
  369. memcpy(key_entry.key, crypto->key,
  370. sizeof(key_entry.key));
  371. memcpy(key_entry.tx_mic, crypto->tx_mic,
  372. sizeof(key_entry.tx_mic));
  373. memcpy(key_entry.rx_mic, crypto->rx_mic,
  374. sizeof(key_entry.rx_mic));
  375. offset = SHARED_KEY_ENTRY(key->hw_key_idx);
  376. rt2800_register_multiwrite(rt2x00dev, offset,
  377. &key_entry, sizeof(key_entry));
  378. }
  379. /*
  380. * The cipher types are stored over multiple registers
  381. * starting with SHARED_KEY_MODE_BASE each word will have
  382. * 32 bits and contains the cipher types for 2 bssidx each.
  383. * Using the correct defines correctly will cause overhead,
  384. * so just calculate the correct offset.
  385. */
  386. field.bit_offset = 4 * (key->hw_key_idx % 8);
  387. field.bit_mask = 0x7 << field.bit_offset;
  388. offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
  389. rt2800_register_read(rt2x00dev, offset, &reg);
  390. rt2x00_set_field32(&reg, field,
  391. (crypto->cmd == SET_KEY) * crypto->cipher);
  392. rt2800_register_write(rt2x00dev, offset, reg);
  393. /*
  394. * Update WCID information
  395. */
  396. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  397. return 0;
  398. }
  399. EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
  400. int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  401. struct rt2x00lib_crypto *crypto,
  402. struct ieee80211_key_conf *key)
  403. {
  404. struct hw_key_entry key_entry;
  405. u32 offset;
  406. if (crypto->cmd == SET_KEY) {
  407. /*
  408. * 1 pairwise key is possible per AID, this means that the AID
  409. * equals our hw_key_idx. Make sure the WCID starts _after_ the
  410. * last possible shared key entry.
  411. */
  412. if (crypto->aid > (256 - 32))
  413. return -ENOSPC;
  414. key->hw_key_idx = 32 + crypto->aid;
  415. memcpy(key_entry.key, crypto->key,
  416. sizeof(key_entry.key));
  417. memcpy(key_entry.tx_mic, crypto->tx_mic,
  418. sizeof(key_entry.tx_mic));
  419. memcpy(key_entry.rx_mic, crypto->rx_mic,
  420. sizeof(key_entry.rx_mic));
  421. offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  422. rt2800_register_multiwrite(rt2x00dev, offset,
  423. &key_entry, sizeof(key_entry));
  424. }
  425. /*
  426. * Update WCID information
  427. */
  428. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  429. return 0;
  430. }
  431. EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
  432. void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
  433. const unsigned int filter_flags)
  434. {
  435. u32 reg;
  436. /*
  437. * Start configuration steps.
  438. * Note that the version error will always be dropped
  439. * and broadcast frames will always be accepted since
  440. * there is no filter for it at this time.
  441. */
  442. rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
  443. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
  444. !(filter_flags & FIF_FCSFAIL));
  445. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
  446. !(filter_flags & FIF_PLCPFAIL));
  447. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
  448. !(filter_flags & FIF_PROMISC_IN_BSS));
  449. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
  450. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
  451. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
  452. !(filter_flags & FIF_ALLMULTI));
  453. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
  454. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
  455. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
  456. !(filter_flags & FIF_CONTROL));
  457. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
  458. !(filter_flags & FIF_CONTROL));
  459. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
  460. !(filter_flags & FIF_CONTROL));
  461. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
  462. !(filter_flags & FIF_CONTROL));
  463. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
  464. !(filter_flags & FIF_CONTROL));
  465. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
  466. !(filter_flags & FIF_PSPOLL));
  467. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
  468. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
  469. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
  470. !(filter_flags & FIF_CONTROL));
  471. rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
  472. }
  473. EXPORT_SYMBOL_GPL(rt2800_config_filter);
  474. void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
  475. struct rt2x00intf_conf *conf, const unsigned int flags)
  476. {
  477. unsigned int beacon_base;
  478. u32 reg;
  479. if (flags & CONFIG_UPDATE_TYPE) {
  480. /*
  481. * Clear current synchronisation setup.
  482. * For the Beacon base registers we only need to clear
  483. * the first byte since that byte contains the VALID and OWNER
  484. * bits which (when set to 0) will invalidate the entire beacon.
  485. */
  486. beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
  487. rt2800_register_write(rt2x00dev, beacon_base, 0);
  488. /*
  489. * Enable synchronisation.
  490. */
  491. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  492. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  493. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
  494. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
  495. (conf->sync == TSF_SYNC_BEACON));
  496. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  497. }
  498. if (flags & CONFIG_UPDATE_MAC) {
  499. reg = le32_to_cpu(conf->mac[1]);
  500. rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
  501. conf->mac[1] = cpu_to_le32(reg);
  502. rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
  503. conf->mac, sizeof(conf->mac));
  504. }
  505. if (flags & CONFIG_UPDATE_BSSID) {
  506. reg = le32_to_cpu(conf->bssid[1]);
  507. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
  508. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
  509. conf->bssid[1] = cpu_to_le32(reg);
  510. rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
  511. conf->bssid, sizeof(conf->bssid));
  512. }
  513. }
  514. EXPORT_SYMBOL_GPL(rt2800_config_intf);
  515. void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
  516. {
  517. u32 reg;
  518. rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
  519. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
  520. rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
  521. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  522. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
  523. !!erp->short_preamble);
  524. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
  525. !!erp->short_preamble);
  526. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  527. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  528. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
  529. erp->cts_protection ? 2 : 0);
  530. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  531. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
  532. erp->basic_rates);
  533. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  534. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  535. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
  536. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
  537. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  538. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  539. rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
  540. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
  541. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
  542. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
  543. rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
  544. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  545. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  546. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  547. erp->beacon_int * 16);
  548. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  549. }
  550. EXPORT_SYMBOL_GPL(rt2800_config_erp);
  551. void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
  552. {
  553. u8 r1;
  554. u8 r3;
  555. rt2800_bbp_read(rt2x00dev, 1, &r1);
  556. rt2800_bbp_read(rt2x00dev, 3, &r3);
  557. /*
  558. * Configure the TX antenna.
  559. */
  560. switch ((int)ant->tx) {
  561. case 1:
  562. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
  563. if (rt2x00_intf_is_pci(rt2x00dev))
  564. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  565. break;
  566. case 2:
  567. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
  568. break;
  569. case 3:
  570. /* Do nothing */
  571. break;
  572. }
  573. /*
  574. * Configure the RX antenna.
  575. */
  576. switch ((int)ant->rx) {
  577. case 1:
  578. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  579. break;
  580. case 2:
  581. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
  582. break;
  583. case 3:
  584. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
  585. break;
  586. }
  587. rt2800_bbp_write(rt2x00dev, 3, r3);
  588. rt2800_bbp_write(rt2x00dev, 1, r1);
  589. }
  590. EXPORT_SYMBOL_GPL(rt2800_config_ant);
  591. static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  592. struct rt2x00lib_conf *libconf)
  593. {
  594. u16 eeprom;
  595. short lna_gain;
  596. if (libconf->rf.channel <= 14) {
  597. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  598. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
  599. } else if (libconf->rf.channel <= 64) {
  600. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  601. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
  602. } else if (libconf->rf.channel <= 128) {
  603. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
  604. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
  605. } else {
  606. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
  607. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
  608. }
  609. rt2x00dev->lna_gain = lna_gain;
  610. }
  611. static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
  612. struct ieee80211_conf *conf,
  613. struct rf_channel *rf,
  614. struct channel_info *info)
  615. {
  616. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  617. if (rt2x00dev->default_ant.tx == 1)
  618. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
  619. if (rt2x00dev->default_ant.rx == 1) {
  620. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
  621. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  622. } else if (rt2x00dev->default_ant.rx == 2)
  623. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  624. if (rf->channel > 14) {
  625. /*
  626. * When TX power is below 0, we should increase it by 7 to
  627. * make it a positive value (Minumum value is -7).
  628. * However this means that values between 0 and 7 have
  629. * double meaning, and we should set a 7DBm boost flag.
  630. */
  631. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
  632. (info->tx_power1 >= 0));
  633. if (info->tx_power1 < 0)
  634. info->tx_power1 += 7;
  635. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
  636. TXPOWER_A_TO_DEV(info->tx_power1));
  637. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
  638. (info->tx_power2 >= 0));
  639. if (info->tx_power2 < 0)
  640. info->tx_power2 += 7;
  641. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
  642. TXPOWER_A_TO_DEV(info->tx_power2));
  643. } else {
  644. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
  645. TXPOWER_G_TO_DEV(info->tx_power1));
  646. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
  647. TXPOWER_G_TO_DEV(info->tx_power2));
  648. }
  649. rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
  650. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  651. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  652. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  653. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  654. udelay(200);
  655. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  656. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  657. rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  658. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  659. udelay(200);
  660. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  661. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  662. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  663. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  664. }
  665. static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
  666. struct ieee80211_conf *conf,
  667. struct rf_channel *rf,
  668. struct channel_info *info)
  669. {
  670. u8 rfcsr;
  671. rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
  672. rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
  673. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  674. rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
  675. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  676. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  677. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
  678. TXPOWER_G_TO_DEV(info->tx_power1));
  679. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  680. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  681. rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
  682. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  683. rt2800_rfcsr_write(rt2x00dev, 24,
  684. rt2x00dev->calibration[conf_is_ht40(conf)]);
  685. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  686. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  687. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  688. }
  689. static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  690. struct ieee80211_conf *conf,
  691. struct rf_channel *rf,
  692. struct channel_info *info)
  693. {
  694. u32 reg;
  695. unsigned int tx_pin;
  696. u8 bbp;
  697. if ((rt2x00_rt(rt2x00dev, RT3070) ||
  698. rt2x00_rt(rt2x00dev, RT3090)) &&
  699. (rt2x00_rf(rt2x00dev, RF2020) ||
  700. rt2x00_rf(rt2x00dev, RF3020) ||
  701. rt2x00_rf(rt2x00dev, RF3021) ||
  702. rt2x00_rf(rt2x00dev, RF3022)))
  703. rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
  704. else
  705. rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
  706. /*
  707. * Change BBP settings
  708. */
  709. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  710. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  711. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  712. rt2800_bbp_write(rt2x00dev, 86, 0);
  713. if (rf->channel <= 14) {
  714. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  715. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  716. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  717. } else {
  718. rt2800_bbp_write(rt2x00dev, 82, 0x84);
  719. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  720. }
  721. } else {
  722. rt2800_bbp_write(rt2x00dev, 82, 0xf2);
  723. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  724. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  725. else
  726. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  727. }
  728. rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
  729. rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
  730. rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
  731. rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
  732. rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
  733. tx_pin = 0;
  734. /* Turn on unused PA or LNA when not using 1T or 1R */
  735. if (rt2x00dev->default_ant.tx != 1) {
  736. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
  737. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
  738. }
  739. /* Turn on unused PA or LNA when not using 1T or 1R */
  740. if (rt2x00dev->default_ant.rx != 1) {
  741. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
  742. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
  743. }
  744. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
  745. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
  746. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
  747. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
  748. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
  749. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
  750. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  751. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  752. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
  753. rt2800_bbp_write(rt2x00dev, 4, bbp);
  754. rt2800_bbp_read(rt2x00dev, 3, &bbp);
  755. rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
  756. rt2800_bbp_write(rt2x00dev, 3, bbp);
  757. if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
  758. if (conf_is_ht40(conf)) {
  759. rt2800_bbp_write(rt2x00dev, 69, 0x1a);
  760. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  761. rt2800_bbp_write(rt2x00dev, 73, 0x16);
  762. } else {
  763. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  764. rt2800_bbp_write(rt2x00dev, 70, 0x08);
  765. rt2800_bbp_write(rt2x00dev, 73, 0x11);
  766. }
  767. }
  768. msleep(1);
  769. }
  770. static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
  771. const int txpower)
  772. {
  773. u32 reg;
  774. u32 value = TXPOWER_G_TO_DEV(txpower);
  775. u8 r1;
  776. rt2800_bbp_read(rt2x00dev, 1, &r1);
  777. rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
  778. rt2800_bbp_write(rt2x00dev, 1, r1);
  779. rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
  780. rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
  781. rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
  782. rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
  783. rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
  784. rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
  785. rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
  786. rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
  787. rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
  788. rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
  789. rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
  790. rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
  791. rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
  792. rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
  793. rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
  794. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
  795. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
  796. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
  797. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
  798. rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
  799. rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
  800. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
  801. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
  802. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
  803. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
  804. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
  805. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
  806. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
  807. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
  808. rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
  809. rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
  810. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
  811. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
  812. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
  813. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
  814. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
  815. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
  816. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
  817. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
  818. rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
  819. rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
  820. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
  821. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
  822. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
  823. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
  824. rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
  825. }
  826. static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  827. struct rt2x00lib_conf *libconf)
  828. {
  829. u32 reg;
  830. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  831. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
  832. libconf->conf->short_frame_max_tx_count);
  833. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
  834. libconf->conf->long_frame_max_tx_count);
  835. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
  836. rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
  837. rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
  838. rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
  839. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  840. }
  841. static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
  842. struct rt2x00lib_conf *libconf)
  843. {
  844. enum dev_state state =
  845. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  846. STATE_SLEEP : STATE_AWAKE;
  847. u32 reg;
  848. if (state == STATE_SLEEP) {
  849. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
  850. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  851. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
  852. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
  853. libconf->conf->listen_interval - 1);
  854. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
  855. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  856. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  857. } else {
  858. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  859. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  860. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
  861. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
  862. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
  863. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  864. }
  865. }
  866. void rt2800_config(struct rt2x00_dev *rt2x00dev,
  867. struct rt2x00lib_conf *libconf,
  868. const unsigned int flags)
  869. {
  870. /* Always recalculate LNA gain before changing configuration */
  871. rt2800_config_lna_gain(rt2x00dev, libconf);
  872. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  873. rt2800_config_channel(rt2x00dev, libconf->conf,
  874. &libconf->rf, &libconf->channel);
  875. if (flags & IEEE80211_CONF_CHANGE_POWER)
  876. rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
  877. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  878. rt2800_config_retry_limit(rt2x00dev, libconf);
  879. if (flags & IEEE80211_CONF_CHANGE_PS)
  880. rt2800_config_ps(rt2x00dev, libconf);
  881. }
  882. EXPORT_SYMBOL_GPL(rt2800_config);
  883. /*
  884. * Link tuning
  885. */
  886. void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  887. {
  888. u32 reg;
  889. /*
  890. * Update FCS error count from register.
  891. */
  892. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  893. qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
  894. }
  895. EXPORT_SYMBOL_GPL(rt2800_link_stats);
  896. static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
  897. {
  898. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  899. if (rt2x00_intf_is_usb(rt2x00dev) &&
  900. rt2x00_rev(rt2x00dev) == RT3070_VERSION)
  901. return 0x1c + (2 * rt2x00dev->lna_gain);
  902. else
  903. return 0x2e + rt2x00dev->lna_gain;
  904. }
  905. if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  906. return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
  907. else
  908. return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
  909. }
  910. static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
  911. struct link_qual *qual, u8 vgc_level)
  912. {
  913. if (qual->vgc_level != vgc_level) {
  914. rt2800_bbp_write(rt2x00dev, 66, vgc_level);
  915. qual->vgc_level = vgc_level;
  916. qual->vgc_level_reg = vgc_level;
  917. }
  918. }
  919. void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  920. {
  921. rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
  922. }
  923. EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
  924. void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
  925. const u32 count)
  926. {
  927. if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)
  928. return;
  929. /*
  930. * When RSSI is better then -80 increase VGC level with 0x10
  931. */
  932. rt2800_set_vgc(rt2x00dev, qual,
  933. rt2800_get_default_vgc(rt2x00dev) +
  934. ((qual->rssi > -80) * 0x10));
  935. }
  936. EXPORT_SYMBOL_GPL(rt2800_link_tuner);
  937. /*
  938. * Initialization functions.
  939. */
  940. int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  941. {
  942. u32 reg;
  943. unsigned int i;
  944. if (rt2x00_intf_is_usb(rt2x00dev)) {
  945. /*
  946. * Wait until BBP and RF are ready.
  947. */
  948. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  949. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  950. if (reg && reg != ~0)
  951. break;
  952. msleep(1);
  953. }
  954. if (i == REGISTER_BUSY_COUNT) {
  955. ERROR(rt2x00dev, "Unstable hardware.\n");
  956. return -EBUSY;
  957. }
  958. rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
  959. rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
  960. reg & ~0x00002000);
  961. } else if (rt2x00_intf_is_pci(rt2x00dev))
  962. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  963. rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  964. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
  965. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
  966. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  967. if (rt2x00_intf_is_usb(rt2x00dev)) {
  968. rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
  969. #if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
  970. rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
  971. USB_MODE_RESET, REGISTER_TIMEOUT);
  972. #endif
  973. }
  974. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  975. rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
  976. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
  977. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
  978. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
  979. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
  980. rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
  981. rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
  982. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
  983. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
  984. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
  985. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
  986. rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
  987. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
  988. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  989. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  990. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  991. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
  992. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  993. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
  994. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  995. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  996. rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
  997. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  998. if (rt2x00_intf_is_usb(rt2x00dev) &&
  999. rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
  1000. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1001. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1002. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1003. } else {
  1004. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
  1005. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1006. }
  1007. rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
  1008. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
  1009. rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
  1010. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
  1011. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
  1012. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
  1013. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
  1014. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
  1015. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
  1016. rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
  1017. rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
  1018. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
  1019. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
  1020. rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
  1021. rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
  1022. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
  1023. if (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION &&
  1024. rt2x00_rev(rt2x00dev) < RT3070_VERSION)
  1025. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
  1026. else
  1027. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
  1028. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
  1029. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
  1030. rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
  1031. rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
  1032. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  1033. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
  1034. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
  1035. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
  1036. rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
  1037. rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
  1038. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  1039. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  1040. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
  1041. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
  1042. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
  1043. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1044. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1045. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1046. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1047. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1048. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1049. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  1050. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  1051. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
  1052. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
  1053. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
  1054. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1055. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1056. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1057. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1058. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1059. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1060. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  1061. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  1062. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
  1063. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
  1064. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
  1065. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1066. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1067. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1068. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1069. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1070. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1071. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  1072. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  1073. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
  1074. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
  1075. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
  1076. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1077. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1078. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1079. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1080. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1081. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1082. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  1083. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  1084. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
  1085. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
  1086. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
  1087. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1088. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1089. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1090. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1091. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1092. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1093. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  1094. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  1095. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
  1096. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
  1097. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
  1098. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1099. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1100. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1101. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1102. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1103. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1104. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  1105. if (rt2x00_intf_is_usb(rt2x00dev)) {
  1106. rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
  1107. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  1108. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  1109. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  1110. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  1111. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  1112. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
  1113. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
  1114. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
  1115. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
  1116. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
  1117. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  1118. }
  1119. rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
  1120. rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
  1121. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  1122. rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
  1123. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
  1124. IEEE80211_MAX_RTS_THRESHOLD);
  1125. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
  1126. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  1127. rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
  1128. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  1129. /*
  1130. * ASIC will keep garbage value after boot, clear encryption keys.
  1131. */
  1132. for (i = 0; i < 4; i++)
  1133. rt2800_register_write(rt2x00dev,
  1134. SHARED_KEY_MODE_ENTRY(i), 0);
  1135. for (i = 0; i < 256; i++) {
  1136. u32 wcid[2] = { 0xffffffff, 0x00ffffff };
  1137. rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
  1138. wcid, sizeof(wcid));
  1139. rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
  1140. rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
  1141. }
  1142. /*
  1143. * Clear all beacons
  1144. * For the Beacon base registers we only need to clear
  1145. * the first byte since that byte contains the VALID and OWNER
  1146. * bits which (when set to 0) will invalidate the entire beacon.
  1147. */
  1148. rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  1149. rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  1150. rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  1151. rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  1152. rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
  1153. rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
  1154. rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
  1155. rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
  1156. if (rt2x00_intf_is_usb(rt2x00dev)) {
  1157. rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
  1158. rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
  1159. rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
  1160. }
  1161. rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
  1162. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
  1163. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
  1164. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
  1165. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
  1166. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
  1167. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
  1168. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
  1169. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
  1170. rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
  1171. rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
  1172. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
  1173. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
  1174. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
  1175. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
  1176. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
  1177. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
  1178. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
  1179. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
  1180. rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
  1181. rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
  1182. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
  1183. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
  1184. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
  1185. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
  1186. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
  1187. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
  1188. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
  1189. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
  1190. rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
  1191. rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
  1192. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
  1193. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
  1194. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
  1195. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
  1196. rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
  1197. /*
  1198. * We must clear the error counters.
  1199. * These registers are cleared on read,
  1200. * so we may pass a useless variable to store the value.
  1201. */
  1202. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  1203. rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
  1204. rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
  1205. rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
  1206. rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
  1207. rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
  1208. return 0;
  1209. }
  1210. EXPORT_SYMBOL_GPL(rt2800_init_registers);
  1211. static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
  1212. {
  1213. unsigned int i;
  1214. u32 reg;
  1215. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1216. rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
  1217. if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
  1218. return 0;
  1219. udelay(REGISTER_BUSY_DELAY);
  1220. }
  1221. ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
  1222. return -EACCES;
  1223. }
  1224. static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  1225. {
  1226. unsigned int i;
  1227. u8 value;
  1228. /*
  1229. * BBP was enabled after firmware was loaded,
  1230. * but we need to reactivate it now.
  1231. */
  1232. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  1233. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  1234. msleep(1);
  1235. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1236. rt2800_bbp_read(rt2x00dev, 0, &value);
  1237. if ((value != 0xff) && (value != 0x00))
  1238. return 0;
  1239. udelay(REGISTER_BUSY_DELAY);
  1240. }
  1241. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1242. return -EACCES;
  1243. }
  1244. int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  1245. {
  1246. unsigned int i;
  1247. u16 eeprom;
  1248. u8 reg_id;
  1249. u8 value;
  1250. if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
  1251. rt2800_wait_bbp_ready(rt2x00dev)))
  1252. return -EACCES;
  1253. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  1254. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  1255. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  1256. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  1257. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  1258. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  1259. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  1260. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  1261. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  1262. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  1263. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  1264. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  1265. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  1266. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  1267. if (rt2x00_rev(rt2x00dev) == RT2860C_VERSION) {
  1268. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  1269. rt2800_bbp_write(rt2x00dev, 73, 0x12);
  1270. }
  1271. if (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)
  1272. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  1273. if (rt2x00_intf_is_usb(rt2x00dev) &&
  1274. rt2x00_rev(rt2x00dev) == RT3070_VERSION) {
  1275. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  1276. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  1277. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  1278. }
  1279. if (rt2x00_rt(rt2x00dev, RT3052)) {
  1280. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  1281. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  1282. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  1283. }
  1284. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1285. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1286. if (eeprom != 0xffff && eeprom != 0x0000) {
  1287. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1288. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1289. rt2800_bbp_write(rt2x00dev, reg_id, value);
  1290. }
  1291. }
  1292. return 0;
  1293. }
  1294. EXPORT_SYMBOL_GPL(rt2800_init_bbp);
  1295. static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
  1296. bool bw40, u8 rfcsr24, u8 filter_target)
  1297. {
  1298. unsigned int i;
  1299. u8 bbp;
  1300. u8 rfcsr;
  1301. u8 passband;
  1302. u8 stopband;
  1303. u8 overtuned = 0;
  1304. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1305. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1306. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
  1307. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1308. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1309. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
  1310. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1311. /*
  1312. * Set power & frequency of passband test tone
  1313. */
  1314. rt2800_bbp_write(rt2x00dev, 24, 0);
  1315. for (i = 0; i < 100; i++) {
  1316. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1317. msleep(1);
  1318. rt2800_bbp_read(rt2x00dev, 55, &passband);
  1319. if (passband)
  1320. break;
  1321. }
  1322. /*
  1323. * Set power & frequency of stopband test tone
  1324. */
  1325. rt2800_bbp_write(rt2x00dev, 24, 0x06);
  1326. for (i = 0; i < 100; i++) {
  1327. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1328. msleep(1);
  1329. rt2800_bbp_read(rt2x00dev, 55, &stopband);
  1330. if ((passband - stopband) <= filter_target) {
  1331. rfcsr24++;
  1332. overtuned += ((passband - stopband) == filter_target);
  1333. } else
  1334. break;
  1335. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1336. }
  1337. rfcsr24 -= !!overtuned;
  1338. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1339. return rfcsr24;
  1340. }
  1341. int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  1342. {
  1343. u8 rfcsr;
  1344. u8 bbp;
  1345. if (rt2x00_intf_is_usb(rt2x00dev) &&
  1346. rt2x00_rev(rt2x00dev) != RT3070_VERSION)
  1347. return 0;
  1348. if (rt2x00_intf_is_pci(rt2x00dev)) {
  1349. if (!rt2x00_rf(rt2x00dev, RF3020) &&
  1350. !rt2x00_rf(rt2x00dev, RF3021) &&
  1351. !rt2x00_rf(rt2x00dev, RF3022))
  1352. return 0;
  1353. }
  1354. /*
  1355. * Init RF calibration.
  1356. */
  1357. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  1358. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
  1359. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1360. msleep(1);
  1361. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
  1362. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1363. if (rt2x00_intf_is_usb(rt2x00dev)) {
  1364. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1365. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1366. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1367. rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
  1368. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1369. rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
  1370. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1371. rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
  1372. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1373. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1374. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1375. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1376. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1377. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1378. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1379. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1380. rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
  1381. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1382. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  1383. rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
  1384. } else if (rt2x00_intf_is_pci(rt2x00dev)) {
  1385. rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
  1386. rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
  1387. rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
  1388. rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
  1389. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1390. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1391. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1392. rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
  1393. rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
  1394. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1395. rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
  1396. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1397. rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
  1398. rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
  1399. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1400. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1401. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1402. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1403. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1404. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1405. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1406. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1407. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1408. rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
  1409. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  1410. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1411. rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
  1412. rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
  1413. rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
  1414. rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
  1415. }
  1416. /*
  1417. * Set RX Filter calibration for 20MHz and 40MHz
  1418. */
  1419. rt2x00dev->calibration[0] =
  1420. rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
  1421. rt2x00dev->calibration[1] =
  1422. rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
  1423. /*
  1424. * Set back to initial state
  1425. */
  1426. rt2800_bbp_write(rt2x00dev, 24, 0);
  1427. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1428. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
  1429. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1430. /*
  1431. * set BBP back to BW20
  1432. */
  1433. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1434. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
  1435. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1436. return 0;
  1437. }
  1438. EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
  1439. int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
  1440. {
  1441. u32 reg;
  1442. rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
  1443. return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
  1444. }
  1445. EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
  1446. static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
  1447. {
  1448. u32 reg;
  1449. mutex_lock(&rt2x00dev->csr_mutex);
  1450. rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
  1451. rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
  1452. rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
  1453. rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
  1454. rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
  1455. /* Wait until the EEPROM has been loaded */
  1456. rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
  1457. /* Apparently the data is read from end to start */
  1458. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
  1459. (u32 *)&rt2x00dev->eeprom[i]);
  1460. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
  1461. (u32 *)&rt2x00dev->eeprom[i + 2]);
  1462. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
  1463. (u32 *)&rt2x00dev->eeprom[i + 4]);
  1464. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
  1465. (u32 *)&rt2x00dev->eeprom[i + 6]);
  1466. mutex_unlock(&rt2x00dev->csr_mutex);
  1467. }
  1468. void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  1469. {
  1470. unsigned int i;
  1471. for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
  1472. rt2800_efuse_read(rt2x00dev, i);
  1473. }
  1474. EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
  1475. int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1476. {
  1477. u16 word;
  1478. u8 *mac;
  1479. u8 default_lna_gain;
  1480. /*
  1481. * Start validation of the data that has been read.
  1482. */
  1483. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1484. if (!is_valid_ether_addr(mac)) {
  1485. random_ether_addr(mac);
  1486. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1487. }
  1488. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1489. if (word == 0xffff) {
  1490. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1491. rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
  1492. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
  1493. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1494. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1495. } else if (rt2x00_rev(rt2x00dev) < RT2883_VERSION) {
  1496. /*
  1497. * There is a max of 2 RX streams for RT28x0 series
  1498. */
  1499. if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
  1500. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1501. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1502. }
  1503. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1504. if (word == 0xffff) {
  1505. rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
  1506. rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
  1507. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1508. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1509. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1510. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
  1511. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
  1512. rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
  1513. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
  1514. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
  1515. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1516. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1517. }
  1518. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1519. if ((word & 0x00ff) == 0x00ff) {
  1520. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1521. rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
  1522. LED_MODE_TXRX_ACTIVITY);
  1523. rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
  1524. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1525. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
  1526. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
  1527. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
  1528. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1529. }
  1530. /*
  1531. * During the LNA validation we are going to use
  1532. * lna0 as correct value. Note that EEPROM_LNA
  1533. * is never validated.
  1534. */
  1535. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
  1536. default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
  1537. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
  1538. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
  1539. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
  1540. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
  1541. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
  1542. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
  1543. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
  1544. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
  1545. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
  1546. if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
  1547. rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
  1548. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
  1549. default_lna_gain);
  1550. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
  1551. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
  1552. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
  1553. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
  1554. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
  1555. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
  1556. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
  1557. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
  1558. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
  1559. rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
  1560. if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
  1561. rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
  1562. rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
  1563. default_lna_gain);
  1564. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
  1565. return 0;
  1566. }
  1567. EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
  1568. int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1569. {
  1570. u32 reg;
  1571. u16 value;
  1572. u16 eeprom;
  1573. /*
  1574. * Read EEPROM word for configuration.
  1575. */
  1576. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1577. /*
  1578. * Identify RF chipset.
  1579. */
  1580. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1581. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  1582. rt2x00_set_chip_rf(rt2x00dev, value, reg);
  1583. if (rt2x00_intf_is_usb(rt2x00dev)) {
  1584. /*
  1585. * The check for rt2860 is not a typo, some rt2870 hardware
  1586. * identifies itself as rt2860 in the CSR register.
  1587. */
  1588. if (rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28600000) ||
  1589. rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28700000) ||
  1590. rt2x00_check_rev(rt2x00dev, 0xfff00000, 0x28800000)) {
  1591. rt2x00_set_chip_rt(rt2x00dev, RT2870);
  1592. } else if (rt2x00_check_rev(rt2x00dev, 0xffff0000, 0x30700000)) {
  1593. rt2x00_set_chip_rt(rt2x00dev, RT3070);
  1594. } else {
  1595. ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
  1596. return -ENODEV;
  1597. }
  1598. }
  1599. rt2x00_print_chip(rt2x00dev);
  1600. if (!rt2x00_rf(rt2x00dev, RF2820) &&
  1601. !rt2x00_rf(rt2x00dev, RF2850) &&
  1602. !rt2x00_rf(rt2x00dev, RF2720) &&
  1603. !rt2x00_rf(rt2x00dev, RF2750) &&
  1604. !rt2x00_rf(rt2x00dev, RF3020) &&
  1605. !rt2x00_rf(rt2x00dev, RF2020) &&
  1606. !rt2x00_rf(rt2x00dev, RF3021) &&
  1607. !rt2x00_rf(rt2x00dev, RF3022) &&
  1608. !rt2x00_rf(rt2x00dev, RF3052)) {
  1609. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1610. return -ENODEV;
  1611. }
  1612. /*
  1613. * Identify default antenna configuration.
  1614. */
  1615. rt2x00dev->default_ant.tx =
  1616. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
  1617. rt2x00dev->default_ant.rx =
  1618. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
  1619. /*
  1620. * Read frequency offset and RF programming sequence.
  1621. */
  1622. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1623. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  1624. /*
  1625. * Read external LNA informations.
  1626. */
  1627. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1628. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  1629. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  1630. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1631. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  1632. /*
  1633. * Detect if this device has an hardware controlled radio.
  1634. */
  1635. if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
  1636. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1637. /*
  1638. * Store led settings, for correct led behaviour.
  1639. */
  1640. #ifdef CONFIG_RT2X00_LIB_LEDS
  1641. rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1642. rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  1643. rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
  1644. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
  1645. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1646. return 0;
  1647. }
  1648. EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
  1649. /*
  1650. * RF value list for rt28x0
  1651. * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
  1652. */
  1653. static const struct rf_channel rf_vals[] = {
  1654. { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
  1655. { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
  1656. { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
  1657. { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
  1658. { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
  1659. { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
  1660. { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
  1661. { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
  1662. { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
  1663. { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
  1664. { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
  1665. { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
  1666. { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
  1667. { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
  1668. /* 802.11 UNI / HyperLan 2 */
  1669. { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
  1670. { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
  1671. { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
  1672. { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
  1673. { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
  1674. { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
  1675. { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
  1676. { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
  1677. { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
  1678. { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
  1679. { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
  1680. { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
  1681. /* 802.11 HyperLan 2 */
  1682. { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
  1683. { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
  1684. { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
  1685. { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
  1686. { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
  1687. { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
  1688. { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
  1689. { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
  1690. { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
  1691. { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
  1692. { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
  1693. { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
  1694. { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
  1695. { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
  1696. { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
  1697. { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
  1698. /* 802.11 UNII */
  1699. { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
  1700. { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
  1701. { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
  1702. { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
  1703. { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
  1704. { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
  1705. { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
  1706. { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
  1707. { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
  1708. { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
  1709. { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
  1710. /* 802.11 Japan */
  1711. { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
  1712. { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
  1713. { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
  1714. { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
  1715. { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
  1716. { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
  1717. { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
  1718. };
  1719. /*
  1720. * RF value list for rt3070
  1721. * Supports: 2.4 GHz
  1722. */
  1723. static const struct rf_channel rf_vals_302x[] = {
  1724. {1, 241, 2, 2 },
  1725. {2, 241, 2, 7 },
  1726. {3, 242, 2, 2 },
  1727. {4, 242, 2, 7 },
  1728. {5, 243, 2, 2 },
  1729. {6, 243, 2, 7 },
  1730. {7, 244, 2, 2 },
  1731. {8, 244, 2, 7 },
  1732. {9, 245, 2, 2 },
  1733. {10, 245, 2, 7 },
  1734. {11, 246, 2, 2 },
  1735. {12, 246, 2, 7 },
  1736. {13, 247, 2, 2 },
  1737. {14, 248, 2, 4 },
  1738. };
  1739. int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1740. {
  1741. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1742. struct channel_info *info;
  1743. char *tx_power1;
  1744. char *tx_power2;
  1745. unsigned int i;
  1746. u16 eeprom;
  1747. /*
  1748. * Disable powersaving as default on PCI devices.
  1749. */
  1750. if (rt2x00_intf_is_pci(rt2x00dev))
  1751. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  1752. /*
  1753. * Initialize all hw fields.
  1754. */
  1755. rt2x00dev->hw->flags =
  1756. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1757. IEEE80211_HW_SIGNAL_DBM |
  1758. IEEE80211_HW_SUPPORTS_PS |
  1759. IEEE80211_HW_PS_NULLFUNC_STACK;
  1760. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  1761. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1762. rt2x00_eeprom_addr(rt2x00dev,
  1763. EEPROM_MAC_ADDR_0));
  1764. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1765. /*
  1766. * Initialize hw_mode information.
  1767. */
  1768. spec->supported_bands = SUPPORT_BAND_2GHZ;
  1769. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  1770. if (rt2x00_rf(rt2x00dev, RF2820) ||
  1771. rt2x00_rf(rt2x00dev, RF2720) ||
  1772. rt2x00_rf(rt2x00dev, RF3052)) {
  1773. spec->num_channels = 14;
  1774. spec->channels = rf_vals;
  1775. } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) {
  1776. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  1777. spec->num_channels = ARRAY_SIZE(rf_vals);
  1778. spec->channels = rf_vals;
  1779. } else if (rt2x00_rf(rt2x00dev, RF3020) ||
  1780. rt2x00_rf(rt2x00dev, RF2020) ||
  1781. rt2x00_rf(rt2x00dev, RF3021) ||
  1782. rt2x00_rf(rt2x00dev, RF3022)) {
  1783. spec->num_channels = ARRAY_SIZE(rf_vals_302x);
  1784. spec->channels = rf_vals_302x;
  1785. }
  1786. /*
  1787. * Initialize HT information.
  1788. */
  1789. if (!rt2x00_rf(rt2x00dev, RF2020))
  1790. spec->ht.ht_supported = true;
  1791. else
  1792. spec->ht.ht_supported = false;
  1793. spec->ht.cap =
  1794. IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  1795. IEEE80211_HT_CAP_GRN_FLD |
  1796. IEEE80211_HT_CAP_SGI_20 |
  1797. IEEE80211_HT_CAP_SGI_40 |
  1798. IEEE80211_HT_CAP_TX_STBC |
  1799. IEEE80211_HT_CAP_RX_STBC;
  1800. spec->ht.ampdu_factor = 3;
  1801. spec->ht.ampdu_density = 4;
  1802. spec->ht.mcs.tx_params =
  1803. IEEE80211_HT_MCS_TX_DEFINED |
  1804. IEEE80211_HT_MCS_TX_RX_DIFF |
  1805. ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
  1806. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  1807. switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
  1808. case 3:
  1809. spec->ht.mcs.rx_mask[2] = 0xff;
  1810. case 2:
  1811. spec->ht.mcs.rx_mask[1] = 0xff;
  1812. case 1:
  1813. spec->ht.mcs.rx_mask[0] = 0xff;
  1814. spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
  1815. break;
  1816. }
  1817. /*
  1818. * Create channel information array
  1819. */
  1820. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  1821. if (!info)
  1822. return -ENOMEM;
  1823. spec->channels_info = info;
  1824. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
  1825. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
  1826. for (i = 0; i < 14; i++) {
  1827. info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
  1828. info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
  1829. }
  1830. if (spec->num_channels > 14) {
  1831. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
  1832. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
  1833. for (i = 14; i < spec->num_channels; i++) {
  1834. info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
  1835. info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
  1836. }
  1837. }
  1838. return 0;
  1839. }
  1840. EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
  1841. /*
  1842. * IEEE80211 stack callback functions.
  1843. */
  1844. static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
  1845. u32 *iv32, u16 *iv16)
  1846. {
  1847. struct rt2x00_dev *rt2x00dev = hw->priv;
  1848. struct mac_iveiv_entry iveiv_entry;
  1849. u32 offset;
  1850. offset = MAC_IVEIV_ENTRY(hw_key_idx);
  1851. rt2800_register_multiread(rt2x00dev, offset,
  1852. &iveiv_entry, sizeof(iveiv_entry));
  1853. memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
  1854. memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
  1855. }
  1856. static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  1857. {
  1858. struct rt2x00_dev *rt2x00dev = hw->priv;
  1859. u32 reg;
  1860. bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
  1861. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  1862. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
  1863. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  1864. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  1865. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
  1866. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  1867. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  1868. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
  1869. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  1870. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  1871. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
  1872. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  1873. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  1874. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
  1875. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  1876. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  1877. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
  1878. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  1879. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  1880. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
  1881. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  1882. return 0;
  1883. }
  1884. static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
  1885. const struct ieee80211_tx_queue_params *params)
  1886. {
  1887. struct rt2x00_dev *rt2x00dev = hw->priv;
  1888. struct data_queue *queue;
  1889. struct rt2x00_field32 field;
  1890. int retval;
  1891. u32 reg;
  1892. u32 offset;
  1893. /*
  1894. * First pass the configuration through rt2x00lib, that will
  1895. * update the queue settings and validate the input. After that
  1896. * we are free to update the registers based on the value
  1897. * in the queue parameter.
  1898. */
  1899. retval = rt2x00mac_conf_tx(hw, queue_idx, params);
  1900. if (retval)
  1901. return retval;
  1902. /*
  1903. * We only need to perform additional register initialization
  1904. * for WMM queues/
  1905. */
  1906. if (queue_idx >= 4)
  1907. return 0;
  1908. queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  1909. /* Update WMM TXOP register */
  1910. offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
  1911. field.bit_offset = (queue_idx & 1) * 16;
  1912. field.bit_mask = 0xffff << field.bit_offset;
  1913. rt2800_register_read(rt2x00dev, offset, &reg);
  1914. rt2x00_set_field32(&reg, field, queue->txop);
  1915. rt2800_register_write(rt2x00dev, offset, reg);
  1916. /* Update WMM registers */
  1917. field.bit_offset = queue_idx * 4;
  1918. field.bit_mask = 0xf << field.bit_offset;
  1919. rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
  1920. rt2x00_set_field32(&reg, field, queue->aifs);
  1921. rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
  1922. rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
  1923. rt2x00_set_field32(&reg, field, queue->cw_min);
  1924. rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
  1925. rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
  1926. rt2x00_set_field32(&reg, field, queue->cw_max);
  1927. rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
  1928. /* Update EDCA registers */
  1929. offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
  1930. rt2800_register_read(rt2x00dev, offset, &reg);
  1931. rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
  1932. rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
  1933. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
  1934. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
  1935. rt2800_register_write(rt2x00dev, offset, reg);
  1936. return 0;
  1937. }
  1938. static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
  1939. {
  1940. struct rt2x00_dev *rt2x00dev = hw->priv;
  1941. u64 tsf;
  1942. u32 reg;
  1943. rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
  1944. tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
  1945. rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
  1946. tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
  1947. return tsf;
  1948. }
  1949. const struct ieee80211_ops rt2800_mac80211_ops = {
  1950. .tx = rt2x00mac_tx,
  1951. .start = rt2x00mac_start,
  1952. .stop = rt2x00mac_stop,
  1953. .add_interface = rt2x00mac_add_interface,
  1954. .remove_interface = rt2x00mac_remove_interface,
  1955. .config = rt2x00mac_config,
  1956. .configure_filter = rt2x00mac_configure_filter,
  1957. .set_tim = rt2x00mac_set_tim,
  1958. .set_key = rt2x00mac_set_key,
  1959. .get_stats = rt2x00mac_get_stats,
  1960. .get_tkip_seq = rt2800_get_tkip_seq,
  1961. .set_rts_threshold = rt2800_set_rts_threshold,
  1962. .bss_info_changed = rt2x00mac_bss_info_changed,
  1963. .conf_tx = rt2800_conf_tx,
  1964. .get_tsf = rt2800_get_tsf,
  1965. .rfkill_poll = rt2x00mac_rfkill_poll,
  1966. };
  1967. EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);