rainier.dts 8.4 KB

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  1. /*
  2. * Device Tree Source for AMCC Rainier
  3. *
  4. * Based on Sequoia code
  5. * Copyright (c) 2007 MontaVista Software, Inc.
  6. *
  7. * FIXME: Draft only!
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without
  11. * any warranty of any kind, whether express or implied.
  12. *
  13. */
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,rainier";
  18. compatible = "amcc,rainier";
  19. dcr-parent = <&/cpus/cpu@0>;
  20. aliases {
  21. ethernet0 = &EMAC0;
  22. ethernet1 = &EMAC1;
  23. serial0 = &UART0;
  24. serial1 = &UART1;
  25. serial2 = &UART2;
  26. serial3 = &UART3;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. cpu@0 {
  32. device_type = "cpu";
  33. model = "PowerPC,440GRx";
  34. reg = <0>;
  35. clock-frequency = <0>; /* Filled in by zImage */
  36. timebase-frequency = <0>; /* Filled in by zImage */
  37. i-cache-line-size = <20>;
  38. d-cache-line-size = <20>;
  39. i-cache-size = <8000>;
  40. d-cache-size = <8000>;
  41. dcr-controller;
  42. dcr-access-method = "native";
  43. };
  44. };
  45. memory {
  46. device_type = "memory";
  47. reg = <0 0 0>; /* Filled in by zImage */
  48. };
  49. UIC0: interrupt-controller0 {
  50. compatible = "ibm,uic-440grx","ibm,uic";
  51. interrupt-controller;
  52. cell-index = <0>;
  53. dcr-reg = <0c0 009>;
  54. #address-cells = <0>;
  55. #size-cells = <0>;
  56. #interrupt-cells = <2>;
  57. };
  58. UIC1: interrupt-controller1 {
  59. compatible = "ibm,uic-440grx","ibm,uic";
  60. interrupt-controller;
  61. cell-index = <1>;
  62. dcr-reg = <0d0 009>;
  63. #address-cells = <0>;
  64. #size-cells = <0>;
  65. #interrupt-cells = <2>;
  66. interrupts = <1e 4 1f 4>; /* cascade */
  67. interrupt-parent = <&UIC0>;
  68. };
  69. UIC2: interrupt-controller2 {
  70. compatible = "ibm,uic-440grx","ibm,uic";
  71. interrupt-controller;
  72. cell-index = <2>;
  73. dcr-reg = <0e0 009>;
  74. #address-cells = <0>;
  75. #size-cells = <0>;
  76. #interrupt-cells = <2>;
  77. interrupts = <1c 4 1d 4>; /* cascade */
  78. interrupt-parent = <&UIC0>;
  79. };
  80. SDR0: sdr {
  81. compatible = "ibm,sdr-440grx", "ibm,sdr-440ep";
  82. dcr-reg = <00e 002>;
  83. };
  84. CPR0: cpr {
  85. compatible = "ibm,cpr-440grx", "ibm,cpr-440ep";
  86. dcr-reg = <00c 002>;
  87. };
  88. plb {
  89. compatible = "ibm,plb-440grx", "ibm,plb4";
  90. #address-cells = <2>;
  91. #size-cells = <1>;
  92. ranges;
  93. clock-frequency = <0>; /* Filled in by zImage */
  94. SDRAM0: sdram {
  95. compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali";
  96. dcr-reg = <010 2>;
  97. };
  98. DMA0: dma {
  99. compatible = "ibm,dma-440grx", "ibm,dma-4xx";
  100. dcr-reg = <100 027>;
  101. };
  102. MAL0: mcmal {
  103. compatible = "ibm,mcmal-440grx", "ibm,mcmal2";
  104. dcr-reg = <180 62>;
  105. num-tx-chans = <2>;
  106. num-rx-chans = <2>;
  107. interrupt-parent = <&MAL0>;
  108. interrupts = <0 1 2 3 4>;
  109. #interrupt-cells = <1>;
  110. #address-cells = <0>;
  111. #size-cells = <0>;
  112. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  113. /*RXEOB*/ 1 &UIC0 b 4
  114. /*SERR*/ 2 &UIC1 0 4
  115. /*TXDE*/ 3 &UIC1 1 4
  116. /*RXDE*/ 4 &UIC1 2 4>;
  117. interrupt-map-mask = <ffffffff>;
  118. };
  119. POB0: opb {
  120. compatible = "ibm,opb-440grx", "ibm,opb";
  121. #address-cells = <1>;
  122. #size-cells = <1>;
  123. ranges = <00000000 1 00000000 80000000
  124. 80000000 1 80000000 80000000>;
  125. interrupt-parent = <&UIC1>;
  126. interrupts = <7 4>;
  127. clock-frequency = <0>; /* Filled in by zImage */
  128. EBC0: ebc {
  129. compatible = "ibm,ebc-440grx", "ibm,ebc";
  130. dcr-reg = <012 2>;
  131. #address-cells = <2>;
  132. #size-cells = <1>;
  133. clock-frequency = <0>; /* Filled in by zImage */
  134. interrupts = <5 1>;
  135. interrupt-parent = <&UIC1>;
  136. nor_flash@0,0 {
  137. compatible = "amd,s29gl256n", "cfi-flash";
  138. bank-width = <2>;
  139. reg = <0 000000 4000000>;
  140. #address-cells = <1>;
  141. #size-cells = <1>;
  142. partition@0 {
  143. label = "Kernel";
  144. reg = <0 180000>;
  145. };
  146. partition@180000 {
  147. label = "ramdisk";
  148. reg = <180000 200000>;
  149. };
  150. partition@380000 {
  151. label = "file system";
  152. reg = <380000 3aa0000>;
  153. };
  154. partition@3e20000 {
  155. label = "kozio";
  156. reg = <3e20000 140000>;
  157. };
  158. partition@3f60000 {
  159. label = "env";
  160. reg = <3f60000 40000>;
  161. };
  162. partition@3fa0000 {
  163. label = "u-boot";
  164. reg = <3fa0000 60000>;
  165. };
  166. };
  167. };
  168. UART0: serial@ef600300 {
  169. device_type = "serial";
  170. compatible = "ns16550";
  171. reg = <ef600300 8>;
  172. virtual-reg = <ef600300>;
  173. clock-frequency = <0>; /* Filled in by zImage */
  174. current-speed = <1c200>;
  175. interrupt-parent = <&UIC0>;
  176. interrupts = <0 4>;
  177. };
  178. UART1: serial@ef600400 {
  179. device_type = "serial";
  180. compatible = "ns16550";
  181. reg = <ef600400 8>;
  182. virtual-reg = <ef600400>;
  183. clock-frequency = <0>;
  184. current-speed = <0>;
  185. interrupt-parent = <&UIC0>;
  186. interrupts = <1 4>;
  187. };
  188. UART2: serial@ef600500 {
  189. device_type = "serial";
  190. compatible = "ns16550";
  191. reg = <ef600500 8>;
  192. virtual-reg = <ef600500>;
  193. clock-frequency = <0>;
  194. current-speed = <0>;
  195. interrupt-parent = <&UIC1>;
  196. interrupts = <3 4>;
  197. };
  198. UART3: serial@ef600600 {
  199. device_type = "serial";
  200. compatible = "ns16550";
  201. reg = <ef600600 8>;
  202. virtual-reg = <ef600600>;
  203. clock-frequency = <0>;
  204. current-speed = <0>;
  205. interrupt-parent = <&UIC1>;
  206. interrupts = <4 4>;
  207. };
  208. IIC0: i2c@ef600700 {
  209. device_type = "i2c";
  210. compatible = "ibm,iic-440grx", "ibm,iic";
  211. reg = <ef600700 14>;
  212. interrupt-parent = <&UIC0>;
  213. interrupts = <2 4>;
  214. };
  215. IIC1: i2c@ef600800 {
  216. device_type = "i2c";
  217. compatible = "ibm,iic-440grx", "ibm,iic";
  218. reg = <ef600800 14>;
  219. interrupt-parent = <&UIC0>;
  220. interrupts = <7 4>;
  221. };
  222. ZMII0: emac-zmii@ef600d00 {
  223. device_type = "zmii-interface";
  224. compatible = "ibm,zmii-440grx", "ibm,zmii";
  225. reg = <ef600d00 c>;
  226. };
  227. RGMII0: emac-rgmii@ef601000 {
  228. device_type = "rgmii-interface";
  229. compatible = "ibm,rgmii-440grx", "ibm,rgmii";
  230. reg = <ef601000 8>;
  231. has-mdio;
  232. };
  233. EMAC0: ethernet@ef600e00 {
  234. linux,network-index = <0>;
  235. device_type = "network";
  236. compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
  237. interrupt-parent = <&EMAC0>;
  238. interrupts = <0 1>;
  239. #interrupt-cells = <1>;
  240. #address-cells = <0>;
  241. #size-cells = <0>;
  242. interrupt-map = </*Status*/ 0 &UIC0 18 4
  243. /*Wake*/ 1 &UIC1 1d 4>;
  244. reg = <ef600e00 70>;
  245. local-mac-address = [000000000000];
  246. mal-device = <&MAL0>;
  247. mal-tx-channel = <0>;
  248. mal-rx-channel = <0>;
  249. cell-index = <0>;
  250. max-frame-size = <5dc>;
  251. rx-fifo-size = <1000>;
  252. tx-fifo-size = <800>;
  253. phy-mode = "rgmii";
  254. phy-map = <00000000>;
  255. zmii-device = <&ZMII0>;
  256. zmii-channel = <0>;
  257. rgmii-device = <&RGMII0>;
  258. rgmii-channel = <0>;
  259. has-inverted-stacr-oc;
  260. has-new-stacr-staopc;
  261. };
  262. EMAC1: ethernet@ef600f00 {
  263. linux,network-index = <1>;
  264. device_type = "network";
  265. compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4";
  266. interrupt-parent = <&EMAC1>;
  267. interrupts = <0 1>;
  268. #interrupt-cells = <1>;
  269. #address-cells = <0>;
  270. #size-cells = <0>;
  271. interrupt-map = </*Status*/ 0 &UIC0 19 4
  272. /*Wake*/ 1 &UIC1 1f 4>;
  273. reg = <ef600f00 70>;
  274. local-mac-address = [000000000000];
  275. mal-device = <&MAL0>;
  276. mal-tx-channel = <1>;
  277. mal-rx-channel = <1>;
  278. cell-index = <1>;
  279. max-frame-size = <5dc>;
  280. rx-fifo-size = <1000>;
  281. tx-fifo-size = <800>;
  282. phy-mode = "rgmii";
  283. phy-map = <00000000>;
  284. zmii-device = <&ZMII0>;
  285. zmii-channel = <1>;
  286. rgmii-device = <&RGMII0>;
  287. rgmii-channel = <1>;
  288. has-inverted-stacr-oc;
  289. has-new-stacr-staopc;
  290. };
  291. };
  292. PCI0: pci@1ec000000 {
  293. device_type = "pci";
  294. #interrupt-cells = <1>;
  295. #size-cells = <2>;
  296. #address-cells = <3>;
  297. compatible = "ibm,plb440grx-pci", "ibm,plb-pci";
  298. primary;
  299. reg = <1 eec00000 8 /* Config space access */
  300. 1 eed00000 4 /* IACK */
  301. 1 eed00000 4 /* Special cycle */
  302. 1 ef400000 40>; /* Internal registers */
  303. /* Outbound ranges, one memory and one IO,
  304. * later cannot be changed. Chip supports a second
  305. * IO range but we don't use it for now
  306. */
  307. ranges = <02000000 0 80000000 1 80000000 0 10000000
  308. 01000000 0 00000000 1 e8000000 0 00100000>;
  309. /* Inbound 2GB range starting at 0 */
  310. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  311. /* All PCI interrupts are routed to IRQ 67 */
  312. interrupt-map-mask = <0000 0 0 0>;
  313. interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
  314. };
  315. };
  316. chosen {
  317. linux,stdout-path = "/plb/opb/serial@ef600300";
  318. bootargs = "console=ttyS0,115200";
  319. };
  320. };