solos-pci.c 33 KB

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  1. /*
  2. * Driver for the Solos PCI ADSL2+ card, designed to support Linux by
  3. * Traverse Technologies -- http://www.traverse.com.au/
  4. * Xrio Limited -- http://www.xrio.com/
  5. *
  6. *
  7. * Copyright © 2008 Traverse Technologies
  8. * Copyright © 2008 Intel Corporation
  9. *
  10. * Authors: Nathan Williams <nathan@traverse.com.au>
  11. * David Woodhouse <dwmw2@infradead.org>
  12. * Treker Chen <treker@xrio.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License
  16. * version 2, as published by the Free Software Foundation.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/kernel.h>
  28. #include <linux/errno.h>
  29. #include <linux/ioport.h>
  30. #include <linux/types.h>
  31. #include <linux/pci.h>
  32. #include <linux/atm.h>
  33. #include <linux/atmdev.h>
  34. #include <linux/skbuff.h>
  35. #include <linux/sysfs.h>
  36. #include <linux/device.h>
  37. #include <linux/kobject.h>
  38. #include <linux/firmware.h>
  39. #include <linux/ctype.h>
  40. #include <linux/swab.h>
  41. #define VERSION "0.07"
  42. #define PTAG "solos-pci"
  43. #define CONFIG_RAM_SIZE 128
  44. #define FLAGS_ADDR 0x7C
  45. #define IRQ_EN_ADDR 0x78
  46. #define FPGA_VER 0x74
  47. #define IRQ_CLEAR 0x70
  48. #define WRITE_FLASH 0x6C
  49. #define PORTS 0x68
  50. #define FLASH_BLOCK 0x64
  51. #define FLASH_BUSY 0x60
  52. #define FPGA_MODE 0x5C
  53. #define FLASH_MODE 0x58
  54. #define TX_DMA_ADDR(port) (0x40 + (4 * (port)))
  55. #define RX_DMA_ADDR(port) (0x30 + (4 * (port)))
  56. #define DATA_RAM_SIZE 32768
  57. #define BUF_SIZE 4096
  58. #define FPGA_PAGE 528 /* FPGA flash page size*/
  59. #define SOLOS_PAGE 512 /* Solos flash page size*/
  60. #define FPGA_BLOCK (FPGA_PAGE * 8) /* FPGA flash block size*/
  61. #define SOLOS_BLOCK (SOLOS_PAGE * 8) /* Solos flash block size*/
  62. #define RX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2)
  63. #define TX_BUF(card, nr) ((card->buffers) + (nr)*BUF_SIZE*2 + BUF_SIZE)
  64. #define RX_DMA_SIZE 2048
  65. static int debug = 0;
  66. static int atmdebug = 0;
  67. static int firmware_upgrade = 0;
  68. static int fpga_upgrade = 0;
  69. struct pkt_hdr {
  70. __le16 size;
  71. __le16 vpi;
  72. __le16 vci;
  73. __le16 type;
  74. };
  75. struct solos_skb_cb {
  76. struct atm_vcc *vcc;
  77. uint32_t dma_addr;
  78. };
  79. #define SKB_CB(skb) ((struct solos_skb_cb *)skb->cb)
  80. #define PKT_DATA 0
  81. #define PKT_COMMAND 1
  82. #define PKT_POPEN 3
  83. #define PKT_PCLOSE 4
  84. #define PKT_STATUS 5
  85. struct solos_card {
  86. void __iomem *config_regs;
  87. void __iomem *buffers;
  88. int nr_ports;
  89. int tx_mask;
  90. struct pci_dev *dev;
  91. struct atm_dev *atmdev[4];
  92. struct tasklet_struct tlet;
  93. spinlock_t tx_lock;
  94. spinlock_t tx_queue_lock;
  95. spinlock_t cli_queue_lock;
  96. spinlock_t param_queue_lock;
  97. struct list_head param_queue;
  98. struct sk_buff_head tx_queue[4];
  99. struct sk_buff_head cli_queue[4];
  100. struct sk_buff *tx_skb[4];
  101. struct sk_buff *rx_skb[4];
  102. wait_queue_head_t param_wq;
  103. wait_queue_head_t fw_wq;
  104. int using_dma;
  105. };
  106. struct solos_param {
  107. struct list_head list;
  108. pid_t pid;
  109. int port;
  110. struct sk_buff *response;
  111. wait_queue_head_t wq;
  112. };
  113. #define SOLOS_CHAN(atmdev) ((int)(unsigned long)(atmdev)->phy_data)
  114. MODULE_AUTHOR("Traverse Technologies <support@traverse.com.au>");
  115. MODULE_DESCRIPTION("Solos PCI driver");
  116. MODULE_VERSION(VERSION);
  117. MODULE_LICENSE("GPL");
  118. MODULE_PARM_DESC(debug, "Enable Loopback");
  119. MODULE_PARM_DESC(atmdebug, "Print ATM data");
  120. MODULE_PARM_DESC(firmware_upgrade, "Initiate Solos firmware upgrade");
  121. MODULE_PARM_DESC(fpga_upgrade, "Initiate FPGA upgrade");
  122. module_param(debug, int, 0444);
  123. module_param(atmdebug, int, 0644);
  124. module_param(firmware_upgrade, int, 0444);
  125. module_param(fpga_upgrade, int, 0444);
  126. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  127. struct atm_vcc *vcc);
  128. static int fpga_tx(struct solos_card *);
  129. static irqreturn_t solos_irq(int irq, void *dev_id);
  130. static struct atm_vcc* find_vcc(struct atm_dev *dev, short vpi, int vci);
  131. static int list_vccs(int vci);
  132. static void release_vccs(struct atm_dev *dev);
  133. static int atm_init(struct solos_card *);
  134. static void atm_remove(struct solos_card *);
  135. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size);
  136. static void solos_bh(unsigned long);
  137. static int print_buffer(struct sk_buff *buf);
  138. static inline void solos_pop(struct atm_vcc *vcc, struct sk_buff *skb)
  139. {
  140. if (vcc->pop)
  141. vcc->pop(vcc, skb);
  142. else
  143. dev_kfree_skb_any(skb);
  144. }
  145. static ssize_t solos_param_show(struct device *dev, struct device_attribute *attr,
  146. char *buf)
  147. {
  148. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  149. struct solos_card *card = atmdev->dev_data;
  150. struct solos_param prm;
  151. struct sk_buff *skb;
  152. struct pkt_hdr *header;
  153. int buflen;
  154. buflen = strlen(attr->attr.name) + 10;
  155. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  156. if (!skb) {
  157. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_show()\n");
  158. return -ENOMEM;
  159. }
  160. header = (void *)skb_put(skb, sizeof(*header));
  161. buflen = snprintf((void *)&header[1], buflen - 1,
  162. "L%05d\n%s\n", current->pid, attr->attr.name);
  163. skb_put(skb, buflen);
  164. header->size = cpu_to_le16(buflen);
  165. header->vpi = cpu_to_le16(0);
  166. header->vci = cpu_to_le16(0);
  167. header->type = cpu_to_le16(PKT_COMMAND);
  168. prm.pid = current->pid;
  169. prm.response = NULL;
  170. prm.port = SOLOS_CHAN(atmdev);
  171. spin_lock_irq(&card->param_queue_lock);
  172. list_add(&prm.list, &card->param_queue);
  173. spin_unlock_irq(&card->param_queue_lock);
  174. fpga_queue(card, prm.port, skb, NULL);
  175. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  176. spin_lock_irq(&card->param_queue_lock);
  177. list_del(&prm.list);
  178. spin_unlock_irq(&card->param_queue_lock);
  179. if (!prm.response)
  180. return -EIO;
  181. buflen = prm.response->len;
  182. memcpy(buf, prm.response->data, buflen);
  183. kfree_skb(prm.response);
  184. return buflen;
  185. }
  186. static ssize_t solos_param_store(struct device *dev, struct device_attribute *attr,
  187. const char *buf, size_t count)
  188. {
  189. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  190. struct solos_card *card = atmdev->dev_data;
  191. struct solos_param prm;
  192. struct sk_buff *skb;
  193. struct pkt_hdr *header;
  194. int buflen;
  195. ssize_t ret;
  196. buflen = strlen(attr->attr.name) + 11 + count;
  197. skb = alloc_skb(sizeof(*header) + buflen, GFP_KERNEL);
  198. if (!skb) {
  199. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in solos_param_store()\n");
  200. return -ENOMEM;
  201. }
  202. header = (void *)skb_put(skb, sizeof(*header));
  203. buflen = snprintf((void *)&header[1], buflen - 1,
  204. "L%05d\n%s\n%s\n", current->pid, attr->attr.name, buf);
  205. skb_put(skb, buflen);
  206. header->size = cpu_to_le16(buflen);
  207. header->vpi = cpu_to_le16(0);
  208. header->vci = cpu_to_le16(0);
  209. header->type = cpu_to_le16(PKT_COMMAND);
  210. prm.pid = current->pid;
  211. prm.response = NULL;
  212. prm.port = SOLOS_CHAN(atmdev);
  213. spin_lock_irq(&card->param_queue_lock);
  214. list_add(&prm.list, &card->param_queue);
  215. spin_unlock_irq(&card->param_queue_lock);
  216. fpga_queue(card, prm.port, skb, NULL);
  217. wait_event_timeout(card->param_wq, prm.response, 5 * HZ);
  218. spin_lock_irq(&card->param_queue_lock);
  219. list_del(&prm.list);
  220. spin_unlock_irq(&card->param_queue_lock);
  221. skb = prm.response;
  222. if (!skb)
  223. return -EIO;
  224. buflen = skb->len;
  225. /* Sometimes it has a newline, sometimes it doesn't. */
  226. if (skb->data[buflen - 1] == '\n')
  227. buflen--;
  228. if (buflen == 2 && !strncmp(skb->data, "OK", 2))
  229. ret = count;
  230. else if (buflen == 5 && !strncmp(skb->data, "ERROR", 5))
  231. ret = -EIO;
  232. else {
  233. /* We know we have enough space allocated for this; we allocated
  234. it ourselves */
  235. skb->data[buflen] = 0;
  236. dev_warn(&card->dev->dev, "Unexpected parameter response: '%s'\n",
  237. skb->data);
  238. ret = -EIO;
  239. }
  240. kfree_skb(skb);
  241. return ret;
  242. }
  243. static char *next_string(struct sk_buff *skb)
  244. {
  245. int i = 0;
  246. char *this = skb->data;
  247. while (i < skb->len) {
  248. if (this[i] == '\n') {
  249. this[i] = 0;
  250. skb_pull(skb, i);
  251. return this;
  252. }
  253. }
  254. return NULL;
  255. }
  256. /*
  257. * Status packet has fields separated by \n, starting with a version number
  258. * for the information therein. Fields are....
  259. *
  260. * packet version
  261. * TxBitRate (version >= 1)
  262. * RxBitRate (version >= 1)
  263. * State (version >= 1)
  264. */
  265. static int process_status(struct solos_card *card, int port, struct sk_buff *skb)
  266. {
  267. char *str, *end, *state_str;
  268. int ver, rate_up, rate_down, state, snr, attn;
  269. if (!card->atmdev[port])
  270. return -ENODEV;
  271. str = next_string(skb);
  272. if (!str)
  273. return -EIO;
  274. ver = simple_strtol(str, NULL, 10);
  275. if (ver < 1) {
  276. dev_warn(&card->dev->dev, "Unexpected status interrupt version %d\n",
  277. ver);
  278. return -EIO;
  279. }
  280. str = next_string(skb);
  281. rate_up = simple_strtol(str, &end, 10);
  282. if (*end)
  283. return -EIO;
  284. str = next_string(skb);
  285. rate_down = simple_strtol(str, &end, 10);
  286. if (*end)
  287. return -EIO;
  288. state_str = next_string(skb);
  289. if (!strcmp(state_str, "Showtime"))
  290. state = ATM_PHY_SIG_FOUND;
  291. else {
  292. state = ATM_PHY_SIG_LOST;
  293. release_vccs(card->atmdev[port]);
  294. }
  295. str = next_string(skb);
  296. snr = simple_strtol(str, &end, 10);
  297. if (*end)
  298. return -EIO;
  299. str = next_string(skb);
  300. attn = simple_strtol(str, &end, 10);
  301. if (*end)
  302. return -EIO;
  303. if (state == ATM_PHY_SIG_LOST && !rate_up && !rate_down)
  304. dev_info(&card->dev->dev, "Port %d ATM state: %s\n",
  305. port, state_str);
  306. else
  307. dev_info(&card->dev->dev, "Port %d ATM state: %s (%d/%d kb/s, SNR %ddB, Attn %ddB)\n",
  308. port, state_str, rate_up/1000, rate_down/1000,
  309. snr, attn);
  310. card->atmdev[port]->link_rate = rate_down;
  311. card->atmdev[port]->signal = state;
  312. return 0;
  313. }
  314. static int process_command(struct solos_card *card, int port, struct sk_buff *skb)
  315. {
  316. struct solos_param *prm;
  317. unsigned long flags;
  318. int cmdpid;
  319. int found = 0;
  320. if (skb->len < 7)
  321. return 0;
  322. if (skb->data[0] != 'L' || !isdigit(skb->data[1]) ||
  323. !isdigit(skb->data[2]) || !isdigit(skb->data[3]) ||
  324. !isdigit(skb->data[4]) || !isdigit(skb->data[5]) ||
  325. skb->data[6] != '\n')
  326. return 0;
  327. cmdpid = simple_strtol(&skb->data[1], NULL, 10);
  328. spin_lock_irqsave(&card->param_queue_lock, flags);
  329. list_for_each_entry(prm, &card->param_queue, list) {
  330. if (prm->port == port && prm->pid == cmdpid) {
  331. prm->response = skb;
  332. skb_pull(skb, 7);
  333. wake_up(&card->param_wq);
  334. found = 1;
  335. break;
  336. }
  337. }
  338. spin_unlock_irqrestore(&card->param_queue_lock, flags);
  339. return found;
  340. }
  341. static ssize_t console_show(struct device *dev, struct device_attribute *attr,
  342. char *buf)
  343. {
  344. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  345. struct solos_card *card = atmdev->dev_data;
  346. struct sk_buff *skb;
  347. spin_lock(&card->cli_queue_lock);
  348. skb = skb_dequeue(&card->cli_queue[SOLOS_CHAN(atmdev)]);
  349. spin_unlock(&card->cli_queue_lock);
  350. if(skb == NULL)
  351. return sprintf(buf, "No data.\n");
  352. memcpy(buf, skb->data, skb->len);
  353. dev_dbg(&card->dev->dev, "len: %d\n", skb->len);
  354. kfree_skb(skb);
  355. return skb->len;
  356. }
  357. static int send_command(struct solos_card *card, int dev, const char *buf, size_t size)
  358. {
  359. struct sk_buff *skb;
  360. struct pkt_hdr *header;
  361. // dev_dbg(&card->dev->dev, "size: %d\n", size);
  362. if (size > (BUF_SIZE - sizeof(*header))) {
  363. dev_dbg(&card->dev->dev, "Command is too big. Dropping request\n");
  364. return 0;
  365. }
  366. skb = alloc_skb(size + sizeof(*header), GFP_ATOMIC);
  367. if (!skb) {
  368. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in send_command()\n");
  369. return 0;
  370. }
  371. header = (void *)skb_put(skb, sizeof(*header));
  372. header->size = cpu_to_le16(size);
  373. header->vpi = cpu_to_le16(0);
  374. header->vci = cpu_to_le16(0);
  375. header->type = cpu_to_le16(PKT_COMMAND);
  376. memcpy(skb_put(skb, size), buf, size);
  377. fpga_queue(card, dev, skb, NULL);
  378. return 0;
  379. }
  380. static ssize_t console_store(struct device *dev, struct device_attribute *attr,
  381. const char *buf, size_t count)
  382. {
  383. struct atm_dev *atmdev = container_of(dev, struct atm_dev, class_dev);
  384. struct solos_card *card = atmdev->dev_data;
  385. int err;
  386. err = send_command(card, SOLOS_CHAN(atmdev), buf, count);
  387. return err?:count;
  388. }
  389. static DEVICE_ATTR(console, 0644, console_show, console_store);
  390. #define SOLOS_ATTR_RO(x) static DEVICE_ATTR(x, 0444, solos_param_show, NULL);
  391. #define SOLOS_ATTR_RW(x) static DEVICE_ATTR(x, 0644, solos_param_show, solos_param_store);
  392. #include "solos-attrlist.c"
  393. #undef SOLOS_ATTR_RO
  394. #undef SOLOS_ATTR_RW
  395. #define SOLOS_ATTR_RO(x) &dev_attr_##x.attr,
  396. #define SOLOS_ATTR_RW(x) &dev_attr_##x.attr,
  397. static struct attribute *solos_attrs[] = {
  398. #include "solos-attrlist.c"
  399. NULL
  400. };
  401. static struct attribute_group solos_attr_group = {
  402. .attrs = solos_attrs,
  403. .name = "parameters",
  404. };
  405. static int flash_upgrade(struct solos_card *card, int chip)
  406. {
  407. const struct firmware *fw;
  408. const char *fw_name;
  409. uint32_t data32 = 0;
  410. int blocksize = 0;
  411. int numblocks = 0;
  412. int offset;
  413. if (chip == 0) {
  414. fw_name = "solos-FPGA.bin";
  415. blocksize = FPGA_BLOCK;
  416. } else {
  417. fw_name = "solos-Firmware.bin";
  418. blocksize = SOLOS_BLOCK;
  419. }
  420. if (request_firmware(&fw, fw_name, &card->dev->dev))
  421. return -ENOENT;
  422. dev_info(&card->dev->dev, "Flash upgrade starting\n");
  423. numblocks = fw->size / blocksize;
  424. dev_info(&card->dev->dev, "Firmware size: %zd\n", fw->size);
  425. dev_info(&card->dev->dev, "Number of blocks: %d\n", numblocks);
  426. dev_info(&card->dev->dev, "Changing FPGA to Update mode\n");
  427. iowrite32(1, card->config_regs + FPGA_MODE);
  428. data32 = ioread32(card->config_regs + FPGA_MODE);
  429. /* Set mode to Chip Erase */
  430. dev_info(&card->dev->dev, "Set FPGA Flash mode to %s Chip Erase\n",
  431. chip?"Solos":"FPGA");
  432. iowrite32((chip * 2), card->config_regs + FLASH_MODE);
  433. iowrite32(1, card->config_regs + WRITE_FLASH);
  434. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  435. for (offset = 0; offset < fw->size; offset += blocksize) {
  436. int i;
  437. /* Clear write flag */
  438. iowrite32(0, card->config_regs + WRITE_FLASH);
  439. /* Set mode to Block Write */
  440. /* dev_info(&card->dev->dev, "Set FPGA Flash mode to Block Write\n"); */
  441. iowrite32(((chip * 2) + 1), card->config_regs + FLASH_MODE);
  442. /* Copy block to buffer, swapping each 16 bits */
  443. for(i = 0; i < blocksize; i += 4) {
  444. uint32_t word = swahb32p((uint32_t *)(fw->data + offset + i));
  445. iowrite32(word, RX_BUF(card, 3) + i);
  446. }
  447. /* Specify block number and then trigger flash write */
  448. iowrite32(offset / blocksize, card->config_regs + FLASH_BLOCK);
  449. iowrite32(1, card->config_regs + WRITE_FLASH);
  450. wait_event(card->fw_wq, !ioread32(card->config_regs + FLASH_BUSY));
  451. }
  452. release_firmware(fw);
  453. iowrite32(0, card->config_regs + WRITE_FLASH);
  454. iowrite32(0, card->config_regs + FPGA_MODE);
  455. iowrite32(0, card->config_regs + FLASH_MODE);
  456. dev_info(&card->dev->dev, "Returning FPGA to Data mode\n");
  457. return 0;
  458. }
  459. static irqreturn_t solos_irq(int irq, void *dev_id)
  460. {
  461. struct solos_card *card = dev_id;
  462. int handled = 1;
  463. //ACK IRQ
  464. iowrite32(0, card->config_regs + IRQ_CLEAR);
  465. //Disable IRQs from FPGA
  466. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  467. if (card->atmdev[0])
  468. tasklet_schedule(&card->tlet);
  469. else
  470. wake_up(&card->fw_wq);
  471. //Enable IRQs from FPGA
  472. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  473. return IRQ_RETVAL(handled);
  474. }
  475. void solos_bh(unsigned long card_arg)
  476. {
  477. struct solos_card *card = (void *)card_arg;
  478. int port;
  479. uint32_t card_flags;
  480. uint32_t rx_done = 0;
  481. card_flags = ioread32(card->config_regs + FLAGS_ADDR);
  482. /* The TX bits are set if the channel is busy; clear if not. We want to
  483. invoke fpga_tx() unless _all_ the bits for active channels are set */
  484. if ((card_flags & card->tx_mask) != card->tx_mask)
  485. fpga_tx(card);
  486. for (port = 0; port < card->nr_ports; port++) {
  487. if (card_flags & (0x10 << port)) {
  488. struct pkt_hdr _hdr, *header;
  489. struct sk_buff *skb;
  490. struct atm_vcc *vcc;
  491. int size;
  492. if (card->using_dma) {
  493. skb = card->rx_skb[port];
  494. card->rx_skb[port] = NULL;
  495. pci_unmap_single(card->dev, SKB_CB(skb)->dma_addr,
  496. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  497. header = (void *)skb->data;
  498. size = le16_to_cpu(header->size);
  499. skb_put(skb, size + sizeof(*header));
  500. skb_pull(skb, sizeof(*header));
  501. } else {
  502. header = &_hdr;
  503. rx_done |= 0x10 << port;
  504. memcpy_fromio(header, RX_BUF(card, port), sizeof(*header));
  505. size = le16_to_cpu(header->size);
  506. skb = alloc_skb(size + 1, GFP_ATOMIC);
  507. if (!skb) {
  508. if (net_ratelimit())
  509. dev_warn(&card->dev->dev, "Failed to allocate sk_buff for RX\n");
  510. continue;
  511. }
  512. memcpy_fromio(skb_put(skb, size),
  513. RX_BUF(card, port) + sizeof(*header),
  514. size);
  515. }
  516. if (atmdebug) {
  517. dev_info(&card->dev->dev, "Received: device %d\n", port);
  518. dev_info(&card->dev->dev, "size: %d VPI: %d VCI: %d\n",
  519. size, le16_to_cpu(header->vpi),
  520. le16_to_cpu(header->vci));
  521. print_buffer(skb);
  522. }
  523. switch (le16_to_cpu(header->type)) {
  524. case PKT_DATA:
  525. vcc = find_vcc(card->atmdev[port], le16_to_cpu(header->vpi),
  526. le16_to_cpu(header->vci));
  527. if (!vcc) {
  528. if (net_ratelimit())
  529. dev_warn(&card->dev->dev, "Received packet for unknown VCI.VPI %d.%d on port %d\n",
  530. le16_to_cpu(header->vci), le16_to_cpu(header->vpi),
  531. port);
  532. continue;
  533. }
  534. atm_charge(vcc, skb->truesize);
  535. vcc->push(vcc, skb);
  536. atomic_inc(&vcc->stats->rx);
  537. break;
  538. case PKT_STATUS:
  539. process_status(card, port, skb);
  540. dev_kfree_skb_any(skb);
  541. break;
  542. case PKT_COMMAND:
  543. default: /* FIXME: Not really, surely? */
  544. if (process_command(card, port, skb))
  545. break;
  546. spin_lock(&card->cli_queue_lock);
  547. if (skb_queue_len(&card->cli_queue[port]) > 10) {
  548. if (net_ratelimit())
  549. dev_warn(&card->dev->dev, "Dropping console response on port %d\n",
  550. port);
  551. dev_kfree_skb_any(skb);
  552. } else
  553. skb_queue_tail(&card->cli_queue[port], skb);
  554. spin_unlock(&card->cli_queue_lock);
  555. break;
  556. }
  557. }
  558. /* Allocate RX skbs for any ports which need them */
  559. if (card->using_dma && card->atmdev[port] &&
  560. !card->rx_skb[port]) {
  561. struct sk_buff *skb = alloc_skb(RX_DMA_SIZE, GFP_ATOMIC);
  562. if (skb) {
  563. SKB_CB(skb)->dma_addr =
  564. pci_map_single(card->dev, skb->data,
  565. RX_DMA_SIZE, PCI_DMA_FROMDEVICE);
  566. iowrite32(SKB_CB(skb)->dma_addr,
  567. card->config_regs + RX_DMA_ADDR(port));
  568. card->rx_skb[port] = skb;
  569. } else {
  570. if (net_ratelimit())
  571. dev_warn(&card->dev->dev, "Failed to allocate RX skb");
  572. /* We'll have to try again later */
  573. tasklet_schedule(&card->tlet);
  574. }
  575. }
  576. }
  577. if (rx_done)
  578. iowrite32(rx_done, card->config_regs + FLAGS_ADDR);
  579. return;
  580. }
  581. static struct atm_vcc *find_vcc(struct atm_dev *dev, short vpi, int vci)
  582. {
  583. struct hlist_head *head;
  584. struct atm_vcc *vcc = NULL;
  585. struct hlist_node *node;
  586. struct sock *s;
  587. read_lock(&vcc_sklist_lock);
  588. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  589. sk_for_each(s, node, head) {
  590. vcc = atm_sk(s);
  591. if (vcc->dev == dev && vcc->vci == vci &&
  592. vcc->vpi == vpi && vcc->qos.rxtp.traffic_class != ATM_NONE)
  593. goto out;
  594. }
  595. vcc = NULL;
  596. out:
  597. read_unlock(&vcc_sklist_lock);
  598. return vcc;
  599. }
  600. static int list_vccs(int vci)
  601. {
  602. struct hlist_head *head;
  603. struct atm_vcc *vcc;
  604. struct hlist_node *node;
  605. struct sock *s;
  606. int num_found = 0;
  607. int i;
  608. read_lock(&vcc_sklist_lock);
  609. if (vci != 0){
  610. head = &vcc_hash[vci & (VCC_HTABLE_SIZE -1)];
  611. sk_for_each(s, node, head) {
  612. num_found ++;
  613. vcc = atm_sk(s);
  614. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  615. vcc->dev->number,
  616. vcc->vpi,
  617. vcc->vci);
  618. }
  619. } else {
  620. for(i = 0; i < VCC_HTABLE_SIZE; i++){
  621. head = &vcc_hash[i];
  622. sk_for_each(s, node, head) {
  623. num_found ++;
  624. vcc = atm_sk(s);
  625. printk(KERN_DEBUG "Device: %d Vpi: %d Vci: %d\n",
  626. vcc->dev->number,
  627. vcc->vpi,
  628. vcc->vci);
  629. }
  630. }
  631. }
  632. read_unlock(&vcc_sklist_lock);
  633. return num_found;
  634. }
  635. static void release_vccs(struct atm_dev *dev)
  636. {
  637. int i;
  638. write_lock_irq(&vcc_sklist_lock);
  639. for (i = 0; i < VCC_HTABLE_SIZE; i++) {
  640. struct hlist_head *head = &vcc_hash[i];
  641. struct hlist_node *node, *tmp;
  642. struct sock *s;
  643. struct atm_vcc *vcc;
  644. sk_for_each_safe(s, node, tmp, head) {
  645. vcc = atm_sk(s);
  646. if (vcc->dev == dev) {
  647. vcc_release_async(vcc, -EPIPE);
  648. sk_del_node_init(s);
  649. }
  650. }
  651. }
  652. write_unlock_irq(&vcc_sklist_lock);
  653. }
  654. static int popen(struct atm_vcc *vcc)
  655. {
  656. struct solos_card *card = vcc->dev->dev_data;
  657. struct sk_buff *skb;
  658. struct pkt_hdr *header;
  659. if (vcc->qos.aal != ATM_AAL5) {
  660. dev_warn(&card->dev->dev, "Unsupported ATM type %d\n",
  661. vcc->qos.aal);
  662. return -EINVAL;
  663. }
  664. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  665. if (!skb && net_ratelimit()) {
  666. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in popen()\n");
  667. return -ENOMEM;
  668. }
  669. header = (void *)skb_put(skb, sizeof(*header));
  670. header->size = cpu_to_le16(0);
  671. header->vpi = cpu_to_le16(vcc->vpi);
  672. header->vci = cpu_to_le16(vcc->vci);
  673. header->type = cpu_to_le16(PKT_POPEN);
  674. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  675. // dev_dbg(&card->dev->dev, "Open for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  676. set_bit(ATM_VF_ADDR, &vcc->flags); // accept the vpi / vci
  677. set_bit(ATM_VF_READY, &vcc->flags);
  678. list_vccs(0);
  679. return 0;
  680. }
  681. static void pclose(struct atm_vcc *vcc)
  682. {
  683. struct solos_card *card = vcc->dev->dev_data;
  684. struct sk_buff *skb;
  685. struct pkt_hdr *header;
  686. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  687. if (!skb) {
  688. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in pclose()\n");
  689. return;
  690. }
  691. header = (void *)skb_put(skb, sizeof(*header));
  692. header->size = cpu_to_le16(0);
  693. header->vpi = cpu_to_le16(vcc->vpi);
  694. header->vci = cpu_to_le16(vcc->vci);
  695. header->type = cpu_to_le16(PKT_PCLOSE);
  696. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, NULL);
  697. // dev_dbg(&card->dev->dev, "Close for vpi %d and vci %d on interface %d\n", vcc->vpi, vcc->vci, SOLOS_CHAN(vcc->dev));
  698. clear_bit(ATM_VF_ADDR, &vcc->flags);
  699. clear_bit(ATM_VF_READY, &vcc->flags);
  700. return;
  701. }
  702. static int print_buffer(struct sk_buff *buf)
  703. {
  704. int len,i;
  705. char msg[500];
  706. char item[10];
  707. len = buf->len;
  708. for (i = 0; i < len; i++){
  709. if(i % 8 == 0)
  710. sprintf(msg, "%02X: ", i);
  711. sprintf(item,"%02X ",*(buf->data + i));
  712. strcat(msg, item);
  713. if(i % 8 == 7) {
  714. sprintf(item, "\n");
  715. strcat(msg, item);
  716. printk(KERN_DEBUG "%s", msg);
  717. }
  718. }
  719. if (i % 8 != 0) {
  720. sprintf(item, "\n");
  721. strcat(msg, item);
  722. printk(KERN_DEBUG "%s", msg);
  723. }
  724. printk(KERN_DEBUG "\n");
  725. return 0;
  726. }
  727. static void fpga_queue(struct solos_card *card, int port, struct sk_buff *skb,
  728. struct atm_vcc *vcc)
  729. {
  730. int old_len;
  731. unsigned long flags;
  732. SKB_CB(skb)->vcc = vcc;
  733. spin_lock_irqsave(&card->tx_queue_lock, flags);
  734. old_len = skb_queue_len(&card->tx_queue[port]);
  735. skb_queue_tail(&card->tx_queue[port], skb);
  736. if (!old_len) {
  737. card->tx_mask |= (1 << port);
  738. }
  739. spin_unlock_irqrestore(&card->tx_queue_lock, flags);
  740. /* Theoretically we could just schedule the tasklet here, but
  741. that introduces latency we don't want -- it's noticeable */
  742. if (!old_len)
  743. fpga_tx(card);
  744. }
  745. static int fpga_tx(struct solos_card *card)
  746. {
  747. uint32_t tx_pending;
  748. uint32_t tx_started = 0;
  749. struct sk_buff *skb;
  750. struct atm_vcc *vcc;
  751. unsigned char port;
  752. unsigned long flags;
  753. spin_lock_irqsave(&card->tx_lock, flags);
  754. tx_pending = ioread32(card->config_regs + FLAGS_ADDR) & card->tx_mask;
  755. dev_vdbg(&card->dev->dev, "TX Flags are %X\n", tx_pending);
  756. for (port = 0; port < card->nr_ports; port++) {
  757. if (card->atmdev[port] && !(tx_pending & (1 << port))) {
  758. struct sk_buff *oldskb = card->tx_skb[port];
  759. if (oldskb)
  760. pci_unmap_single(card->dev, SKB_CB(oldskb)->dma_addr,
  761. oldskb->len, PCI_DMA_TODEVICE);
  762. spin_lock(&card->tx_queue_lock);
  763. skb = skb_dequeue(&card->tx_queue[port]);
  764. if (!skb)
  765. card->tx_mask &= ~(1 << port);
  766. spin_unlock(&card->tx_queue_lock);
  767. if (skb && !card->using_dma) {
  768. memcpy_toio(TX_BUF(card, port), skb->data, skb->len);
  769. tx_started |= 1 << port; //Set TX full flag
  770. oldskb = skb; /* We're done with this skb already */
  771. } else if (skb && card->using_dma) {
  772. SKB_CB(skb)->dma_addr = pci_map_single(card->dev, skb->data,
  773. skb->len, PCI_DMA_TODEVICE);
  774. iowrite32(SKB_CB(skb)->dma_addr,
  775. card->config_regs + TX_DMA_ADDR(port));
  776. }
  777. if (!oldskb)
  778. continue;
  779. /* Clean up and free oldskb now it's gone */
  780. if (atmdebug) {
  781. dev_info(&card->dev->dev, "Transmitted: port %d\n",
  782. port);
  783. print_buffer(oldskb);
  784. }
  785. vcc = SKB_CB(oldskb)->vcc;
  786. if (vcc) {
  787. atomic_inc(&vcc->stats->tx);
  788. solos_pop(vcc, oldskb);
  789. } else
  790. dev_kfree_skb_irq(oldskb);
  791. }
  792. }
  793. if (tx_started)
  794. iowrite32(tx_started, card->config_regs + FLAGS_ADDR);
  795. spin_unlock_irqrestore(&card->tx_lock, flags);
  796. return 0;
  797. }
  798. static int psend(struct atm_vcc *vcc, struct sk_buff *skb)
  799. {
  800. struct solos_card *card = vcc->dev->dev_data;
  801. struct sk_buff *skb2 = NULL;
  802. struct pkt_hdr *header;
  803. int pktlen;
  804. //dev_dbg(&card->dev->dev, "psend called.\n");
  805. //dev_dbg(&card->dev->dev, "dev,vpi,vci = %d,%d,%d\n",SOLOS_CHAN(vcc->dev),vcc->vpi,vcc->vci);
  806. if (debug) {
  807. skb2 = atm_alloc_charge(vcc, skb->len, GFP_ATOMIC);
  808. if (skb2) {
  809. memcpy(skb2->data, skb->data, skb->len);
  810. skb_put(skb2, skb->len);
  811. vcc->push(vcc, skb2);
  812. atomic_inc(&vcc->stats->rx);
  813. }
  814. atomic_inc(&vcc->stats->tx);
  815. solos_pop(vcc, skb);
  816. return 0;
  817. }
  818. pktlen = skb->len;
  819. if (pktlen > (BUF_SIZE - sizeof(*header))) {
  820. dev_warn(&card->dev->dev, "Length of PDU is too large. Dropping PDU.\n");
  821. solos_pop(vcc, skb);
  822. return 0;
  823. }
  824. if (!skb_clone_writable(skb, sizeof(*header))) {
  825. int expand_by = 0;
  826. int ret;
  827. if (skb_headroom(skb) < sizeof(*header))
  828. expand_by = sizeof(*header) - skb_headroom(skb);
  829. ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
  830. if (ret) {
  831. dev_warn(&card->dev->dev, "pskb_expand_head failed.\n");
  832. solos_pop(vcc, skb);
  833. return ret;
  834. }
  835. }
  836. header = (void *)skb_push(skb, sizeof(*header));
  837. /* This does _not_ include the size of the header */
  838. header->size = cpu_to_le16(pktlen);
  839. header->vpi = cpu_to_le16(vcc->vpi);
  840. header->vci = cpu_to_le16(vcc->vci);
  841. header->type = cpu_to_le16(PKT_DATA);
  842. fpga_queue(card, SOLOS_CHAN(vcc->dev), skb, vcc);
  843. return 0;
  844. }
  845. static struct atmdev_ops fpga_ops = {
  846. .open = popen,
  847. .close = pclose,
  848. .ioctl = NULL,
  849. .getsockopt = NULL,
  850. .setsockopt = NULL,
  851. .send = psend,
  852. .send_oam = NULL,
  853. .phy_put = NULL,
  854. .phy_get = NULL,
  855. .change_qos = NULL,
  856. .proc_read = NULL,
  857. .owner = THIS_MODULE
  858. };
  859. static int fpga_probe(struct pci_dev *dev, const struct pci_device_id *id)
  860. {
  861. int err, i;
  862. uint16_t fpga_ver;
  863. uint8_t major_ver, minor_ver;
  864. uint32_t data32;
  865. struct solos_card *card;
  866. if (debug)
  867. return 0;
  868. card = kzalloc(sizeof(*card), GFP_KERNEL);
  869. if (!card)
  870. return -ENOMEM;
  871. card->dev = dev;
  872. init_waitqueue_head(&card->fw_wq);
  873. init_waitqueue_head(&card->param_wq);
  874. err = pci_enable_device(dev);
  875. if (err) {
  876. dev_warn(&dev->dev, "Failed to enable PCI device\n");
  877. goto out;
  878. }
  879. err = pci_set_dma_mask(dev, DMA_32BIT_MASK);
  880. if (err) {
  881. dev_warn(&dev->dev, "Failed to set 32-bit DMA mask\n");
  882. goto out;
  883. }
  884. err = pci_request_regions(dev, "solos");
  885. if (err) {
  886. dev_warn(&dev->dev, "Failed to request regions\n");
  887. goto out;
  888. }
  889. card->config_regs = pci_iomap(dev, 0, CONFIG_RAM_SIZE);
  890. if (!card->config_regs) {
  891. dev_warn(&dev->dev, "Failed to ioremap config registers\n");
  892. goto out_release_regions;
  893. }
  894. card->buffers = pci_iomap(dev, 1, DATA_RAM_SIZE);
  895. if (!card->buffers) {
  896. dev_warn(&dev->dev, "Failed to ioremap data buffers\n");
  897. goto out_unmap_config;
  898. }
  899. // for(i=0;i<64 ;i+=4){
  900. // data32=ioread32(card->buffers + i);
  901. // dev_dbg(&card->dev->dev, "%08lX\n",(unsigned long)data32);
  902. // }
  903. //Fill Config Mem with zeros
  904. for(i = 0; i < 128; i += 4)
  905. iowrite32(0, card->config_regs + i);
  906. //Set RX empty flags
  907. iowrite32(0xF0, card->config_regs + FLAGS_ADDR);
  908. data32 = ioread32(card->config_regs + FPGA_VER);
  909. fpga_ver = (data32 & 0x0000FFFF);
  910. major_ver = ((data32 & 0xFF000000) >> 24);
  911. minor_ver = ((data32 & 0x00FF0000) >> 16);
  912. dev_info(&dev->dev, "Solos FPGA Version %d.%02d svn-%d\n",
  913. major_ver, minor_ver, fpga_ver);
  914. if (fpga_ver > 27)
  915. card->using_dma = 1;
  916. card->nr_ports = 2; /* FIXME: Detect daughterboard */
  917. pci_set_drvdata(dev, card);
  918. tasklet_init(&card->tlet, solos_bh, (unsigned long)card);
  919. spin_lock_init(&card->tx_lock);
  920. spin_lock_init(&card->tx_queue_lock);
  921. spin_lock_init(&card->cli_queue_lock);
  922. spin_lock_init(&card->param_queue_lock);
  923. INIT_LIST_HEAD(&card->param_queue);
  924. /*
  925. // Set Loopback mode
  926. data32 = 0x00010000;
  927. iowrite32(data32,card->config_regs + FLAGS_ADDR);
  928. */
  929. /*
  930. // Fill Buffers with zeros
  931. for (i = 0; i < BUF_SIZE * 8; i += 4)
  932. iowrite32(0, card->buffers + i);
  933. */
  934. /*
  935. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  936. iowrite32(0x12345678, card->buffers + i + (0*BUF_SIZE));
  937. for(i = 0; i < (BUF_SIZE * 1); i += 4)
  938. iowrite32(0xabcdef98, card->buffers + i + (1*BUF_SIZE));
  939. // Read Config Memory
  940. printk(KERN_DEBUG "Reading Config MEM\n");
  941. i = 0;
  942. for(i = 0; i < 16; i++) {
  943. data32=ioread32(card->buffers + i*(BUF_SIZE/2));
  944. printk(KERN_ALERT "Addr: %lX Data: %08lX\n",
  945. (unsigned long)(addr_start + i*(BUF_SIZE/2)),
  946. (unsigned long)data32);
  947. }
  948. */
  949. //dev_dbg(&card->dev->dev, "Requesting IRQ: %d\n",dev->irq);
  950. err = request_irq(dev->irq, solos_irq, IRQF_DISABLED|IRQF_SHARED,
  951. "solos-pci", card);
  952. if (err) {
  953. dev_dbg(&card->dev->dev, "Failed to request interrupt IRQ: %d\n", dev->irq);
  954. goto out_unmap_both;
  955. }
  956. // Enable IRQs
  957. iowrite32(1, card->config_regs + IRQ_EN_ADDR);
  958. if (fpga_upgrade)
  959. flash_upgrade(card, 0);
  960. if (firmware_upgrade)
  961. flash_upgrade(card, 1);
  962. err = atm_init(card);
  963. if (err)
  964. goto out_free_irq;
  965. return 0;
  966. out_free_irq:
  967. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  968. free_irq(dev->irq, card);
  969. tasklet_kill(&card->tlet);
  970. out_unmap_both:
  971. pci_set_drvdata(dev, NULL);
  972. pci_iounmap(dev, card->config_regs);
  973. out_unmap_config:
  974. pci_iounmap(dev, card->buffers);
  975. out_release_regions:
  976. pci_release_regions(dev);
  977. out:
  978. return err;
  979. }
  980. static int atm_init(struct solos_card *card)
  981. {
  982. int i;
  983. for (i = 0; i < card->nr_ports; i++) {
  984. struct sk_buff *skb;
  985. struct pkt_hdr *header;
  986. skb_queue_head_init(&card->tx_queue[i]);
  987. skb_queue_head_init(&card->cli_queue[i]);
  988. card->atmdev[i] = atm_dev_register("solos-pci", &fpga_ops, -1, NULL);
  989. if (!card->atmdev[i]) {
  990. dev_err(&card->dev->dev, "Could not register ATM device %d\n", i);
  991. atm_remove(card);
  992. return -ENODEV;
  993. }
  994. if (device_create_file(&card->atmdev[i]->class_dev, &dev_attr_console))
  995. dev_err(&card->dev->dev, "Could not register console for ATM device %d\n", i);
  996. if (sysfs_create_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group))
  997. dev_err(&card->dev->dev, "Could not register parameter group for ATM device %d\n", i);
  998. dev_info(&card->dev->dev, "Registered ATM device %d\n", card->atmdev[i]->number);
  999. card->atmdev[i]->ci_range.vpi_bits = 8;
  1000. card->atmdev[i]->ci_range.vci_bits = 16;
  1001. card->atmdev[i]->dev_data = card;
  1002. card->atmdev[i]->phy_data = (void *)(unsigned long)i;
  1003. card->atmdev[i]->signal = ATM_PHY_SIG_UNKNOWN;
  1004. skb = alloc_skb(sizeof(*header), GFP_ATOMIC);
  1005. if (!skb) {
  1006. dev_warn(&card->dev->dev, "Failed to allocate sk_buff in atm_init()\n");
  1007. continue;
  1008. }
  1009. header = (void *)skb_put(skb, sizeof(*header));
  1010. header->size = cpu_to_le16(0);
  1011. header->vpi = cpu_to_le16(0);
  1012. header->vci = cpu_to_le16(0);
  1013. header->type = cpu_to_le16(PKT_STATUS);
  1014. fpga_queue(card, i, skb, NULL);
  1015. }
  1016. return 0;
  1017. }
  1018. static void atm_remove(struct solos_card *card)
  1019. {
  1020. int i;
  1021. for (i = 0; i < card->nr_ports; i++) {
  1022. if (card->atmdev[i]) {
  1023. dev_info(&card->dev->dev, "Unregistering ATM device %d\n", card->atmdev[i]->number);
  1024. sysfs_remove_group(&card->atmdev[i]->class_dev.kobj, &solos_attr_group);
  1025. atm_dev_deregister(card->atmdev[i]);
  1026. }
  1027. }
  1028. }
  1029. static void fpga_remove(struct pci_dev *dev)
  1030. {
  1031. struct solos_card *card = pci_get_drvdata(dev);
  1032. if (debug)
  1033. return;
  1034. atm_remove(card);
  1035. dev_vdbg(&dev->dev, "Freeing IRQ\n");
  1036. // Disable IRQs from FPGA
  1037. iowrite32(0, card->config_regs + IRQ_EN_ADDR);
  1038. free_irq(dev->irq, card);
  1039. tasklet_kill(&card->tlet);
  1040. // iowrite32(0x01,pciregs);
  1041. dev_vdbg(&dev->dev, "Unmapping PCI resource\n");
  1042. pci_iounmap(dev, card->buffers);
  1043. pci_iounmap(dev, card->config_regs);
  1044. dev_vdbg(&dev->dev, "Releasing PCI Region\n");
  1045. pci_release_regions(dev);
  1046. pci_disable_device(dev);
  1047. pci_set_drvdata(dev, NULL);
  1048. kfree(card);
  1049. // dev_dbg(&card->dev->dev, "fpga_remove\n");
  1050. return;
  1051. }
  1052. static struct pci_device_id fpga_pci_tbl[] __devinitdata = {
  1053. { 0x10ee, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1054. { 0, }
  1055. };
  1056. MODULE_DEVICE_TABLE(pci,fpga_pci_tbl);
  1057. static struct pci_driver fpga_driver = {
  1058. .name = "solos",
  1059. .id_table = fpga_pci_tbl,
  1060. .probe = fpga_probe,
  1061. .remove = fpga_remove,
  1062. };
  1063. static int __init solos_pci_init(void)
  1064. {
  1065. printk(KERN_INFO "Solos PCI Driver Version %s\n", VERSION);
  1066. return pci_register_driver(&fpga_driver);
  1067. }
  1068. static void __exit solos_pci_exit(void)
  1069. {
  1070. pci_unregister_driver(&fpga_driver);
  1071. printk(KERN_INFO "Solos PCI Driver %s Unloaded\n", VERSION);
  1072. }
  1073. module_init(solos_pci_init);
  1074. module_exit(solos_pci_exit);