sgtl5000.c 41 KB

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  1. /*
  2. * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
  3. *
  4. * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/clk.h>
  18. #include <linux/regmap.h>
  19. #include <linux/regulator/driver.h>
  20. #include <linux/regulator/machine.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/of_device.h>
  23. #include <sound/core.h>
  24. #include <sound/tlv.h>
  25. #include <sound/pcm.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/soc.h>
  28. #include <sound/soc-dapm.h>
  29. #include <sound/initval.h>
  30. #include "sgtl5000.h"
  31. #define SGTL5000_DAP_REG_OFFSET 0x0100
  32. #define SGTL5000_MAX_REG_OFFSET 0x013A
  33. /* default value of sgtl5000 registers */
  34. static const struct reg_default sgtl5000_reg_defaults[] = {
  35. { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
  36. { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
  37. { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
  38. { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
  39. { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
  40. { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
  41. { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
  42. { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
  43. { SGTL5000_CHIP_ANA_POWER, 0x7060 },
  44. { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
  45. { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
  46. { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
  47. { SGTL5000_DAP_SURROUND, 0x0040 },
  48. { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
  49. { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
  50. { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
  51. { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
  52. { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
  53. { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
  54. { SGTL5000_DAP_AVC_CTRL, 0x0510 },
  55. { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
  56. { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
  57. { SGTL5000_DAP_AVC_DECAY, 0x0050 },
  58. };
  59. /* regulator supplies for sgtl5000, VDDD is an optional external supply */
  60. enum sgtl5000_regulator_supplies {
  61. VDDA,
  62. VDDIO,
  63. VDDD,
  64. SGTL5000_SUPPLY_NUM
  65. };
  66. /* vddd is optional supply */
  67. static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
  68. "VDDA",
  69. "VDDIO",
  70. "VDDD"
  71. };
  72. #define LDO_CONSUMER_NAME "VDDD_LDO"
  73. #define LDO_VOLTAGE 1200000
  74. static struct regulator_consumer_supply ldo_consumer[] = {
  75. REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
  76. };
  77. static struct regulator_init_data ldo_init_data = {
  78. .constraints = {
  79. .min_uV = 1200000,
  80. .max_uV = 1200000,
  81. .valid_modes_mask = REGULATOR_MODE_NORMAL,
  82. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  83. },
  84. .num_consumer_supplies = 1,
  85. .consumer_supplies = &ldo_consumer[0],
  86. };
  87. /*
  88. * sgtl5000 internal ldo regulator,
  89. * enabled when VDDD not provided
  90. */
  91. struct ldo_regulator {
  92. struct regulator_desc desc;
  93. struct regulator_dev *dev;
  94. int voltage;
  95. void *codec_data;
  96. bool enabled;
  97. };
  98. /* sgtl5000 private structure in codec */
  99. struct sgtl5000_priv {
  100. int sysclk; /* sysclk rate */
  101. int master; /* i2s master or not */
  102. int fmt; /* i2s data format */
  103. struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
  104. struct ldo_regulator *ldo;
  105. struct regmap *regmap;
  106. struct clk *mclk;
  107. };
  108. /*
  109. * mic_bias power on/off share the same register bits with
  110. * output impedance of mic bias, when power on mic bias, we
  111. * need reclaim it to impedance value.
  112. * 0x0 = Powered off
  113. * 0x1 = 2Kohm
  114. * 0x2 = 4Kohm
  115. * 0x3 = 8Kohm
  116. */
  117. static int mic_bias_event(struct snd_soc_dapm_widget *w,
  118. struct snd_kcontrol *kcontrol, int event)
  119. {
  120. switch (event) {
  121. case SND_SOC_DAPM_POST_PMU:
  122. /* change mic bias resistor to 4Kohm */
  123. snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
  124. SGTL5000_BIAS_R_MASK,
  125. SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
  126. break;
  127. case SND_SOC_DAPM_PRE_PMD:
  128. snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
  129. SGTL5000_BIAS_R_MASK, 0);
  130. break;
  131. }
  132. return 0;
  133. }
  134. /*
  135. * As manual described, ADC/DAC only works when VAG powerup,
  136. * So enabled VAG before ADC/DAC up.
  137. * In power down case, we need wait 400ms when vag fully ramped down.
  138. */
  139. static int power_vag_event(struct snd_soc_dapm_widget *w,
  140. struct snd_kcontrol *kcontrol, int event)
  141. {
  142. const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
  143. switch (event) {
  144. case SND_SOC_DAPM_POST_PMU:
  145. snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
  146. SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
  147. break;
  148. case SND_SOC_DAPM_PRE_PMD:
  149. /*
  150. * Don't clear VAG_POWERUP, when both DAC and ADC are
  151. * operational to prevent inadvertently starving the
  152. * other one of them.
  153. */
  154. if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
  155. mask) != mask) {
  156. snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
  157. SGTL5000_VAG_POWERUP, 0);
  158. msleep(400);
  159. }
  160. break;
  161. default:
  162. break;
  163. }
  164. return 0;
  165. }
  166. /* input sources for ADC */
  167. static const char *adc_mux_text[] = {
  168. "MIC_IN", "LINE_IN"
  169. };
  170. static const struct soc_enum adc_enum =
  171. SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
  172. static const struct snd_kcontrol_new adc_mux =
  173. SOC_DAPM_ENUM("Capture Mux", adc_enum);
  174. /* input sources for DAC */
  175. static const char *dac_mux_text[] = {
  176. "DAC", "LINE_IN"
  177. };
  178. static const struct soc_enum dac_enum =
  179. SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
  180. static const struct snd_kcontrol_new dac_mux =
  181. SOC_DAPM_ENUM("Headphone Mux", dac_enum);
  182. static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
  183. SND_SOC_DAPM_INPUT("LINE_IN"),
  184. SND_SOC_DAPM_INPUT("MIC_IN"),
  185. SND_SOC_DAPM_OUTPUT("HP_OUT"),
  186. SND_SOC_DAPM_OUTPUT("LINE_OUT"),
  187. SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
  188. mic_bias_event,
  189. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  190. SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
  191. SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
  192. SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
  193. SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
  194. /* aif for i2s input */
  195. SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
  196. 0, SGTL5000_CHIP_DIG_POWER,
  197. 0, 0),
  198. /* aif for i2s output */
  199. SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
  200. 0, SGTL5000_CHIP_DIG_POWER,
  201. 1, 0),
  202. SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
  203. SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
  204. SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
  205. SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
  206. };
  207. /* routes for sgtl5000 */
  208. static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
  209. {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
  210. {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
  211. {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
  212. {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
  213. {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
  214. {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
  215. {"LO", NULL, "DAC"}, /* dac --> line_out */
  216. {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
  217. {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
  218. {"LINE_OUT", NULL, "LO"},
  219. {"HP_OUT", NULL, "HP"},
  220. };
  221. /* custom function to fetch info of PCM playback volume */
  222. static int dac_info_volsw(struct snd_kcontrol *kcontrol,
  223. struct snd_ctl_elem_info *uinfo)
  224. {
  225. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  226. uinfo->count = 2;
  227. uinfo->value.integer.min = 0;
  228. uinfo->value.integer.max = 0xfc - 0x3c;
  229. return 0;
  230. }
  231. /*
  232. * custom function to get of PCM playback volume
  233. *
  234. * dac volume register
  235. * 15-------------8-7--------------0
  236. * | R channel vol | L channel vol |
  237. * -------------------------------
  238. *
  239. * PCM volume with 0.5017 dB steps from 0 to -90 dB
  240. *
  241. * register values map to dB
  242. * 0x3B and less = Reserved
  243. * 0x3C = 0 dB
  244. * 0x3D = -0.5 dB
  245. * 0xF0 = -90 dB
  246. * 0xFC and greater = Muted
  247. *
  248. * register value map to userspace value
  249. *
  250. * register value 0x3c(0dB) 0xf0(-90dB)0xfc
  251. * ------------------------------
  252. * userspace value 0xc0 0
  253. */
  254. static int dac_get_volsw(struct snd_kcontrol *kcontrol,
  255. struct snd_ctl_elem_value *ucontrol)
  256. {
  257. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  258. int reg;
  259. int l;
  260. int r;
  261. reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
  262. /* get left channel volume */
  263. l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
  264. /* get right channel volume */
  265. r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
  266. /* make sure value fall in (0x3c,0xfc) */
  267. l = clamp(l, 0x3c, 0xfc);
  268. r = clamp(r, 0x3c, 0xfc);
  269. /* invert it and map to userspace value */
  270. l = 0xfc - l;
  271. r = 0xfc - r;
  272. ucontrol->value.integer.value[0] = l;
  273. ucontrol->value.integer.value[1] = r;
  274. return 0;
  275. }
  276. /*
  277. * custom function to put of PCM playback volume
  278. *
  279. * dac volume register
  280. * 15-------------8-7--------------0
  281. * | R channel vol | L channel vol |
  282. * -------------------------------
  283. *
  284. * PCM volume with 0.5017 dB steps from 0 to -90 dB
  285. *
  286. * register values map to dB
  287. * 0x3B and less = Reserved
  288. * 0x3C = 0 dB
  289. * 0x3D = -0.5 dB
  290. * 0xF0 = -90 dB
  291. * 0xFC and greater = Muted
  292. *
  293. * userspace value map to register value
  294. *
  295. * userspace value 0xc0 0
  296. * ------------------------------
  297. * register value 0x3c(0dB) 0xf0(-90dB)0xfc
  298. */
  299. static int dac_put_volsw(struct snd_kcontrol *kcontrol,
  300. struct snd_ctl_elem_value *ucontrol)
  301. {
  302. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  303. int reg;
  304. int l;
  305. int r;
  306. l = ucontrol->value.integer.value[0];
  307. r = ucontrol->value.integer.value[1];
  308. /* make sure userspace volume fall in (0, 0xfc-0x3c) */
  309. l = clamp(l, 0, 0xfc - 0x3c);
  310. r = clamp(r, 0, 0xfc - 0x3c);
  311. /* invert it, get the value can be set to register */
  312. l = 0xfc - l;
  313. r = 0xfc - r;
  314. /* shift to get the register value */
  315. reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
  316. r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
  317. snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
  318. return 0;
  319. }
  320. static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
  321. /* tlv for mic gain, 0db 20db 30db 40db */
  322. static const unsigned int mic_gain_tlv[] = {
  323. TLV_DB_RANGE_HEAD(2),
  324. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  325. 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
  326. };
  327. /* tlv for hp volume, -51.5db to 12.0db, step .5db */
  328. static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
  329. static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
  330. /* SOC_DOUBLE_S8_TLV with invert */
  331. {
  332. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  333. .name = "PCM Playback Volume",
  334. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
  335. SNDRV_CTL_ELEM_ACCESS_READWRITE,
  336. .info = dac_info_volsw,
  337. .get = dac_get_volsw,
  338. .put = dac_put_volsw,
  339. },
  340. SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
  341. SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
  342. SGTL5000_CHIP_ANA_ADC_CTRL,
  343. 8, 1, 0, capture_6db_attenuate),
  344. SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
  345. SOC_DOUBLE_TLV("Headphone Playback Volume",
  346. SGTL5000_CHIP_ANA_HP_CTRL,
  347. 0, 8,
  348. 0x7f, 1,
  349. headphone_volume),
  350. SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
  351. 5, 1, 0),
  352. SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
  353. 0, 3, 0, mic_gain_tlv),
  354. };
  355. /* mute the codec used by alsa core */
  356. static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  357. {
  358. struct snd_soc_codec *codec = codec_dai->codec;
  359. u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
  360. snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
  361. adcdac_ctrl, mute ? adcdac_ctrl : 0);
  362. return 0;
  363. }
  364. /* set codec format */
  365. static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
  366. {
  367. struct snd_soc_codec *codec = codec_dai->codec;
  368. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  369. u16 i2sctl = 0;
  370. sgtl5000->master = 0;
  371. /*
  372. * i2s clock and frame master setting.
  373. * ONLY support:
  374. * - clock and frame slave,
  375. * - clock and frame master
  376. */
  377. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  378. case SND_SOC_DAIFMT_CBS_CFS:
  379. break;
  380. case SND_SOC_DAIFMT_CBM_CFM:
  381. i2sctl |= SGTL5000_I2S_MASTER;
  382. sgtl5000->master = 1;
  383. break;
  384. default:
  385. return -EINVAL;
  386. }
  387. /* setting i2s data format */
  388. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  389. case SND_SOC_DAIFMT_DSP_A:
  390. i2sctl |= SGTL5000_I2S_MODE_PCM;
  391. break;
  392. case SND_SOC_DAIFMT_DSP_B:
  393. i2sctl |= SGTL5000_I2S_MODE_PCM;
  394. i2sctl |= SGTL5000_I2S_LRALIGN;
  395. break;
  396. case SND_SOC_DAIFMT_I2S:
  397. i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
  398. break;
  399. case SND_SOC_DAIFMT_RIGHT_J:
  400. i2sctl |= SGTL5000_I2S_MODE_RJ;
  401. i2sctl |= SGTL5000_I2S_LRPOL;
  402. break;
  403. case SND_SOC_DAIFMT_LEFT_J:
  404. i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
  405. i2sctl |= SGTL5000_I2S_LRALIGN;
  406. break;
  407. default:
  408. return -EINVAL;
  409. }
  410. sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  411. /* Clock inversion */
  412. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  413. case SND_SOC_DAIFMT_NB_NF:
  414. break;
  415. case SND_SOC_DAIFMT_IB_NF:
  416. i2sctl |= SGTL5000_I2S_SCLK_INV;
  417. break;
  418. default:
  419. return -EINVAL;
  420. }
  421. snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
  422. return 0;
  423. }
  424. /* set codec sysclk */
  425. static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  426. int clk_id, unsigned int freq, int dir)
  427. {
  428. struct snd_soc_codec *codec = codec_dai->codec;
  429. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  430. switch (clk_id) {
  431. case SGTL5000_SYSCLK:
  432. sgtl5000->sysclk = freq;
  433. break;
  434. default:
  435. return -EINVAL;
  436. }
  437. return 0;
  438. }
  439. /*
  440. * set clock according to i2s frame clock,
  441. * sgtl5000 provide 2 clock sources.
  442. * 1. sys_mclk. sample freq can only configure to
  443. * 1/256, 1/384, 1/512 of sys_mclk.
  444. * 2. pll. can derive any audio clocks.
  445. *
  446. * clock setting rules:
  447. * 1. in slave mode, only sys_mclk can use.
  448. * 2. as constraint by sys_mclk, sample freq should
  449. * set to 32k, 44.1k and above.
  450. * 3. using sys_mclk prefer to pll to save power.
  451. */
  452. static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
  453. {
  454. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  455. int clk_ctl = 0;
  456. int sys_fs; /* sample freq */
  457. /*
  458. * sample freq should be divided by frame clock,
  459. * if frame clock lower than 44.1khz, sample feq should set to
  460. * 32khz or 44.1khz.
  461. */
  462. switch (frame_rate) {
  463. case 8000:
  464. case 16000:
  465. sys_fs = 32000;
  466. break;
  467. case 11025:
  468. case 22050:
  469. sys_fs = 44100;
  470. break;
  471. default:
  472. sys_fs = frame_rate;
  473. break;
  474. }
  475. /* set divided factor of frame clock */
  476. switch (sys_fs / frame_rate) {
  477. case 4:
  478. clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
  479. break;
  480. case 2:
  481. clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
  482. break;
  483. case 1:
  484. clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
  485. break;
  486. default:
  487. return -EINVAL;
  488. }
  489. /* set the sys_fs according to frame rate */
  490. switch (sys_fs) {
  491. case 32000:
  492. clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
  493. break;
  494. case 44100:
  495. clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
  496. break;
  497. case 48000:
  498. clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
  499. break;
  500. case 96000:
  501. clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
  502. break;
  503. default:
  504. dev_err(codec->dev, "frame rate %d not supported\n",
  505. frame_rate);
  506. return -EINVAL;
  507. }
  508. /*
  509. * calculate the divider of mclk/sample_freq,
  510. * factor of freq =96k can only be 256, since mclk in range (12m,27m)
  511. */
  512. switch (sgtl5000->sysclk / sys_fs) {
  513. case 256:
  514. clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
  515. SGTL5000_MCLK_FREQ_SHIFT;
  516. break;
  517. case 384:
  518. clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
  519. SGTL5000_MCLK_FREQ_SHIFT;
  520. break;
  521. case 512:
  522. clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
  523. SGTL5000_MCLK_FREQ_SHIFT;
  524. break;
  525. default:
  526. /* if mclk not satisify the divider, use pll */
  527. if (sgtl5000->master) {
  528. clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
  529. SGTL5000_MCLK_FREQ_SHIFT;
  530. } else {
  531. dev_err(codec->dev,
  532. "PLL not supported in slave mode\n");
  533. return -EINVAL;
  534. }
  535. }
  536. /* if using pll, please check manual 6.4.2 for detail */
  537. if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
  538. u64 out, t;
  539. int div2;
  540. int pll_ctl;
  541. unsigned int in, int_div, frac_div;
  542. if (sgtl5000->sysclk > 17000000) {
  543. div2 = 1;
  544. in = sgtl5000->sysclk / 2;
  545. } else {
  546. div2 = 0;
  547. in = sgtl5000->sysclk;
  548. }
  549. if (sys_fs == 44100)
  550. out = 180633600;
  551. else
  552. out = 196608000;
  553. t = do_div(out, in);
  554. int_div = out;
  555. t *= 2048;
  556. do_div(t, in);
  557. frac_div = t;
  558. pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
  559. frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
  560. snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
  561. if (div2)
  562. snd_soc_update_bits(codec,
  563. SGTL5000_CHIP_CLK_TOP_CTRL,
  564. SGTL5000_INPUT_FREQ_DIV2,
  565. SGTL5000_INPUT_FREQ_DIV2);
  566. else
  567. snd_soc_update_bits(codec,
  568. SGTL5000_CHIP_CLK_TOP_CTRL,
  569. SGTL5000_INPUT_FREQ_DIV2,
  570. 0);
  571. /* power up pll */
  572. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  573. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
  574. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
  575. } else {
  576. /* power down pll */
  577. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  578. SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
  579. 0);
  580. }
  581. /* if using pll, clk_ctrl must be set after pll power up */
  582. snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
  583. return 0;
  584. }
  585. /*
  586. * Set PCM DAI bit size and sample rate.
  587. * input: params_rate, params_fmt
  588. */
  589. static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
  590. struct snd_pcm_hw_params *params,
  591. struct snd_soc_dai *dai)
  592. {
  593. struct snd_soc_codec *codec = dai->codec;
  594. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  595. int channels = params_channels(params);
  596. int i2s_ctl = 0;
  597. int stereo;
  598. int ret;
  599. /* sysclk should already set */
  600. if (!sgtl5000->sysclk) {
  601. dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
  602. return -EFAULT;
  603. }
  604. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  605. stereo = SGTL5000_DAC_STEREO;
  606. else
  607. stereo = SGTL5000_ADC_STEREO;
  608. /* set mono to save power */
  609. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
  610. channels == 1 ? 0 : stereo);
  611. /* set codec clock base on lrclk */
  612. ret = sgtl5000_set_clock(codec, params_rate(params));
  613. if (ret)
  614. return ret;
  615. /* set i2s data format */
  616. switch (params_format(params)) {
  617. case SNDRV_PCM_FORMAT_S16_LE:
  618. if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
  619. return -EINVAL;
  620. i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
  621. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
  622. SGTL5000_I2S_SCLKFREQ_SHIFT;
  623. break;
  624. case SNDRV_PCM_FORMAT_S20_3LE:
  625. i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
  626. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  627. SGTL5000_I2S_SCLKFREQ_SHIFT;
  628. break;
  629. case SNDRV_PCM_FORMAT_S24_LE:
  630. i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
  631. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  632. SGTL5000_I2S_SCLKFREQ_SHIFT;
  633. break;
  634. case SNDRV_PCM_FORMAT_S32_LE:
  635. if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
  636. return -EINVAL;
  637. i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
  638. i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
  639. SGTL5000_I2S_SCLKFREQ_SHIFT;
  640. break;
  641. default:
  642. return -EINVAL;
  643. }
  644. snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
  645. SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
  646. i2s_ctl);
  647. return 0;
  648. }
  649. #ifdef CONFIG_REGULATOR
  650. static int ldo_regulator_is_enabled(struct regulator_dev *dev)
  651. {
  652. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  653. return ldo->enabled;
  654. }
  655. static int ldo_regulator_enable(struct regulator_dev *dev)
  656. {
  657. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  658. struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
  659. int reg;
  660. if (ldo_regulator_is_enabled(dev))
  661. return 0;
  662. /* set regulator value firstly */
  663. reg = (1600 - ldo->voltage / 1000) / 50;
  664. reg = clamp(reg, 0x0, 0xf);
  665. /* amend the voltage value, unit: uV */
  666. ldo->voltage = (1600 - reg * 50) * 1000;
  667. /* set voltage to register */
  668. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  669. SGTL5000_LINREG_VDDD_MASK, reg);
  670. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  671. SGTL5000_LINEREG_D_POWERUP,
  672. SGTL5000_LINEREG_D_POWERUP);
  673. /* when internal ldo enabled, simple digital power can be disabled */
  674. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  675. SGTL5000_LINREG_SIMPLE_POWERUP,
  676. 0);
  677. ldo->enabled = 1;
  678. return 0;
  679. }
  680. static int ldo_regulator_disable(struct regulator_dev *dev)
  681. {
  682. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  683. struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
  684. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  685. SGTL5000_LINEREG_D_POWERUP,
  686. 0);
  687. /* clear voltage info */
  688. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  689. SGTL5000_LINREG_VDDD_MASK, 0);
  690. ldo->enabled = 0;
  691. return 0;
  692. }
  693. static int ldo_regulator_get_voltage(struct regulator_dev *dev)
  694. {
  695. struct ldo_regulator *ldo = rdev_get_drvdata(dev);
  696. return ldo->voltage;
  697. }
  698. static struct regulator_ops ldo_regulator_ops = {
  699. .is_enabled = ldo_regulator_is_enabled,
  700. .enable = ldo_regulator_enable,
  701. .disable = ldo_regulator_disable,
  702. .get_voltage = ldo_regulator_get_voltage,
  703. };
  704. static int ldo_regulator_register(struct snd_soc_codec *codec,
  705. struct regulator_init_data *init_data,
  706. int voltage)
  707. {
  708. struct ldo_regulator *ldo;
  709. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  710. struct regulator_config config = { };
  711. ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
  712. if (!ldo) {
  713. dev_err(codec->dev, "failed to allocate ldo_regulator\n");
  714. return -ENOMEM;
  715. }
  716. ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
  717. if (!ldo->desc.name) {
  718. kfree(ldo);
  719. dev_err(codec->dev, "failed to allocate decs name memory\n");
  720. return -ENOMEM;
  721. }
  722. ldo->desc.type = REGULATOR_VOLTAGE;
  723. ldo->desc.owner = THIS_MODULE;
  724. ldo->desc.ops = &ldo_regulator_ops;
  725. ldo->desc.n_voltages = 1;
  726. ldo->codec_data = codec;
  727. ldo->voltage = voltage;
  728. config.dev = codec->dev;
  729. config.driver_data = ldo;
  730. config.init_data = init_data;
  731. ldo->dev = regulator_register(&ldo->desc, &config);
  732. if (IS_ERR(ldo->dev)) {
  733. int ret = PTR_ERR(ldo->dev);
  734. dev_err(codec->dev, "failed to register regulator\n");
  735. kfree(ldo->desc.name);
  736. kfree(ldo);
  737. return ret;
  738. }
  739. sgtl5000->ldo = ldo;
  740. return 0;
  741. }
  742. static int ldo_regulator_remove(struct snd_soc_codec *codec)
  743. {
  744. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  745. struct ldo_regulator *ldo = sgtl5000->ldo;
  746. if (!ldo)
  747. return 0;
  748. regulator_unregister(ldo->dev);
  749. kfree(ldo->desc.name);
  750. kfree(ldo);
  751. return 0;
  752. }
  753. #else
  754. static int ldo_regulator_register(struct snd_soc_codec *codec,
  755. struct regulator_init_data *init_data,
  756. int voltage)
  757. {
  758. dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
  759. return -EINVAL;
  760. }
  761. static int ldo_regulator_remove(struct snd_soc_codec *codec)
  762. {
  763. return 0;
  764. }
  765. #endif
  766. /*
  767. * set dac bias
  768. * common state changes:
  769. * startup:
  770. * off --> standby --> prepare --> on
  771. * standby --> prepare --> on
  772. *
  773. * stop:
  774. * on --> prepare --> standby
  775. */
  776. static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
  777. enum snd_soc_bias_level level)
  778. {
  779. int ret;
  780. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  781. switch (level) {
  782. case SND_SOC_BIAS_ON:
  783. case SND_SOC_BIAS_PREPARE:
  784. break;
  785. case SND_SOC_BIAS_STANDBY:
  786. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  787. ret = regulator_bulk_enable(
  788. ARRAY_SIZE(sgtl5000->supplies),
  789. sgtl5000->supplies);
  790. if (ret)
  791. return ret;
  792. udelay(10);
  793. regcache_cache_only(sgtl5000->regmap, false);
  794. ret = regcache_sync(sgtl5000->regmap);
  795. if (ret != 0) {
  796. dev_err(codec->dev,
  797. "Failed to restore cache: %d\n", ret);
  798. regcache_cache_only(sgtl5000->regmap, true);
  799. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  800. sgtl5000->supplies);
  801. return ret;
  802. }
  803. }
  804. break;
  805. case SND_SOC_BIAS_OFF:
  806. regcache_cache_only(sgtl5000->regmap, true);
  807. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  808. sgtl5000->supplies);
  809. break;
  810. }
  811. codec->dapm.bias_level = level;
  812. return 0;
  813. }
  814. #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  815. SNDRV_PCM_FMTBIT_S20_3LE |\
  816. SNDRV_PCM_FMTBIT_S24_LE |\
  817. SNDRV_PCM_FMTBIT_S32_LE)
  818. static const struct snd_soc_dai_ops sgtl5000_ops = {
  819. .hw_params = sgtl5000_pcm_hw_params,
  820. .digital_mute = sgtl5000_digital_mute,
  821. .set_fmt = sgtl5000_set_dai_fmt,
  822. .set_sysclk = sgtl5000_set_dai_sysclk,
  823. };
  824. static struct snd_soc_dai_driver sgtl5000_dai = {
  825. .name = "sgtl5000",
  826. .playback = {
  827. .stream_name = "Playback",
  828. .channels_min = 1,
  829. .channels_max = 2,
  830. /*
  831. * only support 8~48K + 96K,
  832. * TODO modify hw_param to support more
  833. */
  834. .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
  835. .formats = SGTL5000_FORMATS,
  836. },
  837. .capture = {
  838. .stream_name = "Capture",
  839. .channels_min = 1,
  840. .channels_max = 2,
  841. .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
  842. .formats = SGTL5000_FORMATS,
  843. },
  844. .ops = &sgtl5000_ops,
  845. .symmetric_rates = 1,
  846. };
  847. static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
  848. {
  849. switch (reg) {
  850. case SGTL5000_CHIP_ID:
  851. case SGTL5000_CHIP_ADCDAC_CTRL:
  852. case SGTL5000_CHIP_ANA_STATUS:
  853. return true;
  854. }
  855. return false;
  856. }
  857. static bool sgtl5000_readable(struct device *dev, unsigned int reg)
  858. {
  859. switch (reg) {
  860. case SGTL5000_CHIP_ID:
  861. case SGTL5000_CHIP_DIG_POWER:
  862. case SGTL5000_CHIP_CLK_CTRL:
  863. case SGTL5000_CHIP_I2S_CTRL:
  864. case SGTL5000_CHIP_SSS_CTRL:
  865. case SGTL5000_CHIP_ADCDAC_CTRL:
  866. case SGTL5000_CHIP_DAC_VOL:
  867. case SGTL5000_CHIP_PAD_STRENGTH:
  868. case SGTL5000_CHIP_ANA_ADC_CTRL:
  869. case SGTL5000_CHIP_ANA_HP_CTRL:
  870. case SGTL5000_CHIP_ANA_CTRL:
  871. case SGTL5000_CHIP_LINREG_CTRL:
  872. case SGTL5000_CHIP_REF_CTRL:
  873. case SGTL5000_CHIP_MIC_CTRL:
  874. case SGTL5000_CHIP_LINE_OUT_CTRL:
  875. case SGTL5000_CHIP_LINE_OUT_VOL:
  876. case SGTL5000_CHIP_ANA_POWER:
  877. case SGTL5000_CHIP_PLL_CTRL:
  878. case SGTL5000_CHIP_CLK_TOP_CTRL:
  879. case SGTL5000_CHIP_ANA_STATUS:
  880. case SGTL5000_CHIP_SHORT_CTRL:
  881. case SGTL5000_CHIP_ANA_TEST2:
  882. case SGTL5000_DAP_CTRL:
  883. case SGTL5000_DAP_PEQ:
  884. case SGTL5000_DAP_BASS_ENHANCE:
  885. case SGTL5000_DAP_BASS_ENHANCE_CTRL:
  886. case SGTL5000_DAP_AUDIO_EQ:
  887. case SGTL5000_DAP_SURROUND:
  888. case SGTL5000_DAP_FLT_COEF_ACCESS:
  889. case SGTL5000_DAP_COEF_WR_B0_MSB:
  890. case SGTL5000_DAP_COEF_WR_B0_LSB:
  891. case SGTL5000_DAP_EQ_BASS_BAND0:
  892. case SGTL5000_DAP_EQ_BASS_BAND1:
  893. case SGTL5000_DAP_EQ_BASS_BAND2:
  894. case SGTL5000_DAP_EQ_BASS_BAND3:
  895. case SGTL5000_DAP_EQ_BASS_BAND4:
  896. case SGTL5000_DAP_MAIN_CHAN:
  897. case SGTL5000_DAP_MIX_CHAN:
  898. case SGTL5000_DAP_AVC_CTRL:
  899. case SGTL5000_DAP_AVC_THRESHOLD:
  900. case SGTL5000_DAP_AVC_ATTACK:
  901. case SGTL5000_DAP_AVC_DECAY:
  902. case SGTL5000_DAP_COEF_WR_B1_MSB:
  903. case SGTL5000_DAP_COEF_WR_B1_LSB:
  904. case SGTL5000_DAP_COEF_WR_B2_MSB:
  905. case SGTL5000_DAP_COEF_WR_B2_LSB:
  906. case SGTL5000_DAP_COEF_WR_A1_MSB:
  907. case SGTL5000_DAP_COEF_WR_A1_LSB:
  908. case SGTL5000_DAP_COEF_WR_A2_MSB:
  909. case SGTL5000_DAP_COEF_WR_A2_LSB:
  910. return true;
  911. default:
  912. return false;
  913. }
  914. }
  915. #ifdef CONFIG_SUSPEND
  916. static int sgtl5000_suspend(struct snd_soc_codec *codec)
  917. {
  918. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
  919. return 0;
  920. }
  921. /*
  922. * restore all sgtl5000 registers,
  923. * since a big hole between dap and regular registers,
  924. * we will restore them respectively.
  925. */
  926. static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
  927. {
  928. u16 *cache = codec->reg_cache;
  929. u16 reg;
  930. /* restore regular registers */
  931. for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
  932. /* These regs should restore in particular order */
  933. if (reg == SGTL5000_CHIP_ANA_POWER ||
  934. reg == SGTL5000_CHIP_CLK_CTRL ||
  935. reg == SGTL5000_CHIP_LINREG_CTRL ||
  936. reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
  937. reg == SGTL5000_CHIP_REF_CTRL)
  938. continue;
  939. snd_soc_write(codec, reg, cache[reg]);
  940. }
  941. /* restore dap registers */
  942. for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
  943. snd_soc_write(codec, reg, cache[reg]);
  944. /*
  945. * restore these regs according to the power setting sequence in
  946. * sgtl5000_set_power_regs() and clock setting sequence in
  947. * sgtl5000_set_clock().
  948. *
  949. * The order of restore is:
  950. * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
  951. * SGTL5000_CHIP_ANA_POWER PLL bits set
  952. * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
  953. * SGTL5000_CHIP_ANA_POWER LINREG_D restored
  954. * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
  955. * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
  956. */
  957. snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
  958. cache[SGTL5000_CHIP_LINREG_CTRL]);
  959. snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
  960. cache[SGTL5000_CHIP_ANA_POWER]);
  961. snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
  962. cache[SGTL5000_CHIP_CLK_CTRL]);
  963. snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
  964. cache[SGTL5000_CHIP_REF_CTRL]);
  965. snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
  966. cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
  967. return 0;
  968. }
  969. static int sgtl5000_resume(struct snd_soc_codec *codec)
  970. {
  971. /* Bring the codec back up to standby to enable regulators */
  972. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  973. /* Restore registers by cached in memory */
  974. sgtl5000_restore_regs(codec);
  975. return 0;
  976. }
  977. #else
  978. #define sgtl5000_suspend NULL
  979. #define sgtl5000_resume NULL
  980. #endif /* CONFIG_SUSPEND */
  981. /*
  982. * sgtl5000 has 3 internal power supplies:
  983. * 1. VAG, normally set to vdda/2
  984. * 2. chargepump, set to different value
  985. * according to voltage of vdda and vddio
  986. * 3. line out VAG, normally set to vddio/2
  987. *
  988. * and should be set according to:
  989. * 1. vddd provided by external or not
  990. * 2. vdda and vddio voltage value. > 3.1v or not
  991. * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
  992. */
  993. static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
  994. {
  995. int vddd;
  996. int vdda;
  997. int vddio;
  998. u16 ana_pwr;
  999. u16 lreg_ctrl;
  1000. int vag;
  1001. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1002. vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
  1003. vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
  1004. vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
  1005. vdda = vdda / 1000;
  1006. vddio = vddio / 1000;
  1007. vddd = vddd / 1000;
  1008. if (vdda <= 0 || vddio <= 0 || vddd < 0) {
  1009. dev_err(codec->dev, "regulator voltage not set correctly\n");
  1010. return -EINVAL;
  1011. }
  1012. /* according to datasheet, maximum voltage of supplies */
  1013. if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
  1014. dev_err(codec->dev,
  1015. "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
  1016. vdda, vddio, vddd);
  1017. return -EINVAL;
  1018. }
  1019. /* reset value */
  1020. ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
  1021. ana_pwr |= SGTL5000_DAC_STEREO |
  1022. SGTL5000_ADC_STEREO |
  1023. SGTL5000_REFTOP_POWERUP;
  1024. lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
  1025. if (vddio < 3100 && vdda < 3100) {
  1026. /* enable internal oscillator used for charge pump */
  1027. snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
  1028. SGTL5000_INT_OSC_EN,
  1029. SGTL5000_INT_OSC_EN);
  1030. /* Enable VDDC charge pump */
  1031. ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
  1032. } else if (vddio >= 3100 && vdda >= 3100) {
  1033. /*
  1034. * if vddio and vddd > 3.1v,
  1035. * charge pump should be clean before set ana_pwr
  1036. */
  1037. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  1038. SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
  1039. /* VDDC use VDDIO rail */
  1040. lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
  1041. lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
  1042. SGTL5000_VDDC_MAN_ASSN_SHIFT;
  1043. }
  1044. snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
  1045. snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
  1046. /* set voltage to register */
  1047. snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
  1048. SGTL5000_LINREG_VDDD_MASK, 0x8);
  1049. /*
  1050. * if vddd linear reg has been enabled,
  1051. * simple digital supply should be clear to get
  1052. * proper VDDD voltage.
  1053. */
  1054. if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
  1055. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  1056. SGTL5000_LINREG_SIMPLE_POWERUP,
  1057. 0);
  1058. else
  1059. snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
  1060. SGTL5000_LINREG_SIMPLE_POWERUP |
  1061. SGTL5000_STARTUP_POWERUP,
  1062. 0);
  1063. /*
  1064. * set ADC/DAC VAG to vdda / 2,
  1065. * should stay in range (0.8v, 1.575v)
  1066. */
  1067. vag = vdda / 2;
  1068. if (vag <= SGTL5000_ANA_GND_BASE)
  1069. vag = 0;
  1070. else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
  1071. (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
  1072. vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
  1073. else
  1074. vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
  1075. snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
  1076. SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
  1077. /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
  1078. vag = vddio / 2;
  1079. if (vag <= SGTL5000_LINE_OUT_GND_BASE)
  1080. vag = 0;
  1081. else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
  1082. SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
  1083. vag = SGTL5000_LINE_OUT_GND_MAX;
  1084. else
  1085. vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
  1086. SGTL5000_LINE_OUT_GND_STP;
  1087. snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
  1088. SGTL5000_LINE_OUT_CURRENT_MASK |
  1089. SGTL5000_LINE_OUT_GND_MASK,
  1090. vag << SGTL5000_LINE_OUT_GND_SHIFT |
  1091. SGTL5000_LINE_OUT_CURRENT_360u <<
  1092. SGTL5000_LINE_OUT_CURRENT_SHIFT);
  1093. return 0;
  1094. }
  1095. static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
  1096. {
  1097. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1098. int ret;
  1099. /* set internal ldo to 1.2v */
  1100. ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
  1101. if (ret) {
  1102. dev_err(codec->dev,
  1103. "Failed to register vddd internal supplies: %d\n", ret);
  1104. return ret;
  1105. }
  1106. sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
  1107. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
  1108. sgtl5000->supplies);
  1109. if (ret) {
  1110. ldo_regulator_remove(codec);
  1111. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1112. return ret;
  1113. }
  1114. dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
  1115. return 0;
  1116. }
  1117. static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
  1118. {
  1119. int reg;
  1120. int ret;
  1121. int rev;
  1122. int i;
  1123. int external_vddd = 0;
  1124. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1125. for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
  1126. sgtl5000->supplies[i].supply = supply_names[i];
  1127. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
  1128. sgtl5000->supplies);
  1129. if (!ret)
  1130. external_vddd = 1;
  1131. else {
  1132. ret = sgtl5000_replace_vddd_with_ldo(codec);
  1133. if (ret)
  1134. return ret;
  1135. }
  1136. ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
  1137. sgtl5000->supplies);
  1138. if (ret)
  1139. goto err_regulator_free;
  1140. /* wait for all power rails bring up */
  1141. udelay(10);
  1142. /*
  1143. * workaround for revision 0x11 and later,
  1144. * roll back to use internal LDO
  1145. */
  1146. ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
  1147. if (ret)
  1148. goto err_regulator_disable;
  1149. rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
  1150. if (external_vddd && rev >= 0x11) {
  1151. /* disable all regulator first */
  1152. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1153. sgtl5000->supplies);
  1154. /* free VDDD regulator */
  1155. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1156. sgtl5000->supplies);
  1157. ret = sgtl5000_replace_vddd_with_ldo(codec);
  1158. if (ret)
  1159. return ret;
  1160. ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
  1161. sgtl5000->supplies);
  1162. if (ret)
  1163. goto err_regulator_free;
  1164. /* wait for all power rails bring up */
  1165. udelay(10);
  1166. }
  1167. return 0;
  1168. err_regulator_disable:
  1169. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1170. sgtl5000->supplies);
  1171. err_regulator_free:
  1172. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1173. sgtl5000->supplies);
  1174. if (external_vddd)
  1175. ldo_regulator_remove(codec);
  1176. return ret;
  1177. }
  1178. static int sgtl5000_probe(struct snd_soc_codec *codec)
  1179. {
  1180. int ret;
  1181. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1182. /* setup i2c data ops */
  1183. codec->control_data = sgtl5000->regmap;
  1184. ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
  1185. if (ret < 0) {
  1186. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1187. return ret;
  1188. }
  1189. ret = sgtl5000_enable_regulators(codec);
  1190. if (ret)
  1191. return ret;
  1192. /* power up sgtl5000 */
  1193. ret = sgtl5000_set_power_regs(codec);
  1194. if (ret)
  1195. goto err;
  1196. /* enable small pop, introduce 400ms delay in turning off */
  1197. snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
  1198. SGTL5000_SMALL_POP,
  1199. SGTL5000_SMALL_POP);
  1200. /* disable short cut detector */
  1201. snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
  1202. /*
  1203. * set i2s as default input of sound switch
  1204. * TODO: add sound switch to control and dapm widge.
  1205. */
  1206. snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
  1207. SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
  1208. snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
  1209. SGTL5000_ADC_EN | SGTL5000_DAC_EN);
  1210. /* enable dac volume ramp by default */
  1211. snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
  1212. SGTL5000_DAC_VOL_RAMP_EN |
  1213. SGTL5000_DAC_MUTE_RIGHT |
  1214. SGTL5000_DAC_MUTE_LEFT);
  1215. snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
  1216. snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
  1217. SGTL5000_HP_ZCD_EN |
  1218. SGTL5000_ADC_ZCD_EN);
  1219. snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 2);
  1220. /*
  1221. * disable DAP
  1222. * TODO:
  1223. * Enable DAP in kcontrol and dapm.
  1224. */
  1225. snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
  1226. /* leading to standby state */
  1227. ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1228. if (ret)
  1229. goto err;
  1230. return 0;
  1231. err:
  1232. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1233. sgtl5000->supplies);
  1234. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1235. sgtl5000->supplies);
  1236. ldo_regulator_remove(codec);
  1237. return ret;
  1238. }
  1239. static int sgtl5000_remove(struct snd_soc_codec *codec)
  1240. {
  1241. struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
  1242. sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1243. regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
  1244. sgtl5000->supplies);
  1245. regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
  1246. sgtl5000->supplies);
  1247. ldo_regulator_remove(codec);
  1248. return 0;
  1249. }
  1250. static struct snd_soc_codec_driver sgtl5000_driver = {
  1251. .probe = sgtl5000_probe,
  1252. .remove = sgtl5000_remove,
  1253. .suspend = sgtl5000_suspend,
  1254. .resume = sgtl5000_resume,
  1255. .set_bias_level = sgtl5000_set_bias_level,
  1256. .controls = sgtl5000_snd_controls,
  1257. .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
  1258. .dapm_widgets = sgtl5000_dapm_widgets,
  1259. .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
  1260. .dapm_routes = sgtl5000_dapm_routes,
  1261. .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
  1262. };
  1263. static const struct regmap_config sgtl5000_regmap = {
  1264. .reg_bits = 16,
  1265. .val_bits = 16,
  1266. .max_register = SGTL5000_MAX_REG_OFFSET,
  1267. .volatile_reg = sgtl5000_volatile,
  1268. .readable_reg = sgtl5000_readable,
  1269. .cache_type = REGCACHE_RBTREE,
  1270. .reg_defaults = sgtl5000_reg_defaults,
  1271. .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
  1272. };
  1273. /*
  1274. * Write all the default values from sgtl5000_reg_defaults[] array into the
  1275. * sgtl5000 registers, to make sure we always start with the sane registers
  1276. * values as stated in the datasheet.
  1277. *
  1278. * Since sgtl5000 does not have a reset line, nor a reset command in software,
  1279. * we follow this approach to guarantee we always start from the default values
  1280. * and avoid problems like, not being able to probe after an audio playback
  1281. * followed by a system reset or a 'reboot' command in Linux
  1282. */
  1283. static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
  1284. {
  1285. int i, ret, val, index;
  1286. for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
  1287. val = sgtl5000_reg_defaults[i].def;
  1288. index = sgtl5000_reg_defaults[i].reg;
  1289. ret = regmap_write(sgtl5000->regmap, index, val);
  1290. if (ret)
  1291. return ret;
  1292. }
  1293. return 0;
  1294. }
  1295. static int sgtl5000_i2c_probe(struct i2c_client *client,
  1296. const struct i2c_device_id *id)
  1297. {
  1298. struct sgtl5000_priv *sgtl5000;
  1299. int ret, reg, rev;
  1300. sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
  1301. GFP_KERNEL);
  1302. if (!sgtl5000)
  1303. return -ENOMEM;
  1304. sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
  1305. if (IS_ERR(sgtl5000->regmap)) {
  1306. ret = PTR_ERR(sgtl5000->regmap);
  1307. dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
  1308. return ret;
  1309. }
  1310. sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
  1311. if (IS_ERR(sgtl5000->mclk)) {
  1312. ret = PTR_ERR(sgtl5000->mclk);
  1313. dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
  1314. /* Defer the probe to see if the clk will be provided later */
  1315. if (ret == -ENOENT)
  1316. return -EPROBE_DEFER;
  1317. return ret;
  1318. }
  1319. ret = clk_prepare_enable(sgtl5000->mclk);
  1320. if (ret)
  1321. return ret;
  1322. /* read chip information */
  1323. ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
  1324. if (ret)
  1325. goto disable_clk;
  1326. if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
  1327. SGTL5000_PARTID_PART_ID) {
  1328. dev_err(&client->dev,
  1329. "Device with ID register %x is not a sgtl5000\n", reg);
  1330. ret = -ENODEV;
  1331. goto disable_clk;
  1332. }
  1333. rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
  1334. dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
  1335. i2c_set_clientdata(client, sgtl5000);
  1336. /* Ensure sgtl5000 will start with sane register values */
  1337. ret = sgtl5000_fill_defaults(sgtl5000);
  1338. if (ret)
  1339. goto disable_clk;
  1340. ret = snd_soc_register_codec(&client->dev,
  1341. &sgtl5000_driver, &sgtl5000_dai, 1);
  1342. if (ret)
  1343. goto disable_clk;
  1344. return 0;
  1345. disable_clk:
  1346. clk_disable_unprepare(sgtl5000->mclk);
  1347. return ret;
  1348. }
  1349. static int sgtl5000_i2c_remove(struct i2c_client *client)
  1350. {
  1351. struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
  1352. snd_soc_unregister_codec(&client->dev);
  1353. clk_disable_unprepare(sgtl5000->mclk);
  1354. return 0;
  1355. }
  1356. static const struct i2c_device_id sgtl5000_id[] = {
  1357. {"sgtl5000", 0},
  1358. {},
  1359. };
  1360. MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
  1361. static const struct of_device_id sgtl5000_dt_ids[] = {
  1362. { .compatible = "fsl,sgtl5000", },
  1363. { /* sentinel */ }
  1364. };
  1365. MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
  1366. static struct i2c_driver sgtl5000_i2c_driver = {
  1367. .driver = {
  1368. .name = "sgtl5000",
  1369. .owner = THIS_MODULE,
  1370. .of_match_table = sgtl5000_dt_ids,
  1371. },
  1372. .probe = sgtl5000_i2c_probe,
  1373. .remove = sgtl5000_i2c_remove,
  1374. .id_table = sgtl5000_id,
  1375. };
  1376. module_i2c_driver(sgtl5000_i2c_driver);
  1377. MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
  1378. MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
  1379. MODULE_LICENSE("GPL");