design.txt 11 KB

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  1. Performance Counters for Linux
  2. ------------------------------
  3. Performance counters are special hardware registers available on most modern
  4. CPUs. These registers count the number of certain types of hw events: such
  5. as instructions executed, cachemisses suffered, or branches mis-predicted -
  6. without slowing down the kernel or applications. These registers can also
  7. trigger interrupts when a threshold number of events have passed - and can
  8. thus be used to profile the code that runs on that CPU.
  9. The Linux Performance Counter subsystem provides an abstraction of these
  10. hardware capabilities. It provides per task and per CPU counters, counter
  11. groups, and it provides event capabilities on top of those. It
  12. provides "virtual" 64-bit counters, regardless of the width of the
  13. underlying hardware counters.
  14. Performance counters are accessed via special file descriptors.
  15. There's one file descriptor per virtual counter used.
  16. The special file descriptor is opened via the perf_counter_open()
  17. system call:
  18. int sys_perf_counter_open(struct perf_counter_hw_event *hw_event_uptr,
  19. pid_t pid, int cpu, int group_fd,
  20. unsigned long flags);
  21. The syscall returns the new fd. The fd can be used via the normal
  22. VFS system calls: read() can be used to read the counter, fcntl()
  23. can be used to set the blocking mode, etc.
  24. Multiple counters can be kept open at a time, and the counters
  25. can be poll()ed.
  26. When creating a new counter fd, 'perf_counter_hw_event' is:
  27. /*
  28. * Event to monitor via a performance monitoring counter:
  29. */
  30. struct perf_counter_hw_event {
  31. __u64 event_config;
  32. __u64 irq_period;
  33. __u64 record_type;
  34. __u64 read_format;
  35. __u64 disabled : 1, /* off by default */
  36. nmi : 1, /* NMI sampling */
  37. inherit : 1, /* children inherit it */
  38. pinned : 1, /* must always be on PMU */
  39. exclusive : 1, /* only group on PMU */
  40. exclude_user : 1, /* don't count user */
  41. exclude_kernel : 1, /* ditto kernel */
  42. exclude_hv : 1, /* ditto hypervisor */
  43. exclude_idle : 1, /* don't count when idle */
  44. __reserved_1 : 55;
  45. __u32 extra_config_len;
  46. __u32 __reserved_4;
  47. __u64 __reserved_2;
  48. __u64 __reserved_3;
  49. };
  50. The 'event_config' field specifies what the counter should count. It
  51. is divided into 3 bit-fields:
  52. raw_type: 1 bit (most significant bit) 0x8000_0000_0000_0000
  53. type: 7 bits (next most significant) 0x7f00_0000_0000_0000
  54. event_id: 56 bits (least significant) 0x00ff_0000_0000_0000
  55. If 'raw_type' is 1, then the counter will count a hardware event
  56. specified by the remaining 63 bits of event_config. The encoding is
  57. machine-specific.
  58. If 'raw_type' is 0, then the 'type' field says what kind of counter
  59. this is, with the following encoding:
  60. enum perf_event_types {
  61. PERF_TYPE_HARDWARE = 0,
  62. PERF_TYPE_SOFTWARE = 1,
  63. PERF_TYPE_TRACEPOINT = 2,
  64. };
  65. A counter of PERF_TYPE_HARDWARE will count the hardware event
  66. specified by 'event_id':
  67. /*
  68. * Generalized performance counter event types, used by the hw_event.event_id
  69. * parameter of the sys_perf_counter_open() syscall:
  70. */
  71. enum hw_event_ids {
  72. /*
  73. * Common hardware events, generalized by the kernel:
  74. */
  75. PERF_COUNT_CPU_CYCLES = 0,
  76. PERF_COUNT_INSTRUCTIONS = 1,
  77. PERF_COUNT_CACHE_REFERENCES = 2,
  78. PERF_COUNT_CACHE_MISSES = 3,
  79. PERF_COUNT_BRANCH_INSTRUCTIONS = 4,
  80. PERF_COUNT_BRANCH_MISSES = 5,
  81. PERF_COUNT_BUS_CYCLES = 6,
  82. };
  83. These are standardized types of events that work relatively uniformly
  84. on all CPUs that implement Performance Counters support under Linux,
  85. although there may be variations (e.g., different CPUs might count
  86. cache references and misses at different levels of the cache hierarchy).
  87. If a CPU is not able to count the selected event, then the system call
  88. will return -EINVAL.
  89. More hw_event_types are supported as well, but they are CPU-specific
  90. and accessed as raw events. For example, to count "External bus
  91. cycles while bus lock signal asserted" events on Intel Core CPUs, pass
  92. in a 0x4064 event_id value and set hw_event.raw_type to 1.
  93. A counter of type PERF_TYPE_SOFTWARE will count one of the available
  94. software events, selected by 'event_id':
  95. /*
  96. * Special "software" counters provided by the kernel, even if the hardware
  97. * does not support performance counters. These counters measure various
  98. * physical and sw events of the kernel (and allow the profiling of them as
  99. * well):
  100. */
  101. enum sw_event_ids {
  102. PERF_COUNT_CPU_CLOCK = 0,
  103. PERF_COUNT_TASK_CLOCK = 1,
  104. PERF_COUNT_PAGE_FAULTS = 2,
  105. PERF_COUNT_CONTEXT_SWITCHES = 3,
  106. PERF_COUNT_CPU_MIGRATIONS = 4,
  107. PERF_COUNT_PAGE_FAULTS_MIN = 5,
  108. PERF_COUNT_PAGE_FAULTS_MAJ = 6,
  109. };
  110. Counters come in two flavours: counting counters and sampling
  111. counters. A "counting" counter is one that is used for counting the
  112. number of events that occur, and is characterised by having
  113. irq_period = 0 and record_type = PERF_RECORD_SIMPLE. A read() on a
  114. counting counter simply returns the current value of the counter as
  115. an 8-byte number.
  116. A "sampling" counter is one that is set up to generate an interrupt
  117. every N events, where N is given by 'irq_period'. A sampling counter
  118. has irq_period > 0 and record_type != PERF_RECORD_SIMPLE. The
  119. record_type controls what data is recorded on each interrupt, and the
  120. available values are currently:
  121. /*
  122. * IRQ-notification data record type:
  123. */
  124. enum perf_counter_record_type {
  125. PERF_RECORD_SIMPLE = 0,
  126. PERF_RECORD_IRQ = 1,
  127. PERF_RECORD_GROUP = 2,
  128. };
  129. A record_type value of PERF_RECORD_IRQ will record the instruction
  130. pointer (IP) at which the interrupt occurred. A record_type value of
  131. PERF_RECORD_GROUP will record the event_config and counter value of
  132. all of the other counters in the group, and should only be used on a
  133. group leader (see below). Currently these two values are mutually
  134. exclusive, but record_type will become a bit-mask in future and
  135. support other values.
  136. A sampling counter has an event queue, into which an event is placed
  137. on each interrupt. A read() on a sampling counter will read the next
  138. event from the event queue. If the queue is empty, the read() will
  139. either block or return an EAGAIN error, depending on whether the fd
  140. has been set to non-blocking mode or not.
  141. The 'disabled' bit specifies whether the counter starts out disabled
  142. or enabled. If it is initially disabled, it can be enabled by ioctl
  143. or prctl (see below).
  144. The 'nmi' bit specifies, for hardware events, whether the counter
  145. should be set up to request non-maskable interrupts (NMIs) or normal
  146. interrupts. This bit is ignored if the user doesn't have
  147. CAP_SYS_ADMIN privilege (i.e. is not root) or if the CPU doesn't
  148. generate NMIs from hardware counters.
  149. The 'inherit' bit, if set, specifies that this counter should count
  150. events on descendant tasks as well as the task specified. This only
  151. applies to new descendents, not to any existing descendents at the
  152. time the counter is created (nor to any new descendents of existing
  153. descendents).
  154. The 'pinned' bit, if set, specifies that the counter should always be
  155. on the CPU if at all possible. It only applies to hardware counters
  156. and only to group leaders. If a pinned counter cannot be put onto the
  157. CPU (e.g. because there are not enough hardware counters or because of
  158. a conflict with some other event), then the counter goes into an
  159. 'error' state, where reads return end-of-file (i.e. read() returns 0)
  160. until the counter is subsequently enabled or disabled.
  161. The 'exclusive' bit, if set, specifies that when this counter's group
  162. is on the CPU, it should be the only group using the CPU's counters.
  163. In future, this will allow sophisticated monitoring programs to supply
  164. extra configuration information via 'extra_config_len' to exploit
  165. advanced features of the CPU's Performance Monitor Unit (PMU) that are
  166. not otherwise accessible and that might disrupt other hardware
  167. counters.
  168. The 'exclude_user', 'exclude_kernel' and 'exclude_hv' bits provide a
  169. way to request that counting of events be restricted to times when the
  170. CPU is in user, kernel and/or hypervisor mode.
  171. The 'pid' parameter to the perf_counter_open() system call allows the
  172. counter to be specific to a task:
  173. pid == 0: if the pid parameter is zero, the counter is attached to the
  174. current task.
  175. pid > 0: the counter is attached to a specific task (if the current task
  176. has sufficient privilege to do so)
  177. pid < 0: all tasks are counted (per cpu counters)
  178. The 'cpu' parameter allows a counter to be made specific to a CPU:
  179. cpu >= 0: the counter is restricted to a specific CPU
  180. cpu == -1: the counter counts on all CPUs
  181. (Note: the combination of 'pid == -1' and 'cpu == -1' is not valid.)
  182. A 'pid > 0' and 'cpu == -1' counter is a per task counter that counts
  183. events of that task and 'follows' that task to whatever CPU the task
  184. gets schedule to. Per task counters can be created by any user, for
  185. their own tasks.
  186. A 'pid == -1' and 'cpu == x' counter is a per CPU counter that counts
  187. all events on CPU-x. Per CPU counters need CAP_SYS_ADMIN privilege.
  188. The 'flags' parameter is currently unused and must be zero.
  189. The 'group_fd' parameter allows counter "groups" to be set up. A
  190. counter group has one counter which is the group "leader". The leader
  191. is created first, with group_fd = -1 in the perf_counter_open call
  192. that creates it. The rest of the group members are created
  193. subsequently, with group_fd giving the fd of the group leader.
  194. (A single counter on its own is created with group_fd = -1 and is
  195. considered to be a group with only 1 member.)
  196. A counter group is scheduled onto the CPU as a unit, that is, it will
  197. only be put onto the CPU if all of the counters in the group can be
  198. put onto the CPU. This means that the values of the member counters
  199. can be meaningfully compared, added, divided (to get ratios), etc.,
  200. with each other, since they have counted events for the same set of
  201. executed instructions.
  202. Counters can be enabled and disabled in two ways: via ioctl and via
  203. prctl. When a counter is disabled, it doesn't count or generate
  204. events but does continue to exist and maintain its count value.
  205. An individual counter or counter group can be enabled with
  206. ioctl(fd, PERF_COUNTER_IOC_ENABLE);
  207. or disabled with
  208. ioctl(fd, PERF_COUNTER_IOC_DISABLE);
  209. Enabling or disabling the leader of a group enables or disables the
  210. whole group; that is, while the group leader is disabled, none of the
  211. counters in the group will count. Enabling or disabling a member of a
  212. group other than the leader only affects that counter - disabling an
  213. non-leader stops that counter from counting but doesn't affect any
  214. other counter.
  215. A process can enable or disable all the counter groups that are
  216. attached to it, using prctl:
  217. prctl(PR_TASK_PERF_COUNTERS_ENABLE);
  218. prctl(PR_TASK_PERF_COUNTERS_DISABLE);
  219. This applies to all counters on the current process, whether created
  220. by this process or by another, and doesn't affect any counters that
  221. this process has created on other processes. It only enables or
  222. disables the group leaders, not any other members in the groups.