traps.c 38 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
  7. * Copyright (C) 1995, 1996 Paul M. Antoine
  8. * Copyright (C) 1998 Ulf Carlsson
  9. * Copyright (C) 1999 Silicon Graphics, Inc.
  10. * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11. * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12. * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
  13. */
  14. #include <linux/init.h>
  15. #include <linux/mm.h>
  16. #include <linux/module.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/smp_lock.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/kallsyms.h>
  22. #include <linux/bootmem.h>
  23. #include <linux/interrupt.h>
  24. #include <asm/bootinfo.h>
  25. #include <asm/branch.h>
  26. #include <asm/break.h>
  27. #include <asm/cpu.h>
  28. #include <asm/dsp.h>
  29. #include <asm/fpu.h>
  30. #include <asm/mipsregs.h>
  31. #include <asm/mipsmtregs.h>
  32. #include <asm/module.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/ptrace.h>
  35. #include <asm/sections.h>
  36. #include <asm/system.h>
  37. #include <asm/tlbdebug.h>
  38. #include <asm/traps.h>
  39. #include <asm/uaccess.h>
  40. #include <asm/mmu_context.h>
  41. #include <asm/watch.h>
  42. #include <asm/types.h>
  43. extern asmlinkage void handle_int(void);
  44. extern asmlinkage void handle_tlbm(void);
  45. extern asmlinkage void handle_tlbl(void);
  46. extern asmlinkage void handle_tlbs(void);
  47. extern asmlinkage void handle_adel(void);
  48. extern asmlinkage void handle_ades(void);
  49. extern asmlinkage void handle_ibe(void);
  50. extern asmlinkage void handle_dbe(void);
  51. extern asmlinkage void handle_sys(void);
  52. extern asmlinkage void handle_bp(void);
  53. extern asmlinkage void handle_ri(void);
  54. extern asmlinkage void handle_cpu(void);
  55. extern asmlinkage void handle_ov(void);
  56. extern asmlinkage void handle_tr(void);
  57. extern asmlinkage void handle_fpe(void);
  58. extern asmlinkage void handle_mdmx(void);
  59. extern asmlinkage void handle_watch(void);
  60. extern asmlinkage void handle_mt(void);
  61. extern asmlinkage void handle_dsp(void);
  62. extern asmlinkage void handle_mcheck(void);
  63. extern asmlinkage void handle_reserved(void);
  64. extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  65. struct mips_fpu_struct *ctx);
  66. void (*board_be_init)(void);
  67. int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  68. void (*board_nmi_handler_setup)(void);
  69. void (*board_ejtag_handler_setup)(void);
  70. void (*board_bind_eic_interrupt)(int irq, int regset);
  71. /*
  72. * These constant is for searching for possible module text segments.
  73. * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
  74. */
  75. #define MODULE_RANGE (8*1024*1024)
  76. static void show_trace(unsigned long *stack)
  77. {
  78. const int field = 2 * sizeof(unsigned long);
  79. unsigned long addr;
  80. printk("Call Trace:");
  81. #ifdef CONFIG_KALLSYMS
  82. printk("\n");
  83. #endif
  84. while (!kstack_end(stack)) {
  85. addr = *stack++;
  86. if (__kernel_text_address(addr)) {
  87. printk(" [<%0*lx>] ", field, addr);
  88. print_symbol("%s\n", addr);
  89. }
  90. }
  91. printk("\n");
  92. }
  93. #ifdef CONFIG_KALLSYMS
  94. static int raw_show_trace;
  95. static int __init set_raw_show_trace(char *str)
  96. {
  97. raw_show_trace = 1;
  98. return 1;
  99. }
  100. __setup("raw_show_trace", set_raw_show_trace);
  101. extern unsigned long unwind_stack(struct task_struct *task,
  102. unsigned long **sp, unsigned long pc);
  103. static void show_frametrace(struct task_struct *task, struct pt_regs *regs)
  104. {
  105. const int field = 2 * sizeof(unsigned long);
  106. unsigned long *stack = (long *)regs->regs[29];
  107. unsigned long pc = regs->cp0_epc;
  108. int top = 1;
  109. if (raw_show_trace || !__kernel_text_address(pc)) {
  110. show_trace(stack);
  111. return;
  112. }
  113. printk("Call Trace:\n");
  114. while (__kernel_text_address(pc)) {
  115. printk(" [<%0*lx>] ", field, pc);
  116. print_symbol("%s\n", pc);
  117. pc = unwind_stack(task, &stack, pc);
  118. if (top && pc == 0)
  119. pc = regs->regs[31]; /* leaf? */
  120. top = 0;
  121. }
  122. printk("\n");
  123. }
  124. #else
  125. #define show_frametrace(task, r) show_trace((long *)(r)->regs[29]);
  126. #endif
  127. /*
  128. * This routine abuses get_user()/put_user() to reference pointers
  129. * with at least a bit of error checking ...
  130. */
  131. static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
  132. {
  133. const int field = 2 * sizeof(unsigned long);
  134. long stackdata;
  135. int i;
  136. unsigned long *sp = (unsigned long *)regs->regs[29];
  137. printk("Stack :");
  138. i = 0;
  139. while ((unsigned long) sp & (PAGE_SIZE - 1)) {
  140. if (i && ((i % (64 / field)) == 0))
  141. printk("\n ");
  142. if (i > 39) {
  143. printk(" ...");
  144. break;
  145. }
  146. if (__get_user(stackdata, sp++)) {
  147. printk(" (Bad stack address)");
  148. break;
  149. }
  150. printk(" %0*lx", field, stackdata);
  151. i++;
  152. }
  153. printk("\n");
  154. show_frametrace(task, regs);
  155. }
  156. static noinline void prepare_frametrace(struct pt_regs *regs)
  157. {
  158. __asm__ __volatile__(
  159. "1: la $2, 1b\n\t"
  160. #ifdef CONFIG_64BIT
  161. "sd $2, %0\n\t"
  162. "sd $29, %1\n\t"
  163. "sd $31, %2\n\t"
  164. #else
  165. "sw $2, %0\n\t"
  166. "sw $29, %1\n\t"
  167. "sw $31, %2\n\t"
  168. #endif
  169. : "=m" (regs->cp0_epc),
  170. "=m" (regs->regs[29]), "=m" (regs->regs[31])
  171. : : "memory");
  172. }
  173. void show_stack(struct task_struct *task, unsigned long *sp)
  174. {
  175. struct pt_regs regs;
  176. if (sp) {
  177. regs.regs[29] = (unsigned long)sp;
  178. regs.regs[31] = 0;
  179. regs.cp0_epc = 0;
  180. } else {
  181. if (task && task != current) {
  182. regs.regs[29] = task->thread.reg29;
  183. regs.regs[31] = 0;
  184. regs.cp0_epc = task->thread.reg31;
  185. } else {
  186. prepare_frametrace(&regs);
  187. }
  188. }
  189. show_stacktrace(task, &regs);
  190. }
  191. /*
  192. * The architecture-independent dump_stack generator
  193. */
  194. void dump_stack(void)
  195. {
  196. unsigned long stack;
  197. #ifdef CONFIG_KALLSYMS
  198. if (!raw_show_trace) {
  199. struct pt_regs regs;
  200. prepare_frametrace(&regs);
  201. show_frametrace(current, &regs);
  202. return;
  203. }
  204. #endif
  205. show_trace(&stack);
  206. }
  207. EXPORT_SYMBOL(dump_stack);
  208. void show_code(unsigned int *pc)
  209. {
  210. long i;
  211. printk("\nCode:");
  212. for(i = -3 ; i < 6 ; i++) {
  213. unsigned int insn;
  214. if (__get_user(insn, pc + i)) {
  215. printk(" (Bad address in epc)\n");
  216. break;
  217. }
  218. printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
  219. }
  220. }
  221. void show_regs(struct pt_regs *regs)
  222. {
  223. const int field = 2 * sizeof(unsigned long);
  224. unsigned int cause = regs->cp0_cause;
  225. int i;
  226. printk("Cpu %d\n", smp_processor_id());
  227. /*
  228. * Saved main processor registers
  229. */
  230. for (i = 0; i < 32; ) {
  231. if ((i % 4) == 0)
  232. printk("$%2d :", i);
  233. if (i == 0)
  234. printk(" %0*lx", field, 0UL);
  235. else if (i == 26 || i == 27)
  236. printk(" %*s", field, "");
  237. else
  238. printk(" %0*lx", field, regs->regs[i]);
  239. i++;
  240. if ((i % 4) == 0)
  241. printk("\n");
  242. }
  243. printk("Hi : %0*lx\n", field, regs->hi);
  244. printk("Lo : %0*lx\n", field, regs->lo);
  245. /*
  246. * Saved cp0 registers
  247. */
  248. printk("epc : %0*lx ", field, regs->cp0_epc);
  249. print_symbol("%s ", regs->cp0_epc);
  250. printk(" %s\n", print_tainted());
  251. printk("ra : %0*lx ", field, regs->regs[31]);
  252. print_symbol("%s\n", regs->regs[31]);
  253. printk("Status: %08x ", (uint32_t) regs->cp0_status);
  254. if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
  255. if (regs->cp0_status & ST0_KUO)
  256. printk("KUo ");
  257. if (regs->cp0_status & ST0_IEO)
  258. printk("IEo ");
  259. if (regs->cp0_status & ST0_KUP)
  260. printk("KUp ");
  261. if (regs->cp0_status & ST0_IEP)
  262. printk("IEp ");
  263. if (regs->cp0_status & ST0_KUC)
  264. printk("KUc ");
  265. if (regs->cp0_status & ST0_IEC)
  266. printk("IEc ");
  267. } else {
  268. if (regs->cp0_status & ST0_KX)
  269. printk("KX ");
  270. if (regs->cp0_status & ST0_SX)
  271. printk("SX ");
  272. if (regs->cp0_status & ST0_UX)
  273. printk("UX ");
  274. switch (regs->cp0_status & ST0_KSU) {
  275. case KSU_USER:
  276. printk("USER ");
  277. break;
  278. case KSU_SUPERVISOR:
  279. printk("SUPERVISOR ");
  280. break;
  281. case KSU_KERNEL:
  282. printk("KERNEL ");
  283. break;
  284. default:
  285. printk("BAD_MODE ");
  286. break;
  287. }
  288. if (regs->cp0_status & ST0_ERL)
  289. printk("ERL ");
  290. if (regs->cp0_status & ST0_EXL)
  291. printk("EXL ");
  292. if (regs->cp0_status & ST0_IE)
  293. printk("IE ");
  294. }
  295. printk("\n");
  296. printk("Cause : %08x\n", cause);
  297. cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
  298. if (1 <= cause && cause <= 5)
  299. printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
  300. printk("PrId : %08x\n", read_c0_prid());
  301. }
  302. void show_registers(struct pt_regs *regs)
  303. {
  304. show_regs(regs);
  305. print_modules();
  306. printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
  307. current->comm, current->pid, current_thread_info(), current);
  308. show_stacktrace(current, regs);
  309. show_code((unsigned int *) regs->cp0_epc);
  310. printk("\n");
  311. }
  312. static DEFINE_SPINLOCK(die_lock);
  313. NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
  314. {
  315. static int die_counter;
  316. #ifdef CONFIG_MIPS_MT_SMTC
  317. unsigned long dvpret = dvpe();
  318. #endif /* CONFIG_MIPS_MT_SMTC */
  319. console_verbose();
  320. spin_lock_irq(&die_lock);
  321. bust_spinlocks(1);
  322. #ifdef CONFIG_MIPS_MT_SMTC
  323. mips_mt_regdump(dvpret);
  324. #endif /* CONFIG_MIPS_MT_SMTC */
  325. printk("%s[#%d]:\n", str, ++die_counter);
  326. show_registers(regs);
  327. spin_unlock_irq(&die_lock);
  328. if (in_interrupt())
  329. panic("Fatal exception in interrupt");
  330. if (panic_on_oops) {
  331. printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
  332. ssleep(5);
  333. panic("Fatal exception");
  334. }
  335. do_exit(SIGSEGV);
  336. }
  337. extern const struct exception_table_entry __start___dbe_table[];
  338. extern const struct exception_table_entry __stop___dbe_table[];
  339. void __declare_dbe_table(void)
  340. {
  341. __asm__ __volatile__(
  342. ".section\t__dbe_table,\"a\"\n\t"
  343. ".previous"
  344. );
  345. }
  346. /* Given an address, look for it in the exception tables. */
  347. static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
  348. {
  349. const struct exception_table_entry *e;
  350. e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
  351. if (!e)
  352. e = search_module_dbetables(addr);
  353. return e;
  354. }
  355. asmlinkage void do_be(struct pt_regs *regs)
  356. {
  357. const int field = 2 * sizeof(unsigned long);
  358. const struct exception_table_entry *fixup = NULL;
  359. int data = regs->cp0_cause & 4;
  360. int action = MIPS_BE_FATAL;
  361. /* XXX For now. Fixme, this searches the wrong table ... */
  362. if (data && !user_mode(regs))
  363. fixup = search_dbe_tables(exception_epc(regs));
  364. if (fixup)
  365. action = MIPS_BE_FIXUP;
  366. if (board_be_handler)
  367. action = board_be_handler(regs, fixup != 0);
  368. switch (action) {
  369. case MIPS_BE_DISCARD:
  370. return;
  371. case MIPS_BE_FIXUP:
  372. if (fixup) {
  373. regs->cp0_epc = fixup->nextinsn;
  374. return;
  375. }
  376. break;
  377. default:
  378. break;
  379. }
  380. /*
  381. * Assume it would be too dangerous to continue ...
  382. */
  383. printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
  384. data ? "Data" : "Instruction",
  385. field, regs->cp0_epc, field, regs->regs[31]);
  386. die_if_kernel("Oops", regs);
  387. force_sig(SIGBUS, current);
  388. }
  389. static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
  390. {
  391. unsigned int __user *epc;
  392. epc = (unsigned int __user *) regs->cp0_epc +
  393. ((regs->cp0_cause & CAUSEF_BD) != 0);
  394. if (!get_user(*opcode, epc))
  395. return 0;
  396. force_sig(SIGSEGV, current);
  397. return 1;
  398. }
  399. /*
  400. * ll/sc emulation
  401. */
  402. #define OPCODE 0xfc000000
  403. #define BASE 0x03e00000
  404. #define RT 0x001f0000
  405. #define OFFSET 0x0000ffff
  406. #define LL 0xc0000000
  407. #define SC 0xe0000000
  408. #define SPEC3 0x7c000000
  409. #define RD 0x0000f800
  410. #define FUNC 0x0000003f
  411. #define RDHWR 0x0000003b
  412. /*
  413. * The ll_bit is cleared by r*_switch.S
  414. */
  415. unsigned long ll_bit;
  416. static struct task_struct *ll_task = NULL;
  417. static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
  418. {
  419. unsigned long value, __user *vaddr;
  420. long offset;
  421. int signal = 0;
  422. /*
  423. * analyse the ll instruction that just caused a ri exception
  424. * and put the referenced address to addr.
  425. */
  426. /* sign extend offset */
  427. offset = opcode & OFFSET;
  428. offset <<= 16;
  429. offset >>= 16;
  430. vaddr = (unsigned long __user *)
  431. ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
  432. if ((unsigned long)vaddr & 3) {
  433. signal = SIGBUS;
  434. goto sig;
  435. }
  436. if (get_user(value, vaddr)) {
  437. signal = SIGSEGV;
  438. goto sig;
  439. }
  440. preempt_disable();
  441. if (ll_task == NULL || ll_task == current) {
  442. ll_bit = 1;
  443. } else {
  444. ll_bit = 0;
  445. }
  446. ll_task = current;
  447. preempt_enable();
  448. compute_return_epc(regs);
  449. regs->regs[(opcode & RT) >> 16] = value;
  450. return;
  451. sig:
  452. force_sig(signal, current);
  453. }
  454. static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
  455. {
  456. unsigned long __user *vaddr;
  457. unsigned long reg;
  458. long offset;
  459. int signal = 0;
  460. /*
  461. * analyse the sc instruction that just caused a ri exception
  462. * and put the referenced address to addr.
  463. */
  464. /* sign extend offset */
  465. offset = opcode & OFFSET;
  466. offset <<= 16;
  467. offset >>= 16;
  468. vaddr = (unsigned long __user *)
  469. ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
  470. reg = (opcode & RT) >> 16;
  471. if ((unsigned long)vaddr & 3) {
  472. signal = SIGBUS;
  473. goto sig;
  474. }
  475. preempt_disable();
  476. if (ll_bit == 0 || ll_task != current) {
  477. compute_return_epc(regs);
  478. regs->regs[reg] = 0;
  479. preempt_enable();
  480. return;
  481. }
  482. preempt_enable();
  483. if (put_user(regs->regs[reg], vaddr)) {
  484. signal = SIGSEGV;
  485. goto sig;
  486. }
  487. compute_return_epc(regs);
  488. regs->regs[reg] = 1;
  489. return;
  490. sig:
  491. force_sig(signal, current);
  492. }
  493. /*
  494. * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
  495. * opcodes are supposed to result in coprocessor unusable exceptions if
  496. * executed on ll/sc-less processors. That's the theory. In practice a
  497. * few processors such as NEC's VR4100 throw reserved instruction exceptions
  498. * instead, so we're doing the emulation thing in both exception handlers.
  499. */
  500. static inline int simulate_llsc(struct pt_regs *regs)
  501. {
  502. unsigned int opcode;
  503. if (unlikely(get_insn_opcode(regs, &opcode)))
  504. return -EFAULT;
  505. if ((opcode & OPCODE) == LL) {
  506. simulate_ll(regs, opcode);
  507. return 0;
  508. }
  509. if ((opcode & OPCODE) == SC) {
  510. simulate_sc(regs, opcode);
  511. return 0;
  512. }
  513. return -EFAULT; /* Strange things going on ... */
  514. }
  515. /*
  516. * Simulate trapping 'rdhwr' instructions to provide user accessible
  517. * registers not implemented in hardware. The only current use of this
  518. * is the thread area pointer.
  519. */
  520. static inline int simulate_rdhwr(struct pt_regs *regs)
  521. {
  522. struct thread_info *ti = task_thread_info(current);
  523. unsigned int opcode;
  524. if (unlikely(get_insn_opcode(regs, &opcode)))
  525. return -EFAULT;
  526. if (unlikely(compute_return_epc(regs)))
  527. return -EFAULT;
  528. if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
  529. int rd = (opcode & RD) >> 11;
  530. int rt = (opcode & RT) >> 16;
  531. switch (rd) {
  532. case 29:
  533. regs->regs[rt] = ti->tp_value;
  534. return 0;
  535. default:
  536. return -EFAULT;
  537. }
  538. }
  539. /* Not ours. */
  540. return -EFAULT;
  541. }
  542. asmlinkage void do_ov(struct pt_regs *regs)
  543. {
  544. siginfo_t info;
  545. die_if_kernel("Integer overflow", regs);
  546. info.si_code = FPE_INTOVF;
  547. info.si_signo = SIGFPE;
  548. info.si_errno = 0;
  549. info.si_addr = (void __user *) regs->cp0_epc;
  550. force_sig_info(SIGFPE, &info, current);
  551. }
  552. /*
  553. * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
  554. */
  555. asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
  556. {
  557. die_if_kernel("FP exception in kernel code", regs);
  558. if (fcr31 & FPU_CSR_UNI_X) {
  559. int sig;
  560. preempt_disable();
  561. #ifdef CONFIG_PREEMPT
  562. if (!is_fpu_owner()) {
  563. /* We might lose fpu before disabling preempt... */
  564. own_fpu();
  565. BUG_ON(!used_math());
  566. restore_fp(current);
  567. }
  568. #endif
  569. /*
  570. * Unimplemented operation exception. If we've got the full
  571. * software emulator on-board, let's use it...
  572. *
  573. * Force FPU to dump state into task/thread context. We're
  574. * moving a lot of data here for what is probably a single
  575. * instruction, but the alternative is to pre-decode the FP
  576. * register operands before invoking the emulator, which seems
  577. * a bit extreme for what should be an infrequent event.
  578. */
  579. save_fp(current);
  580. /* Ensure 'resume' not overwrite saved fp context again. */
  581. lose_fpu();
  582. preempt_enable();
  583. /* Run the emulator */
  584. sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
  585. preempt_disable();
  586. own_fpu(); /* Using the FPU again. */
  587. /*
  588. * We can't allow the emulated instruction to leave any of
  589. * the cause bit set in $fcr31.
  590. */
  591. current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
  592. /* Restore the hardware register state */
  593. restore_fp(current);
  594. preempt_enable();
  595. /* If something went wrong, signal */
  596. if (sig)
  597. force_sig(sig, current);
  598. return;
  599. }
  600. force_sig(SIGFPE, current);
  601. }
  602. asmlinkage void do_bp(struct pt_regs *regs)
  603. {
  604. unsigned int opcode, bcode;
  605. siginfo_t info;
  606. die_if_kernel("Break instruction in kernel code", regs);
  607. if (get_insn_opcode(regs, &opcode))
  608. return;
  609. /*
  610. * There is the ancient bug in the MIPS assemblers that the break
  611. * code starts left to bit 16 instead to bit 6 in the opcode.
  612. * Gas is bug-compatible, but not always, grrr...
  613. * We handle both cases with a simple heuristics. --macro
  614. */
  615. bcode = ((opcode >> 6) & ((1 << 20) - 1));
  616. if (bcode < (1 << 10))
  617. bcode <<= 10;
  618. /*
  619. * (A short test says that IRIX 5.3 sends SIGTRAP for all break
  620. * insns, even for break codes that indicate arithmetic failures.
  621. * Weird ...)
  622. * But should we continue the brokenness??? --macro
  623. */
  624. switch (bcode) {
  625. case BRK_OVERFLOW << 10:
  626. case BRK_DIVZERO << 10:
  627. if (bcode == (BRK_DIVZERO << 10))
  628. info.si_code = FPE_INTDIV;
  629. else
  630. info.si_code = FPE_INTOVF;
  631. info.si_signo = SIGFPE;
  632. info.si_errno = 0;
  633. info.si_addr = (void __user *) regs->cp0_epc;
  634. force_sig_info(SIGFPE, &info, current);
  635. break;
  636. default:
  637. force_sig(SIGTRAP, current);
  638. }
  639. }
  640. asmlinkage void do_tr(struct pt_regs *regs)
  641. {
  642. unsigned int opcode, tcode = 0;
  643. siginfo_t info;
  644. die_if_kernel("Trap instruction in kernel code", regs);
  645. if (get_insn_opcode(regs, &opcode))
  646. return;
  647. /* Immediate versions don't provide a code. */
  648. if (!(opcode & OPCODE))
  649. tcode = ((opcode >> 6) & ((1 << 10) - 1));
  650. /*
  651. * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
  652. * insns, even for trap codes that indicate arithmetic failures.
  653. * Weird ...)
  654. * But should we continue the brokenness??? --macro
  655. */
  656. switch (tcode) {
  657. case BRK_OVERFLOW:
  658. case BRK_DIVZERO:
  659. if (tcode == BRK_DIVZERO)
  660. info.si_code = FPE_INTDIV;
  661. else
  662. info.si_code = FPE_INTOVF;
  663. info.si_signo = SIGFPE;
  664. info.si_errno = 0;
  665. info.si_addr = (void __user *) regs->cp0_epc;
  666. force_sig_info(SIGFPE, &info, current);
  667. break;
  668. default:
  669. force_sig(SIGTRAP, current);
  670. }
  671. }
  672. asmlinkage void do_ri(struct pt_regs *regs)
  673. {
  674. die_if_kernel("Reserved instruction in kernel code", regs);
  675. if (!cpu_has_llsc)
  676. if (!simulate_llsc(regs))
  677. return;
  678. if (!simulate_rdhwr(regs))
  679. return;
  680. force_sig(SIGILL, current);
  681. }
  682. asmlinkage void do_cpu(struct pt_regs *regs)
  683. {
  684. unsigned int cpid;
  685. die_if_kernel("do_cpu invoked from kernel context!", regs);
  686. cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
  687. switch (cpid) {
  688. case 0:
  689. if (!cpu_has_llsc)
  690. if (!simulate_llsc(regs))
  691. return;
  692. if (!simulate_rdhwr(regs))
  693. return;
  694. break;
  695. case 1:
  696. preempt_disable();
  697. own_fpu();
  698. if (used_math()) { /* Using the FPU again. */
  699. restore_fp(current);
  700. } else { /* First time FPU user. */
  701. init_fpu();
  702. set_used_math();
  703. }
  704. preempt_enable();
  705. if (!cpu_has_fpu) {
  706. int sig = fpu_emulator_cop1Handler(regs,
  707. &current->thread.fpu);
  708. if (sig)
  709. force_sig(sig, current);
  710. #ifdef CONFIG_MIPS_MT_FPAFF
  711. else {
  712. /*
  713. * MIPS MT processors may have fewer FPU contexts
  714. * than CPU threads. If we've emulated more than
  715. * some threshold number of instructions, force
  716. * migration to a "CPU" that has FP support.
  717. */
  718. if(mt_fpemul_threshold > 0
  719. && ((current->thread.emulated_fp++
  720. > mt_fpemul_threshold))) {
  721. /*
  722. * If there's no FPU present, or if the
  723. * application has already restricted
  724. * the allowed set to exclude any CPUs
  725. * with FPUs, we'll skip the procedure.
  726. */
  727. if (cpus_intersects(current->cpus_allowed,
  728. mt_fpu_cpumask)) {
  729. cpumask_t tmask;
  730. cpus_and(tmask,
  731. current->thread.user_cpus_allowed,
  732. mt_fpu_cpumask);
  733. set_cpus_allowed(current, tmask);
  734. current->thread.mflags |= MF_FPUBOUND;
  735. }
  736. }
  737. }
  738. #endif /* CONFIG_MIPS_MT_FPAFF */
  739. }
  740. return;
  741. case 2:
  742. case 3:
  743. die_if_kernel("do_cpu invoked from kernel context!", regs);
  744. break;
  745. }
  746. force_sig(SIGILL, current);
  747. }
  748. asmlinkage void do_mdmx(struct pt_regs *regs)
  749. {
  750. force_sig(SIGILL, current);
  751. }
  752. asmlinkage void do_watch(struct pt_regs *regs)
  753. {
  754. /*
  755. * We use the watch exception where available to detect stack
  756. * overflows.
  757. */
  758. dump_tlb_all();
  759. show_regs(regs);
  760. panic("Caught WATCH exception - probably caused by stack overflow.");
  761. }
  762. asmlinkage void do_mcheck(struct pt_regs *regs)
  763. {
  764. const int field = 2 * sizeof(unsigned long);
  765. int multi_match = regs->cp0_status & ST0_TS;
  766. show_regs(regs);
  767. if (multi_match) {
  768. printk("Index : %0x\n", read_c0_index());
  769. printk("Pagemask: %0x\n", read_c0_pagemask());
  770. printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
  771. printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
  772. printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
  773. printk("\n");
  774. dump_tlb_all();
  775. }
  776. show_code((unsigned int *) regs->cp0_epc);
  777. /*
  778. * Some chips may have other causes of machine check (e.g. SB1
  779. * graduation timer)
  780. */
  781. panic("Caught Machine Check exception - %scaused by multiple "
  782. "matching entries in the TLB.",
  783. (multi_match) ? "" : "not ");
  784. }
  785. asmlinkage void do_mt(struct pt_regs *regs)
  786. {
  787. int subcode;
  788. subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
  789. >> VPECONTROL_EXCPT_SHIFT;
  790. switch (subcode) {
  791. case 0:
  792. printk(KERN_DEBUG "Thread Underflow\n");
  793. break;
  794. case 1:
  795. printk(KERN_DEBUG "Thread Overflow\n");
  796. break;
  797. case 2:
  798. printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
  799. break;
  800. case 3:
  801. printk(KERN_DEBUG "Gating Storage Exception\n");
  802. break;
  803. case 4:
  804. printk(KERN_DEBUG "YIELD Scheduler Exception\n");
  805. break;
  806. case 5:
  807. printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
  808. break;
  809. default:
  810. printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
  811. subcode);
  812. break;
  813. }
  814. die_if_kernel("MIPS MT Thread exception in kernel", regs);
  815. force_sig(SIGILL, current);
  816. }
  817. asmlinkage void do_dsp(struct pt_regs *regs)
  818. {
  819. if (cpu_has_dsp)
  820. panic("Unexpected DSP exception\n");
  821. force_sig(SIGILL, current);
  822. }
  823. asmlinkage void do_reserved(struct pt_regs *regs)
  824. {
  825. /*
  826. * Game over - no way to handle this if it ever occurs. Most probably
  827. * caused by a new unknown cpu type or after another deadly
  828. * hard/software error.
  829. */
  830. show_regs(regs);
  831. panic("Caught reserved exception %ld - should not happen.",
  832. (regs->cp0_cause & 0x7f) >> 2);
  833. }
  834. asmlinkage void do_default_vi(struct pt_regs *regs)
  835. {
  836. show_regs(regs);
  837. panic("Caught unexpected vectored interrupt.");
  838. }
  839. /*
  840. * Some MIPS CPUs can enable/disable for cache parity detection, but do
  841. * it different ways.
  842. */
  843. static inline void parity_protection_init(void)
  844. {
  845. switch (current_cpu_data.cputype) {
  846. case CPU_24K:
  847. case CPU_34K:
  848. case CPU_5KC:
  849. write_c0_ecc(0x80000000);
  850. back_to_back_c0_hazard();
  851. /* Set the PE bit (bit 31) in the c0_errctl register. */
  852. printk(KERN_INFO "Cache parity protection %sabled\n",
  853. (read_c0_ecc() & 0x80000000) ? "en" : "dis");
  854. break;
  855. case CPU_20KC:
  856. case CPU_25KF:
  857. /* Clear the DE bit (bit 16) in the c0_status register. */
  858. printk(KERN_INFO "Enable cache parity protection for "
  859. "MIPS 20KC/25KF CPUs.\n");
  860. clear_c0_status(ST0_DE);
  861. break;
  862. default:
  863. break;
  864. }
  865. }
  866. asmlinkage void cache_parity_error(void)
  867. {
  868. const int field = 2 * sizeof(unsigned long);
  869. unsigned int reg_val;
  870. /* For the moment, report the problem and hang. */
  871. printk("Cache error exception:\n");
  872. printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
  873. reg_val = read_c0_cacheerr();
  874. printk("c0_cacheerr == %08x\n", reg_val);
  875. printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
  876. reg_val & (1<<30) ? "secondary" : "primary",
  877. reg_val & (1<<31) ? "data" : "insn");
  878. printk("Error bits: %s%s%s%s%s%s%s\n",
  879. reg_val & (1<<29) ? "ED " : "",
  880. reg_val & (1<<28) ? "ET " : "",
  881. reg_val & (1<<26) ? "EE " : "",
  882. reg_val & (1<<25) ? "EB " : "",
  883. reg_val & (1<<24) ? "EI " : "",
  884. reg_val & (1<<23) ? "E1 " : "",
  885. reg_val & (1<<22) ? "E0 " : "");
  886. printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
  887. #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
  888. if (reg_val & (1<<22))
  889. printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
  890. if (reg_val & (1<<23))
  891. printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
  892. #endif
  893. panic("Can't handle the cache error!");
  894. }
  895. /*
  896. * SDBBP EJTAG debug exception handler.
  897. * We skip the instruction and return to the next instruction.
  898. */
  899. void ejtag_exception_handler(struct pt_regs *regs)
  900. {
  901. const int field = 2 * sizeof(unsigned long);
  902. unsigned long depc, old_epc;
  903. unsigned int debug;
  904. printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
  905. depc = read_c0_depc();
  906. debug = read_c0_debug();
  907. printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
  908. if (debug & 0x80000000) {
  909. /*
  910. * In branch delay slot.
  911. * We cheat a little bit here and use EPC to calculate the
  912. * debug return address (DEPC). EPC is restored after the
  913. * calculation.
  914. */
  915. old_epc = regs->cp0_epc;
  916. regs->cp0_epc = depc;
  917. __compute_return_epc(regs);
  918. depc = regs->cp0_epc;
  919. regs->cp0_epc = old_epc;
  920. } else
  921. depc += 4;
  922. write_c0_depc(depc);
  923. #if 0
  924. printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
  925. write_c0_debug(debug | 0x100);
  926. #endif
  927. }
  928. /*
  929. * NMI exception handler.
  930. */
  931. void nmi_exception_handler(struct pt_regs *regs)
  932. {
  933. #ifdef CONFIG_MIPS_MT_SMTC
  934. unsigned long dvpret = dvpe();
  935. bust_spinlocks(1);
  936. printk("NMI taken!!!!\n");
  937. mips_mt_regdump(dvpret);
  938. #else
  939. bust_spinlocks(1);
  940. printk("NMI taken!!!!\n");
  941. #endif /* CONFIG_MIPS_MT_SMTC */
  942. die("NMI", regs);
  943. while(1) ;
  944. }
  945. #define VECTORSPACING 0x100 /* for EI/VI mode */
  946. unsigned long ebase;
  947. unsigned long exception_handlers[32];
  948. unsigned long vi_handlers[64];
  949. /*
  950. * As a side effect of the way this is implemented we're limited
  951. * to interrupt handlers in the address range from
  952. * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
  953. */
  954. void *set_except_vector(int n, void *addr)
  955. {
  956. unsigned long handler = (unsigned long) addr;
  957. unsigned long old_handler = exception_handlers[n];
  958. exception_handlers[n] = handler;
  959. if (n == 0 && cpu_has_divec) {
  960. *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
  961. (0x03ffffff & (handler >> 2));
  962. flush_icache_range(ebase + 0x200, ebase + 0x204);
  963. }
  964. return (void *)old_handler;
  965. }
  966. #ifdef CONFIG_CPU_MIPSR2_SRS
  967. /*
  968. * MIPSR2 shadow register set allocation
  969. * FIXME: SMP...
  970. */
  971. static struct shadow_registers {
  972. /*
  973. * Number of shadow register sets supported
  974. */
  975. unsigned long sr_supported;
  976. /*
  977. * Bitmap of allocated shadow registers
  978. */
  979. unsigned long sr_allocated;
  980. } shadow_registers;
  981. static void mips_srs_init(void)
  982. {
  983. shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
  984. printk(KERN_INFO "%d MIPSR2 register sets available\n",
  985. shadow_registers.sr_supported);
  986. shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
  987. }
  988. int mips_srs_max(void)
  989. {
  990. return shadow_registers.sr_supported;
  991. }
  992. int mips_srs_alloc(void)
  993. {
  994. struct shadow_registers *sr = &shadow_registers;
  995. int set;
  996. again:
  997. set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
  998. if (set >= sr->sr_supported)
  999. return -1;
  1000. if (test_and_set_bit(set, &sr->sr_allocated))
  1001. goto again;
  1002. return set;
  1003. }
  1004. void mips_srs_free(int set)
  1005. {
  1006. struct shadow_registers *sr = &shadow_registers;
  1007. clear_bit(set, &sr->sr_allocated);
  1008. }
  1009. static void *set_vi_srs_handler(int n, void *addr, int srs)
  1010. {
  1011. unsigned long handler;
  1012. unsigned long old_handler = vi_handlers[n];
  1013. u32 *w;
  1014. unsigned char *b;
  1015. if (!cpu_has_veic && !cpu_has_vint)
  1016. BUG();
  1017. if (addr == NULL) {
  1018. handler = (unsigned long) do_default_vi;
  1019. srs = 0;
  1020. } else
  1021. handler = (unsigned long) addr;
  1022. vi_handlers[n] = (unsigned long) addr;
  1023. b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
  1024. if (srs >= mips_srs_max())
  1025. panic("Shadow register set %d not supported", srs);
  1026. if (cpu_has_veic) {
  1027. if (board_bind_eic_interrupt)
  1028. board_bind_eic_interrupt (n, srs);
  1029. } else if (cpu_has_vint) {
  1030. /* SRSMap is only defined if shadow sets are implemented */
  1031. if (mips_srs_max() > 1)
  1032. change_c0_srsmap (0xf << n*4, srs << n*4);
  1033. }
  1034. if (srs == 0) {
  1035. /*
  1036. * If no shadow set is selected then use the default handler
  1037. * that does normal register saving and a standard interrupt exit
  1038. */
  1039. extern char except_vec_vi, except_vec_vi_lui;
  1040. extern char except_vec_vi_ori, except_vec_vi_end;
  1041. #ifdef CONFIG_MIPS_MT_SMTC
  1042. /*
  1043. * We need to provide the SMTC vectored interrupt handler
  1044. * not only with the address of the handler, but with the
  1045. * Status.IM bit to be masked before going there.
  1046. */
  1047. extern char except_vec_vi_mori;
  1048. const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
  1049. #endif /* CONFIG_MIPS_MT_SMTC */
  1050. const int handler_len = &except_vec_vi_end - &except_vec_vi;
  1051. const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
  1052. const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
  1053. if (handler_len > VECTORSPACING) {
  1054. /*
  1055. * Sigh... panicing won't help as the console
  1056. * is probably not configured :(
  1057. */
  1058. panic ("VECTORSPACING too small");
  1059. }
  1060. memcpy (b, &except_vec_vi, handler_len);
  1061. #ifdef CONFIG_MIPS_MT_SMTC
  1062. if (n > 7)
  1063. printk("Vector index %d exceeds SMTC maximum\n", n);
  1064. w = (u32 *)(b + mori_offset);
  1065. *w = (*w & 0xffff0000) | (0x100 << n);
  1066. #endif /* CONFIG_MIPS_MT_SMTC */
  1067. w = (u32 *)(b + lui_offset);
  1068. *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
  1069. w = (u32 *)(b + ori_offset);
  1070. *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
  1071. flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
  1072. }
  1073. else {
  1074. /*
  1075. * In other cases jump directly to the interrupt handler
  1076. *
  1077. * It is the handlers responsibility to save registers if required
  1078. * (eg hi/lo) and return from the exception using "eret"
  1079. */
  1080. w = (u32 *)b;
  1081. *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
  1082. *w = 0;
  1083. flush_icache_range((unsigned long)b, (unsigned long)(b+8));
  1084. }
  1085. return (void *)old_handler;
  1086. }
  1087. void *set_vi_handler(int n, void *addr)
  1088. {
  1089. return set_vi_srs_handler(n, addr, 0);
  1090. }
  1091. #else
  1092. static inline void mips_srs_init(void)
  1093. {
  1094. }
  1095. #endif /* CONFIG_CPU_MIPSR2_SRS */
  1096. /*
  1097. * This is used by native signal handling
  1098. */
  1099. asmlinkage int (*save_fp_context)(struct sigcontext *sc);
  1100. asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
  1101. extern asmlinkage int _save_fp_context(struct sigcontext *sc);
  1102. extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
  1103. extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
  1104. extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
  1105. #ifdef CONFIG_SMP
  1106. static int smp_save_fp_context(struct sigcontext *sc)
  1107. {
  1108. return cpu_has_fpu
  1109. ? _save_fp_context(sc)
  1110. : fpu_emulator_save_context(sc);
  1111. }
  1112. static int smp_restore_fp_context(struct sigcontext *sc)
  1113. {
  1114. return cpu_has_fpu
  1115. ? _restore_fp_context(sc)
  1116. : fpu_emulator_restore_context(sc);
  1117. }
  1118. #endif
  1119. static inline void signal_init(void)
  1120. {
  1121. #ifdef CONFIG_SMP
  1122. /* For now just do the cpu_has_fpu check when the functions are invoked */
  1123. save_fp_context = smp_save_fp_context;
  1124. restore_fp_context = smp_restore_fp_context;
  1125. #else
  1126. if (cpu_has_fpu) {
  1127. save_fp_context = _save_fp_context;
  1128. restore_fp_context = _restore_fp_context;
  1129. } else {
  1130. save_fp_context = fpu_emulator_save_context;
  1131. restore_fp_context = fpu_emulator_restore_context;
  1132. }
  1133. #endif
  1134. }
  1135. #ifdef CONFIG_MIPS32_COMPAT
  1136. /*
  1137. * This is used by 32-bit signal stuff on the 64-bit kernel
  1138. */
  1139. asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
  1140. asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
  1141. extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
  1142. extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
  1143. extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
  1144. extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
  1145. static inline void signal32_init(void)
  1146. {
  1147. if (cpu_has_fpu) {
  1148. save_fp_context32 = _save_fp_context32;
  1149. restore_fp_context32 = _restore_fp_context32;
  1150. } else {
  1151. save_fp_context32 = fpu_emulator_save_context32;
  1152. restore_fp_context32 = fpu_emulator_restore_context32;
  1153. }
  1154. }
  1155. #endif
  1156. extern void cpu_cache_init(void);
  1157. extern void tlb_init(void);
  1158. extern void flush_tlb_handlers(void);
  1159. void __init per_cpu_trap_init(void)
  1160. {
  1161. unsigned int cpu = smp_processor_id();
  1162. unsigned int status_set = ST0_CU0;
  1163. #ifdef CONFIG_MIPS_MT_SMTC
  1164. int secondaryTC = 0;
  1165. int bootTC = (cpu == 0);
  1166. /*
  1167. * Only do per_cpu_trap_init() for first TC of Each VPE.
  1168. * Note that this hack assumes that the SMTC init code
  1169. * assigns TCs consecutively and in ascending order.
  1170. */
  1171. if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
  1172. ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
  1173. secondaryTC = 1;
  1174. #endif /* CONFIG_MIPS_MT_SMTC */
  1175. /*
  1176. * Disable coprocessors and select 32-bit or 64-bit addressing
  1177. * and the 16/32 or 32/32 FPR register model. Reset the BEV
  1178. * flag that some firmware may have left set and the TS bit (for
  1179. * IP27). Set XX for ISA IV code to work.
  1180. */
  1181. #ifdef CONFIG_64BIT
  1182. status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
  1183. #endif
  1184. if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
  1185. status_set |= ST0_XX;
  1186. change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
  1187. status_set);
  1188. if (cpu_has_dsp)
  1189. set_c0_status(ST0_MX);
  1190. #ifdef CONFIG_CPU_MIPSR2
  1191. write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
  1192. #endif
  1193. #ifdef CONFIG_MIPS_MT_SMTC
  1194. if (!secondaryTC) {
  1195. #endif /* CONFIG_MIPS_MT_SMTC */
  1196. /*
  1197. * Interrupt handling.
  1198. */
  1199. if (cpu_has_veic || cpu_has_vint) {
  1200. write_c0_ebase (ebase);
  1201. /* Setting vector spacing enables EI/VI mode */
  1202. change_c0_intctl (0x3e0, VECTORSPACING);
  1203. }
  1204. if (cpu_has_divec) {
  1205. if (cpu_has_mipsmt) {
  1206. unsigned int vpflags = dvpe();
  1207. set_c0_cause(CAUSEF_IV);
  1208. evpe(vpflags);
  1209. } else
  1210. set_c0_cause(CAUSEF_IV);
  1211. }
  1212. #ifdef CONFIG_MIPS_MT_SMTC
  1213. }
  1214. #endif /* CONFIG_MIPS_MT_SMTC */
  1215. cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
  1216. TLBMISS_HANDLER_SETUP();
  1217. atomic_inc(&init_mm.mm_count);
  1218. current->active_mm = &init_mm;
  1219. BUG_ON(current->mm);
  1220. enter_lazy_tlb(&init_mm, current);
  1221. #ifdef CONFIG_MIPS_MT_SMTC
  1222. if (bootTC) {
  1223. #endif /* CONFIG_MIPS_MT_SMTC */
  1224. cpu_cache_init();
  1225. tlb_init();
  1226. #ifdef CONFIG_MIPS_MT_SMTC
  1227. }
  1228. #endif /* CONFIG_MIPS_MT_SMTC */
  1229. }
  1230. /* Install CPU exception handler */
  1231. void __init set_handler (unsigned long offset, void *addr, unsigned long size)
  1232. {
  1233. memcpy((void *)(ebase + offset), addr, size);
  1234. flush_icache_range(ebase + offset, ebase + offset + size);
  1235. }
  1236. /* Install uncached CPU exception handler */
  1237. void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
  1238. {
  1239. #ifdef CONFIG_32BIT
  1240. unsigned long uncached_ebase = KSEG1ADDR(ebase);
  1241. #endif
  1242. #ifdef CONFIG_64BIT
  1243. unsigned long uncached_ebase = TO_UNCAC(ebase);
  1244. #endif
  1245. memcpy((void *)(uncached_ebase + offset), addr, size);
  1246. }
  1247. void __init trap_init(void)
  1248. {
  1249. extern char except_vec3_generic, except_vec3_r4000;
  1250. extern char except_vec4;
  1251. unsigned long i;
  1252. if (cpu_has_veic || cpu_has_vint)
  1253. ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
  1254. else
  1255. ebase = CAC_BASE;
  1256. mips_srs_init();
  1257. per_cpu_trap_init();
  1258. /*
  1259. * Copy the generic exception handlers to their final destination.
  1260. * This will be overriden later as suitable for a particular
  1261. * configuration.
  1262. */
  1263. set_handler(0x180, &except_vec3_generic, 0x80);
  1264. /*
  1265. * Setup default vectors
  1266. */
  1267. for (i = 0; i <= 31; i++)
  1268. set_except_vector(i, handle_reserved);
  1269. /*
  1270. * Copy the EJTAG debug exception vector handler code to it's final
  1271. * destination.
  1272. */
  1273. if (cpu_has_ejtag && board_ejtag_handler_setup)
  1274. board_ejtag_handler_setup ();
  1275. /*
  1276. * Only some CPUs have the watch exceptions.
  1277. */
  1278. if (cpu_has_watch)
  1279. set_except_vector(23, handle_watch);
  1280. /*
  1281. * Initialise interrupt handlers
  1282. */
  1283. if (cpu_has_veic || cpu_has_vint) {
  1284. int nvec = cpu_has_veic ? 64 : 8;
  1285. for (i = 0; i < nvec; i++)
  1286. set_vi_handler(i, NULL);
  1287. }
  1288. else if (cpu_has_divec)
  1289. set_handler(0x200, &except_vec4, 0x8);
  1290. /*
  1291. * Some CPUs can enable/disable for cache parity detection, but does
  1292. * it different ways.
  1293. */
  1294. parity_protection_init();
  1295. /*
  1296. * The Data Bus Errors / Instruction Bus Errors are signaled
  1297. * by external hardware. Therefore these two exceptions
  1298. * may have board specific handlers.
  1299. */
  1300. if (board_be_init)
  1301. board_be_init();
  1302. set_except_vector(0, handle_int);
  1303. set_except_vector(1, handle_tlbm);
  1304. set_except_vector(2, handle_tlbl);
  1305. set_except_vector(3, handle_tlbs);
  1306. set_except_vector(4, handle_adel);
  1307. set_except_vector(5, handle_ades);
  1308. set_except_vector(6, handle_ibe);
  1309. set_except_vector(7, handle_dbe);
  1310. set_except_vector(8, handle_sys);
  1311. set_except_vector(9, handle_bp);
  1312. set_except_vector(10, handle_ri);
  1313. set_except_vector(11, handle_cpu);
  1314. set_except_vector(12, handle_ov);
  1315. set_except_vector(13, handle_tr);
  1316. if (current_cpu_data.cputype == CPU_R6000 ||
  1317. current_cpu_data.cputype == CPU_R6000A) {
  1318. /*
  1319. * The R6000 is the only R-series CPU that features a machine
  1320. * check exception (similar to the R4000 cache error) and
  1321. * unaligned ldc1/sdc1 exception. The handlers have not been
  1322. * written yet. Well, anyway there is no R6000 machine on the
  1323. * current list of targets for Linux/MIPS.
  1324. * (Duh, crap, there is someone with a triple R6k machine)
  1325. */
  1326. //set_except_vector(14, handle_mc);
  1327. //set_except_vector(15, handle_ndc);
  1328. }
  1329. if (board_nmi_handler_setup)
  1330. board_nmi_handler_setup();
  1331. if (cpu_has_fpu && !cpu_has_nofpuex)
  1332. set_except_vector(15, handle_fpe);
  1333. set_except_vector(22, handle_mdmx);
  1334. if (cpu_has_mcheck)
  1335. set_except_vector(24, handle_mcheck);
  1336. if (cpu_has_mipsmt)
  1337. set_except_vector(25, handle_mt);
  1338. if (cpu_has_dsp)
  1339. set_except_vector(26, handle_dsp);
  1340. if (cpu_has_vce)
  1341. /* Special exception: R4[04]00 uses also the divec space. */
  1342. memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
  1343. else if (cpu_has_4kex)
  1344. memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
  1345. else
  1346. memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
  1347. signal_init();
  1348. #ifdef CONFIG_MIPS32_COMPAT
  1349. signal32_init();
  1350. #endif
  1351. flush_icache_range(ebase, ebase + 0x400);
  1352. flush_tlb_handlers();
  1353. }