octeon_edac-lmc.c 3.1 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2009 Wind River Systems,
  7. * written by Ralf Baechle <ralf@linux-mips.org>
  8. */
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/slab.h>
  12. #include <linux/io.h>
  13. #include <linux/edac.h>
  14. #include <asm/octeon/cvmx.h>
  15. #include "edac_core.h"
  16. #include "edac_module.h"
  17. #include "octeon_edac-lmc.h"
  18. #define EDAC_MOD_STR "octeon"
  19. static struct mem_ctl_info *mc_cavium;
  20. static void *lmc_base;
  21. static void co_lmc_poll(struct mem_ctl_info *mci)
  22. {
  23. union lmc_mem_cfg0 cfg0;
  24. union lmc_fadr fadr;
  25. char msg[64];
  26. fadr.u64 = readq(lmc_base + LMC_FADR);
  27. cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
  28. snprintf(msg, sizeof(msg), "DIMM %d rank %d bank %d row %d col %d",
  29. fadr.fdimm, fadr.fbunk, fadr.fbank, fadr.frow, fadr.fcol);
  30. if (cfg0.sec_err) {
  31. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
  32. msg, "");
  33. cfg0.intr_sec_ena = -1; /* Done, re-arm */
  34. }
  35. if (cfg0.ded_err) {
  36. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
  37. msg, "");
  38. cfg0.intr_ded_ena = -1; /* Done, re-arm */
  39. }
  40. writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
  41. }
  42. static int __devinit co_lmc_probe(struct platform_device *pdev)
  43. {
  44. struct mem_ctl_info *mci;
  45. union lmc_mem_cfg0 cfg0;
  46. int res = 0;
  47. mci = edac_mc_alloc(0, 0, 0, 0);
  48. if (!mci)
  49. return -ENOMEM;
  50. mci->pdev = &pdev->dev;
  51. platform_set_drvdata(pdev, mci);
  52. mci->dev_name = dev_name(&pdev->dev);
  53. mci->mod_name = "octeon-lmc";
  54. mci->ctl_name = "co_lmc_err";
  55. mci->edac_check = co_lmc_poll;
  56. if (edac_mc_add_mc(mci) > 0) {
  57. pr_err("%s: edac_mc_add_mc() failed\n", __func__);
  58. goto err;
  59. }
  60. cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0); /* We poll */
  61. cfg0.intr_ded_ena = 0;
  62. cfg0.intr_sec_ena = 0;
  63. writeq(cfg0.u64, lmc_base + LMC_MEM_CFG0);
  64. mc_cavium = mci;
  65. return 0;
  66. err:
  67. edac_mc_free(mci);
  68. return res;
  69. }
  70. static int co_lmc_remove(struct platform_device *pdev)
  71. {
  72. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  73. mc_cavium = NULL;
  74. edac_mc_del_mc(&pdev->dev);
  75. edac_mc_free(mci);
  76. return 0;
  77. }
  78. static struct platform_driver co_lmc_driver = {
  79. .probe = co_lmc_probe,
  80. .remove = co_lmc_remove,
  81. .driver = {
  82. .name = "co_lmc_edac",
  83. }
  84. };
  85. static int __init co_edac_init(void)
  86. {
  87. union lmc_mem_cfg0 cfg0;
  88. int ret;
  89. lmc_base = ioremap_nocache(LMC_BASE, LMC_SIZE);
  90. if (!lmc_base)
  91. return -ENOMEM;
  92. cfg0.u64 = readq(lmc_base + LMC_MEM_CFG0);
  93. if (!cfg0.ecc_ena) {
  94. pr_info(EDAC_MOD_STR " LMC EDAC: ECC disabled, good bye\n");
  95. ret = -ENODEV;
  96. goto out;
  97. }
  98. ret = platform_driver_register(&co_lmc_driver);
  99. if (ret) {
  100. pr_warning(EDAC_MOD_STR " LMC EDAC failed to register\n");
  101. goto out;
  102. }
  103. return ret;
  104. out:
  105. iounmap(lmc_base);
  106. return ret;
  107. }
  108. static void __exit co_edac_exit(void)
  109. {
  110. platform_driver_unregister(&co_lmc_driver);
  111. iounmap(lmc_base);
  112. }
  113. module_init(co_edac_init);
  114. module_exit(co_edac_exit);
  115. MODULE_LICENSE("GPL");
  116. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");