cx23885.h 16 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/pci.h>
  22. #include <linux/i2c.h>
  23. #include <linux/i2c-algo-bit.h>
  24. #include <linux/kdev_t.h>
  25. #include <media/v4l2-device.h>
  26. #include <media/tuner.h>
  27. #include <media/tveeprom.h>
  28. #include <media/videobuf-dma-sg.h>
  29. #include <media/videobuf-dvb.h>
  30. #include "btcx-risc.h"
  31. #include "cx23885-reg.h"
  32. #include "media/cx2341x.h"
  33. #include <linux/version.h>
  34. #include <linux/mutex.h>
  35. #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2)
  36. #define UNSET (-1U)
  37. #define CX23885_MAXBOARDS 8
  38. /* Max number of inputs by card */
  39. #define MAX_CX23885_INPUT 8
  40. #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
  41. #define RESOURCE_OVERLAY 1
  42. #define RESOURCE_VIDEO 2
  43. #define RESOURCE_VBI 4
  44. #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
  45. #define CX23885_BOARD_NOAUTO UNSET
  46. #define CX23885_BOARD_UNKNOWN 0
  47. #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
  48. #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
  49. #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
  50. #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
  51. #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
  52. #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
  53. #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
  54. #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
  55. #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
  56. #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
  57. #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
  58. #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
  59. #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
  60. #define CX23885_BOARD_TBS_6920 14
  61. #define CX23885_BOARD_TEVII_S470 15
  62. #define CX23885_BOARD_DVBWORLD_2005 16
  63. #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
  64. #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
  65. #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
  66. #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
  67. #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
  68. #define CX23885_BOARD_MYGICA_X8506 22
  69. #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
  70. #define GPIO_0 0x00000001
  71. #define GPIO_1 0x00000002
  72. #define GPIO_2 0x00000004
  73. #define GPIO_3 0x00000008
  74. #define GPIO_4 0x00000010
  75. #define GPIO_5 0x00000020
  76. #define GPIO_6 0x00000040
  77. #define GPIO_7 0x00000080
  78. #define GPIO_8 0x00000100
  79. #define GPIO_9 0x00000200
  80. #define GPIO_10 0x00000400
  81. #define GPIO_11 0x00000800
  82. #define GPIO_12 0x00001000
  83. #define GPIO_13 0x00002000
  84. #define GPIO_14 0x00004000
  85. #define GPIO_15 0x00008000
  86. /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
  87. #define CX23885_NORMS (\
  88. V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
  89. V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
  90. V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
  91. V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
  92. struct cx23885_fmt {
  93. char *name;
  94. u32 fourcc; /* v4l2 format id */
  95. int depth;
  96. int flags;
  97. u32 cxformat;
  98. };
  99. struct cx23885_ctrl {
  100. struct v4l2_queryctrl v;
  101. u32 off;
  102. u32 reg;
  103. u32 mask;
  104. u32 shift;
  105. };
  106. struct cx23885_tvnorm {
  107. char *name;
  108. v4l2_std_id id;
  109. u32 cxiformat;
  110. u32 cxoformat;
  111. };
  112. struct cx23885_fh {
  113. struct cx23885_dev *dev;
  114. enum v4l2_buf_type type;
  115. int radio;
  116. u32 resources;
  117. /* video overlay */
  118. struct v4l2_window win;
  119. struct v4l2_clip *clips;
  120. unsigned int nclips;
  121. /* video capture */
  122. struct cx23885_fmt *fmt;
  123. unsigned int width, height;
  124. /* vbi capture */
  125. struct videobuf_queue vidq;
  126. struct videobuf_queue vbiq;
  127. /* MPEG Encoder specifics ONLY */
  128. struct videobuf_queue mpegq;
  129. atomic_t v4l_reading;
  130. };
  131. enum cx23885_itype {
  132. CX23885_VMUX_COMPOSITE1 = 1,
  133. CX23885_VMUX_COMPOSITE2,
  134. CX23885_VMUX_COMPOSITE3,
  135. CX23885_VMUX_COMPOSITE4,
  136. CX23885_VMUX_SVIDEO,
  137. CX23885_VMUX_TELEVISION,
  138. CX23885_VMUX_CABLE,
  139. CX23885_VMUX_DVB,
  140. CX23885_VMUX_DEBUG,
  141. CX23885_RADIO,
  142. };
  143. enum cx23885_src_sel_type {
  144. CX23885_SRC_SEL_EXT_656_VIDEO = 0,
  145. CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
  146. };
  147. /* buffer for one video frame */
  148. struct cx23885_buffer {
  149. /* common v4l buffer stuff -- must be first */
  150. struct videobuf_buffer vb;
  151. /* cx23885 specific */
  152. unsigned int bpl;
  153. struct btcx_riscmem risc;
  154. struct cx23885_fmt *fmt;
  155. u32 count;
  156. };
  157. struct cx23885_input {
  158. enum cx23885_itype type;
  159. unsigned int vmux;
  160. u32 gpio0, gpio1, gpio2, gpio3;
  161. };
  162. typedef enum {
  163. CX23885_MPEG_UNDEFINED = 0,
  164. CX23885_MPEG_DVB,
  165. CX23885_ANALOG_VIDEO,
  166. CX23885_MPEG_ENCODER,
  167. } port_t;
  168. struct cx23885_board {
  169. char *name;
  170. port_t porta, portb, portc;
  171. unsigned int tuner_type;
  172. unsigned int radio_type;
  173. unsigned char tuner_addr;
  174. unsigned char radio_addr;
  175. /* Vendors can and do run the PCIe bridge at different
  176. * clock rates, driven physically by crystals on the PCBs.
  177. * The core has to accomodate this. This allows the user
  178. * to add new boards with new frequencys. The value is
  179. * expressed in Hz.
  180. *
  181. * The core framework will default this value based on
  182. * current designs, but it can vary.
  183. */
  184. u32 clk_freq;
  185. struct cx23885_input input[MAX_CX23885_INPUT];
  186. int cimax; /* for NetUP */
  187. };
  188. struct cx23885_subid {
  189. u16 subvendor;
  190. u16 subdevice;
  191. u32 card;
  192. };
  193. struct cx23885_i2c {
  194. struct cx23885_dev *dev;
  195. int nr;
  196. /* i2c i/o */
  197. struct i2c_adapter i2c_adap;
  198. struct i2c_algo_bit_data i2c_algo;
  199. struct i2c_client i2c_client;
  200. u32 i2c_rc;
  201. /* 885 registers used for raw addess */
  202. u32 i2c_period;
  203. u32 reg_ctrl;
  204. u32 reg_stat;
  205. u32 reg_addr;
  206. u32 reg_rdata;
  207. u32 reg_wdata;
  208. };
  209. struct cx23885_dmaqueue {
  210. struct list_head active;
  211. struct list_head queued;
  212. struct timer_list timeout;
  213. struct btcx_riscmem stopper;
  214. u32 count;
  215. };
  216. struct cx23885_tsport {
  217. struct cx23885_dev *dev;
  218. int nr;
  219. int sram_chno;
  220. struct videobuf_dvb_frontends frontends;
  221. /* dma queues */
  222. struct cx23885_dmaqueue mpegq;
  223. u32 ts_packet_size;
  224. u32 ts_packet_count;
  225. int width;
  226. int height;
  227. spinlock_t slock;
  228. /* registers */
  229. u32 reg_gpcnt;
  230. u32 reg_gpcnt_ctl;
  231. u32 reg_dma_ctl;
  232. u32 reg_lngth;
  233. u32 reg_hw_sop_ctrl;
  234. u32 reg_gen_ctrl;
  235. u32 reg_bd_pkt_status;
  236. u32 reg_sop_status;
  237. u32 reg_fifo_ovfl_stat;
  238. u32 reg_vld_misc;
  239. u32 reg_ts_clk_en;
  240. u32 reg_ts_int_msk;
  241. u32 reg_ts_int_stat;
  242. u32 reg_src_sel;
  243. /* Default register vals */
  244. int pci_irqmask;
  245. u32 dma_ctl_val;
  246. u32 ts_int_msk_val;
  247. u32 gen_ctrl_val;
  248. u32 ts_clk_en_val;
  249. u32 src_sel_val;
  250. u32 vld_misc_val;
  251. u32 hw_sop_ctrl_val;
  252. /* Allow a single tsport to have multiple frontends */
  253. u32 num_frontends;
  254. void *port_priv;
  255. /* FIXME: temporary hack */
  256. int (*set_frontend_save) (struct dvb_frontend *,
  257. struct dvb_frontend_parameters *);
  258. };
  259. struct cx23885_dev {
  260. struct list_head devlist;
  261. atomic_t refcount;
  262. struct v4l2_device v4l2_dev;
  263. /* pci stuff */
  264. struct pci_dev *pci;
  265. unsigned char pci_rev, pci_lat;
  266. int pci_bus, pci_slot;
  267. u32 __iomem *lmmio;
  268. u8 __iomem *bmmio;
  269. int pci_irqmask;
  270. int hwrevision;
  271. /* This valud is board specific and is used to configure the
  272. * AV core so we see nice clean and stable video and audio. */
  273. u32 clk_freq;
  274. /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
  275. struct cx23885_i2c i2c_bus[3];
  276. int nr;
  277. struct mutex lock;
  278. /* board details */
  279. unsigned int board;
  280. char name[32];
  281. struct cx23885_tsport ts1, ts2;
  282. /* sram configuration */
  283. struct sram_channel *sram_channels;
  284. enum {
  285. CX23885_BRIDGE_UNDEFINED = 0,
  286. CX23885_BRIDGE_885 = 885,
  287. CX23885_BRIDGE_887 = 887,
  288. } bridge;
  289. /* Analog video */
  290. u32 resources;
  291. unsigned int input;
  292. u32 tvaudio;
  293. v4l2_std_id tvnorm;
  294. unsigned int tuner_type;
  295. unsigned char tuner_addr;
  296. unsigned int radio_type;
  297. unsigned char radio_addr;
  298. unsigned int has_radio;
  299. struct v4l2_subdev *sd_cx25840;
  300. /* V4l */
  301. u32 freq;
  302. struct video_device *video_dev;
  303. struct video_device *vbi_dev;
  304. struct video_device *radio_dev;
  305. struct cx23885_dmaqueue vidq;
  306. struct cx23885_dmaqueue vbiq;
  307. spinlock_t slock;
  308. /* MPEG Encoder ONLY settings */
  309. u32 cx23417_mailbox;
  310. struct cx2341x_mpeg_params mpeg_params;
  311. struct video_device *v4l_device;
  312. atomic_t v4l_reader_count;
  313. struct cx23885_tvnorm encodernorm;
  314. };
  315. static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
  316. {
  317. return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
  318. }
  319. #define call_all(dev, o, f, args...) \
  320. v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
  321. extern struct list_head cx23885_devlist;
  322. #define SRAM_CH01 0 /* Video A */
  323. #define SRAM_CH02 1 /* VBI A */
  324. #define SRAM_CH03 2 /* Video B */
  325. #define SRAM_CH04 3 /* Transport via B */
  326. #define SRAM_CH05 4 /* VBI B */
  327. #define SRAM_CH06 5 /* Video C */
  328. #define SRAM_CH07 6 /* Transport via C */
  329. #define SRAM_CH08 7 /* Audio Internal A */
  330. #define SRAM_CH09 8 /* Audio Internal B */
  331. #define SRAM_CH10 9 /* Audio External */
  332. #define SRAM_CH11 10 /* COMB_3D_N */
  333. #define SRAM_CH12 11 /* Comb 3D N1 */
  334. #define SRAM_CH13 12 /* Comb 3D N2 */
  335. #define SRAM_CH14 13 /* MOE Vid */
  336. #define SRAM_CH15 14 /* MOE RSLT */
  337. struct sram_channel {
  338. char *name;
  339. u32 cmds_start;
  340. u32 ctrl_start;
  341. u32 cdt;
  342. u32 fifo_start;
  343. u32 fifo_size;
  344. u32 ptr1_reg;
  345. u32 ptr2_reg;
  346. u32 cnt1_reg;
  347. u32 cnt2_reg;
  348. u32 jumponly;
  349. };
  350. /* ----------------------------------------------------------- */
  351. #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
  352. #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
  353. #define cx_andor(reg, mask, value) \
  354. writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
  355. ((value) & (mask)), dev->lmmio+((reg)>>2))
  356. #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
  357. #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
  358. /* ----------------------------------------------------------- */
  359. /* cx23885-core.c */
  360. extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
  361. struct sram_channel *ch,
  362. unsigned int bpl, u32 risc);
  363. extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
  364. struct sram_channel *ch);
  365. extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
  366. u32 reg, u32 mask, u32 value);
  367. extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
  368. struct scatterlist *sglist,
  369. unsigned int top_offset, unsigned int bottom_offset,
  370. unsigned int bpl, unsigned int padding, unsigned int lines);
  371. void cx23885_cancel_buffers(struct cx23885_tsport *port);
  372. extern int cx23885_restart_queue(struct cx23885_tsport *port,
  373. struct cx23885_dmaqueue *q);
  374. extern void cx23885_wakeup(struct cx23885_tsport *port,
  375. struct cx23885_dmaqueue *q, u32 count);
  376. extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
  377. extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
  378. extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
  379. int asoutput);
  380. /* ----------------------------------------------------------- */
  381. /* cx23885-cards.c */
  382. extern struct cx23885_board cx23885_boards[];
  383. extern const unsigned int cx23885_bcount;
  384. extern struct cx23885_subid cx23885_subids[];
  385. extern const unsigned int cx23885_idcount;
  386. extern int cx23885_tuner_callback(void *priv, int component,
  387. int command, int arg);
  388. extern void cx23885_card_list(struct cx23885_dev *dev);
  389. extern int cx23885_ir_init(struct cx23885_dev *dev);
  390. extern void cx23885_gpio_setup(struct cx23885_dev *dev);
  391. extern void cx23885_card_setup(struct cx23885_dev *dev);
  392. extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
  393. extern int cx23885_dvb_register(struct cx23885_tsport *port);
  394. extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
  395. extern int cx23885_buf_prepare(struct videobuf_queue *q,
  396. struct cx23885_tsport *port,
  397. struct cx23885_buffer *buf,
  398. enum v4l2_field field);
  399. extern void cx23885_buf_queue(struct cx23885_tsport *port,
  400. struct cx23885_buffer *buf);
  401. extern void cx23885_free_buffer(struct videobuf_queue *q,
  402. struct cx23885_buffer *buf);
  403. /* ----------------------------------------------------------- */
  404. /* cx23885-video.c */
  405. /* Video */
  406. extern int cx23885_video_register(struct cx23885_dev *dev);
  407. extern void cx23885_video_unregister(struct cx23885_dev *dev);
  408. extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
  409. /* ----------------------------------------------------------- */
  410. /* cx23885-vbi.c */
  411. extern int cx23885_vbi_fmt(struct file *file, void *priv,
  412. struct v4l2_format *f);
  413. extern void cx23885_vbi_timeout(unsigned long data);
  414. extern struct videobuf_queue_ops cx23885_vbi_qops;
  415. /* cx23885-i2c.c */
  416. extern int cx23885_i2c_register(struct cx23885_i2c *bus);
  417. extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
  418. extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
  419. /* ----------------------------------------------------------- */
  420. /* cx23885-417.c */
  421. extern int cx23885_417_register(struct cx23885_dev *dev);
  422. extern void cx23885_417_unregister(struct cx23885_dev *dev);
  423. extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
  424. extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
  425. extern void cx23885_mc417_init(struct cx23885_dev *dev);
  426. extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
  427. extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
  428. extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
  429. extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
  430. extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
  431. /* ----------------------------------------------------------- */
  432. /* tv norms */
  433. static inline unsigned int norm_maxw(v4l2_std_id norm)
  434. {
  435. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
  436. }
  437. static inline unsigned int norm_maxh(v4l2_std_id norm)
  438. {
  439. return (norm & V4L2_STD_625_50) ? 576 : 480;
  440. }
  441. static inline unsigned int norm_swidth(v4l2_std_id norm)
  442. {
  443. return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
  444. }