gdth.c 175 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/mutex.h>
  117. #include <linux/slab.h>
  118. #ifdef GDTH_RTC
  119. #include <linux/mc146818rtc.h>
  120. #endif
  121. #include <linux/reboot.h>
  122. #include <asm/dma.h>
  123. #include <asm/system.h>
  124. #include <asm/io.h>
  125. #include <asm/uaccess.h>
  126. #include <linux/spinlock.h>
  127. #include <linux/blkdev.h>
  128. #include <linux/scatterlist.h>
  129. #include "scsi.h"
  130. #include <scsi/scsi_host.h>
  131. #include "gdth.h"
  132. static DEFINE_MUTEX(gdth_mutex);
  133. static void gdth_delay(int milliseconds);
  134. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs);
  135. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  136. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  137. int gdth_from_wait, int* pIndex);
  138. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  139. Scsi_Cmnd *scp);
  140. static int gdth_async_event(gdth_ha_str *ha);
  141. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  142. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority);
  143. static void gdth_next(gdth_ha_str *ha);
  144. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b);
  145. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  146. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  147. u16 idx, gdth_evt_data *evt);
  148. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  149. static void gdth_readapp_event(gdth_ha_str *ha, u8 application,
  150. gdth_evt_str *estr);
  151. static void gdth_clear_events(void);
  152. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  153. char *buffer, u16 count);
  154. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  155. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive);
  156. static void gdth_enable_int(gdth_ha_str *ha);
  157. static int gdth_test_busy(gdth_ha_str *ha);
  158. static int gdth_get_cmd_index(gdth_ha_str *ha);
  159. static void gdth_release_event(gdth_ha_str *ha);
  160. static int gdth_wait(gdth_ha_str *ha, int index,u32 time);
  161. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  162. u32 p1, u64 p2,u64 p3);
  163. static int gdth_search_drives(gdth_ha_str *ha);
  164. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive);
  165. static const char *gdth_ctr_name(gdth_ha_str *ha);
  166. static int gdth_open(struct inode *inode, struct file *filep);
  167. static int gdth_close(struct inode *inode, struct file *filep);
  168. static long gdth_unlocked_ioctl(struct file *filep, unsigned int cmd,
  169. unsigned long arg);
  170. static void gdth_flush(gdth_ha_str *ha);
  171. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  172. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  173. struct gdth_cmndinfo *cmndinfo);
  174. static void gdth_scsi_done(struct scsi_cmnd *scp);
  175. #ifdef DEBUG_GDTH
  176. static u8 DebugState = DEBUG_GDTH;
  177. #ifdef __SERIAL__
  178. #define MAX_SERBUF 160
  179. static void ser_init(void);
  180. static void ser_puts(char *str);
  181. static void ser_putc(char c);
  182. static int ser_printk(const char *fmt, ...);
  183. static char strbuf[MAX_SERBUF+1];
  184. #ifdef __COM2__
  185. #define COM_BASE 0x2f8
  186. #else
  187. #define COM_BASE 0x3f8
  188. #endif
  189. static void ser_init()
  190. {
  191. unsigned port=COM_BASE;
  192. outb(0x80,port+3);
  193. outb(0,port+1);
  194. /* 19200 Baud, if 9600: outb(12,port) */
  195. outb(6, port);
  196. outb(3,port+3);
  197. outb(0,port+1);
  198. /*
  199. ser_putc('I');
  200. ser_putc(' ');
  201. */
  202. }
  203. static void ser_puts(char *str)
  204. {
  205. char *ptr;
  206. ser_init();
  207. for (ptr=str;*ptr;++ptr)
  208. ser_putc(*ptr);
  209. }
  210. static void ser_putc(char c)
  211. {
  212. unsigned port=COM_BASE;
  213. while ((inb(port+5) & 0x20)==0);
  214. outb(c,port);
  215. if (c==0x0a)
  216. {
  217. while ((inb(port+5) & 0x20)==0);
  218. outb(0x0d,port);
  219. }
  220. }
  221. static int ser_printk(const char *fmt, ...)
  222. {
  223. va_list args;
  224. int i;
  225. va_start(args,fmt);
  226. i = vsprintf(strbuf,fmt,args);
  227. ser_puts(strbuf);
  228. va_end(args);
  229. return i;
  230. }
  231. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  232. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  233. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  234. #else /* !__SERIAL__ */
  235. #define TRACE(a) {if (DebugState==1) {printk a;}}
  236. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  237. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  238. #endif
  239. #else /* !DEBUG */
  240. #define TRACE(a)
  241. #define TRACE2(a)
  242. #define TRACE3(a)
  243. #endif
  244. #ifdef GDTH_STATISTICS
  245. static u32 max_rq=0, max_index=0, max_sg=0;
  246. #ifdef INT_COAL
  247. static u32 max_int_coal=0;
  248. #endif
  249. static u32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  250. static struct timer_list gdth_timer;
  251. #endif
  252. #define PTR2USHORT(a) (u16)(unsigned long)(a)
  253. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  254. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  255. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  256. #ifdef CONFIG_ISA
  257. static u8 gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  258. #endif
  259. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  260. static u8 gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  261. #endif
  262. static u8 gdth_polling; /* polling if TRUE */
  263. static int gdth_ctr_count = 0; /* controller count */
  264. static LIST_HEAD(gdth_instances); /* controller list */
  265. static u8 gdth_write_through = FALSE; /* write through */
  266. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  267. static int elastidx;
  268. static int eoldidx;
  269. static int major;
  270. #define DIN 1 /* IN data direction */
  271. #define DOU 2 /* OUT data direction */
  272. #define DNO DIN /* no data transfer */
  273. #define DUN DIN /* unknown data direction */
  274. static u8 gdth_direction_tab[0x100] = {
  275. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  276. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  277. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  278. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  279. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  284. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  285. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  286. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  290. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  291. };
  292. /* LILO and modprobe/insmod parameters */
  293. /* IRQ list for GDT3000/3020 EISA controllers */
  294. static int irq[MAXHA] __initdata =
  295. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  296. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  297. /* disable driver flag */
  298. static int disable __initdata = 0;
  299. /* reserve flag */
  300. static int reserve_mode = 1;
  301. /* reserve list */
  302. static int reserve_list[MAX_RES_ARGS] =
  303. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  304. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  305. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  306. /* scan order for PCI controllers */
  307. static int reverse_scan = 0;
  308. /* virtual channel for the host drives */
  309. static int hdr_channel = 0;
  310. /* max. IDs per channel */
  311. static int max_ids = MAXID;
  312. /* rescan all IDs */
  313. static int rescan = 0;
  314. /* shared access */
  315. static int shared_access = 1;
  316. /* enable support for EISA and ISA controllers */
  317. static int probe_eisa_isa = 0;
  318. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  319. static int force_dma32 = 0;
  320. /* parameters for modprobe/insmod */
  321. module_param_array(irq, int, NULL, 0);
  322. module_param(disable, int, 0);
  323. module_param(reserve_mode, int, 0);
  324. module_param_array(reserve_list, int, NULL, 0);
  325. module_param(reverse_scan, int, 0);
  326. module_param(hdr_channel, int, 0);
  327. module_param(max_ids, int, 0);
  328. module_param(rescan, int, 0);
  329. module_param(shared_access, int, 0);
  330. module_param(probe_eisa_isa, int, 0);
  331. module_param(force_dma32, int, 0);
  332. MODULE_AUTHOR("Achim Leubner");
  333. MODULE_LICENSE("GPL");
  334. /* ioctl interface */
  335. static const struct file_operations gdth_fops = {
  336. .unlocked_ioctl = gdth_unlocked_ioctl,
  337. .open = gdth_open,
  338. .release = gdth_close,
  339. .llseek = noop_llseek,
  340. };
  341. #include "gdth_proc.h"
  342. #include "gdth_proc.c"
  343. static gdth_ha_str *gdth_find_ha(int hanum)
  344. {
  345. gdth_ha_str *ha;
  346. list_for_each_entry(ha, &gdth_instances, list)
  347. if (hanum == ha->hanum)
  348. return ha;
  349. return NULL;
  350. }
  351. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  352. {
  353. struct gdth_cmndinfo *priv = NULL;
  354. unsigned long flags;
  355. int i;
  356. spin_lock_irqsave(&ha->smp_lock, flags);
  357. for (i=0; i<GDTH_MAXCMDS; ++i) {
  358. if (ha->cmndinfo[i].index == 0) {
  359. priv = &ha->cmndinfo[i];
  360. memset(priv, 0, sizeof(*priv));
  361. priv->index = i+1;
  362. break;
  363. }
  364. }
  365. spin_unlock_irqrestore(&ha->smp_lock, flags);
  366. return priv;
  367. }
  368. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  369. {
  370. BUG_ON(!priv);
  371. priv->index = 0;
  372. }
  373. static void gdth_delay(int milliseconds)
  374. {
  375. if (milliseconds == 0) {
  376. udelay(1);
  377. } else {
  378. mdelay(milliseconds);
  379. }
  380. }
  381. static void gdth_scsi_done(struct scsi_cmnd *scp)
  382. {
  383. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  384. int internal_command = cmndinfo->internal_command;
  385. TRACE2(("gdth_scsi_done()\n"));
  386. gdth_put_cmndinfo(cmndinfo);
  387. scp->host_scribble = NULL;
  388. if (internal_command)
  389. complete((struct completion *)scp->request);
  390. else
  391. scp->scsi_done(scp);
  392. }
  393. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  394. int timeout, u32 *info)
  395. {
  396. gdth_ha_str *ha = shost_priv(sdev->host);
  397. Scsi_Cmnd *scp;
  398. struct gdth_cmndinfo cmndinfo;
  399. DECLARE_COMPLETION_ONSTACK(wait);
  400. int rval;
  401. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  402. if (!scp)
  403. return -ENOMEM;
  404. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  405. if (!scp->sense_buffer) {
  406. kfree(scp);
  407. return -ENOMEM;
  408. }
  409. scp->device = sdev;
  410. memset(&cmndinfo, 0, sizeof(cmndinfo));
  411. /* use request field to save the ptr. to completion struct. */
  412. scp->request = (struct request *)&wait;
  413. scp->cmd_len = 12;
  414. scp->cmnd = cmnd;
  415. cmndinfo.priority = IOCTL_PRI;
  416. cmndinfo.internal_cmd_str = gdtcmd;
  417. cmndinfo.internal_command = 1;
  418. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  419. __gdth_queuecommand(ha, scp, &cmndinfo);
  420. wait_for_completion(&wait);
  421. rval = cmndinfo.status;
  422. if (info)
  423. *info = cmndinfo.info;
  424. kfree(scp->sense_buffer);
  425. kfree(scp);
  426. return rval;
  427. }
  428. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  429. int timeout, u32 *info)
  430. {
  431. struct scsi_device *sdev = scsi_get_host_dev(shost);
  432. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  433. scsi_free_host_dev(sdev);
  434. return rval;
  435. }
  436. static void gdth_eval_mapping(u32 size, u32 *cyls, int *heads, int *secs)
  437. {
  438. *cyls = size /HEADS/SECS;
  439. if (*cyls <= MAXCYLS) {
  440. *heads = HEADS;
  441. *secs = SECS;
  442. } else { /* too high for 64*32 */
  443. *cyls = size /MEDHEADS/MEDSECS;
  444. if (*cyls <= MAXCYLS) {
  445. *heads = MEDHEADS;
  446. *secs = MEDSECS;
  447. } else { /* too high for 127*63 */
  448. *cyls = size /BIGHEADS/BIGSECS;
  449. *heads = BIGHEADS;
  450. *secs = BIGSECS;
  451. }
  452. }
  453. }
  454. /* controller search and initialization functions */
  455. #ifdef CONFIG_EISA
  456. static int __init gdth_search_eisa(u16 eisa_adr)
  457. {
  458. u32 id;
  459. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  460. id = inl(eisa_adr+ID0REG);
  461. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  462. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  463. return 0; /* not EISA configured */
  464. return 1;
  465. }
  466. if (id == GDT3_ID) /* GDT3000 */
  467. return 1;
  468. return 0;
  469. }
  470. #endif /* CONFIG_EISA */
  471. #ifdef CONFIG_ISA
  472. static int __init gdth_search_isa(u32 bios_adr)
  473. {
  474. void __iomem *addr;
  475. u32 id;
  476. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  477. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(u32))) != NULL) {
  478. id = readl(addr);
  479. iounmap(addr);
  480. if (id == GDT2_ID) /* GDT2000 */
  481. return 1;
  482. }
  483. return 0;
  484. }
  485. #endif /* CONFIG_ISA */
  486. #ifdef CONFIG_PCI
  487. static bool gdth_search_vortex(u16 device)
  488. {
  489. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  490. return true;
  491. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  492. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  493. return true;
  494. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  495. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  496. return true;
  497. return false;
  498. }
  499. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  500. static int gdth_pci_init_one(struct pci_dev *pdev,
  501. const struct pci_device_id *ent);
  502. static void gdth_pci_remove_one(struct pci_dev *pdev);
  503. static void gdth_remove_one(gdth_ha_str *ha);
  504. /* Vortex only makes RAID controllers.
  505. * We do not really want to specify all 550 ids here, so wildcard match.
  506. */
  507. static const struct pci_device_id gdthtable[] = {
  508. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  509. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  510. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  511. { } /* terminate list */
  512. };
  513. MODULE_DEVICE_TABLE(pci, gdthtable);
  514. static struct pci_driver gdth_pci_driver = {
  515. .name = "gdth",
  516. .id_table = gdthtable,
  517. .probe = gdth_pci_init_one,
  518. .remove = gdth_pci_remove_one,
  519. };
  520. static void __devexit gdth_pci_remove_one(struct pci_dev *pdev)
  521. {
  522. gdth_ha_str *ha = pci_get_drvdata(pdev);
  523. pci_set_drvdata(pdev, NULL);
  524. list_del(&ha->list);
  525. gdth_remove_one(ha);
  526. pci_disable_device(pdev);
  527. }
  528. static int __devinit gdth_pci_init_one(struct pci_dev *pdev,
  529. const struct pci_device_id *ent)
  530. {
  531. u16 vendor = pdev->vendor;
  532. u16 device = pdev->device;
  533. unsigned long base0, base1, base2;
  534. int rc;
  535. gdth_pci_str gdth_pcistr;
  536. gdth_ha_str *ha = NULL;
  537. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  538. gdth_ctr_count, vendor, device));
  539. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  540. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  541. return -ENODEV;
  542. rc = pci_enable_device(pdev);
  543. if (rc)
  544. return rc;
  545. if (gdth_ctr_count >= MAXHA)
  546. return -EBUSY;
  547. /* GDT PCI controller found, resources are already in pdev */
  548. gdth_pcistr.pdev = pdev;
  549. base0 = pci_resource_flags(pdev, 0);
  550. base1 = pci_resource_flags(pdev, 1);
  551. base2 = pci_resource_flags(pdev, 2);
  552. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  553. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  554. if (!(base0 & IORESOURCE_MEM))
  555. return -ENODEV;
  556. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  557. } else { /* GDT6110, GDT6120, .. */
  558. if (!(base0 & IORESOURCE_MEM) ||
  559. !(base2 & IORESOURCE_MEM) ||
  560. !(base1 & IORESOURCE_IO))
  561. return -ENODEV;
  562. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  563. gdth_pcistr.io = pci_resource_start(pdev, 1);
  564. }
  565. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  566. gdth_pcistr.pdev->bus->number,
  567. PCI_SLOT(gdth_pcistr.pdev->devfn),
  568. gdth_pcistr.irq,
  569. gdth_pcistr.dpmem));
  570. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  571. if (rc)
  572. return rc;
  573. return 0;
  574. }
  575. #endif /* CONFIG_PCI */
  576. #ifdef CONFIG_EISA
  577. static int __init gdth_init_eisa(u16 eisa_adr,gdth_ha_str *ha)
  578. {
  579. u32 retries,id;
  580. u8 prot_ver,eisacf,i,irq_found;
  581. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  582. /* disable board interrupts, deinitialize services */
  583. outb(0xff,eisa_adr+EDOORREG);
  584. outb(0x00,eisa_adr+EDENABREG);
  585. outb(0x00,eisa_adr+EINTENABREG);
  586. outb(0xff,eisa_adr+LDOORREG);
  587. retries = INIT_RETRIES;
  588. gdth_delay(20);
  589. while (inb(eisa_adr+EDOORREG) != 0xff) {
  590. if (--retries == 0) {
  591. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  592. return 0;
  593. }
  594. gdth_delay(1);
  595. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  596. }
  597. prot_ver = inb(eisa_adr+MAILBOXREG);
  598. outb(0xff,eisa_adr+EDOORREG);
  599. if (prot_ver != PROTOCOL_VERSION) {
  600. printk("GDT-EISA: Illegal protocol version\n");
  601. return 0;
  602. }
  603. ha->bmic = eisa_adr;
  604. ha->brd_phys = (u32)eisa_adr >> 12;
  605. outl(0,eisa_adr+MAILBOXREG);
  606. outl(0,eisa_adr+MAILBOXREG+4);
  607. outl(0,eisa_adr+MAILBOXREG+8);
  608. outl(0,eisa_adr+MAILBOXREG+12);
  609. /* detect IRQ */
  610. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  611. ha->oem_id = OEM_ID_ICP;
  612. ha->type = GDT_EISA;
  613. ha->stype = id;
  614. outl(1,eisa_adr+MAILBOXREG+8);
  615. outb(0xfe,eisa_adr+LDOORREG);
  616. retries = INIT_RETRIES;
  617. gdth_delay(20);
  618. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  619. if (--retries == 0) {
  620. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  621. return 0;
  622. }
  623. gdth_delay(1);
  624. }
  625. ha->irq = inb(eisa_adr+MAILBOXREG);
  626. outb(0xff,eisa_adr+EDOORREG);
  627. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  628. /* check the result */
  629. if (ha->irq == 0) {
  630. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  631. for (i = 0, irq_found = FALSE;
  632. i < MAXHA && irq[i] != 0xff; ++i) {
  633. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  634. irq_found = TRUE;
  635. break;
  636. }
  637. }
  638. if (irq_found) {
  639. ha->irq = irq[i];
  640. irq[i] = 0;
  641. printk("GDT-EISA: Can not detect controller IRQ,\n");
  642. printk("Use IRQ setting from command line (IRQ = %d)\n",
  643. ha->irq);
  644. } else {
  645. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  646. printk("the controller BIOS or use command line parameters\n");
  647. return 0;
  648. }
  649. }
  650. } else {
  651. eisacf = inb(eisa_adr+EISAREG) & 7;
  652. if (eisacf > 4) /* level triggered */
  653. eisacf -= 4;
  654. ha->irq = gdth_irq_tab[eisacf];
  655. ha->oem_id = OEM_ID_ICP;
  656. ha->type = GDT_EISA;
  657. ha->stype = id;
  658. }
  659. ha->dma64_support = 0;
  660. return 1;
  661. }
  662. #endif /* CONFIG_EISA */
  663. #ifdef CONFIG_ISA
  664. static int __init gdth_init_isa(u32 bios_adr,gdth_ha_str *ha)
  665. {
  666. register gdt2_dpram_str __iomem *dp2_ptr;
  667. int i;
  668. u8 irq_drq,prot_ver;
  669. u32 retries;
  670. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  671. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  672. if (ha->brd == NULL) {
  673. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  674. return 0;
  675. }
  676. dp2_ptr = ha->brd;
  677. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  678. /* reset interface area */
  679. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  680. if (readl(&dp2_ptr->u) != 0) {
  681. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  682. iounmap(ha->brd);
  683. return 0;
  684. }
  685. /* disable board interrupts, read DRQ and IRQ */
  686. writeb(0xff, &dp2_ptr->io.irqdel);
  687. writeb(0x00, &dp2_ptr->io.irqen);
  688. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  689. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  690. irq_drq = readb(&dp2_ptr->io.rq);
  691. for (i=0; i<3; ++i) {
  692. if ((irq_drq & 1)==0)
  693. break;
  694. irq_drq >>= 1;
  695. }
  696. ha->drq = gdth_drq_tab[i];
  697. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  698. for (i=1; i<5; ++i) {
  699. if ((irq_drq & 1)==0)
  700. break;
  701. irq_drq >>= 1;
  702. }
  703. ha->irq = gdth_irq_tab[i];
  704. /* deinitialize services */
  705. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  706. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  707. writeb(0, &dp2_ptr->io.event);
  708. retries = INIT_RETRIES;
  709. gdth_delay(20);
  710. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  711. if (--retries == 0) {
  712. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  713. iounmap(ha->brd);
  714. return 0;
  715. }
  716. gdth_delay(1);
  717. }
  718. prot_ver = (u8)readl(&dp2_ptr->u.ic.S_Info[0]);
  719. writeb(0, &dp2_ptr->u.ic.Status);
  720. writeb(0xff, &dp2_ptr->io.irqdel);
  721. if (prot_ver != PROTOCOL_VERSION) {
  722. printk("GDT-ISA: Illegal protocol version\n");
  723. iounmap(ha->brd);
  724. return 0;
  725. }
  726. ha->oem_id = OEM_ID_ICP;
  727. ha->type = GDT_ISA;
  728. ha->ic_all_size = sizeof(dp2_ptr->u);
  729. ha->stype= GDT2_ID;
  730. ha->brd_phys = bios_adr >> 4;
  731. /* special request to controller BIOS */
  732. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  733. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  734. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  735. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  736. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  737. writeb(0, &dp2_ptr->io.event);
  738. retries = INIT_RETRIES;
  739. gdth_delay(20);
  740. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  741. if (--retries == 0) {
  742. printk("GDT-ISA: Initialization error\n");
  743. iounmap(ha->brd);
  744. return 0;
  745. }
  746. gdth_delay(1);
  747. }
  748. writeb(0, &dp2_ptr->u.ic.Status);
  749. writeb(0xff, &dp2_ptr->io.irqdel);
  750. ha->dma64_support = 0;
  751. return 1;
  752. }
  753. #endif /* CONFIG_ISA */
  754. #ifdef CONFIG_PCI
  755. static int __devinit gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  756. gdth_ha_str *ha)
  757. {
  758. register gdt6_dpram_str __iomem *dp6_ptr;
  759. register gdt6c_dpram_str __iomem *dp6c_ptr;
  760. register gdt6m_dpram_str __iomem *dp6m_ptr;
  761. u32 retries;
  762. u8 prot_ver;
  763. u16 command;
  764. int i, found = FALSE;
  765. TRACE(("gdth_init_pci()\n"));
  766. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  767. ha->oem_id = OEM_ID_INTEL;
  768. else
  769. ha->oem_id = OEM_ID_ICP;
  770. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  771. ha->stype = (u32)pdev->device;
  772. ha->irq = pdev->irq;
  773. ha->pdev = pdev;
  774. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  775. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  776. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  777. if (ha->brd == NULL) {
  778. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  779. return 0;
  780. }
  781. /* check and reset interface area */
  782. dp6_ptr = ha->brd;
  783. writel(DPMEM_MAGIC, &dp6_ptr->u);
  784. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  785. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  786. pcistr->dpmem);
  787. found = FALSE;
  788. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  789. iounmap(ha->brd);
  790. ha->brd = ioremap(i, sizeof(u16));
  791. if (ha->brd == NULL) {
  792. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  793. return 0;
  794. }
  795. if (readw(ha->brd) != 0xffff) {
  796. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  797. continue;
  798. }
  799. iounmap(ha->brd);
  800. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  801. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  802. if (ha->brd == NULL) {
  803. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  804. return 0;
  805. }
  806. dp6_ptr = ha->brd;
  807. writel(DPMEM_MAGIC, &dp6_ptr->u);
  808. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  809. printk("GDT-PCI: Use free address at 0x%x\n", i);
  810. found = TRUE;
  811. break;
  812. }
  813. }
  814. if (!found) {
  815. printk("GDT-PCI: No free address found!\n");
  816. iounmap(ha->brd);
  817. return 0;
  818. }
  819. }
  820. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  821. if (readl(&dp6_ptr->u) != 0) {
  822. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  823. iounmap(ha->brd);
  824. return 0;
  825. }
  826. /* disable board interrupts, deinit services */
  827. writeb(0xff, &dp6_ptr->io.irqdel);
  828. writeb(0x00, &dp6_ptr->io.irqen);
  829. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  830. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  831. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  832. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  833. writeb(0, &dp6_ptr->io.event);
  834. retries = INIT_RETRIES;
  835. gdth_delay(20);
  836. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  837. if (--retries == 0) {
  838. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  839. iounmap(ha->brd);
  840. return 0;
  841. }
  842. gdth_delay(1);
  843. }
  844. prot_ver = (u8)readl(&dp6_ptr->u.ic.S_Info[0]);
  845. writeb(0, &dp6_ptr->u.ic.S_Status);
  846. writeb(0xff, &dp6_ptr->io.irqdel);
  847. if (prot_ver != PROTOCOL_VERSION) {
  848. printk("GDT-PCI: Illegal protocol version\n");
  849. iounmap(ha->brd);
  850. return 0;
  851. }
  852. ha->type = GDT_PCI;
  853. ha->ic_all_size = sizeof(dp6_ptr->u);
  854. /* special command to controller BIOS */
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  857. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  858. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  859. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  860. writeb(0, &dp6_ptr->io.event);
  861. retries = INIT_RETRIES;
  862. gdth_delay(20);
  863. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  864. if (--retries == 0) {
  865. printk("GDT-PCI: Initialization error\n");
  866. iounmap(ha->brd);
  867. return 0;
  868. }
  869. gdth_delay(1);
  870. }
  871. writeb(0, &dp6_ptr->u.ic.S_Status);
  872. writeb(0xff, &dp6_ptr->io.irqdel);
  873. ha->dma64_support = 0;
  874. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  875. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  876. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  877. pcistr->dpmem,ha->irq));
  878. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  879. if (ha->brd == NULL) {
  880. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  881. iounmap(ha->brd);
  882. return 0;
  883. }
  884. /* check and reset interface area */
  885. dp6c_ptr = ha->brd;
  886. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  887. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  888. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  889. pcistr->dpmem);
  890. found = FALSE;
  891. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  892. iounmap(ha->brd);
  893. ha->brd = ioremap(i, sizeof(u16));
  894. if (ha->brd == NULL) {
  895. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  896. return 0;
  897. }
  898. if (readw(ha->brd) != 0xffff) {
  899. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  900. continue;
  901. }
  902. iounmap(ha->brd);
  903. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  904. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  905. if (ha->brd == NULL) {
  906. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  907. return 0;
  908. }
  909. dp6c_ptr = ha->brd;
  910. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  911. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  912. printk("GDT-PCI: Use free address at 0x%x\n", i);
  913. found = TRUE;
  914. break;
  915. }
  916. }
  917. if (!found) {
  918. printk("GDT-PCI: No free address found!\n");
  919. iounmap(ha->brd);
  920. return 0;
  921. }
  922. }
  923. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  924. if (readl(&dp6c_ptr->u) != 0) {
  925. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  926. iounmap(ha->brd);
  927. return 0;
  928. }
  929. /* disable board interrupts, deinit services */
  930. outb(0x00,PTR2USHORT(&ha->plx->control1));
  931. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  932. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  933. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  934. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  935. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  936. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  937. retries = INIT_RETRIES;
  938. gdth_delay(20);
  939. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  940. if (--retries == 0) {
  941. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  942. iounmap(ha->brd);
  943. return 0;
  944. }
  945. gdth_delay(1);
  946. }
  947. prot_ver = (u8)readl(&dp6c_ptr->u.ic.S_Info[0]);
  948. writeb(0, &dp6c_ptr->u.ic.Status);
  949. if (prot_ver != PROTOCOL_VERSION) {
  950. printk("GDT-PCI: Illegal protocol version\n");
  951. iounmap(ha->brd);
  952. return 0;
  953. }
  954. ha->type = GDT_PCINEW;
  955. ha->ic_all_size = sizeof(dp6c_ptr->u);
  956. /* special command to controller BIOS */
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  959. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  960. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  961. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  962. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  963. retries = INIT_RETRIES;
  964. gdth_delay(20);
  965. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  966. if (--retries == 0) {
  967. printk("GDT-PCI: Initialization error\n");
  968. iounmap(ha->brd);
  969. return 0;
  970. }
  971. gdth_delay(1);
  972. }
  973. writeb(0, &dp6c_ptr->u.ic.S_Status);
  974. ha->dma64_support = 0;
  975. } else { /* MPR */
  976. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  977. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  978. if (ha->brd == NULL) {
  979. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  980. return 0;
  981. }
  982. /* manipulate config. space to enable DPMEM, start RP controller */
  983. pci_read_config_word(pdev, PCI_COMMAND, &command);
  984. command |= 6;
  985. pci_write_config_word(pdev, PCI_COMMAND, command);
  986. if (pci_resource_start(pdev, 8) == 1UL)
  987. pci_resource_start(pdev, 8) = 0UL;
  988. i = 0xFEFF0001UL;
  989. pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
  990. gdth_delay(1);
  991. pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
  992. pci_resource_start(pdev, 8));
  993. dp6m_ptr = ha->brd;
  994. /* Ensure that it is safe to access the non HW portions of DPMEM.
  995. * Aditional check needed for Xscale based RAID controllers */
  996. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  997. gdth_delay(1);
  998. /* check and reset interface area */
  999. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1000. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1001. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1002. pcistr->dpmem);
  1003. found = FALSE;
  1004. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1005. iounmap(ha->brd);
  1006. ha->brd = ioremap(i, sizeof(u16));
  1007. if (ha->brd == NULL) {
  1008. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1009. return 0;
  1010. }
  1011. if (readw(ha->brd) != 0xffff) {
  1012. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1013. continue;
  1014. }
  1015. iounmap(ha->brd);
  1016. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1017. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1018. if (ha->brd == NULL) {
  1019. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1020. return 0;
  1021. }
  1022. dp6m_ptr = ha->brd;
  1023. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1024. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1025. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1026. found = TRUE;
  1027. break;
  1028. }
  1029. }
  1030. if (!found) {
  1031. printk("GDT-PCI: No free address found!\n");
  1032. iounmap(ha->brd);
  1033. return 0;
  1034. }
  1035. }
  1036. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1037. /* disable board interrupts, deinit services */
  1038. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1039. &dp6m_ptr->i960r.edoor_en_reg);
  1040. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1041. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1042. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1043. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1044. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1045. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1046. retries = INIT_RETRIES;
  1047. gdth_delay(20);
  1048. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1049. if (--retries == 0) {
  1050. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1051. iounmap(ha->brd);
  1052. return 0;
  1053. }
  1054. gdth_delay(1);
  1055. }
  1056. prot_ver = (u8)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1057. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1058. if (prot_ver != PROTOCOL_VERSION) {
  1059. printk("GDT-PCI: Illegal protocol version\n");
  1060. iounmap(ha->brd);
  1061. return 0;
  1062. }
  1063. ha->type = GDT_PCIMPR;
  1064. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1065. /* special command to controller BIOS */
  1066. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1067. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1068. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1069. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1070. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1071. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1072. retries = INIT_RETRIES;
  1073. gdth_delay(20);
  1074. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1075. if (--retries == 0) {
  1076. printk("GDT-PCI: Initialization error\n");
  1077. iounmap(ha->brd);
  1078. return 0;
  1079. }
  1080. gdth_delay(1);
  1081. }
  1082. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1083. /* read FW version to detect 64-bit DMA support */
  1084. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1085. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1086. retries = INIT_RETRIES;
  1087. gdth_delay(20);
  1088. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1089. if (--retries == 0) {
  1090. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1091. iounmap(ha->brd);
  1092. return 0;
  1093. }
  1094. gdth_delay(1);
  1095. }
  1096. prot_ver = (u8)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1097. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1098. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1099. ha->dma64_support = 0;
  1100. else
  1101. ha->dma64_support = 1;
  1102. }
  1103. return 1;
  1104. }
  1105. #endif /* CONFIG_PCI */
  1106. /* controller protocol functions */
  1107. static void __devinit gdth_enable_int(gdth_ha_str *ha)
  1108. {
  1109. unsigned long flags;
  1110. gdt2_dpram_str __iomem *dp2_ptr;
  1111. gdt6_dpram_str __iomem *dp6_ptr;
  1112. gdt6m_dpram_str __iomem *dp6m_ptr;
  1113. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1114. spin_lock_irqsave(&ha->smp_lock, flags);
  1115. if (ha->type == GDT_EISA) {
  1116. outb(0xff, ha->bmic + EDOORREG);
  1117. outb(0xff, ha->bmic + EDENABREG);
  1118. outb(0x01, ha->bmic + EINTENABREG);
  1119. } else if (ha->type == GDT_ISA) {
  1120. dp2_ptr = ha->brd;
  1121. writeb(1, &dp2_ptr->io.irqdel);
  1122. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1123. writeb(1, &dp2_ptr->io.irqen);
  1124. } else if (ha->type == GDT_PCI) {
  1125. dp6_ptr = ha->brd;
  1126. writeb(1, &dp6_ptr->io.irqdel);
  1127. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1128. writeb(1, &dp6_ptr->io.irqen);
  1129. } else if (ha->type == GDT_PCINEW) {
  1130. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1131. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1132. } else if (ha->type == GDT_PCIMPR) {
  1133. dp6m_ptr = ha->brd;
  1134. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1135. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1136. &dp6m_ptr->i960r.edoor_en_reg);
  1137. }
  1138. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1139. }
  1140. /* return IStatus if interrupt was from this card else 0 */
  1141. static u8 gdth_get_status(gdth_ha_str *ha)
  1142. {
  1143. u8 IStatus = 0;
  1144. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1145. if (ha->type == GDT_EISA)
  1146. IStatus = inb((u16)ha->bmic + EDOORREG);
  1147. else if (ha->type == GDT_ISA)
  1148. IStatus =
  1149. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1150. else if (ha->type == GDT_PCI)
  1151. IStatus =
  1152. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1153. else if (ha->type == GDT_PCINEW)
  1154. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1155. else if (ha->type == GDT_PCIMPR)
  1156. IStatus =
  1157. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1158. return IStatus;
  1159. }
  1160. static int gdth_test_busy(gdth_ha_str *ha)
  1161. {
  1162. register int gdtsema0 = 0;
  1163. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1164. if (ha->type == GDT_EISA)
  1165. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1166. else if (ha->type == GDT_ISA)
  1167. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1168. else if (ha->type == GDT_PCI)
  1169. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1170. else if (ha->type == GDT_PCINEW)
  1171. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1172. else if (ha->type == GDT_PCIMPR)
  1173. gdtsema0 =
  1174. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1175. return (gdtsema0 & 1);
  1176. }
  1177. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1178. {
  1179. int i;
  1180. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1181. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1182. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1183. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1184. ha->cmd_tab[i].service = ha->pccb->Service;
  1185. ha->pccb->CommandIndex = (u32)i+2;
  1186. return (i+2);
  1187. }
  1188. }
  1189. return 0;
  1190. }
  1191. static void gdth_set_sema0(gdth_ha_str *ha)
  1192. {
  1193. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1194. if (ha->type == GDT_EISA) {
  1195. outb(1, ha->bmic + SEMA0REG);
  1196. } else if (ha->type == GDT_ISA) {
  1197. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1198. } else if (ha->type == GDT_PCI) {
  1199. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1200. } else if (ha->type == GDT_PCINEW) {
  1201. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1202. } else if (ha->type == GDT_PCIMPR) {
  1203. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1204. }
  1205. }
  1206. static void gdth_copy_command(gdth_ha_str *ha)
  1207. {
  1208. register gdth_cmd_str *cmd_ptr;
  1209. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1210. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1211. gdt6_dpram_str __iomem *dp6_ptr;
  1212. gdt2_dpram_str __iomem *dp2_ptr;
  1213. u16 cp_count,dp_offset,cmd_no;
  1214. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1215. cp_count = ha->cmd_len;
  1216. dp_offset= ha->cmd_offs_dpmem;
  1217. cmd_no = ha->cmd_cnt;
  1218. cmd_ptr = ha->pccb;
  1219. ++ha->cmd_cnt;
  1220. if (ha->type == GDT_EISA)
  1221. return; /* no DPMEM, no copy */
  1222. /* set cpcount dword aligned */
  1223. if (cp_count & 3)
  1224. cp_count += (4 - (cp_count & 3));
  1225. ha->cmd_offs_dpmem += cp_count;
  1226. /* set offset and service, copy command to DPMEM */
  1227. if (ha->type == GDT_ISA) {
  1228. dp2_ptr = ha->brd;
  1229. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1230. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1231. writew((u16)cmd_ptr->Service,
  1232. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1233. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1234. } else if (ha->type == GDT_PCI) {
  1235. dp6_ptr = ha->brd;
  1236. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1237. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1238. writew((u16)cmd_ptr->Service,
  1239. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1240. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1241. } else if (ha->type == GDT_PCINEW) {
  1242. dp6c_ptr = ha->brd;
  1243. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1244. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1245. writew((u16)cmd_ptr->Service,
  1246. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1247. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1248. } else if (ha->type == GDT_PCIMPR) {
  1249. dp6m_ptr = ha->brd;
  1250. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1251. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1252. writew((u16)cmd_ptr->Service,
  1253. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1254. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1255. }
  1256. }
  1257. static void gdth_release_event(gdth_ha_str *ha)
  1258. {
  1259. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1260. #ifdef GDTH_STATISTICS
  1261. {
  1262. u32 i,j;
  1263. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1264. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1265. ++i;
  1266. }
  1267. if (max_index < i) {
  1268. max_index = i;
  1269. TRACE3(("GDT: max_index = %d\n",(u16)i));
  1270. }
  1271. }
  1272. #endif
  1273. if (ha->pccb->OpCode == GDT_INIT)
  1274. ha->pccb->Service |= 0x80;
  1275. if (ha->type == GDT_EISA) {
  1276. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1277. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1278. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1279. } else if (ha->type == GDT_ISA) {
  1280. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1281. } else if (ha->type == GDT_PCI) {
  1282. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1283. } else if (ha->type == GDT_PCINEW) {
  1284. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1285. } else if (ha->type == GDT_PCIMPR) {
  1286. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1287. }
  1288. }
  1289. static int gdth_wait(gdth_ha_str *ha, int index, u32 time)
  1290. {
  1291. int answer_found = FALSE;
  1292. int wait_index = 0;
  1293. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1294. if (index == 0)
  1295. return 1; /* no wait required */
  1296. do {
  1297. __gdth_interrupt(ha, true, &wait_index);
  1298. if (wait_index == index) {
  1299. answer_found = TRUE;
  1300. break;
  1301. }
  1302. gdth_delay(1);
  1303. } while (--time);
  1304. while (gdth_test_busy(ha))
  1305. gdth_delay(0);
  1306. return (answer_found);
  1307. }
  1308. static int gdth_internal_cmd(gdth_ha_str *ha, u8 service, u16 opcode,
  1309. u32 p1, u64 p2, u64 p3)
  1310. {
  1311. register gdth_cmd_str *cmd_ptr;
  1312. int retries,index;
  1313. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1314. cmd_ptr = ha->pccb;
  1315. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1316. /* make command */
  1317. for (retries = INIT_RETRIES;;) {
  1318. cmd_ptr->Service = service;
  1319. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1320. if (!(index=gdth_get_cmd_index(ha))) {
  1321. TRACE(("GDT: No free command index found\n"));
  1322. return 0;
  1323. }
  1324. gdth_set_sema0(ha);
  1325. cmd_ptr->OpCode = opcode;
  1326. cmd_ptr->BoardNode = LOCALBOARD;
  1327. if (service == CACHESERVICE) {
  1328. if (opcode == GDT_IOCTL) {
  1329. cmd_ptr->u.ioctl.subfunc = p1;
  1330. cmd_ptr->u.ioctl.channel = (u32)p2;
  1331. cmd_ptr->u.ioctl.param_size = (u16)p3;
  1332. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1333. } else {
  1334. if (ha->cache_feat & GDT_64BIT) {
  1335. cmd_ptr->u.cache64.DeviceNo = (u16)p1;
  1336. cmd_ptr->u.cache64.BlockNo = p2;
  1337. } else {
  1338. cmd_ptr->u.cache.DeviceNo = (u16)p1;
  1339. cmd_ptr->u.cache.BlockNo = (u32)p2;
  1340. }
  1341. }
  1342. } else if (service == SCSIRAWSERVICE) {
  1343. if (ha->raw_feat & GDT_64BIT) {
  1344. cmd_ptr->u.raw64.direction = p1;
  1345. cmd_ptr->u.raw64.bus = (u8)p2;
  1346. cmd_ptr->u.raw64.target = (u8)p3;
  1347. cmd_ptr->u.raw64.lun = (u8)(p3 >> 8);
  1348. } else {
  1349. cmd_ptr->u.raw.direction = p1;
  1350. cmd_ptr->u.raw.bus = (u8)p2;
  1351. cmd_ptr->u.raw.target = (u8)p3;
  1352. cmd_ptr->u.raw.lun = (u8)(p3 >> 8);
  1353. }
  1354. } else if (service == SCREENSERVICE) {
  1355. if (opcode == GDT_REALTIME) {
  1356. *(u32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1357. *(u32 *)&cmd_ptr->u.screen.su.data[4] = (u32)p2;
  1358. *(u32 *)&cmd_ptr->u.screen.su.data[8] = (u32)p3;
  1359. }
  1360. }
  1361. ha->cmd_len = sizeof(gdth_cmd_str);
  1362. ha->cmd_offs_dpmem = 0;
  1363. ha->cmd_cnt = 0;
  1364. gdth_copy_command(ha);
  1365. gdth_release_event(ha);
  1366. gdth_delay(20);
  1367. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1368. printk("GDT: Initialization error (timeout service %d)\n",service);
  1369. return 0;
  1370. }
  1371. if (ha->status != S_BSY || --retries == 0)
  1372. break;
  1373. gdth_delay(1);
  1374. }
  1375. return (ha->status != S_OK ? 0:1);
  1376. }
  1377. /* search for devices */
  1378. static int __devinit gdth_search_drives(gdth_ha_str *ha)
  1379. {
  1380. u16 cdev_cnt, i;
  1381. int ok;
  1382. u32 bus_no, drv_cnt, drv_no, j;
  1383. gdth_getch_str *chn;
  1384. gdth_drlist_str *drl;
  1385. gdth_iochan_str *ioc;
  1386. gdth_raw_iochan_str *iocr;
  1387. gdth_arcdl_str *alst;
  1388. gdth_alist_str *alst2;
  1389. gdth_oem_str_ioctl *oemstr;
  1390. #ifdef INT_COAL
  1391. gdth_perf_modes *pmod;
  1392. #endif
  1393. #ifdef GDTH_RTC
  1394. u8 rtc[12];
  1395. unsigned long flags;
  1396. #endif
  1397. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1398. ok = 0;
  1399. /* initialize controller services, at first: screen service */
  1400. ha->screen_feat = 0;
  1401. if (!force_dma32) {
  1402. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1403. if (ok)
  1404. ha->screen_feat = GDT_64BIT;
  1405. }
  1406. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1407. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1408. if (!ok) {
  1409. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1410. ha->hanum, ha->status);
  1411. return 0;
  1412. }
  1413. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1414. #ifdef GDTH_RTC
  1415. /* read realtime clock info, send to controller */
  1416. /* 1. wait for the falling edge of update flag */
  1417. spin_lock_irqsave(&rtc_lock, flags);
  1418. for (j = 0; j < 1000000; ++j)
  1419. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1420. break;
  1421. for (j = 0; j < 1000000; ++j)
  1422. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1423. break;
  1424. /* 2. read info */
  1425. do {
  1426. for (j = 0; j < 12; ++j)
  1427. rtc[j] = CMOS_READ(j);
  1428. } while (rtc[0] != CMOS_READ(0));
  1429. spin_unlock_irqrestore(&rtc_lock, flags);
  1430. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(u32 *)&rtc[0],
  1431. *(u32 *)&rtc[4], *(u32 *)&rtc[8]));
  1432. /* 3. send to controller firmware */
  1433. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(u32 *)&rtc[0],
  1434. *(u32 *)&rtc[4], *(u32 *)&rtc[8]);
  1435. #endif
  1436. /* unfreeze all IOs */
  1437. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1438. /* initialize cache service */
  1439. ha->cache_feat = 0;
  1440. if (!force_dma32) {
  1441. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1442. 0, 0);
  1443. if (ok)
  1444. ha->cache_feat = GDT_64BIT;
  1445. }
  1446. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1447. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1448. if (!ok) {
  1449. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1450. ha->hanum, ha->status);
  1451. return 0;
  1452. }
  1453. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1454. cdev_cnt = (u16)ha->info;
  1455. ha->fw_vers = ha->service;
  1456. #ifdef INT_COAL
  1457. if (ha->type == GDT_PCIMPR) {
  1458. /* set perf. modes */
  1459. pmod = (gdth_perf_modes *)ha->pscratch;
  1460. pmod->version = 1;
  1461. pmod->st_mode = 1; /* enable one status buffer */
  1462. *((u64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1463. pmod->st_buff_indx1 = COALINDEX;
  1464. pmod->st_buff_addr2 = 0;
  1465. pmod->st_buff_u_addr2 = 0;
  1466. pmod->st_buff_indx2 = 0;
  1467. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1468. pmod->cmd_mode = 0; // disable all cmd buffers
  1469. pmod->cmd_buff_addr1 = 0;
  1470. pmod->cmd_buff_u_addr1 = 0;
  1471. pmod->cmd_buff_indx1 = 0;
  1472. pmod->cmd_buff_addr2 = 0;
  1473. pmod->cmd_buff_u_addr2 = 0;
  1474. pmod->cmd_buff_indx2 = 0;
  1475. pmod->cmd_buff_size = 0;
  1476. pmod->reserved1 = 0;
  1477. pmod->reserved2 = 0;
  1478. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1479. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1480. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1481. }
  1482. }
  1483. #endif
  1484. /* detect number of buses - try new IOCTL */
  1485. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1486. iocr->hdr.version = 0xffffffff;
  1487. iocr->hdr.list_entries = MAXBUS;
  1488. iocr->hdr.first_chan = 0;
  1489. iocr->hdr.last_chan = MAXBUS-1;
  1490. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1491. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1492. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1493. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1494. ha->bus_cnt = iocr->hdr.chan_count;
  1495. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1496. if (iocr->list[bus_no].proc_id < MAXID)
  1497. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1498. else
  1499. ha->bus_id[bus_no] = 0xff;
  1500. }
  1501. } else {
  1502. /* old method */
  1503. chn = (gdth_getch_str *)ha->pscratch;
  1504. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1505. chn->channel_no = bus_no;
  1506. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1507. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1508. IO_CHANNEL | INVALID_CHANNEL,
  1509. sizeof(gdth_getch_str))) {
  1510. if (bus_no == 0) {
  1511. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1512. ha->hanum, ha->status);
  1513. return 0;
  1514. }
  1515. break;
  1516. }
  1517. if (chn->siop_id < MAXID)
  1518. ha->bus_id[bus_no] = chn->siop_id;
  1519. else
  1520. ha->bus_id[bus_no] = 0xff;
  1521. }
  1522. ha->bus_cnt = (u8)bus_no;
  1523. }
  1524. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1525. /* read cache configuration */
  1526. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1527. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1528. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1529. ha->hanum, ha->status);
  1530. return 0;
  1531. }
  1532. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1533. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1534. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1535. ha->cpar.write_back,ha->cpar.block_size));
  1536. /* read board info and features */
  1537. ha->more_proc = FALSE;
  1538. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1539. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1540. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1541. sizeof(gdth_binfo_str));
  1542. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1543. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1544. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1545. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1546. ha->more_proc = TRUE;
  1547. }
  1548. } else {
  1549. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1550. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1551. }
  1552. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1553. /* read more informations */
  1554. if (ha->more_proc) {
  1555. /* physical drives, channel addresses */
  1556. ioc = (gdth_iochan_str *)ha->pscratch;
  1557. ioc->hdr.version = 0xffffffff;
  1558. ioc->hdr.list_entries = MAXBUS;
  1559. ioc->hdr.first_chan = 0;
  1560. ioc->hdr.last_chan = MAXBUS-1;
  1561. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1562. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1563. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1564. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1565. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1566. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1567. }
  1568. } else {
  1569. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1570. ha->raw[bus_no].address = IO_CHANNEL;
  1571. ha->raw[bus_no].local_no = bus_no;
  1572. }
  1573. }
  1574. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1575. chn = (gdth_getch_str *)ha->pscratch;
  1576. chn->channel_no = ha->raw[bus_no].local_no;
  1577. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1578. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1579. ha->raw[bus_no].address | INVALID_CHANNEL,
  1580. sizeof(gdth_getch_str))) {
  1581. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1582. TRACE2(("Channel %d: %d phys. drives\n",
  1583. bus_no,chn->drive_cnt));
  1584. }
  1585. if (ha->raw[bus_no].pdev_cnt > 0) {
  1586. drl = (gdth_drlist_str *)ha->pscratch;
  1587. drl->sc_no = ha->raw[bus_no].local_no;
  1588. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1589. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1590. SCSI_DR_LIST | L_CTRL_PATTERN,
  1591. ha->raw[bus_no].address | INVALID_CHANNEL,
  1592. sizeof(gdth_drlist_str))) {
  1593. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1594. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1595. } else {
  1596. ha->raw[bus_no].pdev_cnt = 0;
  1597. }
  1598. }
  1599. }
  1600. /* logical drives */
  1601. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1602. INVALID_CHANNEL,sizeof(u32))) {
  1603. drv_cnt = *(u32 *)ha->pscratch;
  1604. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1605. INVALID_CHANNEL,drv_cnt * sizeof(u32))) {
  1606. for (j = 0; j < drv_cnt; ++j) {
  1607. drv_no = ((u32 *)ha->pscratch)[j];
  1608. if (drv_no < MAX_LDRIVES) {
  1609. ha->hdr[drv_no].is_logdrv = TRUE;
  1610. TRACE2(("Drive %d is log. drive\n",drv_no));
  1611. }
  1612. }
  1613. }
  1614. alst = (gdth_arcdl_str *)ha->pscratch;
  1615. alst->entries_avail = MAX_LDRIVES;
  1616. alst->first_entry = 0;
  1617. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1618. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1619. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1620. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1621. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1622. for (j = 0; j < alst->entries_init; ++j) {
  1623. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1624. ha->hdr[j].is_master = alst->list[j].is_master;
  1625. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1626. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1627. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1628. }
  1629. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1630. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1631. 0, 35 * sizeof(gdth_alist_str))) {
  1632. for (j = 0; j < 35; ++j) {
  1633. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1634. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1635. ha->hdr[j].is_master = alst2->is_master;
  1636. ha->hdr[j].is_parity = alst2->is_parity;
  1637. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1638. ha->hdr[j].master_no = alst2->cd_handle;
  1639. }
  1640. }
  1641. }
  1642. }
  1643. /* initialize raw service */
  1644. ha->raw_feat = 0;
  1645. if (!force_dma32) {
  1646. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1647. if (ok)
  1648. ha->raw_feat = GDT_64BIT;
  1649. }
  1650. if (force_dma32 || (!ok && ha->status == (u16)S_NOFUNC))
  1651. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1652. if (!ok) {
  1653. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1654. ha->hanum, ha->status);
  1655. return 0;
  1656. }
  1657. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1658. /* set/get features raw service (scatter/gather) */
  1659. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1660. 0, 0)) {
  1661. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1662. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1663. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1664. ha->info));
  1665. ha->raw_feat |= (u16)ha->info;
  1666. }
  1667. }
  1668. /* set/get features cache service (equal to raw service) */
  1669. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1670. SCATTER_GATHER,0)) {
  1671. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1672. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1673. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1674. ha->info));
  1675. ha->cache_feat |= (u16)ha->info;
  1676. }
  1677. }
  1678. /* reserve drives for raw service */
  1679. if (reserve_mode != 0) {
  1680. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1681. reserve_mode == 1 ? 1 : 3, 0, 0);
  1682. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1683. ha->status));
  1684. }
  1685. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1686. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1687. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1688. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1689. reserve_list[i], reserve_list[i+1],
  1690. reserve_list[i+2], reserve_list[i+3]));
  1691. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1692. reserve_list[i+1], reserve_list[i+2] |
  1693. (reserve_list[i+3] << 8))) {
  1694. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1695. ha->hanum, ha->status);
  1696. }
  1697. }
  1698. }
  1699. /* Determine OEM string using IOCTL */
  1700. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1701. oemstr->params.ctl_version = 0x01;
  1702. oemstr->params.buffer_size = sizeof(oemstr->text);
  1703. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1704. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1705. sizeof(gdth_oem_str_ioctl))) {
  1706. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1707. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1708. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1709. /* Save the Host Drive inquiry data */
  1710. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1711. sizeof(ha->oem_name));
  1712. } else {
  1713. /* Old method, based on PCI ID */
  1714. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1715. printk("GDT-HA %d: Name: %s\n",
  1716. ha->hanum, ha->binfo.type_string);
  1717. if (ha->oem_id == OEM_ID_INTEL)
  1718. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1719. else
  1720. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1721. }
  1722. /* scanning for host drives */
  1723. for (i = 0; i < cdev_cnt; ++i)
  1724. gdth_analyse_hdrive(ha, i);
  1725. TRACE(("gdth_search_drives() OK\n"));
  1726. return 1;
  1727. }
  1728. static int gdth_analyse_hdrive(gdth_ha_str *ha, u16 hdrive)
  1729. {
  1730. u32 drv_cyls;
  1731. int drv_hds, drv_secs;
  1732. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1733. if (hdrive >= MAX_HDRIVES)
  1734. return 0;
  1735. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1736. return 0;
  1737. ha->hdr[hdrive].present = TRUE;
  1738. ha->hdr[hdrive].size = ha->info;
  1739. /* evaluate mapping (sectors per head, heads per cylinder) */
  1740. ha->hdr[hdrive].size &= ~SECS32;
  1741. if (ha->info2 == 0) {
  1742. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1743. } else {
  1744. drv_hds = ha->info2 & 0xff;
  1745. drv_secs = (ha->info2 >> 8) & 0xff;
  1746. drv_cyls = (u32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1747. }
  1748. ha->hdr[hdrive].heads = (u8)drv_hds;
  1749. ha->hdr[hdrive].secs = (u8)drv_secs;
  1750. /* round size */
  1751. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1752. if (ha->cache_feat & GDT_64BIT) {
  1753. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1754. && ha->info2 != 0) {
  1755. ha->hdr[hdrive].size = ((u64)ha->info2 << 32) | ha->info;
  1756. }
  1757. }
  1758. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1759. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1760. /* get informations about device */
  1761. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1762. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1763. hdrive,ha->info));
  1764. ha->hdr[hdrive].devtype = (u16)ha->info;
  1765. }
  1766. /* cluster info */
  1767. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1768. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1769. hdrive,ha->info));
  1770. if (!shared_access)
  1771. ha->hdr[hdrive].cluster_type = (u8)ha->info;
  1772. }
  1773. /* R/W attributes */
  1774. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1775. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1776. hdrive,ha->info));
  1777. ha->hdr[hdrive].rw_attribs = (u8)ha->info;
  1778. }
  1779. return 1;
  1780. }
  1781. /* command queueing/sending functions */
  1782. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 priority)
  1783. {
  1784. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1785. register Scsi_Cmnd *pscp;
  1786. register Scsi_Cmnd *nscp;
  1787. unsigned long flags;
  1788. TRACE(("gdth_putq() priority %d\n",priority));
  1789. spin_lock_irqsave(&ha->smp_lock, flags);
  1790. if (!cmndinfo->internal_command)
  1791. cmndinfo->priority = priority;
  1792. if (ha->req_first==NULL) {
  1793. ha->req_first = scp; /* queue was empty */
  1794. scp->SCp.ptr = NULL;
  1795. } else { /* queue not empty */
  1796. pscp = ha->req_first;
  1797. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1798. /* priority: 0-highest,..,0xff-lowest */
  1799. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1800. pscp = nscp;
  1801. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1802. }
  1803. pscp->SCp.ptr = (char *)scp;
  1804. scp->SCp.ptr = (char *)nscp;
  1805. }
  1806. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1807. #ifdef GDTH_STATISTICS
  1808. flags = 0;
  1809. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1810. ++flags;
  1811. if (max_rq < flags) {
  1812. max_rq = flags;
  1813. TRACE3(("GDT: max_rq = %d\n",(u16)max_rq));
  1814. }
  1815. #endif
  1816. }
  1817. static void gdth_next(gdth_ha_str *ha)
  1818. {
  1819. register Scsi_Cmnd *pscp;
  1820. register Scsi_Cmnd *nscp;
  1821. u8 b, t, l, firsttime;
  1822. u8 this_cmd, next_cmd;
  1823. unsigned long flags = 0;
  1824. int cmd_index;
  1825. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1826. if (!gdth_polling)
  1827. spin_lock_irqsave(&ha->smp_lock, flags);
  1828. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1829. this_cmd = firsttime = TRUE;
  1830. next_cmd = gdth_polling ? FALSE:TRUE;
  1831. cmd_index = 0;
  1832. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1833. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1834. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1835. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1836. if (!nscp_cmndinfo->internal_command) {
  1837. b = nscp->device->channel;
  1838. t = nscp->device->id;
  1839. l = nscp->device->lun;
  1840. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1841. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1842. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1843. continue;
  1844. }
  1845. } else
  1846. b = t = l = 0;
  1847. if (firsttime) {
  1848. if (gdth_test_busy(ha)) { /* controller busy ? */
  1849. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1850. if (!gdth_polling) {
  1851. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1852. return;
  1853. }
  1854. while (gdth_test_busy(ha))
  1855. gdth_delay(1);
  1856. }
  1857. firsttime = FALSE;
  1858. }
  1859. if (!nscp_cmndinfo->internal_command) {
  1860. if (nscp_cmndinfo->phase == -1) {
  1861. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1862. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1863. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1864. b, t, l));
  1865. /* TEST_UNIT_READY -> set scan mode */
  1866. if ((ha->scan_mode & 0x0f) == 0) {
  1867. if (b == 0 && t == 0 && l == 0) {
  1868. ha->scan_mode |= 1;
  1869. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1870. }
  1871. } else if ((ha->scan_mode & 0x0f) == 1) {
  1872. if (b == 0 && ((t == 0 && l == 1) ||
  1873. (t == 1 && l == 0))) {
  1874. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1875. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1876. | SCSIRAWSERVICE;
  1877. ha->scan_mode = 0x12;
  1878. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1879. ha->scan_mode));
  1880. } else {
  1881. ha->scan_mode &= 0x10;
  1882. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1883. }
  1884. } else if (ha->scan_mode == 0x12) {
  1885. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1886. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1887. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1888. ha->scan_mode &= 0x10;
  1889. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1890. ha->scan_mode));
  1891. }
  1892. }
  1893. }
  1894. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1895. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1896. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1897. /* always GDT_CLUST_INFO! */
  1898. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1899. }
  1900. }
  1901. }
  1902. if (nscp_cmndinfo->OpCode != -1) {
  1903. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1904. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1905. this_cmd = FALSE;
  1906. next_cmd = FALSE;
  1907. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1908. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1909. this_cmd = FALSE;
  1910. next_cmd = FALSE;
  1911. } else {
  1912. memset((char*)nscp->sense_buffer,0,16);
  1913. nscp->sense_buffer[0] = 0x70;
  1914. nscp->sense_buffer[2] = NOT_READY;
  1915. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1916. if (!nscp_cmndinfo->wait_for_completion)
  1917. nscp_cmndinfo->wait_for_completion++;
  1918. else
  1919. gdth_scsi_done(nscp);
  1920. }
  1921. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1922. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1923. this_cmd = FALSE;
  1924. next_cmd = FALSE;
  1925. } else if (b != ha->virt_bus) {
  1926. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1927. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1928. this_cmd = FALSE;
  1929. else
  1930. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1931. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1932. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1933. nscp->cmnd[0], b, t, l));
  1934. nscp->result = DID_BAD_TARGET << 16;
  1935. if (!nscp_cmndinfo->wait_for_completion)
  1936. nscp_cmndinfo->wait_for_completion++;
  1937. else
  1938. gdth_scsi_done(nscp);
  1939. } else {
  1940. switch (nscp->cmnd[0]) {
  1941. case TEST_UNIT_READY:
  1942. case INQUIRY:
  1943. case REQUEST_SENSE:
  1944. case READ_CAPACITY:
  1945. case VERIFY:
  1946. case START_STOP:
  1947. case MODE_SENSE:
  1948. case SERVICE_ACTION_IN:
  1949. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1950. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1951. nscp->cmnd[4],nscp->cmnd[5]));
  1952. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1953. /* return UNIT_ATTENTION */
  1954. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1955. nscp->cmnd[0], t));
  1956. ha->hdr[t].media_changed = FALSE;
  1957. memset((char*)nscp->sense_buffer,0,16);
  1958. nscp->sense_buffer[0] = 0x70;
  1959. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1960. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1961. if (!nscp_cmndinfo->wait_for_completion)
  1962. nscp_cmndinfo->wait_for_completion++;
  1963. else
  1964. gdth_scsi_done(nscp);
  1965. } else if (gdth_internal_cache_cmd(ha, nscp))
  1966. gdth_scsi_done(nscp);
  1967. break;
  1968. case ALLOW_MEDIUM_REMOVAL:
  1969. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1970. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1971. nscp->cmnd[4],nscp->cmnd[5]));
  1972. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1973. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1974. nscp->result = DID_OK << 16;
  1975. nscp->sense_buffer[0] = 0;
  1976. if (!nscp_cmndinfo->wait_for_completion)
  1977. nscp_cmndinfo->wait_for_completion++;
  1978. else
  1979. gdth_scsi_done(nscp);
  1980. } else {
  1981. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1982. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1983. nscp->cmnd[4],nscp->cmnd[3]));
  1984. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1985. this_cmd = FALSE;
  1986. }
  1987. break;
  1988. case RESERVE:
  1989. case RELEASE:
  1990. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  1991. "RESERVE" : "RELEASE"));
  1992. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1993. this_cmd = FALSE;
  1994. break;
  1995. case READ_6:
  1996. case WRITE_6:
  1997. case READ_10:
  1998. case WRITE_10:
  1999. case READ_16:
  2000. case WRITE_16:
  2001. if (ha->hdr[t].media_changed) {
  2002. /* return UNIT_ATTENTION */
  2003. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2004. nscp->cmnd[0], t));
  2005. ha->hdr[t].media_changed = FALSE;
  2006. memset((char*)nscp->sense_buffer,0,16);
  2007. nscp->sense_buffer[0] = 0x70;
  2008. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2009. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2010. if (!nscp_cmndinfo->wait_for_completion)
  2011. nscp_cmndinfo->wait_for_completion++;
  2012. else
  2013. gdth_scsi_done(nscp);
  2014. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2015. this_cmd = FALSE;
  2016. break;
  2017. default:
  2018. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2019. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2020. nscp->cmnd[4],nscp->cmnd[5]));
  2021. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2022. ha->hanum, nscp->cmnd[0]);
  2023. nscp->result = DID_ABORT << 16;
  2024. if (!nscp_cmndinfo->wait_for_completion)
  2025. nscp_cmndinfo->wait_for_completion++;
  2026. else
  2027. gdth_scsi_done(nscp);
  2028. break;
  2029. }
  2030. }
  2031. if (!this_cmd)
  2032. break;
  2033. if (nscp == ha->req_first)
  2034. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2035. else
  2036. pscp->SCp.ptr = nscp->SCp.ptr;
  2037. if (!next_cmd)
  2038. break;
  2039. }
  2040. if (ha->cmd_cnt > 0) {
  2041. gdth_release_event(ha);
  2042. }
  2043. if (!gdth_polling)
  2044. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2045. if (gdth_polling && ha->cmd_cnt > 0) {
  2046. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2047. printk("GDT-HA %d: Command %d timed out !\n",
  2048. ha->hanum, cmd_index);
  2049. }
  2050. }
  2051. /*
  2052. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2053. * buffers, kmap_atomic() as needed.
  2054. */
  2055. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2056. char *buffer, u16 count)
  2057. {
  2058. u16 cpcount,i, max_sg = scsi_sg_count(scp);
  2059. u16 cpsum,cpnow;
  2060. struct scatterlist *sl;
  2061. char *address;
  2062. cpcount = min_t(u16, count, scsi_bufflen(scp));
  2063. if (cpcount) {
  2064. cpsum=0;
  2065. scsi_for_each_sg(scp, sl, max_sg, i) {
  2066. unsigned long flags;
  2067. cpnow = (u16)sl->length;
  2068. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2069. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2070. if (cpsum+cpnow > cpcount)
  2071. cpnow = cpcount - cpsum;
  2072. cpsum += cpnow;
  2073. if (!sg_page(sl)) {
  2074. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2075. ha->hanum);
  2076. return;
  2077. }
  2078. local_irq_save(flags);
  2079. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2080. memcpy(address, buffer, cpnow);
  2081. flush_dcache_page(sg_page(sl));
  2082. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2083. local_irq_restore(flags);
  2084. if (cpsum == cpcount)
  2085. break;
  2086. buffer += cpnow;
  2087. }
  2088. } else if (count) {
  2089. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2090. ha->hanum);
  2091. WARN_ON(1);
  2092. }
  2093. }
  2094. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2095. {
  2096. u8 t;
  2097. gdth_inq_data inq;
  2098. gdth_rdcap_data rdc;
  2099. gdth_sense_data sd;
  2100. gdth_modep_data mpd;
  2101. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2102. t = scp->device->id;
  2103. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2104. scp->cmnd[0],t));
  2105. scp->result = DID_OK << 16;
  2106. scp->sense_buffer[0] = 0;
  2107. switch (scp->cmnd[0]) {
  2108. case TEST_UNIT_READY:
  2109. case VERIFY:
  2110. case START_STOP:
  2111. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2112. break;
  2113. case INQUIRY:
  2114. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2115. t,ha->hdr[t].devtype));
  2116. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2117. /* you can here set all disks to removable, if you want to do
  2118. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2119. inq.modif_rmb = 0x00;
  2120. if ((ha->hdr[t].devtype & 1) ||
  2121. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2122. inq.modif_rmb = 0x80;
  2123. inq.version = 2;
  2124. inq.resp_aenc = 2;
  2125. inq.add_length= 32;
  2126. strcpy(inq.vendor,ha->oem_name);
  2127. sprintf(inq.product,"Host Drive #%02d",t);
  2128. strcpy(inq.revision," ");
  2129. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2130. break;
  2131. case REQUEST_SENSE:
  2132. TRACE2(("Request sense hdrive %d\n",t));
  2133. sd.errorcode = 0x70;
  2134. sd.segno = 0x00;
  2135. sd.key = NO_SENSE;
  2136. sd.info = 0;
  2137. sd.add_length= 0;
  2138. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2139. break;
  2140. case MODE_SENSE:
  2141. TRACE2(("Mode sense hdrive %d\n",t));
  2142. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2143. mpd.hd.data_length = sizeof(gdth_modep_data);
  2144. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2145. mpd.hd.bd_length = sizeof(mpd.bd);
  2146. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2147. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2148. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2149. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2150. break;
  2151. case READ_CAPACITY:
  2152. TRACE2(("Read capacity hdrive %d\n",t));
  2153. if (ha->hdr[t].size > (u64)0xffffffff)
  2154. rdc.last_block_no = 0xffffffff;
  2155. else
  2156. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2157. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2158. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2159. break;
  2160. case SERVICE_ACTION_IN:
  2161. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2162. (ha->cache_feat & GDT_64BIT)) {
  2163. gdth_rdcap16_data rdc16;
  2164. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2165. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2166. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2167. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2168. sizeof(gdth_rdcap16_data));
  2169. } else {
  2170. scp->result = DID_ABORT << 16;
  2171. }
  2172. break;
  2173. default:
  2174. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2175. break;
  2176. }
  2177. if (!cmndinfo->wait_for_completion)
  2178. cmndinfo->wait_for_completion++;
  2179. else
  2180. return 1;
  2181. return 0;
  2182. }
  2183. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u16 hdrive)
  2184. {
  2185. register gdth_cmd_str *cmdp;
  2186. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2187. u32 cnt, blockcnt;
  2188. u64 no, blockno;
  2189. int i, cmd_index, read_write, sgcnt, mode64;
  2190. cmdp = ha->pccb;
  2191. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2192. scp->cmnd[0],scp->cmd_len,hdrive));
  2193. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2194. return 0;
  2195. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2196. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2197. not required, should not occur due to error return on
  2198. READ_CAPACITY_16 */
  2199. cmdp->Service = CACHESERVICE;
  2200. cmdp->RequestBuffer = scp;
  2201. /* search free command index */
  2202. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2203. TRACE(("GDT: No free command index found\n"));
  2204. return 0;
  2205. }
  2206. /* if it's the first command, set command semaphore */
  2207. if (ha->cmd_cnt == 0)
  2208. gdth_set_sema0(ha);
  2209. /* fill command */
  2210. read_write = 0;
  2211. if (cmndinfo->OpCode != -1)
  2212. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2213. else if (scp->cmnd[0] == RESERVE)
  2214. cmdp->OpCode = GDT_RESERVE_DRV;
  2215. else if (scp->cmnd[0] == RELEASE)
  2216. cmdp->OpCode = GDT_RELEASE_DRV;
  2217. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2218. if (scp->cmnd[4] & 1) /* prevent ? */
  2219. cmdp->OpCode = GDT_MOUNT;
  2220. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2221. cmdp->OpCode = GDT_UNMOUNT;
  2222. else
  2223. cmdp->OpCode = GDT_FLUSH;
  2224. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2225. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2226. ) {
  2227. read_write = 1;
  2228. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2229. (ha->cache_feat & GDT_WR_THROUGH)))
  2230. cmdp->OpCode = GDT_WRITE_THR;
  2231. else
  2232. cmdp->OpCode = GDT_WRITE;
  2233. } else {
  2234. read_write = 2;
  2235. cmdp->OpCode = GDT_READ;
  2236. }
  2237. cmdp->BoardNode = LOCALBOARD;
  2238. if (mode64) {
  2239. cmdp->u.cache64.DeviceNo = hdrive;
  2240. cmdp->u.cache64.BlockNo = 1;
  2241. cmdp->u.cache64.sg_canz = 0;
  2242. } else {
  2243. cmdp->u.cache.DeviceNo = hdrive;
  2244. cmdp->u.cache.BlockNo = 1;
  2245. cmdp->u.cache.sg_canz = 0;
  2246. }
  2247. if (read_write) {
  2248. if (scp->cmd_len == 16) {
  2249. memcpy(&no, &scp->cmnd[2], sizeof(u64));
  2250. blockno = be64_to_cpu(no);
  2251. memcpy(&cnt, &scp->cmnd[10], sizeof(u32));
  2252. blockcnt = be32_to_cpu(cnt);
  2253. } else if (scp->cmd_len == 10) {
  2254. memcpy(&no, &scp->cmnd[2], sizeof(u32));
  2255. blockno = be32_to_cpu(no);
  2256. memcpy(&cnt, &scp->cmnd[7], sizeof(u16));
  2257. blockcnt = be16_to_cpu(cnt);
  2258. } else {
  2259. memcpy(&no, &scp->cmnd[0], sizeof(u32));
  2260. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2261. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2262. }
  2263. if (mode64) {
  2264. cmdp->u.cache64.BlockNo = blockno;
  2265. cmdp->u.cache64.BlockCnt = blockcnt;
  2266. } else {
  2267. cmdp->u.cache.BlockNo = (u32)blockno;
  2268. cmdp->u.cache.BlockCnt = blockcnt;
  2269. }
  2270. if (scsi_bufflen(scp)) {
  2271. cmndinfo->dma_dir = (read_write == 1 ?
  2272. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2273. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2274. cmndinfo->dma_dir);
  2275. if (mode64) {
  2276. struct scatterlist *sl;
  2277. cmdp->u.cache64.DestAddr= (u64)-1;
  2278. cmdp->u.cache64.sg_canz = sgcnt;
  2279. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2280. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2281. #ifdef GDTH_DMA_STATISTICS
  2282. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2283. ha->dma64_cnt++;
  2284. else
  2285. ha->dma32_cnt++;
  2286. #endif
  2287. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2288. }
  2289. } else {
  2290. struct scatterlist *sl;
  2291. cmdp->u.cache.DestAddr= 0xffffffff;
  2292. cmdp->u.cache.sg_canz = sgcnt;
  2293. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2294. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2295. #ifdef GDTH_DMA_STATISTICS
  2296. ha->dma32_cnt++;
  2297. #endif
  2298. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2299. }
  2300. }
  2301. #ifdef GDTH_STATISTICS
  2302. if (max_sg < (u32)sgcnt) {
  2303. max_sg = (u32)sgcnt;
  2304. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2305. }
  2306. #endif
  2307. }
  2308. }
  2309. /* evaluate command size, check space */
  2310. if (mode64) {
  2311. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2312. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2313. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2314. cmdp->u.cache64.sg_lst[0].sg_len));
  2315. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2316. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2317. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2318. (u16)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2319. } else {
  2320. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2321. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2322. cmdp->u.cache.sg_lst[0].sg_ptr,
  2323. cmdp->u.cache.sg_lst[0].sg_len));
  2324. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2325. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2326. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2327. (u16)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2328. }
  2329. if (ha->cmd_len & 3)
  2330. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2331. if (ha->cmd_cnt > 0) {
  2332. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2333. ha->ic_all_size) {
  2334. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2335. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2336. return 0;
  2337. }
  2338. }
  2339. /* copy command */
  2340. gdth_copy_command(ha);
  2341. return cmd_index;
  2342. }
  2343. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, u8 b)
  2344. {
  2345. register gdth_cmd_str *cmdp;
  2346. u16 i;
  2347. dma_addr_t sense_paddr;
  2348. int cmd_index, sgcnt, mode64;
  2349. u8 t,l;
  2350. struct page *page;
  2351. unsigned long offset;
  2352. struct gdth_cmndinfo *cmndinfo;
  2353. t = scp->device->id;
  2354. l = scp->device->lun;
  2355. cmdp = ha->pccb;
  2356. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2357. scp->cmnd[0],b,t,l));
  2358. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2359. return 0;
  2360. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2361. cmdp->Service = SCSIRAWSERVICE;
  2362. cmdp->RequestBuffer = scp;
  2363. /* search free command index */
  2364. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2365. TRACE(("GDT: No free command index found\n"));
  2366. return 0;
  2367. }
  2368. /* if it's the first command, set command semaphore */
  2369. if (ha->cmd_cnt == 0)
  2370. gdth_set_sema0(ha);
  2371. cmndinfo = gdth_cmnd_priv(scp);
  2372. /* fill command */
  2373. if (cmndinfo->OpCode != -1) {
  2374. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2375. cmdp->BoardNode = LOCALBOARD;
  2376. if (mode64) {
  2377. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2378. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2379. cmdp->OpCode, cmdp->u.raw64.direction));
  2380. /* evaluate command size */
  2381. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2382. } else {
  2383. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2384. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2385. cmdp->OpCode, cmdp->u.raw.direction));
  2386. /* evaluate command size */
  2387. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2388. }
  2389. } else {
  2390. page = virt_to_page(scp->sense_buffer);
  2391. offset = (unsigned long)scp->sense_buffer & ~PAGE_MASK;
  2392. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2393. 16,PCI_DMA_FROMDEVICE);
  2394. cmndinfo->sense_paddr = sense_paddr;
  2395. cmdp->OpCode = GDT_WRITE; /* always */
  2396. cmdp->BoardNode = LOCALBOARD;
  2397. if (mode64) {
  2398. cmdp->u.raw64.reserved = 0;
  2399. cmdp->u.raw64.mdisc_time = 0;
  2400. cmdp->u.raw64.mcon_time = 0;
  2401. cmdp->u.raw64.clen = scp->cmd_len;
  2402. cmdp->u.raw64.target = t;
  2403. cmdp->u.raw64.lun = l;
  2404. cmdp->u.raw64.bus = b;
  2405. cmdp->u.raw64.priority = 0;
  2406. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2407. cmdp->u.raw64.sense_len = 16;
  2408. cmdp->u.raw64.sense_data = sense_paddr;
  2409. cmdp->u.raw64.direction =
  2410. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2411. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2412. cmdp->u.raw64.sg_ranz = 0;
  2413. } else {
  2414. cmdp->u.raw.reserved = 0;
  2415. cmdp->u.raw.mdisc_time = 0;
  2416. cmdp->u.raw.mcon_time = 0;
  2417. cmdp->u.raw.clen = scp->cmd_len;
  2418. cmdp->u.raw.target = t;
  2419. cmdp->u.raw.lun = l;
  2420. cmdp->u.raw.bus = b;
  2421. cmdp->u.raw.priority = 0;
  2422. cmdp->u.raw.link_p = 0;
  2423. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2424. cmdp->u.raw.sense_len = 16;
  2425. cmdp->u.raw.sense_data = sense_paddr;
  2426. cmdp->u.raw.direction =
  2427. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2428. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2429. cmdp->u.raw.sg_ranz = 0;
  2430. }
  2431. if (scsi_bufflen(scp)) {
  2432. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2433. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2434. cmndinfo->dma_dir);
  2435. if (mode64) {
  2436. struct scatterlist *sl;
  2437. cmdp->u.raw64.sdata = (u64)-1;
  2438. cmdp->u.raw64.sg_ranz = sgcnt;
  2439. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2440. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2441. #ifdef GDTH_DMA_STATISTICS
  2442. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (u64)0xffffffff)
  2443. ha->dma64_cnt++;
  2444. else
  2445. ha->dma32_cnt++;
  2446. #endif
  2447. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2448. }
  2449. } else {
  2450. struct scatterlist *sl;
  2451. cmdp->u.raw.sdata = 0xffffffff;
  2452. cmdp->u.raw.sg_ranz = sgcnt;
  2453. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2454. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2455. #ifdef GDTH_DMA_STATISTICS
  2456. ha->dma32_cnt++;
  2457. #endif
  2458. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2459. }
  2460. }
  2461. #ifdef GDTH_STATISTICS
  2462. if (max_sg < sgcnt) {
  2463. max_sg = sgcnt;
  2464. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2465. }
  2466. #endif
  2467. }
  2468. if (mode64) {
  2469. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2470. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2471. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2472. cmdp->u.raw64.sg_lst[0].sg_len));
  2473. /* evaluate command size */
  2474. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2475. (u16)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2476. } else {
  2477. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2478. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2479. cmdp->u.raw.sg_lst[0].sg_ptr,
  2480. cmdp->u.raw.sg_lst[0].sg_len));
  2481. /* evaluate command size */
  2482. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2483. (u16)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2484. }
  2485. }
  2486. /* check space */
  2487. if (ha->cmd_len & 3)
  2488. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2489. if (ha->cmd_cnt > 0) {
  2490. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2491. ha->ic_all_size) {
  2492. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2493. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2494. return 0;
  2495. }
  2496. }
  2497. /* copy command */
  2498. gdth_copy_command(ha);
  2499. return cmd_index;
  2500. }
  2501. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2502. {
  2503. register gdth_cmd_str *cmdp;
  2504. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2505. int cmd_index;
  2506. cmdp= ha->pccb;
  2507. TRACE2(("gdth_special_cmd(): "));
  2508. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2509. return 0;
  2510. *cmdp = *cmndinfo->internal_cmd_str;
  2511. cmdp->RequestBuffer = scp;
  2512. /* search free command index */
  2513. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2514. TRACE(("GDT: No free command index found\n"));
  2515. return 0;
  2516. }
  2517. /* if it's the first command, set command semaphore */
  2518. if (ha->cmd_cnt == 0)
  2519. gdth_set_sema0(ha);
  2520. /* evaluate command size, check space */
  2521. if (cmdp->OpCode == GDT_IOCTL) {
  2522. TRACE2(("IOCTL\n"));
  2523. ha->cmd_len =
  2524. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(u64);
  2525. } else if (cmdp->Service == CACHESERVICE) {
  2526. TRACE2(("cache command %d\n",cmdp->OpCode));
  2527. if (ha->cache_feat & GDT_64BIT)
  2528. ha->cmd_len =
  2529. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2530. else
  2531. ha->cmd_len =
  2532. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2533. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2534. TRACE2(("raw command %d\n",cmdp->OpCode));
  2535. if (ha->raw_feat & GDT_64BIT)
  2536. ha->cmd_len =
  2537. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2538. else
  2539. ha->cmd_len =
  2540. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2541. }
  2542. if (ha->cmd_len & 3)
  2543. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2544. if (ha->cmd_cnt > 0) {
  2545. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2546. ha->ic_all_size) {
  2547. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2548. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2549. return 0;
  2550. }
  2551. }
  2552. /* copy command */
  2553. gdth_copy_command(ha);
  2554. return cmd_index;
  2555. }
  2556. /* Controller event handling functions */
  2557. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, u16 source,
  2558. u16 idx, gdth_evt_data *evt)
  2559. {
  2560. gdth_evt_str *e;
  2561. struct timeval tv;
  2562. /* no GDTH_LOCK_HA() ! */
  2563. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2564. if (source == 0) /* no source -> no event */
  2565. return NULL;
  2566. if (ebuffer[elastidx].event_source == source &&
  2567. ebuffer[elastidx].event_idx == idx &&
  2568. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2569. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2570. (char *)&evt->eu, evt->size)) ||
  2571. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2572. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2573. (char *)&evt->event_string)))) {
  2574. e = &ebuffer[elastidx];
  2575. do_gettimeofday(&tv);
  2576. e->last_stamp = tv.tv_sec;
  2577. ++e->same_count;
  2578. } else {
  2579. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2580. ++elastidx;
  2581. if (elastidx == MAX_EVENTS)
  2582. elastidx = 0;
  2583. if (elastidx == eoldidx) { /* reached mark ? */
  2584. ++eoldidx;
  2585. if (eoldidx == MAX_EVENTS)
  2586. eoldidx = 0;
  2587. }
  2588. }
  2589. e = &ebuffer[elastidx];
  2590. e->event_source = source;
  2591. e->event_idx = idx;
  2592. do_gettimeofday(&tv);
  2593. e->first_stamp = e->last_stamp = tv.tv_sec;
  2594. e->same_count = 1;
  2595. e->event_data = *evt;
  2596. e->application = 0;
  2597. }
  2598. return e;
  2599. }
  2600. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2601. {
  2602. gdth_evt_str *e;
  2603. int eindex;
  2604. unsigned long flags;
  2605. TRACE2(("gdth_read_event() handle %d\n", handle));
  2606. spin_lock_irqsave(&ha->smp_lock, flags);
  2607. if (handle == -1)
  2608. eindex = eoldidx;
  2609. else
  2610. eindex = handle;
  2611. estr->event_source = 0;
  2612. if (eindex < 0 || eindex >= MAX_EVENTS) {
  2613. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2614. return eindex;
  2615. }
  2616. e = &ebuffer[eindex];
  2617. if (e->event_source != 0) {
  2618. if (eindex != elastidx) {
  2619. if (++eindex == MAX_EVENTS)
  2620. eindex = 0;
  2621. } else {
  2622. eindex = -1;
  2623. }
  2624. memcpy(estr, e, sizeof(gdth_evt_str));
  2625. }
  2626. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2627. return eindex;
  2628. }
  2629. static void gdth_readapp_event(gdth_ha_str *ha,
  2630. u8 application, gdth_evt_str *estr)
  2631. {
  2632. gdth_evt_str *e;
  2633. int eindex;
  2634. unsigned long flags;
  2635. u8 found = FALSE;
  2636. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2637. spin_lock_irqsave(&ha->smp_lock, flags);
  2638. eindex = eoldidx;
  2639. for (;;) {
  2640. e = &ebuffer[eindex];
  2641. if (e->event_source == 0)
  2642. break;
  2643. if ((e->application & application) == 0) {
  2644. e->application |= application;
  2645. found = TRUE;
  2646. break;
  2647. }
  2648. if (eindex == elastidx)
  2649. break;
  2650. if (++eindex == MAX_EVENTS)
  2651. eindex = 0;
  2652. }
  2653. if (found)
  2654. memcpy(estr, e, sizeof(gdth_evt_str));
  2655. else
  2656. estr->event_source = 0;
  2657. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2658. }
  2659. static void gdth_clear_events(void)
  2660. {
  2661. TRACE(("gdth_clear_events()"));
  2662. eoldidx = elastidx = 0;
  2663. ebuffer[0].event_source = 0;
  2664. }
  2665. /* SCSI interface functions */
  2666. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2667. int gdth_from_wait, int* pIndex)
  2668. {
  2669. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2670. gdt6_dpram_str __iomem *dp6_ptr;
  2671. gdt2_dpram_str __iomem *dp2_ptr;
  2672. Scsi_Cmnd *scp;
  2673. int rval, i;
  2674. u8 IStatus;
  2675. u16 Service;
  2676. unsigned long flags = 0;
  2677. #ifdef INT_COAL
  2678. int coalesced = FALSE;
  2679. int next = FALSE;
  2680. gdth_coal_status *pcs = NULL;
  2681. int act_int_coal = 0;
  2682. #endif
  2683. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2684. /* if polling and not from gdth_wait() -> return */
  2685. if (gdth_polling) {
  2686. if (!gdth_from_wait) {
  2687. return IRQ_HANDLED;
  2688. }
  2689. }
  2690. if (!gdth_polling)
  2691. spin_lock_irqsave(&ha->smp_lock, flags);
  2692. /* search controller */
  2693. IStatus = gdth_get_status(ha);
  2694. if (IStatus == 0) {
  2695. /* spurious interrupt */
  2696. if (!gdth_polling)
  2697. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2698. return IRQ_HANDLED;
  2699. }
  2700. #ifdef GDTH_STATISTICS
  2701. ++act_ints;
  2702. #endif
  2703. #ifdef INT_COAL
  2704. /* See if the fw is returning coalesced status */
  2705. if (IStatus == COALINDEX) {
  2706. /* Coalesced status. Setup the initial status
  2707. buffer pointer and flags */
  2708. pcs = ha->coal_stat;
  2709. coalesced = TRUE;
  2710. next = TRUE;
  2711. }
  2712. do {
  2713. if (coalesced) {
  2714. /* For coalesced requests all status
  2715. information is found in the status buffer */
  2716. IStatus = (u8)(pcs->status & 0xff);
  2717. }
  2718. #endif
  2719. if (ha->type == GDT_EISA) {
  2720. if (IStatus & 0x80) { /* error flag */
  2721. IStatus &= ~0x80;
  2722. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2723. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2724. } else /* no error */
  2725. ha->status = S_OK;
  2726. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2727. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2728. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2729. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2730. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2731. } else if (ha->type == GDT_ISA) {
  2732. dp2_ptr = ha->brd;
  2733. if (IStatus & 0x80) { /* error flag */
  2734. IStatus &= ~0x80;
  2735. ha->status = readw(&dp2_ptr->u.ic.Status);
  2736. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2737. } else /* no error */
  2738. ha->status = S_OK;
  2739. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2740. ha->service = readw(&dp2_ptr->u.ic.Service);
  2741. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2742. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2743. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2744. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2745. } else if (ha->type == GDT_PCI) {
  2746. dp6_ptr = ha->brd;
  2747. if (IStatus & 0x80) { /* error flag */
  2748. IStatus &= ~0x80;
  2749. ha->status = readw(&dp6_ptr->u.ic.Status);
  2750. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2751. } else /* no error */
  2752. ha->status = S_OK;
  2753. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2754. ha->service = readw(&dp6_ptr->u.ic.Service);
  2755. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2756. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2757. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2758. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2759. } else if (ha->type == GDT_PCINEW) {
  2760. if (IStatus & 0x80) { /* error flag */
  2761. IStatus &= ~0x80;
  2762. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2763. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2764. } else
  2765. ha->status = S_OK;
  2766. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2767. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2768. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2769. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2770. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2771. } else if (ha->type == GDT_PCIMPR) {
  2772. dp6m_ptr = ha->brd;
  2773. if (IStatus & 0x80) { /* error flag */
  2774. IStatus &= ~0x80;
  2775. #ifdef INT_COAL
  2776. if (coalesced)
  2777. ha->status = pcs->ext_status & 0xffff;
  2778. else
  2779. #endif
  2780. ha->status = readw(&dp6m_ptr->i960r.status);
  2781. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2782. } else /* no error */
  2783. ha->status = S_OK;
  2784. #ifdef INT_COAL
  2785. /* get information */
  2786. if (coalesced) {
  2787. ha->info = pcs->info0;
  2788. ha->info2 = pcs->info1;
  2789. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2790. } else
  2791. #endif
  2792. {
  2793. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2794. ha->service = readw(&dp6m_ptr->i960r.service);
  2795. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2796. }
  2797. /* event string */
  2798. if (IStatus == ASYNCINDEX) {
  2799. if (ha->service != SCREENSERVICE &&
  2800. (ha->fw_vers & 0xff) >= 0x1a) {
  2801. ha->dvr.severity = readb
  2802. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2803. for (i = 0; i < 256; ++i) {
  2804. ha->dvr.event_string[i] = readb
  2805. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2806. if (ha->dvr.event_string[i] == 0)
  2807. break;
  2808. }
  2809. }
  2810. }
  2811. #ifdef INT_COAL
  2812. /* Make sure that non coalesced interrupts get cleared
  2813. before being handled by gdth_async_event/gdth_sync_event */
  2814. if (!coalesced)
  2815. #endif
  2816. {
  2817. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2818. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2819. }
  2820. } else {
  2821. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2822. if (!gdth_polling)
  2823. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2824. return IRQ_HANDLED;
  2825. }
  2826. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2827. IStatus,ha->status,ha->info));
  2828. if (gdth_from_wait) {
  2829. *pIndex = (int)IStatus;
  2830. }
  2831. if (IStatus == ASYNCINDEX) {
  2832. TRACE2(("gdth_interrupt() async. event\n"));
  2833. gdth_async_event(ha);
  2834. if (!gdth_polling)
  2835. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2836. gdth_next(ha);
  2837. return IRQ_HANDLED;
  2838. }
  2839. if (IStatus == SPEZINDEX) {
  2840. TRACE2(("Service unknown or not initialized !\n"));
  2841. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2842. ha->dvr.eu.driver.ionode = ha->hanum;
  2843. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2844. if (!gdth_polling)
  2845. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2846. return IRQ_HANDLED;
  2847. }
  2848. scp = ha->cmd_tab[IStatus-2].cmnd;
  2849. Service = ha->cmd_tab[IStatus-2].service;
  2850. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2851. if (scp == UNUSED_CMND) {
  2852. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2853. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2854. ha->dvr.eu.driver.ionode = ha->hanum;
  2855. ha->dvr.eu.driver.index = IStatus;
  2856. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2857. if (!gdth_polling)
  2858. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2859. return IRQ_HANDLED;
  2860. }
  2861. if (scp == INTERNAL_CMND) {
  2862. TRACE(("gdth_interrupt() answer to internal command\n"));
  2863. if (!gdth_polling)
  2864. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2865. return IRQ_HANDLED;
  2866. }
  2867. TRACE(("gdth_interrupt() sync. status\n"));
  2868. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2869. if (!gdth_polling)
  2870. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2871. if (rval == 2) {
  2872. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2873. } else if (rval == 1) {
  2874. gdth_scsi_done(scp);
  2875. }
  2876. #ifdef INT_COAL
  2877. if (coalesced) {
  2878. /* go to the next status in the status buffer */
  2879. ++pcs;
  2880. #ifdef GDTH_STATISTICS
  2881. ++act_int_coal;
  2882. if (act_int_coal > max_int_coal) {
  2883. max_int_coal = act_int_coal;
  2884. printk("GDT: max_int_coal = %d\n",(u16)max_int_coal);
  2885. }
  2886. #endif
  2887. /* see if there is another status */
  2888. if (pcs->status == 0)
  2889. /* Stop the coalesce loop */
  2890. next = FALSE;
  2891. }
  2892. } while (next);
  2893. /* coalescing only for new GDT_PCIMPR controllers available */
  2894. if (ha->type == GDT_PCIMPR && coalesced) {
  2895. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2896. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2897. }
  2898. #endif
  2899. gdth_next(ha);
  2900. return IRQ_HANDLED;
  2901. }
  2902. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2903. {
  2904. gdth_ha_str *ha = dev_id;
  2905. return __gdth_interrupt(ha, false, NULL);
  2906. }
  2907. static int gdth_sync_event(gdth_ha_str *ha, int service, u8 index,
  2908. Scsi_Cmnd *scp)
  2909. {
  2910. gdth_msg_str *msg;
  2911. gdth_cmd_str *cmdp;
  2912. u8 b, t;
  2913. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2914. cmdp = ha->pccb;
  2915. TRACE(("gdth_sync_event() serv %d status %d\n",
  2916. service,ha->status));
  2917. if (service == SCREENSERVICE) {
  2918. msg = ha->pmsg;
  2919. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2920. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2921. if (msg->msg_len > MSGLEN+1)
  2922. msg->msg_len = MSGLEN+1;
  2923. if (msg->msg_len)
  2924. if (!(msg->msg_answer && msg->msg_ext)) {
  2925. msg->msg_text[msg->msg_len] = '\0';
  2926. printk("%s",msg->msg_text);
  2927. }
  2928. if (msg->msg_ext && !msg->msg_answer) {
  2929. while (gdth_test_busy(ha))
  2930. gdth_delay(0);
  2931. cmdp->Service = SCREENSERVICE;
  2932. cmdp->RequestBuffer = SCREEN_CMND;
  2933. gdth_get_cmd_index(ha);
  2934. gdth_set_sema0(ha);
  2935. cmdp->OpCode = GDT_READ;
  2936. cmdp->BoardNode = LOCALBOARD;
  2937. cmdp->u.screen.reserved = 0;
  2938. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2939. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2940. ha->cmd_offs_dpmem = 0;
  2941. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2942. + sizeof(u64);
  2943. ha->cmd_cnt = 0;
  2944. gdth_copy_command(ha);
  2945. gdth_release_event(ha);
  2946. return 0;
  2947. }
  2948. if (msg->msg_answer && msg->msg_alen) {
  2949. /* default answers (getchar() not possible) */
  2950. if (msg->msg_alen == 1) {
  2951. msg->msg_alen = 0;
  2952. msg->msg_len = 1;
  2953. msg->msg_text[0] = 0;
  2954. } else {
  2955. msg->msg_alen -= 2;
  2956. msg->msg_len = 2;
  2957. msg->msg_text[0] = 1;
  2958. msg->msg_text[1] = 0;
  2959. }
  2960. msg->msg_ext = 0;
  2961. msg->msg_answer = 0;
  2962. while (gdth_test_busy(ha))
  2963. gdth_delay(0);
  2964. cmdp->Service = SCREENSERVICE;
  2965. cmdp->RequestBuffer = SCREEN_CMND;
  2966. gdth_get_cmd_index(ha);
  2967. gdth_set_sema0(ha);
  2968. cmdp->OpCode = GDT_WRITE;
  2969. cmdp->BoardNode = LOCALBOARD;
  2970. cmdp->u.screen.reserved = 0;
  2971. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2972. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2973. ha->cmd_offs_dpmem = 0;
  2974. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2975. + sizeof(u64);
  2976. ha->cmd_cnt = 0;
  2977. gdth_copy_command(ha);
  2978. gdth_release_event(ha);
  2979. return 0;
  2980. }
  2981. printk("\n");
  2982. } else {
  2983. b = scp->device->channel;
  2984. t = scp->device->id;
  2985. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2986. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2987. }
  2988. /* cache or raw service */
  2989. if (ha->status == S_BSY) {
  2990. TRACE2(("Controller busy -> retry !\n"));
  2991. if (cmndinfo->OpCode == GDT_MOUNT)
  2992. cmndinfo->OpCode = GDT_CLUST_INFO;
  2993. /* retry */
  2994. return 2;
  2995. }
  2996. if (scsi_bufflen(scp))
  2997. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2998. cmndinfo->dma_dir);
  2999. if (cmndinfo->sense_paddr)
  3000. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3001. PCI_DMA_FROMDEVICE);
  3002. if (ha->status == S_OK) {
  3003. cmndinfo->status = S_OK;
  3004. cmndinfo->info = ha->info;
  3005. if (cmndinfo->OpCode != -1) {
  3006. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3007. cmndinfo->OpCode));
  3008. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3009. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3010. ha->hdr[t].cluster_type = (u8)ha->info;
  3011. if (!(ha->hdr[t].cluster_type &
  3012. CLUSTER_MOUNTED)) {
  3013. /* NOT MOUNTED -> MOUNT */
  3014. cmndinfo->OpCode = GDT_MOUNT;
  3015. if (ha->hdr[t].cluster_type &
  3016. CLUSTER_RESERVED) {
  3017. /* cluster drive RESERVED (on the other node) */
  3018. cmndinfo->phase = -2; /* reservation conflict */
  3019. }
  3020. } else {
  3021. cmndinfo->OpCode = -1;
  3022. }
  3023. } else {
  3024. if (cmndinfo->OpCode == GDT_MOUNT) {
  3025. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3026. ha->hdr[t].media_changed = TRUE;
  3027. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3028. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3029. ha->hdr[t].media_changed = TRUE;
  3030. }
  3031. cmndinfo->OpCode = -1;
  3032. }
  3033. /* retry */
  3034. cmndinfo->priority = HIGH_PRI;
  3035. return 2;
  3036. } else {
  3037. /* RESERVE/RELEASE ? */
  3038. if (scp->cmnd[0] == RESERVE) {
  3039. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3040. } else if (scp->cmnd[0] == RELEASE) {
  3041. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3042. }
  3043. scp->result = DID_OK << 16;
  3044. scp->sense_buffer[0] = 0;
  3045. }
  3046. } else {
  3047. cmndinfo->status = ha->status;
  3048. cmndinfo->info = ha->info;
  3049. if (cmndinfo->OpCode != -1) {
  3050. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3051. cmndinfo->OpCode, ha->status));
  3052. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3053. cmndinfo->OpCode == GDT_SCAN_END) {
  3054. cmndinfo->OpCode = -1;
  3055. /* retry */
  3056. cmndinfo->priority = HIGH_PRI;
  3057. return 2;
  3058. }
  3059. memset((char*)scp->sense_buffer,0,16);
  3060. scp->sense_buffer[0] = 0x70;
  3061. scp->sense_buffer[2] = NOT_READY;
  3062. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3063. } else if (service == CACHESERVICE) {
  3064. if (ha->status == S_CACHE_UNKNOWN &&
  3065. (ha->hdr[t].cluster_type &
  3066. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3067. /* bus reset -> force GDT_CLUST_INFO */
  3068. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3069. }
  3070. memset((char*)scp->sense_buffer,0,16);
  3071. if (ha->status == (u16)S_CACHE_RESERV) {
  3072. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3073. } else {
  3074. scp->sense_buffer[0] = 0x70;
  3075. scp->sense_buffer[2] = NOT_READY;
  3076. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3077. }
  3078. if (!cmndinfo->internal_command) {
  3079. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3080. ha->dvr.eu.sync.ionode = ha->hanum;
  3081. ha->dvr.eu.sync.service = service;
  3082. ha->dvr.eu.sync.status = ha->status;
  3083. ha->dvr.eu.sync.info = ha->info;
  3084. ha->dvr.eu.sync.hostdrive = t;
  3085. if (ha->status >= 0x8000)
  3086. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3087. else
  3088. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3089. }
  3090. } else {
  3091. /* sense buffer filled from controller firmware (DMA) */
  3092. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3093. scp->result = DID_BAD_TARGET << 16;
  3094. } else {
  3095. scp->result = (DID_OK << 16) | ha->info;
  3096. }
  3097. }
  3098. }
  3099. if (!cmndinfo->wait_for_completion)
  3100. cmndinfo->wait_for_completion++;
  3101. else
  3102. return 1;
  3103. }
  3104. return 0;
  3105. }
  3106. static char *async_cache_tab[] = {
  3107. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3108. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3109. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3110. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3111. /* 2*/ "\005\000\002\006\004"
  3112. "GDT HA %u, Host Drive %lu not ready",
  3113. /* 3*/ "\005\000\002\006\004"
  3114. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3115. /* 4*/ "\005\000\002\006\004"
  3116. "GDT HA %u, mirror update on Host Drive %lu failed",
  3117. /* 5*/ "\005\000\002\006\004"
  3118. "GDT HA %u, Mirror Drive %lu failed",
  3119. /* 6*/ "\005\000\002\006\004"
  3120. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3121. /* 7*/ "\005\000\002\006\004"
  3122. "GDT HA %u, Host Drive %lu write protected",
  3123. /* 8*/ "\005\000\002\006\004"
  3124. "GDT HA %u, media changed in Host Drive %lu",
  3125. /* 9*/ "\005\000\002\006\004"
  3126. "GDT HA %u, Host Drive %lu is offline",
  3127. /*10*/ "\005\000\002\006\004"
  3128. "GDT HA %u, media change of Mirror Drive %lu",
  3129. /*11*/ "\005\000\002\006\004"
  3130. "GDT HA %u, Mirror Drive %lu is write protected",
  3131. /*12*/ "\005\000\002\006\004"
  3132. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3133. /*13*/ "\007\000\002\006\002\010\002"
  3134. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3135. /*14*/ "\005\000\002\006\002"
  3136. "GDT HA %u, Array Drive %u: FAIL state entered",
  3137. /*15*/ "\005\000\002\006\002"
  3138. "GDT HA %u, Array Drive %u: error",
  3139. /*16*/ "\007\000\002\006\002\010\002"
  3140. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3141. /*17*/ "\005\000\002\006\002"
  3142. "GDT HA %u, Array Drive %u: parity build failed",
  3143. /*18*/ "\005\000\002\006\002"
  3144. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3145. /*19*/ "\005\000\002\010\002"
  3146. "GDT HA %u, Test of Hot Fix %u failed",
  3147. /*20*/ "\005\000\002\006\002"
  3148. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3149. /*21*/ "\005\000\002\006\002"
  3150. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3151. /*22*/ "\007\000\002\006\002\010\002"
  3152. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3153. /*23*/ "\005\000\002\006\002"
  3154. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3155. /*24*/ "\005\000\002\010\002"
  3156. "GDT HA %u, mirror update on Cache Drive %u completed",
  3157. /*25*/ "\005\000\002\010\002"
  3158. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3159. /*26*/ "\005\000\002\006\002"
  3160. "GDT HA %u, Array Drive %u: drive rebuild started",
  3161. /*27*/ "\005\000\002\012\001"
  3162. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3163. /*28*/ "\005\000\002\012\001"
  3164. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3165. /*29*/ "\007\000\002\012\001\013\001"
  3166. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3167. /*30*/ "\007\000\002\012\001\013\001"
  3168. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3169. /*31*/ "\007\000\002\012\001\013\001"
  3170. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3171. /*32*/ "\007\000\002\012\001\013\001"
  3172. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3173. /*33*/ "\007\000\002\012\001\013\001"
  3174. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3175. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3176. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3177. /*35*/ "\007\000\002\012\001\013\001"
  3178. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3179. /*36*/ "\007\000\002\012\001\013\001"
  3180. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3181. /*37*/ "\007\000\002\012\001\006\004"
  3182. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3183. /*38*/ "\007\000\002\012\001\013\001"
  3184. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3185. /*39*/ "\007\000\002\012\001\013\001"
  3186. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3187. /*40*/ "\007\000\002\012\001\013\001"
  3188. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3189. /*41*/ "\007\000\002\012\001\013\001"
  3190. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3191. /*42*/ "\005\000\002\006\002"
  3192. "GDT HA %u, Array Drive %u: drive build started",
  3193. /*43*/ "\003\000\002"
  3194. "GDT HA %u, DRAM parity error detected",
  3195. /*44*/ "\005\000\002\006\002"
  3196. "GDT HA %u, Mirror Drive %u: update started",
  3197. /*45*/ "\007\000\002\006\002\010\002"
  3198. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3199. /*46*/ "\005\000\002\006\002"
  3200. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3201. /*47*/ "\005\000\002\006\002"
  3202. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3203. /*48*/ "\005\000\002\006\002"
  3204. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3205. /*49*/ "\005\000\002\006\002"
  3206. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3207. /*50*/ "\007\000\002\012\001\013\001"
  3208. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3209. /*51*/ "\005\000\002\006\002"
  3210. "GDT HA %u, Array Drive %u: expand started",
  3211. /*52*/ "\005\000\002\006\002"
  3212. "GDT HA %u, Array Drive %u: expand finished successfully",
  3213. /*53*/ "\005\000\002\006\002"
  3214. "GDT HA %u, Array Drive %u: expand failed",
  3215. /*54*/ "\003\000\002"
  3216. "GDT HA %u, CPU temperature critical",
  3217. /*55*/ "\003\000\002"
  3218. "GDT HA %u, CPU temperature OK",
  3219. /*56*/ "\005\000\002\006\004"
  3220. "GDT HA %u, Host drive %lu created",
  3221. /*57*/ "\005\000\002\006\002"
  3222. "GDT HA %u, Array Drive %u: expand restarted",
  3223. /*58*/ "\005\000\002\006\002"
  3224. "GDT HA %u, Array Drive %u: expand stopped",
  3225. /*59*/ "\005\000\002\010\002"
  3226. "GDT HA %u, Mirror Drive %u: drive build quited",
  3227. /*60*/ "\005\000\002\006\002"
  3228. "GDT HA %u, Array Drive %u: parity build quited",
  3229. /*61*/ "\005\000\002\006\002"
  3230. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3231. /*62*/ "\005\000\002\006\002"
  3232. "GDT HA %u, Array Drive %u: parity verify started",
  3233. /*63*/ "\005\000\002\006\002"
  3234. "GDT HA %u, Array Drive %u: parity verify done",
  3235. /*64*/ "\005\000\002\006\002"
  3236. "GDT HA %u, Array Drive %u: parity verify failed",
  3237. /*65*/ "\005\000\002\006\002"
  3238. "GDT HA %u, Array Drive %u: parity error detected",
  3239. /*66*/ "\005\000\002\006\002"
  3240. "GDT HA %u, Array Drive %u: parity verify quited",
  3241. /*67*/ "\005\000\002\006\002"
  3242. "GDT HA %u, Host Drive %u reserved",
  3243. /*68*/ "\005\000\002\006\002"
  3244. "GDT HA %u, Host Drive %u mounted and released",
  3245. /*69*/ "\005\000\002\006\002"
  3246. "GDT HA %u, Host Drive %u released",
  3247. /*70*/ "\003\000\002"
  3248. "GDT HA %u, DRAM error detected and corrected with ECC",
  3249. /*71*/ "\003\000\002"
  3250. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3251. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3252. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3253. /*73*/ "\005\000\002\006\002"
  3254. "GDT HA %u, Host drive %u resetted locally",
  3255. /*74*/ "\005\000\002\006\002"
  3256. "GDT HA %u, Host drive %u resetted remotely",
  3257. /*75*/ "\003\000\002"
  3258. "GDT HA %u, async. status 75 unknown",
  3259. };
  3260. static int gdth_async_event(gdth_ha_str *ha)
  3261. {
  3262. gdth_cmd_str *cmdp;
  3263. int cmd_index;
  3264. cmdp= ha->pccb;
  3265. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3266. ha->hanum, ha->service));
  3267. if (ha->service == SCREENSERVICE) {
  3268. if (ha->status == MSG_REQUEST) {
  3269. while (gdth_test_busy(ha))
  3270. gdth_delay(0);
  3271. cmdp->Service = SCREENSERVICE;
  3272. cmdp->RequestBuffer = SCREEN_CMND;
  3273. cmd_index = gdth_get_cmd_index(ha);
  3274. gdth_set_sema0(ha);
  3275. cmdp->OpCode = GDT_READ;
  3276. cmdp->BoardNode = LOCALBOARD;
  3277. cmdp->u.screen.reserved = 0;
  3278. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3279. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3280. ha->cmd_offs_dpmem = 0;
  3281. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3282. + sizeof(u64);
  3283. ha->cmd_cnt = 0;
  3284. gdth_copy_command(ha);
  3285. if (ha->type == GDT_EISA)
  3286. printk("[EISA slot %d] ",(u16)ha->brd_phys);
  3287. else if (ha->type == GDT_ISA)
  3288. printk("[DPMEM 0x%4X] ",(u16)ha->brd_phys);
  3289. else
  3290. printk("[PCI %d/%d] ",(u16)(ha->brd_phys>>8),
  3291. (u16)((ha->brd_phys>>3)&0x1f));
  3292. gdth_release_event(ha);
  3293. }
  3294. } else {
  3295. if (ha->type == GDT_PCIMPR &&
  3296. (ha->fw_vers & 0xff) >= 0x1a) {
  3297. ha->dvr.size = 0;
  3298. ha->dvr.eu.async.ionode = ha->hanum;
  3299. ha->dvr.eu.async.status = ha->status;
  3300. /* severity and event_string already set! */
  3301. } else {
  3302. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3303. ha->dvr.eu.async.ionode = ha->hanum;
  3304. ha->dvr.eu.async.service = ha->service;
  3305. ha->dvr.eu.async.status = ha->status;
  3306. ha->dvr.eu.async.info = ha->info;
  3307. *(u32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3308. }
  3309. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3310. gdth_log_event( &ha->dvr, NULL );
  3311. /* new host drive from expand? */
  3312. if (ha->service == CACHESERVICE && ha->status == 56) {
  3313. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3314. (u16)ha->info));
  3315. /* gdth_analyse_hdrive(hanum, (u16)ha->info); */
  3316. }
  3317. }
  3318. return 1;
  3319. }
  3320. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3321. {
  3322. gdth_stackframe stack;
  3323. char *f = NULL;
  3324. int i,j;
  3325. TRACE2(("gdth_log_event()\n"));
  3326. if (dvr->size == 0) {
  3327. if (buffer == NULL) {
  3328. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3329. } else {
  3330. sprintf(buffer,"Adapter %d: %s\n",
  3331. dvr->eu.async.ionode,dvr->event_string);
  3332. }
  3333. } else if (dvr->eu.async.service == CACHESERVICE &&
  3334. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3335. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3336. dvr->eu.async.status));
  3337. f = async_cache_tab[dvr->eu.async.status];
  3338. /* i: parameter to push, j: stack element to fill */
  3339. for (j=0,i=1; i < f[0]; i+=2) {
  3340. switch (f[i+1]) {
  3341. case 4:
  3342. stack.b[j++] = *(u32*)&dvr->eu.stream[(int)f[i]];
  3343. break;
  3344. case 2:
  3345. stack.b[j++] = *(u16*)&dvr->eu.stream[(int)f[i]];
  3346. break;
  3347. case 1:
  3348. stack.b[j++] = *(u8*)&dvr->eu.stream[(int)f[i]];
  3349. break;
  3350. default:
  3351. break;
  3352. }
  3353. }
  3354. if (buffer == NULL) {
  3355. printk(&f[(int)f[0]],stack);
  3356. printk("\n");
  3357. } else {
  3358. sprintf(buffer,&f[(int)f[0]],stack);
  3359. }
  3360. } else {
  3361. if (buffer == NULL) {
  3362. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3363. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3364. } else {
  3365. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3366. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3367. }
  3368. }
  3369. }
  3370. #ifdef GDTH_STATISTICS
  3371. static u8 gdth_timer_running;
  3372. static void gdth_timeout(unsigned long data)
  3373. {
  3374. u32 i;
  3375. Scsi_Cmnd *nscp;
  3376. gdth_ha_str *ha;
  3377. unsigned long flags;
  3378. if(unlikely(list_empty(&gdth_instances))) {
  3379. gdth_timer_running = 0;
  3380. return;
  3381. }
  3382. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3383. spin_lock_irqsave(&ha->smp_lock, flags);
  3384. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3385. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3386. ++act_stats;
  3387. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3388. ++act_rq;
  3389. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3390. act_ints, act_ios, act_stats, act_rq));
  3391. act_ints = act_ios = 0;
  3392. gdth_timer.expires = jiffies + 30 * HZ;
  3393. add_timer(&gdth_timer);
  3394. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3395. }
  3396. static void gdth_timer_init(void)
  3397. {
  3398. if (gdth_timer_running)
  3399. return;
  3400. gdth_timer_running = 1;
  3401. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3402. gdth_timer.expires = jiffies + HZ;
  3403. gdth_timer.data = 0L;
  3404. gdth_timer.function = gdth_timeout;
  3405. add_timer(&gdth_timer);
  3406. }
  3407. #else
  3408. static inline void gdth_timer_init(void)
  3409. {
  3410. }
  3411. #endif
  3412. static void __init internal_setup(char *str,int *ints)
  3413. {
  3414. int i, argc;
  3415. char *cur_str, *argv;
  3416. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3417. str ? str:"NULL", ints ? ints[0]:0));
  3418. /* read irq[] from ints[] */
  3419. if (ints) {
  3420. argc = ints[0];
  3421. if (argc > 0) {
  3422. if (argc > MAXHA)
  3423. argc = MAXHA;
  3424. for (i = 0; i < argc; ++i)
  3425. irq[i] = ints[i+1];
  3426. }
  3427. }
  3428. /* analyse string */
  3429. argv = str;
  3430. while (argv && (cur_str = strchr(argv, ':'))) {
  3431. int val = 0, c = *++cur_str;
  3432. if (c == 'n' || c == 'N')
  3433. val = 0;
  3434. else if (c == 'y' || c == 'Y')
  3435. val = 1;
  3436. else
  3437. val = (int)simple_strtoul(cur_str, NULL, 0);
  3438. if (!strncmp(argv, "disable:", 8))
  3439. disable = val;
  3440. else if (!strncmp(argv, "reserve_mode:", 13))
  3441. reserve_mode = val;
  3442. else if (!strncmp(argv, "reverse_scan:", 13))
  3443. reverse_scan = val;
  3444. else if (!strncmp(argv, "hdr_channel:", 12))
  3445. hdr_channel = val;
  3446. else if (!strncmp(argv, "max_ids:", 8))
  3447. max_ids = val;
  3448. else if (!strncmp(argv, "rescan:", 7))
  3449. rescan = val;
  3450. else if (!strncmp(argv, "shared_access:", 14))
  3451. shared_access = val;
  3452. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3453. probe_eisa_isa = val;
  3454. else if (!strncmp(argv, "reserve_list:", 13)) {
  3455. reserve_list[0] = val;
  3456. for (i = 1; i < MAX_RES_ARGS; i++) {
  3457. cur_str = strchr(cur_str, ',');
  3458. if (!cur_str)
  3459. break;
  3460. if (!isdigit((int)*++cur_str)) {
  3461. --cur_str;
  3462. break;
  3463. }
  3464. reserve_list[i] =
  3465. (int)simple_strtoul(cur_str, NULL, 0);
  3466. }
  3467. if (!cur_str)
  3468. break;
  3469. argv = ++cur_str;
  3470. continue;
  3471. }
  3472. if ((argv = strchr(argv, ',')))
  3473. ++argv;
  3474. }
  3475. }
  3476. int __init option_setup(char *str)
  3477. {
  3478. int ints[MAXHA];
  3479. char *cur = str;
  3480. int i = 1;
  3481. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3482. while (cur && isdigit(*cur) && i < MAXHA) {
  3483. ints[i++] = simple_strtoul(cur, NULL, 0);
  3484. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3485. }
  3486. ints[0] = i - 1;
  3487. internal_setup(cur, ints);
  3488. return 1;
  3489. }
  3490. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3491. {
  3492. TRACE2(("gdth_ctr_name()\n"));
  3493. if (ha->type == GDT_EISA) {
  3494. switch (ha->stype) {
  3495. case GDT3_ID:
  3496. return("GDT3000/3020");
  3497. case GDT3A_ID:
  3498. return("GDT3000A/3020A/3050A");
  3499. case GDT3B_ID:
  3500. return("GDT3000B/3010A");
  3501. }
  3502. } else if (ha->type == GDT_ISA) {
  3503. return("GDT2000/2020");
  3504. } else if (ha->type == GDT_PCI) {
  3505. switch (ha->pdev->device) {
  3506. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3507. return("GDT6000/6020/6050");
  3508. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3509. return("GDT6000B/6010");
  3510. }
  3511. }
  3512. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3513. return("");
  3514. }
  3515. static const char *gdth_info(struct Scsi_Host *shp)
  3516. {
  3517. gdth_ha_str *ha = shost_priv(shp);
  3518. TRACE2(("gdth_info()\n"));
  3519. return ((const char *)ha->binfo.type_string);
  3520. }
  3521. static enum blk_eh_timer_return gdth_timed_out(struct scsi_cmnd *scp)
  3522. {
  3523. gdth_ha_str *ha = shost_priv(scp->device->host);
  3524. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3525. u8 b, t;
  3526. unsigned long flags;
  3527. enum blk_eh_timer_return retval = BLK_EH_NOT_HANDLED;
  3528. TRACE(("%s() cmd 0x%x\n", scp->cmnd[0], __func__));
  3529. b = scp->device->channel;
  3530. t = scp->device->id;
  3531. /*
  3532. * We don't really honor the command timeout, but we try to
  3533. * honor 6 times of the actual command timeout! So reset the
  3534. * timer if this is less than 6th timeout on this command!
  3535. */
  3536. if (++cmndinfo->timeout_count < 6)
  3537. retval = BLK_EH_RESET_TIMER;
  3538. /* Reset the timeout if it is locked IO */
  3539. spin_lock_irqsave(&ha->smp_lock, flags);
  3540. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha, b)].lock) ||
  3541. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  3542. TRACE2(("%s(): locked IO, reset timeout\n", __func__));
  3543. retval = BLK_EH_RESET_TIMER;
  3544. }
  3545. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3546. return retval;
  3547. }
  3548. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3549. {
  3550. gdth_ha_str *ha = shost_priv(scp->device->host);
  3551. int i;
  3552. unsigned long flags;
  3553. Scsi_Cmnd *cmnd;
  3554. u8 b;
  3555. TRACE2(("gdth_eh_bus_reset()\n"));
  3556. b = scp->device->channel;
  3557. /* clear command tab */
  3558. spin_lock_irqsave(&ha->smp_lock, flags);
  3559. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3560. cmnd = ha->cmd_tab[i].cmnd;
  3561. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3562. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3563. }
  3564. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3565. if (b == ha->virt_bus) {
  3566. /* host drives */
  3567. for (i = 0; i < MAX_HDRIVES; ++i) {
  3568. if (ha->hdr[i].present) {
  3569. spin_lock_irqsave(&ha->smp_lock, flags);
  3570. gdth_polling = TRUE;
  3571. while (gdth_test_busy(ha))
  3572. gdth_delay(0);
  3573. if (gdth_internal_cmd(ha, CACHESERVICE,
  3574. GDT_CLUST_RESET, i, 0, 0))
  3575. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3576. gdth_polling = FALSE;
  3577. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3578. }
  3579. }
  3580. } else {
  3581. /* raw devices */
  3582. spin_lock_irqsave(&ha->smp_lock, flags);
  3583. for (i = 0; i < MAXID; ++i)
  3584. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3585. gdth_polling = TRUE;
  3586. while (gdth_test_busy(ha))
  3587. gdth_delay(0);
  3588. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3589. BUS_L2P(ha,b), 0, 0);
  3590. gdth_polling = FALSE;
  3591. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3592. }
  3593. return SUCCESS;
  3594. }
  3595. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3596. {
  3597. u8 b, t;
  3598. gdth_ha_str *ha = shost_priv(sdev->host);
  3599. struct scsi_device *sd;
  3600. unsigned capacity;
  3601. sd = sdev;
  3602. capacity = cap;
  3603. b = sd->channel;
  3604. t = sd->id;
  3605. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3606. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3607. /* raw device or host drive without mapping information */
  3608. TRACE2(("Evaluate mapping\n"));
  3609. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3610. } else {
  3611. ip[0] = ha->hdr[t].heads;
  3612. ip[1] = ha->hdr[t].secs;
  3613. ip[2] = capacity / ip[0] / ip[1];
  3614. }
  3615. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3616. ip[0],ip[1],ip[2]));
  3617. return 0;
  3618. }
  3619. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3620. void (*done)(struct scsi_cmnd *))
  3621. {
  3622. gdth_ha_str *ha = shost_priv(scp->device->host);
  3623. struct gdth_cmndinfo *cmndinfo;
  3624. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3625. cmndinfo = gdth_get_cmndinfo(ha);
  3626. BUG_ON(!cmndinfo);
  3627. scp->scsi_done = done;
  3628. cmndinfo->timeout_count = 0;
  3629. cmndinfo->priority = DEFAULT_PRI;
  3630. return __gdth_queuecommand(ha, scp, cmndinfo);
  3631. }
  3632. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3633. struct gdth_cmndinfo *cmndinfo)
  3634. {
  3635. scp->host_scribble = (unsigned char *)cmndinfo;
  3636. cmndinfo->wait_for_completion = 1;
  3637. cmndinfo->phase = -1;
  3638. cmndinfo->OpCode = -1;
  3639. #ifdef GDTH_STATISTICS
  3640. ++act_ios;
  3641. #endif
  3642. gdth_putq(ha, scp, cmndinfo->priority);
  3643. gdth_next(ha);
  3644. return 0;
  3645. }
  3646. static int gdth_open(struct inode *inode, struct file *filep)
  3647. {
  3648. gdth_ha_str *ha;
  3649. mutex_lock(&gdth_mutex);
  3650. list_for_each_entry(ha, &gdth_instances, list) {
  3651. if (!ha->sdev)
  3652. ha->sdev = scsi_get_host_dev(ha->shost);
  3653. }
  3654. mutex_unlock(&gdth_mutex);
  3655. TRACE(("gdth_open()\n"));
  3656. return 0;
  3657. }
  3658. static int gdth_close(struct inode *inode, struct file *filep)
  3659. {
  3660. TRACE(("gdth_close()\n"));
  3661. return 0;
  3662. }
  3663. static int ioc_event(void __user *arg)
  3664. {
  3665. gdth_ioctl_event evt;
  3666. gdth_ha_str *ha;
  3667. unsigned long flags;
  3668. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3669. return -EFAULT;
  3670. ha = gdth_find_ha(evt.ionode);
  3671. if (!ha)
  3672. return -EFAULT;
  3673. if (evt.erase == 0xff) {
  3674. if (evt.event.event_source == ES_TEST)
  3675. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3676. else if (evt.event.event_source == ES_DRIVER)
  3677. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3678. else if (evt.event.event_source == ES_SYNC)
  3679. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3680. else
  3681. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3682. spin_lock_irqsave(&ha->smp_lock, flags);
  3683. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3684. &evt.event.event_data);
  3685. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3686. } else if (evt.erase == 0xfe) {
  3687. gdth_clear_events();
  3688. } else if (evt.erase == 0) {
  3689. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3690. } else {
  3691. gdth_readapp_event(ha, evt.erase, &evt.event);
  3692. }
  3693. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3694. return -EFAULT;
  3695. return 0;
  3696. }
  3697. static int ioc_lockdrv(void __user *arg)
  3698. {
  3699. gdth_ioctl_lockdrv ldrv;
  3700. u8 i, j;
  3701. unsigned long flags;
  3702. gdth_ha_str *ha;
  3703. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3704. return -EFAULT;
  3705. ha = gdth_find_ha(ldrv.ionode);
  3706. if (!ha)
  3707. return -EFAULT;
  3708. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3709. j = ldrv.drives[i];
  3710. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3711. continue;
  3712. if (ldrv.lock) {
  3713. spin_lock_irqsave(&ha->smp_lock, flags);
  3714. ha->hdr[j].lock = 1;
  3715. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3716. gdth_wait_completion(ha, ha->bus_cnt, j);
  3717. } else {
  3718. spin_lock_irqsave(&ha->smp_lock, flags);
  3719. ha->hdr[j].lock = 0;
  3720. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3721. gdth_next(ha);
  3722. }
  3723. }
  3724. return 0;
  3725. }
  3726. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3727. {
  3728. gdth_ioctl_reset res;
  3729. gdth_cmd_str cmd;
  3730. gdth_ha_str *ha;
  3731. int rval;
  3732. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3733. res.number >= MAX_HDRIVES)
  3734. return -EFAULT;
  3735. ha = gdth_find_ha(res.ionode);
  3736. if (!ha)
  3737. return -EFAULT;
  3738. if (!ha->hdr[res.number].present)
  3739. return 0;
  3740. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3741. cmd.Service = CACHESERVICE;
  3742. cmd.OpCode = GDT_CLUST_RESET;
  3743. if (ha->cache_feat & GDT_64BIT)
  3744. cmd.u.cache64.DeviceNo = res.number;
  3745. else
  3746. cmd.u.cache.DeviceNo = res.number;
  3747. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3748. if (rval < 0)
  3749. return rval;
  3750. res.status = rval;
  3751. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3752. return -EFAULT;
  3753. return 0;
  3754. }
  3755. static int ioc_general(void __user *arg, char *cmnd)
  3756. {
  3757. gdth_ioctl_general gen;
  3758. char *buf = NULL;
  3759. u64 paddr;
  3760. gdth_ha_str *ha;
  3761. int rval;
  3762. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3763. return -EFAULT;
  3764. ha = gdth_find_ha(gen.ionode);
  3765. if (!ha)
  3766. return -EFAULT;
  3767. if (gen.data_len > INT_MAX)
  3768. return -EINVAL;
  3769. if (gen.sense_len > INT_MAX)
  3770. return -EINVAL;
  3771. if (gen.data_len + gen.sense_len > INT_MAX)
  3772. return -EINVAL;
  3773. if (gen.data_len + gen.sense_len != 0) {
  3774. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3775. FALSE, &paddr)))
  3776. return -EFAULT;
  3777. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3778. gen.data_len + gen.sense_len)) {
  3779. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3780. return -EFAULT;
  3781. }
  3782. if (gen.command.OpCode == GDT_IOCTL) {
  3783. gen.command.u.ioctl.p_param = paddr;
  3784. } else if (gen.command.Service == CACHESERVICE) {
  3785. if (ha->cache_feat & GDT_64BIT) {
  3786. /* copy elements from 32-bit IOCTL structure */
  3787. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3788. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3789. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3790. /* addresses */
  3791. if (ha->cache_feat & SCATTER_GATHER) {
  3792. gen.command.u.cache64.DestAddr = (u64)-1;
  3793. gen.command.u.cache64.sg_canz = 1;
  3794. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3795. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3796. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3797. } else {
  3798. gen.command.u.cache64.DestAddr = paddr;
  3799. gen.command.u.cache64.sg_canz = 0;
  3800. }
  3801. } else {
  3802. if (ha->cache_feat & SCATTER_GATHER) {
  3803. gen.command.u.cache.DestAddr = 0xffffffff;
  3804. gen.command.u.cache.sg_canz = 1;
  3805. gen.command.u.cache.sg_lst[0].sg_ptr = (u32)paddr;
  3806. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3807. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3808. } else {
  3809. gen.command.u.cache.DestAddr = paddr;
  3810. gen.command.u.cache.sg_canz = 0;
  3811. }
  3812. }
  3813. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3814. if (ha->raw_feat & GDT_64BIT) {
  3815. /* copy elements from 32-bit IOCTL structure */
  3816. char cmd[16];
  3817. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3818. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3819. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3820. gen.command.u.raw64.target = gen.command.u.raw.target;
  3821. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3822. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3823. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3824. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3825. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3826. /* addresses */
  3827. if (ha->raw_feat & SCATTER_GATHER) {
  3828. gen.command.u.raw64.sdata = (u64)-1;
  3829. gen.command.u.raw64.sg_ranz = 1;
  3830. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3831. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3832. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3833. } else {
  3834. gen.command.u.raw64.sdata = paddr;
  3835. gen.command.u.raw64.sg_ranz = 0;
  3836. }
  3837. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3838. } else {
  3839. if (ha->raw_feat & SCATTER_GATHER) {
  3840. gen.command.u.raw.sdata = 0xffffffff;
  3841. gen.command.u.raw.sg_ranz = 1;
  3842. gen.command.u.raw.sg_lst[0].sg_ptr = (u32)paddr;
  3843. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3844. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3845. } else {
  3846. gen.command.u.raw.sdata = paddr;
  3847. gen.command.u.raw.sg_ranz = 0;
  3848. }
  3849. gen.command.u.raw.sense_data = (u32)paddr + gen.data_len;
  3850. }
  3851. } else {
  3852. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3853. return -EFAULT;
  3854. }
  3855. }
  3856. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3857. if (rval < 0)
  3858. return rval;
  3859. gen.status = rval;
  3860. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3861. gen.data_len + gen.sense_len)) {
  3862. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3863. return -EFAULT;
  3864. }
  3865. if (copy_to_user(arg, &gen,
  3866. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3867. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3868. return -EFAULT;
  3869. }
  3870. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3871. return 0;
  3872. }
  3873. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3874. {
  3875. gdth_ioctl_rescan *rsc;
  3876. gdth_cmd_str *cmd;
  3877. gdth_ha_str *ha;
  3878. u8 i;
  3879. int rc = -ENOMEM;
  3880. u32 cluster_type = 0;
  3881. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3882. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3883. if (!rsc || !cmd)
  3884. goto free_fail;
  3885. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3886. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3887. rc = -EFAULT;
  3888. goto free_fail;
  3889. }
  3890. memset(cmd, 0, sizeof(gdth_cmd_str));
  3891. for (i = 0; i < MAX_HDRIVES; ++i) {
  3892. if (!ha->hdr[i].present) {
  3893. rsc->hdr_list[i].bus = 0xff;
  3894. continue;
  3895. }
  3896. rsc->hdr_list[i].bus = ha->virt_bus;
  3897. rsc->hdr_list[i].target = i;
  3898. rsc->hdr_list[i].lun = 0;
  3899. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3900. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3901. cmd->Service = CACHESERVICE;
  3902. cmd->OpCode = GDT_CLUST_INFO;
  3903. if (ha->cache_feat & GDT_64BIT)
  3904. cmd->u.cache64.DeviceNo = i;
  3905. else
  3906. cmd->u.cache.DeviceNo = i;
  3907. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3908. rsc->hdr_list[i].cluster_type = cluster_type;
  3909. }
  3910. }
  3911. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3912. rc = -EFAULT;
  3913. else
  3914. rc = 0;
  3915. free_fail:
  3916. kfree(rsc);
  3917. kfree(cmd);
  3918. return rc;
  3919. }
  3920. static int ioc_rescan(void __user *arg, char *cmnd)
  3921. {
  3922. gdth_ioctl_rescan *rsc;
  3923. gdth_cmd_str *cmd;
  3924. u16 i, status, hdr_cnt;
  3925. u32 info;
  3926. int cyls, hds, secs;
  3927. int rc = -ENOMEM;
  3928. unsigned long flags;
  3929. gdth_ha_str *ha;
  3930. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3931. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3932. if (!cmd || !rsc)
  3933. goto free_fail;
  3934. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3935. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3936. rc = -EFAULT;
  3937. goto free_fail;
  3938. }
  3939. memset(cmd, 0, sizeof(gdth_cmd_str));
  3940. if (rsc->flag == 0) {
  3941. /* old method: re-init. cache service */
  3942. cmd->Service = CACHESERVICE;
  3943. if (ha->cache_feat & GDT_64BIT) {
  3944. cmd->OpCode = GDT_X_INIT_HOST;
  3945. cmd->u.cache64.DeviceNo = LINUX_OS;
  3946. } else {
  3947. cmd->OpCode = GDT_INIT;
  3948. cmd->u.cache.DeviceNo = LINUX_OS;
  3949. }
  3950. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3951. i = 0;
  3952. hdr_cnt = (status == S_OK ? (u16)info : 0);
  3953. } else {
  3954. i = rsc->hdr_no;
  3955. hdr_cnt = i + 1;
  3956. }
  3957. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3958. cmd->Service = CACHESERVICE;
  3959. cmd->OpCode = GDT_INFO;
  3960. if (ha->cache_feat & GDT_64BIT)
  3961. cmd->u.cache64.DeviceNo = i;
  3962. else
  3963. cmd->u.cache.DeviceNo = i;
  3964. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3965. spin_lock_irqsave(&ha->smp_lock, flags);
  3966. rsc->hdr_list[i].bus = ha->virt_bus;
  3967. rsc->hdr_list[i].target = i;
  3968. rsc->hdr_list[i].lun = 0;
  3969. if (status != S_OK) {
  3970. ha->hdr[i].present = FALSE;
  3971. } else {
  3972. ha->hdr[i].present = TRUE;
  3973. ha->hdr[i].size = info;
  3974. /* evaluate mapping */
  3975. ha->hdr[i].size &= ~SECS32;
  3976. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3977. ha->hdr[i].heads = hds;
  3978. ha->hdr[i].secs = secs;
  3979. /* round size */
  3980. ha->hdr[i].size = cyls * hds * secs;
  3981. }
  3982. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3983. if (status != S_OK)
  3984. continue;
  3985. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3986. /* but we need ha->info2, not yet stored in scp->SCp */
  3987. /* devtype, cluster info, R/W attribs */
  3988. cmd->Service = CACHESERVICE;
  3989. cmd->OpCode = GDT_DEVTYPE;
  3990. if (ha->cache_feat & GDT_64BIT)
  3991. cmd->u.cache64.DeviceNo = i;
  3992. else
  3993. cmd->u.cache.DeviceNo = i;
  3994. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3995. spin_lock_irqsave(&ha->smp_lock, flags);
  3996. ha->hdr[i].devtype = (status == S_OK ? (u16)info : 0);
  3997. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3998. cmd->Service = CACHESERVICE;
  3999. cmd->OpCode = GDT_CLUST_INFO;
  4000. if (ha->cache_feat & GDT_64BIT)
  4001. cmd->u.cache64.DeviceNo = i;
  4002. else
  4003. cmd->u.cache.DeviceNo = i;
  4004. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4005. spin_lock_irqsave(&ha->smp_lock, flags);
  4006. ha->hdr[i].cluster_type =
  4007. ((status == S_OK && !shared_access) ? (u16)info : 0);
  4008. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4009. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4010. cmd->Service = CACHESERVICE;
  4011. cmd->OpCode = GDT_RW_ATTRIBS;
  4012. if (ha->cache_feat & GDT_64BIT)
  4013. cmd->u.cache64.DeviceNo = i;
  4014. else
  4015. cmd->u.cache.DeviceNo = i;
  4016. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4017. spin_lock_irqsave(&ha->smp_lock, flags);
  4018. ha->hdr[i].rw_attribs = (status == S_OK ? (u16)info : 0);
  4019. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4020. }
  4021. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4022. rc = -EFAULT;
  4023. else
  4024. rc = 0;
  4025. free_fail:
  4026. kfree(rsc);
  4027. kfree(cmd);
  4028. return rc;
  4029. }
  4030. static int gdth_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
  4031. {
  4032. gdth_ha_str *ha;
  4033. Scsi_Cmnd *scp;
  4034. unsigned long flags;
  4035. char cmnd[MAX_COMMAND_SIZE];
  4036. void __user *argp = (void __user *)arg;
  4037. memset(cmnd, 0xff, 12);
  4038. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4039. switch (cmd) {
  4040. case GDTIOCTL_CTRCNT:
  4041. {
  4042. int cnt = gdth_ctr_count;
  4043. if (put_user(cnt, (int __user *)argp))
  4044. return -EFAULT;
  4045. break;
  4046. }
  4047. case GDTIOCTL_DRVERS:
  4048. {
  4049. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4050. if (put_user(ver, (int __user *)argp))
  4051. return -EFAULT;
  4052. break;
  4053. }
  4054. case GDTIOCTL_OSVERS:
  4055. {
  4056. gdth_ioctl_osvers osv;
  4057. osv.version = (u8)(LINUX_VERSION_CODE >> 16);
  4058. osv.subversion = (u8)(LINUX_VERSION_CODE >> 8);
  4059. osv.revision = (u16)(LINUX_VERSION_CODE & 0xff);
  4060. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4061. return -EFAULT;
  4062. break;
  4063. }
  4064. case GDTIOCTL_CTRTYPE:
  4065. {
  4066. gdth_ioctl_ctrtype ctrt;
  4067. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4068. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4069. return -EFAULT;
  4070. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4071. ctrt.type = (u8)((ha->stype>>20) - 0x10);
  4072. } else {
  4073. if (ha->type != GDT_PCIMPR) {
  4074. ctrt.type = (u8)((ha->stype<<4) + 6);
  4075. } else {
  4076. ctrt.type =
  4077. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4078. if (ha->stype >= 0x300)
  4079. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4080. else
  4081. ctrt.ext_type = 0x6000 | ha->stype;
  4082. }
  4083. ctrt.device_id = ha->pdev->device;
  4084. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4085. }
  4086. ctrt.info = ha->brd_phys;
  4087. ctrt.oem_id = ha->oem_id;
  4088. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4089. return -EFAULT;
  4090. break;
  4091. }
  4092. case GDTIOCTL_GENERAL:
  4093. return ioc_general(argp, cmnd);
  4094. case GDTIOCTL_EVENT:
  4095. return ioc_event(argp);
  4096. case GDTIOCTL_LOCKDRV:
  4097. return ioc_lockdrv(argp);
  4098. case GDTIOCTL_LOCKCHN:
  4099. {
  4100. gdth_ioctl_lockchn lchn;
  4101. u8 i, j;
  4102. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4103. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4104. return -EFAULT;
  4105. i = lchn.channel;
  4106. if (i < ha->bus_cnt) {
  4107. if (lchn.lock) {
  4108. spin_lock_irqsave(&ha->smp_lock, flags);
  4109. ha->raw[i].lock = 1;
  4110. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4111. for (j = 0; j < ha->tid_cnt; ++j)
  4112. gdth_wait_completion(ha, i, j);
  4113. } else {
  4114. spin_lock_irqsave(&ha->smp_lock, flags);
  4115. ha->raw[i].lock = 0;
  4116. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4117. for (j = 0; j < ha->tid_cnt; ++j)
  4118. gdth_next(ha);
  4119. }
  4120. }
  4121. break;
  4122. }
  4123. case GDTIOCTL_RESCAN:
  4124. return ioc_rescan(argp, cmnd);
  4125. case GDTIOCTL_HDRLIST:
  4126. return ioc_hdrlist(argp, cmnd);
  4127. case GDTIOCTL_RESET_BUS:
  4128. {
  4129. gdth_ioctl_reset res;
  4130. int rval;
  4131. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4132. (NULL == (ha = gdth_find_ha(res.ionode))))
  4133. return -EFAULT;
  4134. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4135. if (!scp)
  4136. return -ENOMEM;
  4137. scp->device = ha->sdev;
  4138. scp->cmd_len = 12;
  4139. scp->device->channel = res.number;
  4140. rval = gdth_eh_bus_reset(scp);
  4141. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4142. kfree(scp);
  4143. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4144. return -EFAULT;
  4145. break;
  4146. }
  4147. case GDTIOCTL_RESET_DRV:
  4148. return ioc_resetdrv(argp, cmnd);
  4149. default:
  4150. break;
  4151. }
  4152. return 0;
  4153. }
  4154. static long gdth_unlocked_ioctl(struct file *file, unsigned int cmd,
  4155. unsigned long arg)
  4156. {
  4157. int ret;
  4158. mutex_lock(&gdth_mutex);
  4159. ret = gdth_ioctl(file, cmd, arg);
  4160. mutex_unlock(&gdth_mutex);
  4161. return ret;
  4162. }
  4163. /* flush routine */
  4164. static void gdth_flush(gdth_ha_str *ha)
  4165. {
  4166. int i;
  4167. gdth_cmd_str gdtcmd;
  4168. char cmnd[MAX_COMMAND_SIZE];
  4169. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4170. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4171. for (i = 0; i < MAX_HDRIVES; ++i) {
  4172. if (ha->hdr[i].present) {
  4173. gdtcmd.BoardNode = LOCALBOARD;
  4174. gdtcmd.Service = CACHESERVICE;
  4175. gdtcmd.OpCode = GDT_FLUSH;
  4176. if (ha->cache_feat & GDT_64BIT) {
  4177. gdtcmd.u.cache64.DeviceNo = i;
  4178. gdtcmd.u.cache64.BlockNo = 1;
  4179. gdtcmd.u.cache64.sg_canz = 0;
  4180. } else {
  4181. gdtcmd.u.cache.DeviceNo = i;
  4182. gdtcmd.u.cache.BlockNo = 1;
  4183. gdtcmd.u.cache.sg_canz = 0;
  4184. }
  4185. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4186. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4187. }
  4188. }
  4189. }
  4190. /* configure lun */
  4191. static int gdth_slave_configure(struct scsi_device *sdev)
  4192. {
  4193. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4194. sdev->skip_ms_page_3f = 1;
  4195. sdev->skip_ms_page_8 = 1;
  4196. return 0;
  4197. }
  4198. static struct scsi_host_template gdth_template = {
  4199. .name = "GDT SCSI Disk Array Controller",
  4200. .info = gdth_info,
  4201. .queuecommand = gdth_queuecommand,
  4202. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4203. .slave_configure = gdth_slave_configure,
  4204. .bios_param = gdth_bios_param,
  4205. .proc_info = gdth_proc_info,
  4206. .eh_timed_out = gdth_timed_out,
  4207. .proc_name = "gdth",
  4208. .can_queue = GDTH_MAXCMDS,
  4209. .this_id = -1,
  4210. .sg_tablesize = GDTH_MAXSG,
  4211. .cmd_per_lun = GDTH_MAXC_P_L,
  4212. .unchecked_isa_dma = 1,
  4213. .use_clustering = ENABLE_CLUSTERING,
  4214. };
  4215. #ifdef CONFIG_ISA
  4216. static int __init gdth_isa_probe_one(u32 isa_bios)
  4217. {
  4218. struct Scsi_Host *shp;
  4219. gdth_ha_str *ha;
  4220. dma_addr_t scratch_dma_handle = 0;
  4221. int error, i;
  4222. if (!gdth_search_isa(isa_bios))
  4223. return -ENXIO;
  4224. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4225. if (!shp)
  4226. return -ENOMEM;
  4227. ha = shost_priv(shp);
  4228. error = -ENODEV;
  4229. if (!gdth_init_isa(isa_bios,ha))
  4230. goto out_host_put;
  4231. /* controller found and initialized */
  4232. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4233. isa_bios, ha->irq, ha->drq);
  4234. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4235. if (error) {
  4236. printk("GDT-ISA: Unable to allocate IRQ\n");
  4237. goto out_host_put;
  4238. }
  4239. error = request_dma(ha->drq, "gdth");
  4240. if (error) {
  4241. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4242. goto out_free_irq;
  4243. }
  4244. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4245. enable_dma(ha->drq);
  4246. shp->unchecked_isa_dma = 1;
  4247. shp->irq = ha->irq;
  4248. shp->dma_channel = ha->drq;
  4249. ha->hanum = gdth_ctr_count++;
  4250. ha->shost = shp;
  4251. ha->pccb = &ha->cmdext;
  4252. ha->ccb_phys = 0L;
  4253. ha->pdev = NULL;
  4254. error = -ENOMEM;
  4255. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4256. &scratch_dma_handle);
  4257. if (!ha->pscratch)
  4258. goto out_dec_counters;
  4259. ha->scratch_phys = scratch_dma_handle;
  4260. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4261. &scratch_dma_handle);
  4262. if (!ha->pmsg)
  4263. goto out_free_pscratch;
  4264. ha->msg_phys = scratch_dma_handle;
  4265. #ifdef INT_COAL
  4266. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4267. sizeof(gdth_coal_status) * MAXOFFSETS,
  4268. &scratch_dma_handle);
  4269. if (!ha->coal_stat)
  4270. goto out_free_pmsg;
  4271. ha->coal_stat_phys = scratch_dma_handle;
  4272. #endif
  4273. ha->scratch_busy = FALSE;
  4274. ha->req_first = NULL;
  4275. ha->tid_cnt = MAX_HDRIVES;
  4276. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4277. ha->tid_cnt = max_ids;
  4278. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4279. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4280. ha->scan_mode = rescan ? 0x10 : 0;
  4281. error = -ENODEV;
  4282. if (!gdth_search_drives(ha)) {
  4283. printk("GDT-ISA: Error during device scan\n");
  4284. goto out_free_coal_stat;
  4285. }
  4286. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4287. hdr_channel = ha->bus_cnt;
  4288. ha->virt_bus = hdr_channel;
  4289. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4290. shp->max_cmd_len = 16;
  4291. shp->max_id = ha->tid_cnt;
  4292. shp->max_lun = MAXLUN;
  4293. shp->max_channel = ha->bus_cnt;
  4294. spin_lock_init(&ha->smp_lock);
  4295. gdth_enable_int(ha);
  4296. error = scsi_add_host(shp, NULL);
  4297. if (error)
  4298. goto out_free_coal_stat;
  4299. list_add_tail(&ha->list, &gdth_instances);
  4300. gdth_timer_init();
  4301. scsi_scan_host(shp);
  4302. return 0;
  4303. out_free_coal_stat:
  4304. #ifdef INT_COAL
  4305. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4306. ha->coal_stat, ha->coal_stat_phys);
  4307. out_free_pmsg:
  4308. #endif
  4309. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4310. ha->pmsg, ha->msg_phys);
  4311. out_free_pscratch:
  4312. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4313. ha->pscratch, ha->scratch_phys);
  4314. out_dec_counters:
  4315. gdth_ctr_count--;
  4316. out_free_irq:
  4317. free_irq(ha->irq, ha);
  4318. out_host_put:
  4319. scsi_host_put(shp);
  4320. return error;
  4321. }
  4322. #endif /* CONFIG_ISA */
  4323. #ifdef CONFIG_EISA
  4324. static int __init gdth_eisa_probe_one(u16 eisa_slot)
  4325. {
  4326. struct Scsi_Host *shp;
  4327. gdth_ha_str *ha;
  4328. dma_addr_t scratch_dma_handle = 0;
  4329. int error, i;
  4330. if (!gdth_search_eisa(eisa_slot))
  4331. return -ENXIO;
  4332. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4333. if (!shp)
  4334. return -ENOMEM;
  4335. ha = shost_priv(shp);
  4336. error = -ENODEV;
  4337. if (!gdth_init_eisa(eisa_slot,ha))
  4338. goto out_host_put;
  4339. /* controller found and initialized */
  4340. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4341. eisa_slot >> 12, ha->irq);
  4342. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4343. if (error) {
  4344. printk("GDT-EISA: Unable to allocate IRQ\n");
  4345. goto out_host_put;
  4346. }
  4347. shp->unchecked_isa_dma = 0;
  4348. shp->irq = ha->irq;
  4349. shp->dma_channel = 0xff;
  4350. ha->hanum = gdth_ctr_count++;
  4351. ha->shost = shp;
  4352. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4353. ha->pccb = &ha->cmdext;
  4354. ha->ccb_phys = 0L;
  4355. error = -ENOMEM;
  4356. ha->pdev = NULL;
  4357. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4358. &scratch_dma_handle);
  4359. if (!ha->pscratch)
  4360. goto out_free_irq;
  4361. ha->scratch_phys = scratch_dma_handle;
  4362. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4363. &scratch_dma_handle);
  4364. if (!ha->pmsg)
  4365. goto out_free_pscratch;
  4366. ha->msg_phys = scratch_dma_handle;
  4367. #ifdef INT_COAL
  4368. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4369. sizeof(gdth_coal_status) * MAXOFFSETS,
  4370. &scratch_dma_handle);
  4371. if (!ha->coal_stat)
  4372. goto out_free_pmsg;
  4373. ha->coal_stat_phys = scratch_dma_handle;
  4374. #endif
  4375. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4376. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4377. if (!ha->ccb_phys)
  4378. goto out_free_coal_stat;
  4379. ha->scratch_busy = FALSE;
  4380. ha->req_first = NULL;
  4381. ha->tid_cnt = MAX_HDRIVES;
  4382. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4383. ha->tid_cnt = max_ids;
  4384. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4385. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4386. ha->scan_mode = rescan ? 0x10 : 0;
  4387. if (!gdth_search_drives(ha)) {
  4388. printk("GDT-EISA: Error during device scan\n");
  4389. error = -ENODEV;
  4390. goto out_free_ccb_phys;
  4391. }
  4392. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4393. hdr_channel = ha->bus_cnt;
  4394. ha->virt_bus = hdr_channel;
  4395. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4396. shp->max_cmd_len = 16;
  4397. shp->max_id = ha->tid_cnt;
  4398. shp->max_lun = MAXLUN;
  4399. shp->max_channel = ha->bus_cnt;
  4400. spin_lock_init(&ha->smp_lock);
  4401. gdth_enable_int(ha);
  4402. error = scsi_add_host(shp, NULL);
  4403. if (error)
  4404. goto out_free_ccb_phys;
  4405. list_add_tail(&ha->list, &gdth_instances);
  4406. gdth_timer_init();
  4407. scsi_scan_host(shp);
  4408. return 0;
  4409. out_free_ccb_phys:
  4410. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4411. PCI_DMA_BIDIRECTIONAL);
  4412. out_free_coal_stat:
  4413. #ifdef INT_COAL
  4414. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4415. ha->coal_stat, ha->coal_stat_phys);
  4416. out_free_pmsg:
  4417. #endif
  4418. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4419. ha->pmsg, ha->msg_phys);
  4420. out_free_pscratch:
  4421. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4422. ha->pscratch, ha->scratch_phys);
  4423. out_free_irq:
  4424. free_irq(ha->irq, ha);
  4425. gdth_ctr_count--;
  4426. out_host_put:
  4427. scsi_host_put(shp);
  4428. return error;
  4429. }
  4430. #endif /* CONFIG_EISA */
  4431. #ifdef CONFIG_PCI
  4432. static int __devinit gdth_pci_probe_one(gdth_pci_str *pcistr,
  4433. gdth_ha_str **ha_out)
  4434. {
  4435. struct Scsi_Host *shp;
  4436. gdth_ha_str *ha;
  4437. dma_addr_t scratch_dma_handle = 0;
  4438. int error, i;
  4439. struct pci_dev *pdev = pcistr->pdev;
  4440. *ha_out = NULL;
  4441. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4442. if (!shp)
  4443. return -ENOMEM;
  4444. ha = shost_priv(shp);
  4445. error = -ENODEV;
  4446. if (!gdth_init_pci(pdev, pcistr, ha))
  4447. goto out_host_put;
  4448. /* controller found and initialized */
  4449. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4450. pdev->bus->number,
  4451. PCI_SLOT(pdev->devfn),
  4452. ha->irq);
  4453. error = request_irq(ha->irq, gdth_interrupt,
  4454. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4455. if (error) {
  4456. printk("GDT-PCI: Unable to allocate IRQ\n");
  4457. goto out_host_put;
  4458. }
  4459. shp->unchecked_isa_dma = 0;
  4460. shp->irq = ha->irq;
  4461. shp->dma_channel = 0xff;
  4462. ha->hanum = gdth_ctr_count++;
  4463. ha->shost = shp;
  4464. ha->pccb = &ha->cmdext;
  4465. ha->ccb_phys = 0L;
  4466. error = -ENOMEM;
  4467. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4468. &scratch_dma_handle);
  4469. if (!ha->pscratch)
  4470. goto out_free_irq;
  4471. ha->scratch_phys = scratch_dma_handle;
  4472. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4473. &scratch_dma_handle);
  4474. if (!ha->pmsg)
  4475. goto out_free_pscratch;
  4476. ha->msg_phys = scratch_dma_handle;
  4477. #ifdef INT_COAL
  4478. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4479. sizeof(gdth_coal_status) * MAXOFFSETS,
  4480. &scratch_dma_handle);
  4481. if (!ha->coal_stat)
  4482. goto out_free_pmsg;
  4483. ha->coal_stat_phys = scratch_dma_handle;
  4484. #endif
  4485. ha->scratch_busy = FALSE;
  4486. ha->req_first = NULL;
  4487. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4488. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4489. ha->tid_cnt = max_ids;
  4490. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4491. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4492. ha->scan_mode = rescan ? 0x10 : 0;
  4493. error = -ENODEV;
  4494. if (!gdth_search_drives(ha)) {
  4495. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4496. goto out_free_coal_stat;
  4497. }
  4498. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4499. hdr_channel = ha->bus_cnt;
  4500. ha->virt_bus = hdr_channel;
  4501. /* 64-bit DMA only supported from FW >= x.43 */
  4502. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4503. !ha->dma64_support) {
  4504. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4505. printk(KERN_WARNING "GDT-PCI %d: "
  4506. "Unable to set 32-bit DMA\n", ha->hanum);
  4507. goto out_free_coal_stat;
  4508. }
  4509. } else {
  4510. shp->max_cmd_len = 16;
  4511. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4512. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4513. } else if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  4514. printk(KERN_WARNING "GDT-PCI %d: "
  4515. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4516. goto out_free_coal_stat;
  4517. }
  4518. }
  4519. shp->max_id = ha->tid_cnt;
  4520. shp->max_lun = MAXLUN;
  4521. shp->max_channel = ha->bus_cnt;
  4522. spin_lock_init(&ha->smp_lock);
  4523. gdth_enable_int(ha);
  4524. error = scsi_add_host(shp, &pdev->dev);
  4525. if (error)
  4526. goto out_free_coal_stat;
  4527. list_add_tail(&ha->list, &gdth_instances);
  4528. pci_set_drvdata(ha->pdev, ha);
  4529. gdth_timer_init();
  4530. scsi_scan_host(shp);
  4531. *ha_out = ha;
  4532. return 0;
  4533. out_free_coal_stat:
  4534. #ifdef INT_COAL
  4535. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4536. ha->coal_stat, ha->coal_stat_phys);
  4537. out_free_pmsg:
  4538. #endif
  4539. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4540. ha->pmsg, ha->msg_phys);
  4541. out_free_pscratch:
  4542. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4543. ha->pscratch, ha->scratch_phys);
  4544. out_free_irq:
  4545. free_irq(ha->irq, ha);
  4546. gdth_ctr_count--;
  4547. out_host_put:
  4548. scsi_host_put(shp);
  4549. return error;
  4550. }
  4551. #endif /* CONFIG_PCI */
  4552. static void gdth_remove_one(gdth_ha_str *ha)
  4553. {
  4554. struct Scsi_Host *shp = ha->shost;
  4555. TRACE2(("gdth_remove_one()\n"));
  4556. scsi_remove_host(shp);
  4557. gdth_flush(ha);
  4558. if (ha->sdev) {
  4559. scsi_free_host_dev(ha->sdev);
  4560. ha->sdev = NULL;
  4561. }
  4562. if (shp->irq)
  4563. free_irq(shp->irq,ha);
  4564. #ifdef CONFIG_ISA
  4565. if (shp->dma_channel != 0xff)
  4566. free_dma(shp->dma_channel);
  4567. #endif
  4568. #ifdef INT_COAL
  4569. if (ha->coal_stat)
  4570. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4571. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4572. #endif
  4573. if (ha->pscratch)
  4574. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4575. ha->pscratch, ha->scratch_phys);
  4576. if (ha->pmsg)
  4577. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4578. ha->pmsg, ha->msg_phys);
  4579. if (ha->ccb_phys)
  4580. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4581. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4582. scsi_host_put(shp);
  4583. }
  4584. static int gdth_halt(struct notifier_block *nb, unsigned long event, void *buf)
  4585. {
  4586. gdth_ha_str *ha;
  4587. TRACE2(("gdth_halt() event %d\n", (int)event));
  4588. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4589. return NOTIFY_DONE;
  4590. list_for_each_entry(ha, &gdth_instances, list)
  4591. gdth_flush(ha);
  4592. return NOTIFY_OK;
  4593. }
  4594. static struct notifier_block gdth_notifier = {
  4595. gdth_halt, NULL, 0
  4596. };
  4597. static int __init gdth_init(void)
  4598. {
  4599. if (disable) {
  4600. printk("GDT-HA: Controller driver disabled from"
  4601. " command line !\n");
  4602. return 0;
  4603. }
  4604. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4605. GDTH_VERSION_STR);
  4606. /* initializations */
  4607. gdth_polling = TRUE;
  4608. gdth_clear_events();
  4609. init_timer(&gdth_timer);
  4610. /* As default we do not probe for EISA or ISA controllers */
  4611. if (probe_eisa_isa) {
  4612. /* scanning for controllers, at first: ISA controller */
  4613. #ifdef CONFIG_ISA
  4614. u32 isa_bios;
  4615. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4616. isa_bios += 0x8000UL)
  4617. gdth_isa_probe_one(isa_bios);
  4618. #endif
  4619. #ifdef CONFIG_EISA
  4620. {
  4621. u16 eisa_slot;
  4622. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4623. eisa_slot += 0x1000)
  4624. gdth_eisa_probe_one(eisa_slot);
  4625. }
  4626. #endif
  4627. }
  4628. #ifdef CONFIG_PCI
  4629. /* scanning for PCI controllers */
  4630. if (pci_register_driver(&gdth_pci_driver)) {
  4631. gdth_ha_str *ha;
  4632. list_for_each_entry(ha, &gdth_instances, list)
  4633. gdth_remove_one(ha);
  4634. return -ENODEV;
  4635. }
  4636. #endif /* CONFIG_PCI */
  4637. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4638. major = register_chrdev(0,"gdth", &gdth_fops);
  4639. register_reboot_notifier(&gdth_notifier);
  4640. gdth_polling = FALSE;
  4641. return 0;
  4642. }
  4643. static void __exit gdth_exit(void)
  4644. {
  4645. gdth_ha_str *ha;
  4646. unregister_chrdev(major, "gdth");
  4647. unregister_reboot_notifier(&gdth_notifier);
  4648. #ifdef GDTH_STATISTICS
  4649. del_timer_sync(&gdth_timer);
  4650. #endif
  4651. #ifdef CONFIG_PCI
  4652. pci_unregister_driver(&gdth_pci_driver);
  4653. #endif
  4654. list_for_each_entry(ha, &gdth_instances, list)
  4655. gdth_remove_one(ha);
  4656. }
  4657. module_init(gdth_init);
  4658. module_exit(gdth_exit);
  4659. #ifndef MODULE
  4660. __setup("gdth=", option_setup);
  4661. #endif