spi-s3c64xx.c 44 KB

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  1. /*
  2. * Copyright (C) 2009 Samsung Electronics Ltd.
  3. * Jaswinder Singh <jassi.brar@samsung.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/delay.h>
  24. #include <linux/clk.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/dmaengine.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/spi/spi.h>
  30. #include <linux/gpio.h>
  31. #include <linux/of.h>
  32. #include <linux/of_gpio.h>
  33. #include <linux/platform_data/spi-s3c64xx.h>
  34. #ifdef CONFIG_S3C_DMA
  35. #include <mach/dma.h>
  36. #endif
  37. #define MAX_SPI_PORTS 3
  38. #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
  39. /* Registers and bit-fields */
  40. #define S3C64XX_SPI_CH_CFG 0x00
  41. #define S3C64XX_SPI_CLK_CFG 0x04
  42. #define S3C64XX_SPI_MODE_CFG 0x08
  43. #define S3C64XX_SPI_SLAVE_SEL 0x0C
  44. #define S3C64XX_SPI_INT_EN 0x10
  45. #define S3C64XX_SPI_STATUS 0x14
  46. #define S3C64XX_SPI_TX_DATA 0x18
  47. #define S3C64XX_SPI_RX_DATA 0x1C
  48. #define S3C64XX_SPI_PACKET_CNT 0x20
  49. #define S3C64XX_SPI_PENDING_CLR 0x24
  50. #define S3C64XX_SPI_SWAP_CFG 0x28
  51. #define S3C64XX_SPI_FB_CLK 0x2C
  52. #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
  53. #define S3C64XX_SPI_CH_SW_RST (1<<5)
  54. #define S3C64XX_SPI_CH_SLAVE (1<<4)
  55. #define S3C64XX_SPI_CPOL_L (1<<3)
  56. #define S3C64XX_SPI_CPHA_B (1<<2)
  57. #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
  58. #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
  59. #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
  60. #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
  61. #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
  62. #define S3C64XX_SPI_PSR_MASK 0xff
  63. #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
  64. #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
  65. #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
  66. #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
  67. #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
  68. #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
  69. #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
  70. #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
  71. #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
  72. #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
  73. #define S3C64XX_SPI_MODE_4BURST (1<<0)
  74. #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
  75. #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
  76. #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
  77. #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
  78. #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
  79. #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
  80. #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
  81. #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
  82. #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
  83. #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
  84. #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
  85. #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
  86. #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
  87. #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
  88. #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
  89. #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
  90. #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
  91. #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
  92. #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
  93. #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
  94. #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
  95. #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
  96. #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
  97. #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
  98. #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
  99. #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
  100. #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
  101. #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
  102. #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
  103. #define S3C64XX_SPI_FBCLK_MSK (3<<0)
  104. #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
  105. #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
  106. (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
  107. #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
  108. #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
  109. FIFO_LVL_MASK(i))
  110. #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
  111. #define S3C64XX_SPI_TRAILCNT_OFF 19
  112. #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
  113. #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
  114. #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
  115. #define RXBUSY (1<<2)
  116. #define TXBUSY (1<<3)
  117. struct s3c64xx_spi_dma_data {
  118. struct dma_chan *ch;
  119. enum dma_transfer_direction direction;
  120. unsigned int dmach;
  121. };
  122. /**
  123. * struct s3c64xx_spi_info - SPI Controller hardware info
  124. * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
  125. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
  126. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
  127. * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
  128. * @clk_from_cmu: True, if the controller does not include a clock mux and
  129. * prescaler unit.
  130. *
  131. * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
  132. * differ in some aspects such as the size of the fifo and spi bus clock
  133. * setup. Such differences are specified to the driver using this structure
  134. * which is provided as driver data to the driver.
  135. */
  136. struct s3c64xx_spi_port_config {
  137. int fifo_lvl_mask[MAX_SPI_PORTS];
  138. int rx_lvl_offset;
  139. int tx_st_done;
  140. int quirks;
  141. bool high_speed;
  142. bool clk_from_cmu;
  143. };
  144. /**
  145. * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
  146. * @clk: Pointer to the spi clock.
  147. * @src_clk: Pointer to the clock used to generate SPI signals.
  148. * @master: Pointer to the SPI Protocol master.
  149. * @cntrlr_info: Platform specific data for the controller this driver manages.
  150. * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
  151. * @queue: To log SPI xfer requests.
  152. * @lock: Controller specific lock.
  153. * @state: Set of FLAGS to indicate status.
  154. * @rx_dmach: Controller's DMA channel for Rx.
  155. * @tx_dmach: Controller's DMA channel for Tx.
  156. * @sfr_start: BUS address of SPI controller regs.
  157. * @regs: Pointer to ioremap'ed controller registers.
  158. * @irq: interrupt
  159. * @xfer_completion: To indicate completion of xfer task.
  160. * @cur_mode: Stores the active configuration of the controller.
  161. * @cur_bpw: Stores the active bits per word settings.
  162. * @cur_speed: Stores the active xfer clock speed.
  163. */
  164. struct s3c64xx_spi_driver_data {
  165. void __iomem *regs;
  166. struct clk *clk;
  167. struct clk *src_clk;
  168. struct platform_device *pdev;
  169. struct spi_master *master;
  170. struct s3c64xx_spi_info *cntrlr_info;
  171. struct spi_device *tgl_spi;
  172. struct list_head queue;
  173. spinlock_t lock;
  174. unsigned long sfr_start;
  175. struct completion xfer_completion;
  176. unsigned state;
  177. unsigned cur_mode, cur_bpw;
  178. unsigned cur_speed;
  179. struct s3c64xx_spi_dma_data rx_dma;
  180. struct s3c64xx_spi_dma_data tx_dma;
  181. #ifdef CONFIG_S3C_DMA
  182. struct samsung_dma_ops *ops;
  183. #endif
  184. struct s3c64xx_spi_port_config *port_conf;
  185. unsigned int port_id;
  186. unsigned long gpios[4];
  187. bool cs_gpio;
  188. };
  189. static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
  190. {
  191. void __iomem *regs = sdd->regs;
  192. unsigned long loops;
  193. u32 val;
  194. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  195. val = readl(regs + S3C64XX_SPI_CH_CFG);
  196. val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
  197. writel(val, regs + S3C64XX_SPI_CH_CFG);
  198. val = readl(regs + S3C64XX_SPI_CH_CFG);
  199. val |= S3C64XX_SPI_CH_SW_RST;
  200. val &= ~S3C64XX_SPI_CH_HS_EN;
  201. writel(val, regs + S3C64XX_SPI_CH_CFG);
  202. /* Flush TxFIFO*/
  203. loops = msecs_to_loops(1);
  204. do {
  205. val = readl(regs + S3C64XX_SPI_STATUS);
  206. } while (TX_FIFO_LVL(val, sdd) && loops--);
  207. if (loops == 0)
  208. dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
  209. /* Flush RxFIFO*/
  210. loops = msecs_to_loops(1);
  211. do {
  212. val = readl(regs + S3C64XX_SPI_STATUS);
  213. if (RX_FIFO_LVL(val, sdd))
  214. readl(regs + S3C64XX_SPI_RX_DATA);
  215. else
  216. break;
  217. } while (loops--);
  218. if (loops == 0)
  219. dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
  220. val = readl(regs + S3C64XX_SPI_CH_CFG);
  221. val &= ~S3C64XX_SPI_CH_SW_RST;
  222. writel(val, regs + S3C64XX_SPI_CH_CFG);
  223. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  224. val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  225. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  226. }
  227. static void s3c64xx_spi_dmacb(void *data)
  228. {
  229. struct s3c64xx_spi_driver_data *sdd;
  230. struct s3c64xx_spi_dma_data *dma = data;
  231. unsigned long flags;
  232. if (dma->direction == DMA_DEV_TO_MEM)
  233. sdd = container_of(data,
  234. struct s3c64xx_spi_driver_data, rx_dma);
  235. else
  236. sdd = container_of(data,
  237. struct s3c64xx_spi_driver_data, tx_dma);
  238. spin_lock_irqsave(&sdd->lock, flags);
  239. if (dma->direction == DMA_DEV_TO_MEM) {
  240. sdd->state &= ~RXBUSY;
  241. if (!(sdd->state & TXBUSY))
  242. complete(&sdd->xfer_completion);
  243. } else {
  244. sdd->state &= ~TXBUSY;
  245. if (!(sdd->state & RXBUSY))
  246. complete(&sdd->xfer_completion);
  247. }
  248. spin_unlock_irqrestore(&sdd->lock, flags);
  249. }
  250. #ifdef CONFIG_S3C_DMA
  251. /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
  252. static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
  253. .name = "samsung-spi-dma",
  254. };
  255. static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
  256. unsigned len, dma_addr_t buf)
  257. {
  258. struct s3c64xx_spi_driver_data *sdd;
  259. struct samsung_dma_prep info;
  260. struct samsung_dma_config config;
  261. if (dma->direction == DMA_DEV_TO_MEM) {
  262. sdd = container_of((void *)dma,
  263. struct s3c64xx_spi_driver_data, rx_dma);
  264. config.direction = sdd->rx_dma.direction;
  265. config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
  266. config.width = sdd->cur_bpw / 8;
  267. sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
  268. } else {
  269. sdd = container_of((void *)dma,
  270. struct s3c64xx_spi_driver_data, tx_dma);
  271. config.direction = sdd->tx_dma.direction;
  272. config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
  273. config.width = sdd->cur_bpw / 8;
  274. sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
  275. }
  276. info.cap = DMA_SLAVE;
  277. info.len = len;
  278. info.fp = s3c64xx_spi_dmacb;
  279. info.fp_param = dma;
  280. info.direction = dma->direction;
  281. info.buf = buf;
  282. sdd->ops->prepare((enum dma_ch)dma->ch, &info);
  283. sdd->ops->trigger((enum dma_ch)dma->ch);
  284. }
  285. static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
  286. {
  287. struct samsung_dma_req req;
  288. struct device *dev = &sdd->pdev->dev;
  289. sdd->ops = samsung_dma_get_ops();
  290. req.cap = DMA_SLAVE;
  291. req.client = &s3c64xx_spi_dma_client;
  292. sdd->rx_dma.ch = (void *)sdd->ops->request(sdd->rx_dma.dmach, &req, dev, "rx");
  293. sdd->tx_dma.ch = (void *)sdd->ops->request(sdd->tx_dma.dmach, &req, dev, "tx");
  294. return 1;
  295. }
  296. static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
  297. {
  298. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  299. /*
  300. * If DMA resource was not available during
  301. * probe, no need to continue with dma requests
  302. * else Acquire DMA channels
  303. */
  304. while (!is_polling(sdd) && !acquire_dma(sdd))
  305. usleep_range(10000, 11000);
  306. pm_runtime_get_sync(&sdd->pdev->dev);
  307. return 0;
  308. }
  309. static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
  310. {
  311. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  312. /* Free DMA channels */
  313. if (!is_polling(sdd)) {
  314. sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
  315. &s3c64xx_spi_dma_client);
  316. sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
  317. &s3c64xx_spi_dma_client);
  318. }
  319. pm_runtime_put(&sdd->pdev->dev);
  320. return 0;
  321. }
  322. static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
  323. struct s3c64xx_spi_dma_data *dma)
  324. {
  325. sdd->ops->stop((enum dma_ch)dma->ch);
  326. }
  327. #else
  328. static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
  329. unsigned len, dma_addr_t buf)
  330. {
  331. struct s3c64xx_spi_driver_data *sdd;
  332. struct dma_slave_config config;
  333. struct scatterlist sg;
  334. struct dma_async_tx_descriptor *desc;
  335. if (dma->direction == DMA_DEV_TO_MEM) {
  336. sdd = container_of((void *)dma,
  337. struct s3c64xx_spi_driver_data, rx_dma);
  338. config.direction = dma->direction;
  339. config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
  340. config.src_addr_width = sdd->cur_bpw / 8;
  341. config.src_maxburst = 1;
  342. dmaengine_slave_config(dma->ch, &config);
  343. } else {
  344. sdd = container_of((void *)dma,
  345. struct s3c64xx_spi_driver_data, tx_dma);
  346. config.direction = dma->direction;
  347. config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
  348. config.dst_addr_width = sdd->cur_bpw / 8;
  349. config.dst_maxburst = 1;
  350. dmaengine_slave_config(dma->ch, &config);
  351. }
  352. sg_init_table(&sg, 1);
  353. sg_dma_len(&sg) = len;
  354. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf)),
  355. len, offset_in_page(buf));
  356. sg_dma_address(&sg) = buf;
  357. desc = dmaengine_prep_slave_sg(dma->ch,
  358. &sg, 1, dma->direction, DMA_PREP_INTERRUPT);
  359. desc->callback = s3c64xx_spi_dmacb;
  360. desc->callback_param = dma;
  361. dmaengine_submit(desc);
  362. dma_async_issue_pending(dma->ch);
  363. }
  364. static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
  365. {
  366. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  367. dma_filter_fn filter = sdd->cntrlr_info->filter;
  368. struct device *dev = &sdd->pdev->dev;
  369. dma_cap_mask_t mask;
  370. int ret;
  371. if (is_polling(sdd))
  372. return 0;
  373. dma_cap_zero(mask);
  374. dma_cap_set(DMA_SLAVE, mask);
  375. /* Acquire DMA channels */
  376. sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
  377. (void*)sdd->rx_dma.dmach, dev, "rx");
  378. if (!sdd->rx_dma.ch) {
  379. dev_err(dev, "Failed to get RX DMA channel\n");
  380. ret = -EBUSY;
  381. goto out;
  382. }
  383. sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
  384. (void*)sdd->tx_dma.dmach, dev, "tx");
  385. if (!sdd->tx_dma.ch) {
  386. dev_err(dev, "Failed to get TX DMA channel\n");
  387. ret = -EBUSY;
  388. goto out_rx;
  389. }
  390. ret = pm_runtime_get_sync(&sdd->pdev->dev);
  391. if (ret < 0) {
  392. dev_err(dev, "Failed to enable device: %d\n", ret);
  393. goto out_tx;
  394. }
  395. return 0;
  396. out_tx:
  397. dma_release_channel(sdd->tx_dma.ch);
  398. out_rx:
  399. dma_release_channel(sdd->rx_dma.ch);
  400. out:
  401. return ret;
  402. }
  403. static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
  404. {
  405. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
  406. /* Free DMA channels */
  407. if (!is_polling(sdd)) {
  408. dma_release_channel(sdd->rx_dma.ch);
  409. dma_release_channel(sdd->tx_dma.ch);
  410. }
  411. pm_runtime_put(&sdd->pdev->dev);
  412. return 0;
  413. }
  414. static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
  415. struct s3c64xx_spi_dma_data *dma)
  416. {
  417. dmaengine_terminate_all(dma->ch);
  418. }
  419. #endif
  420. static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
  421. struct spi_device *spi,
  422. struct spi_transfer *xfer, int dma_mode)
  423. {
  424. void __iomem *regs = sdd->regs;
  425. u32 modecfg, chcfg;
  426. modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
  427. modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
  428. chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
  429. chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
  430. if (dma_mode) {
  431. chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
  432. } else {
  433. /* Always shift in data in FIFO, even if xfer is Tx only,
  434. * this helps setting PCKT_CNT value for generating clocks
  435. * as exactly needed.
  436. */
  437. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  438. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  439. | S3C64XX_SPI_PACKET_CNT_EN,
  440. regs + S3C64XX_SPI_PACKET_CNT);
  441. }
  442. if (xfer->tx_buf != NULL) {
  443. sdd->state |= TXBUSY;
  444. chcfg |= S3C64XX_SPI_CH_TXCH_ON;
  445. if (dma_mode) {
  446. modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
  447. prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
  448. } else {
  449. switch (sdd->cur_bpw) {
  450. case 32:
  451. iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
  452. xfer->tx_buf, xfer->len / 4);
  453. break;
  454. case 16:
  455. iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
  456. xfer->tx_buf, xfer->len / 2);
  457. break;
  458. default:
  459. iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
  460. xfer->tx_buf, xfer->len);
  461. break;
  462. }
  463. }
  464. }
  465. if (xfer->rx_buf != NULL) {
  466. sdd->state |= RXBUSY;
  467. if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
  468. && !(sdd->cur_mode & SPI_CPHA))
  469. chcfg |= S3C64XX_SPI_CH_HS_EN;
  470. if (dma_mode) {
  471. modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
  472. chcfg |= S3C64XX_SPI_CH_RXCH_ON;
  473. writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
  474. | S3C64XX_SPI_PACKET_CNT_EN,
  475. regs + S3C64XX_SPI_PACKET_CNT);
  476. prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
  477. }
  478. }
  479. writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
  480. writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
  481. }
  482. static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
  483. struct spi_device *spi)
  484. {
  485. struct s3c64xx_spi_csinfo *cs;
  486. if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
  487. if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
  488. /* Deselect the last toggled device */
  489. cs = sdd->tgl_spi->controller_data;
  490. if (sdd->cs_gpio)
  491. gpio_set_value(cs->line,
  492. spi->mode & SPI_CS_HIGH ? 0 : 1);
  493. }
  494. sdd->tgl_spi = NULL;
  495. }
  496. cs = spi->controller_data;
  497. if (sdd->cs_gpio)
  498. gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
  499. /* Start the signals */
  500. writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
  501. }
  502. static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
  503. int timeout_ms)
  504. {
  505. void __iomem *regs = sdd->regs;
  506. unsigned long val = 1;
  507. u32 status;
  508. /* max fifo depth available */
  509. u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
  510. if (timeout_ms)
  511. val = msecs_to_loops(timeout_ms);
  512. do {
  513. status = readl(regs + S3C64XX_SPI_STATUS);
  514. } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
  515. /* return the actual received data length */
  516. return RX_FIFO_LVL(status, sdd);
  517. }
  518. static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
  519. struct spi_transfer *xfer, int dma_mode)
  520. {
  521. void __iomem *regs = sdd->regs;
  522. unsigned long val;
  523. int ms;
  524. /* millisecs to xfer 'len' bytes @ 'cur_speed' */
  525. ms = xfer->len * 8 * 1000 / sdd->cur_speed;
  526. ms += 10; /* some tolerance */
  527. if (dma_mode) {
  528. val = msecs_to_jiffies(ms) + 10;
  529. val = wait_for_completion_timeout(&sdd->xfer_completion, val);
  530. } else {
  531. u32 status;
  532. val = msecs_to_loops(ms);
  533. do {
  534. status = readl(regs + S3C64XX_SPI_STATUS);
  535. } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
  536. }
  537. if (dma_mode) {
  538. u32 status;
  539. /*
  540. * If the previous xfer was completed within timeout, then
  541. * proceed further else return -EIO.
  542. * DmaTx returns after simply writing data in the FIFO,
  543. * w/o waiting for real transmission on the bus to finish.
  544. * DmaRx returns only after Dma read data from FIFO which
  545. * needs bus transmission to finish, so we don't worry if
  546. * Xfer involved Rx(with or without Tx).
  547. */
  548. if (val && !xfer->rx_buf) {
  549. val = msecs_to_loops(10);
  550. status = readl(regs + S3C64XX_SPI_STATUS);
  551. while ((TX_FIFO_LVL(status, sdd)
  552. || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
  553. && --val) {
  554. cpu_relax();
  555. status = readl(regs + S3C64XX_SPI_STATUS);
  556. }
  557. }
  558. /* If timed out while checking rx/tx status return error */
  559. if (!val)
  560. return -EIO;
  561. } else {
  562. int loops;
  563. u32 cpy_len;
  564. u8 *buf;
  565. /* If it was only Tx */
  566. if (!xfer->rx_buf) {
  567. sdd->state &= ~TXBUSY;
  568. return 0;
  569. }
  570. /*
  571. * If the receive length is bigger than the controller fifo
  572. * size, calculate the loops and read the fifo as many times.
  573. * loops = length / max fifo size (calculated by using the
  574. * fifo mask).
  575. * For any size less than the fifo size the below code is
  576. * executed atleast once.
  577. */
  578. loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
  579. buf = xfer->rx_buf;
  580. do {
  581. /* wait for data to be received in the fifo */
  582. cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
  583. (loops ? ms : 0));
  584. switch (sdd->cur_bpw) {
  585. case 32:
  586. ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
  587. buf, cpy_len / 4);
  588. break;
  589. case 16:
  590. ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
  591. buf, cpy_len / 2);
  592. break;
  593. default:
  594. ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
  595. buf, cpy_len);
  596. break;
  597. }
  598. buf = buf + cpy_len;
  599. } while (loops--);
  600. sdd->state &= ~RXBUSY;
  601. }
  602. return 0;
  603. }
  604. static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
  605. struct spi_device *spi)
  606. {
  607. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  608. if (sdd->tgl_spi == spi)
  609. sdd->tgl_spi = NULL;
  610. if (sdd->cs_gpio)
  611. gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
  612. /* Quiese the signals */
  613. writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
  614. }
  615. static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
  616. {
  617. void __iomem *regs = sdd->regs;
  618. u32 val;
  619. /* Disable Clock */
  620. if (sdd->port_conf->clk_from_cmu) {
  621. clk_disable_unprepare(sdd->src_clk);
  622. } else {
  623. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  624. val &= ~S3C64XX_SPI_ENCLK_ENABLE;
  625. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  626. }
  627. /* Set Polarity and Phase */
  628. val = readl(regs + S3C64XX_SPI_CH_CFG);
  629. val &= ~(S3C64XX_SPI_CH_SLAVE |
  630. S3C64XX_SPI_CPOL_L |
  631. S3C64XX_SPI_CPHA_B);
  632. if (sdd->cur_mode & SPI_CPOL)
  633. val |= S3C64XX_SPI_CPOL_L;
  634. if (sdd->cur_mode & SPI_CPHA)
  635. val |= S3C64XX_SPI_CPHA_B;
  636. writel(val, regs + S3C64XX_SPI_CH_CFG);
  637. /* Set Channel & DMA Mode */
  638. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  639. val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
  640. | S3C64XX_SPI_MODE_CH_TSZ_MASK);
  641. switch (sdd->cur_bpw) {
  642. case 32:
  643. val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
  644. val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
  645. break;
  646. case 16:
  647. val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
  648. val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
  649. break;
  650. default:
  651. val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
  652. val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
  653. break;
  654. }
  655. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  656. if (sdd->port_conf->clk_from_cmu) {
  657. /* Configure Clock */
  658. /* There is half-multiplier before the SPI */
  659. clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
  660. /* Enable Clock */
  661. clk_prepare_enable(sdd->src_clk);
  662. } else {
  663. /* Configure Clock */
  664. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  665. val &= ~S3C64XX_SPI_PSR_MASK;
  666. val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
  667. & S3C64XX_SPI_PSR_MASK);
  668. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  669. /* Enable Clock */
  670. val = readl(regs + S3C64XX_SPI_CLK_CFG);
  671. val |= S3C64XX_SPI_ENCLK_ENABLE;
  672. writel(val, regs + S3C64XX_SPI_CLK_CFG);
  673. }
  674. }
  675. #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
  676. static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
  677. struct spi_message *msg)
  678. {
  679. struct device *dev = &sdd->pdev->dev;
  680. struct spi_transfer *xfer;
  681. if (is_polling(sdd) || msg->is_dma_mapped)
  682. return 0;
  683. /* First mark all xfer unmapped */
  684. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  685. xfer->rx_dma = XFER_DMAADDR_INVALID;
  686. xfer->tx_dma = XFER_DMAADDR_INVALID;
  687. }
  688. /* Map until end or first fail */
  689. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  690. if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
  691. continue;
  692. if (xfer->tx_buf != NULL) {
  693. xfer->tx_dma = dma_map_single(dev,
  694. (void *)xfer->tx_buf, xfer->len,
  695. DMA_TO_DEVICE);
  696. if (dma_mapping_error(dev, xfer->tx_dma)) {
  697. dev_err(dev, "dma_map_single Tx failed\n");
  698. xfer->tx_dma = XFER_DMAADDR_INVALID;
  699. return -ENOMEM;
  700. }
  701. }
  702. if (xfer->rx_buf != NULL) {
  703. xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
  704. xfer->len, DMA_FROM_DEVICE);
  705. if (dma_mapping_error(dev, xfer->rx_dma)) {
  706. dev_err(dev, "dma_map_single Rx failed\n");
  707. dma_unmap_single(dev, xfer->tx_dma,
  708. xfer->len, DMA_TO_DEVICE);
  709. xfer->tx_dma = XFER_DMAADDR_INVALID;
  710. xfer->rx_dma = XFER_DMAADDR_INVALID;
  711. return -ENOMEM;
  712. }
  713. }
  714. }
  715. return 0;
  716. }
  717. static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
  718. struct spi_message *msg)
  719. {
  720. struct device *dev = &sdd->pdev->dev;
  721. struct spi_transfer *xfer;
  722. if (is_polling(sdd) || msg->is_dma_mapped)
  723. return;
  724. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  725. if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
  726. continue;
  727. if (xfer->rx_buf != NULL
  728. && xfer->rx_dma != XFER_DMAADDR_INVALID)
  729. dma_unmap_single(dev, xfer->rx_dma,
  730. xfer->len, DMA_FROM_DEVICE);
  731. if (xfer->tx_buf != NULL
  732. && xfer->tx_dma != XFER_DMAADDR_INVALID)
  733. dma_unmap_single(dev, xfer->tx_dma,
  734. xfer->len, DMA_TO_DEVICE);
  735. }
  736. }
  737. static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
  738. struct spi_message *msg)
  739. {
  740. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  741. struct spi_device *spi = msg->spi;
  742. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  743. struct spi_transfer *xfer;
  744. int status = 0, cs_toggle = 0;
  745. u32 speed;
  746. u8 bpw;
  747. /* If Master's(controller) state differs from that needed by Slave */
  748. if (sdd->cur_speed != spi->max_speed_hz
  749. || sdd->cur_mode != spi->mode
  750. || sdd->cur_bpw != spi->bits_per_word) {
  751. sdd->cur_bpw = spi->bits_per_word;
  752. sdd->cur_speed = spi->max_speed_hz;
  753. sdd->cur_mode = spi->mode;
  754. s3c64xx_spi_config(sdd);
  755. }
  756. /* Map all the transfers if needed */
  757. if (s3c64xx_spi_map_mssg(sdd, msg)) {
  758. dev_err(&spi->dev,
  759. "Xfer: Unable to map message buffers!\n");
  760. status = -ENOMEM;
  761. goto out;
  762. }
  763. /* Configure feedback delay */
  764. writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
  765. list_for_each_entry(xfer, &msg->transfers, transfer_list) {
  766. unsigned long flags;
  767. int use_dma;
  768. INIT_COMPLETION(sdd->xfer_completion);
  769. /* Only BPW and Speed may change across transfers */
  770. bpw = xfer->bits_per_word;
  771. speed = xfer->speed_hz ? : spi->max_speed_hz;
  772. if (xfer->len % (bpw / 8)) {
  773. dev_err(&spi->dev,
  774. "Xfer length(%u) not a multiple of word size(%u)\n",
  775. xfer->len, bpw / 8);
  776. status = -EIO;
  777. goto out;
  778. }
  779. if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
  780. sdd->cur_bpw = bpw;
  781. sdd->cur_speed = speed;
  782. s3c64xx_spi_config(sdd);
  783. }
  784. /* Polling method for xfers not bigger than FIFO capacity */
  785. use_dma = 0;
  786. if (!is_polling(sdd) &&
  787. (sdd->rx_dma.ch && sdd->tx_dma.ch &&
  788. (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
  789. use_dma = 1;
  790. spin_lock_irqsave(&sdd->lock, flags);
  791. /* Pending only which is to be done */
  792. sdd->state &= ~RXBUSY;
  793. sdd->state &= ~TXBUSY;
  794. enable_datapath(sdd, spi, xfer, use_dma);
  795. /* Slave Select */
  796. enable_cs(sdd, spi);
  797. spin_unlock_irqrestore(&sdd->lock, flags);
  798. status = wait_for_xfer(sdd, xfer, use_dma);
  799. if (status) {
  800. dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
  801. xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
  802. (sdd->state & RXBUSY) ? 'f' : 'p',
  803. (sdd->state & TXBUSY) ? 'f' : 'p',
  804. xfer->len);
  805. if (use_dma) {
  806. if (xfer->tx_buf != NULL
  807. && (sdd->state & TXBUSY))
  808. s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
  809. if (xfer->rx_buf != NULL
  810. && (sdd->state & RXBUSY))
  811. s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
  812. }
  813. goto out;
  814. }
  815. if (xfer->delay_usecs)
  816. udelay(xfer->delay_usecs);
  817. if (xfer->cs_change) {
  818. /* Hint that the next mssg is gonna be
  819. for the same device */
  820. if (list_is_last(&xfer->transfer_list,
  821. &msg->transfers))
  822. cs_toggle = 1;
  823. }
  824. msg->actual_length += xfer->len;
  825. flush_fifo(sdd);
  826. }
  827. out:
  828. if (!cs_toggle || status)
  829. disable_cs(sdd, spi);
  830. else
  831. sdd->tgl_spi = spi;
  832. s3c64xx_spi_unmap_mssg(sdd, msg);
  833. msg->status = status;
  834. spi_finalize_current_message(master);
  835. return 0;
  836. }
  837. static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
  838. struct spi_device *spi)
  839. {
  840. struct s3c64xx_spi_csinfo *cs;
  841. struct device_node *slave_np, *data_np = NULL;
  842. struct s3c64xx_spi_driver_data *sdd;
  843. u32 fb_delay = 0;
  844. sdd = spi_master_get_devdata(spi->master);
  845. slave_np = spi->dev.of_node;
  846. if (!slave_np) {
  847. dev_err(&spi->dev, "device node not found\n");
  848. return ERR_PTR(-EINVAL);
  849. }
  850. data_np = of_get_child_by_name(slave_np, "controller-data");
  851. if (!data_np) {
  852. dev_err(&spi->dev, "child node 'controller-data' not found\n");
  853. return ERR_PTR(-EINVAL);
  854. }
  855. cs = kzalloc(sizeof(*cs), GFP_KERNEL);
  856. if (!cs) {
  857. dev_err(&spi->dev, "could not allocate memory for controller data\n");
  858. of_node_put(data_np);
  859. return ERR_PTR(-ENOMEM);
  860. }
  861. /* The CS line is asserted/deasserted by the gpio pin */
  862. if (sdd->cs_gpio)
  863. cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
  864. if (!gpio_is_valid(cs->line)) {
  865. dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
  866. kfree(cs);
  867. of_node_put(data_np);
  868. return ERR_PTR(-EINVAL);
  869. }
  870. of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
  871. cs->fb_delay = fb_delay;
  872. of_node_put(data_np);
  873. return cs;
  874. }
  875. /*
  876. * Here we only check the validity of requested configuration
  877. * and save the configuration in a local data-structure.
  878. * The controller is actually configured only just before we
  879. * get a message to transfer.
  880. */
  881. static int s3c64xx_spi_setup(struct spi_device *spi)
  882. {
  883. struct s3c64xx_spi_csinfo *cs = spi->controller_data;
  884. struct s3c64xx_spi_driver_data *sdd;
  885. struct s3c64xx_spi_info *sci;
  886. struct spi_message *msg;
  887. unsigned long flags;
  888. int err;
  889. sdd = spi_master_get_devdata(spi->master);
  890. if (!cs && spi->dev.of_node) {
  891. cs = s3c64xx_get_slave_ctrldata(spi);
  892. spi->controller_data = cs;
  893. }
  894. if (IS_ERR_OR_NULL(cs)) {
  895. dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
  896. return -ENODEV;
  897. }
  898. /* Request gpio only if cs line is asserted by gpio pins */
  899. if (sdd->cs_gpio) {
  900. err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
  901. dev_name(&spi->dev));
  902. if (err) {
  903. dev_err(&spi->dev,
  904. "Failed to get /CS gpio [%d]: %d\n",
  905. cs->line, err);
  906. goto err_gpio_req;
  907. }
  908. }
  909. if (!spi_get_ctldata(spi))
  910. spi_set_ctldata(spi, cs);
  911. sci = sdd->cntrlr_info;
  912. spin_lock_irqsave(&sdd->lock, flags);
  913. list_for_each_entry(msg, &sdd->queue, queue) {
  914. /* Is some mssg is already queued for this device */
  915. if (msg->spi == spi) {
  916. dev_err(&spi->dev,
  917. "setup: attempt while mssg in queue!\n");
  918. spin_unlock_irqrestore(&sdd->lock, flags);
  919. err = -EBUSY;
  920. goto err_msgq;
  921. }
  922. }
  923. spin_unlock_irqrestore(&sdd->lock, flags);
  924. pm_runtime_get_sync(&sdd->pdev->dev);
  925. /* Check if we can provide the requested rate */
  926. if (!sdd->port_conf->clk_from_cmu) {
  927. u32 psr, speed;
  928. /* Max possible */
  929. speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
  930. if (spi->max_speed_hz > speed)
  931. spi->max_speed_hz = speed;
  932. psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
  933. psr &= S3C64XX_SPI_PSR_MASK;
  934. if (psr == S3C64XX_SPI_PSR_MASK)
  935. psr--;
  936. speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
  937. if (spi->max_speed_hz < speed) {
  938. if (psr+1 < S3C64XX_SPI_PSR_MASK) {
  939. psr++;
  940. } else {
  941. err = -EINVAL;
  942. goto setup_exit;
  943. }
  944. }
  945. speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
  946. if (spi->max_speed_hz >= speed) {
  947. spi->max_speed_hz = speed;
  948. } else {
  949. dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
  950. spi->max_speed_hz);
  951. err = -EINVAL;
  952. goto setup_exit;
  953. }
  954. }
  955. pm_runtime_put(&sdd->pdev->dev);
  956. disable_cs(sdd, spi);
  957. return 0;
  958. setup_exit:
  959. /* setup() returns with device de-selected */
  960. disable_cs(sdd, spi);
  961. err_msgq:
  962. gpio_free(cs->line);
  963. spi_set_ctldata(spi, NULL);
  964. err_gpio_req:
  965. if (spi->dev.of_node)
  966. kfree(cs);
  967. return err;
  968. }
  969. static void s3c64xx_spi_cleanup(struct spi_device *spi)
  970. {
  971. struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
  972. struct s3c64xx_spi_driver_data *sdd;
  973. sdd = spi_master_get_devdata(spi->master);
  974. if (cs && sdd->cs_gpio) {
  975. gpio_free(cs->line);
  976. if (spi->dev.of_node)
  977. kfree(cs);
  978. }
  979. spi_set_ctldata(spi, NULL);
  980. }
  981. static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
  982. {
  983. struct s3c64xx_spi_driver_data *sdd = data;
  984. struct spi_master *spi = sdd->master;
  985. unsigned int val, clr = 0;
  986. val = readl(sdd->regs + S3C64XX_SPI_STATUS);
  987. if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
  988. clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
  989. dev_err(&spi->dev, "RX overrun\n");
  990. }
  991. if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
  992. clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
  993. dev_err(&spi->dev, "RX underrun\n");
  994. }
  995. if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
  996. clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
  997. dev_err(&spi->dev, "TX overrun\n");
  998. }
  999. if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
  1000. clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  1001. dev_err(&spi->dev, "TX underrun\n");
  1002. }
  1003. /* Clear the pending irq by setting and then clearing it */
  1004. writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  1005. writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
  1006. return IRQ_HANDLED;
  1007. }
  1008. static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
  1009. {
  1010. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  1011. void __iomem *regs = sdd->regs;
  1012. unsigned int val;
  1013. sdd->cur_speed = 0;
  1014. writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
  1015. /* Disable Interrupts - we use Polling if not DMA mode */
  1016. writel(0, regs + S3C64XX_SPI_INT_EN);
  1017. if (!sdd->port_conf->clk_from_cmu)
  1018. writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
  1019. regs + S3C64XX_SPI_CLK_CFG);
  1020. writel(0, regs + S3C64XX_SPI_MODE_CFG);
  1021. writel(0, regs + S3C64XX_SPI_PACKET_CNT);
  1022. /* Clear any irq pending bits, should set and clear the bits */
  1023. val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
  1024. S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
  1025. S3C64XX_SPI_PND_TX_OVERRUN_CLR |
  1026. S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
  1027. writel(val, regs + S3C64XX_SPI_PENDING_CLR);
  1028. writel(0, regs + S3C64XX_SPI_PENDING_CLR);
  1029. writel(0, regs + S3C64XX_SPI_SWAP_CFG);
  1030. val = readl(regs + S3C64XX_SPI_MODE_CFG);
  1031. val &= ~S3C64XX_SPI_MODE_4BURST;
  1032. val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  1033. val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
  1034. writel(val, regs + S3C64XX_SPI_MODE_CFG);
  1035. flush_fifo(sdd);
  1036. }
  1037. #ifdef CONFIG_OF
  1038. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  1039. {
  1040. struct s3c64xx_spi_info *sci;
  1041. u32 temp;
  1042. sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
  1043. if (!sci) {
  1044. dev_err(dev, "memory allocation for spi_info failed\n");
  1045. return ERR_PTR(-ENOMEM);
  1046. }
  1047. if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
  1048. dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
  1049. sci->src_clk_nr = 0;
  1050. } else {
  1051. sci->src_clk_nr = temp;
  1052. }
  1053. if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
  1054. dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
  1055. sci->num_cs = 1;
  1056. } else {
  1057. sci->num_cs = temp;
  1058. }
  1059. return sci;
  1060. }
  1061. #else
  1062. static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
  1063. {
  1064. return dev->platform_data;
  1065. }
  1066. #endif
  1067. static const struct of_device_id s3c64xx_spi_dt_match[];
  1068. static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
  1069. struct platform_device *pdev)
  1070. {
  1071. #ifdef CONFIG_OF
  1072. if (pdev->dev.of_node) {
  1073. const struct of_device_id *match;
  1074. match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
  1075. return (struct s3c64xx_spi_port_config *)match->data;
  1076. }
  1077. #endif
  1078. return (struct s3c64xx_spi_port_config *)
  1079. platform_get_device_id(pdev)->driver_data;
  1080. }
  1081. static int s3c64xx_spi_probe(struct platform_device *pdev)
  1082. {
  1083. struct resource *mem_res;
  1084. struct resource *res;
  1085. struct s3c64xx_spi_driver_data *sdd;
  1086. struct s3c64xx_spi_info *sci = pdev->dev.platform_data;
  1087. struct spi_master *master;
  1088. int ret, irq;
  1089. char clk_name[16];
  1090. if (!sci && pdev->dev.of_node) {
  1091. sci = s3c64xx_spi_parse_dt(&pdev->dev);
  1092. if (IS_ERR(sci))
  1093. return PTR_ERR(sci);
  1094. }
  1095. if (!sci) {
  1096. dev_err(&pdev->dev, "platform_data missing!\n");
  1097. return -ENODEV;
  1098. }
  1099. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1100. if (mem_res == NULL) {
  1101. dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
  1102. return -ENXIO;
  1103. }
  1104. irq = platform_get_irq(pdev, 0);
  1105. if (irq < 0) {
  1106. dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
  1107. return irq;
  1108. }
  1109. master = spi_alloc_master(&pdev->dev,
  1110. sizeof(struct s3c64xx_spi_driver_data));
  1111. if (master == NULL) {
  1112. dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
  1113. return -ENOMEM;
  1114. }
  1115. platform_set_drvdata(pdev, master);
  1116. sdd = spi_master_get_devdata(master);
  1117. sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
  1118. sdd->master = master;
  1119. sdd->cntrlr_info = sci;
  1120. sdd->pdev = pdev;
  1121. sdd->sfr_start = mem_res->start;
  1122. sdd->cs_gpio = true;
  1123. if (pdev->dev.of_node) {
  1124. if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
  1125. sdd->cs_gpio = false;
  1126. ret = of_alias_get_id(pdev->dev.of_node, "spi");
  1127. if (ret < 0) {
  1128. dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
  1129. ret);
  1130. goto err0;
  1131. }
  1132. sdd->port_id = ret;
  1133. } else {
  1134. sdd->port_id = pdev->id;
  1135. }
  1136. sdd->cur_bpw = 8;
  1137. if (!sdd->pdev->dev.of_node) {
  1138. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  1139. if (!res) {
  1140. dev_warn(&pdev->dev, "Unable to get SPI tx dma "
  1141. "resource. Switching to poll mode\n");
  1142. sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
  1143. } else
  1144. sdd->tx_dma.dmach = res->start;
  1145. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  1146. if (!res) {
  1147. dev_warn(&pdev->dev, "Unable to get SPI rx dma "
  1148. "resource. Switching to poll mode\n");
  1149. sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
  1150. } else
  1151. sdd->rx_dma.dmach = res->start;
  1152. }
  1153. sdd->tx_dma.direction = DMA_MEM_TO_DEV;
  1154. sdd->rx_dma.direction = DMA_DEV_TO_MEM;
  1155. master->dev.of_node = pdev->dev.of_node;
  1156. master->bus_num = sdd->port_id;
  1157. master->setup = s3c64xx_spi_setup;
  1158. master->cleanup = s3c64xx_spi_cleanup;
  1159. master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
  1160. master->transfer_one_message = s3c64xx_spi_transfer_one_message;
  1161. master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
  1162. master->num_chipselect = sci->num_cs;
  1163. master->dma_alignment = 8;
  1164. master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
  1165. SPI_BPW_MASK(8);
  1166. /* the spi->mode bits understood by this driver: */
  1167. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  1168. sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
  1169. if (IS_ERR(sdd->regs)) {
  1170. ret = PTR_ERR(sdd->regs);
  1171. goto err0;
  1172. }
  1173. if (sci->cfg_gpio && sci->cfg_gpio()) {
  1174. dev_err(&pdev->dev, "Unable to config gpio\n");
  1175. ret = -EBUSY;
  1176. goto err0;
  1177. }
  1178. /* Setup clocks */
  1179. sdd->clk = devm_clk_get(&pdev->dev, "spi");
  1180. if (IS_ERR(sdd->clk)) {
  1181. dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
  1182. ret = PTR_ERR(sdd->clk);
  1183. goto err0;
  1184. }
  1185. if (clk_prepare_enable(sdd->clk)) {
  1186. dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
  1187. ret = -EBUSY;
  1188. goto err0;
  1189. }
  1190. sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
  1191. sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
  1192. if (IS_ERR(sdd->src_clk)) {
  1193. dev_err(&pdev->dev,
  1194. "Unable to acquire clock '%s'\n", clk_name);
  1195. ret = PTR_ERR(sdd->src_clk);
  1196. goto err2;
  1197. }
  1198. if (clk_prepare_enable(sdd->src_clk)) {
  1199. dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
  1200. ret = -EBUSY;
  1201. goto err2;
  1202. }
  1203. /* Setup Deufult Mode */
  1204. s3c64xx_spi_hwinit(sdd, sdd->port_id);
  1205. spin_lock_init(&sdd->lock);
  1206. init_completion(&sdd->xfer_completion);
  1207. INIT_LIST_HEAD(&sdd->queue);
  1208. ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
  1209. "spi-s3c64xx", sdd);
  1210. if (ret != 0) {
  1211. dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
  1212. irq, ret);
  1213. goto err3;
  1214. }
  1215. writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
  1216. S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
  1217. sdd->regs + S3C64XX_SPI_INT_EN);
  1218. if (spi_register_master(master)) {
  1219. dev_err(&pdev->dev, "cannot register SPI master\n");
  1220. ret = -EBUSY;
  1221. goto err3;
  1222. }
  1223. dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
  1224. sdd->port_id, master->num_chipselect);
  1225. dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n",
  1226. mem_res->end, mem_res->start,
  1227. sdd->rx_dma.dmach, sdd->tx_dma.dmach);
  1228. pm_runtime_enable(&pdev->dev);
  1229. return 0;
  1230. err3:
  1231. clk_disable_unprepare(sdd->src_clk);
  1232. err2:
  1233. clk_disable_unprepare(sdd->clk);
  1234. err0:
  1235. spi_master_put(master);
  1236. return ret;
  1237. }
  1238. static int s3c64xx_spi_remove(struct platform_device *pdev)
  1239. {
  1240. struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
  1241. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1242. pm_runtime_disable(&pdev->dev);
  1243. spi_unregister_master(master);
  1244. writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
  1245. clk_disable_unprepare(sdd->src_clk);
  1246. clk_disable_unprepare(sdd->clk);
  1247. spi_master_put(master);
  1248. return 0;
  1249. }
  1250. #ifdef CONFIG_PM_SLEEP
  1251. static int s3c64xx_spi_suspend(struct device *dev)
  1252. {
  1253. struct spi_master *master = dev_get_drvdata(dev);
  1254. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1255. spi_master_suspend(master);
  1256. /* Disable the clock */
  1257. clk_disable_unprepare(sdd->src_clk);
  1258. clk_disable_unprepare(sdd->clk);
  1259. sdd->cur_speed = 0; /* Output Clock is stopped */
  1260. return 0;
  1261. }
  1262. static int s3c64xx_spi_resume(struct device *dev)
  1263. {
  1264. struct spi_master *master = dev_get_drvdata(dev);
  1265. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1266. struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
  1267. if (sci->cfg_gpio)
  1268. sci->cfg_gpio();
  1269. /* Enable the clock */
  1270. clk_prepare_enable(sdd->src_clk);
  1271. clk_prepare_enable(sdd->clk);
  1272. s3c64xx_spi_hwinit(sdd, sdd->port_id);
  1273. spi_master_resume(master);
  1274. return 0;
  1275. }
  1276. #endif /* CONFIG_PM_SLEEP */
  1277. #ifdef CONFIG_PM_RUNTIME
  1278. static int s3c64xx_spi_runtime_suspend(struct device *dev)
  1279. {
  1280. struct spi_master *master = dev_get_drvdata(dev);
  1281. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1282. clk_disable_unprepare(sdd->clk);
  1283. clk_disable_unprepare(sdd->src_clk);
  1284. return 0;
  1285. }
  1286. static int s3c64xx_spi_runtime_resume(struct device *dev)
  1287. {
  1288. struct spi_master *master = dev_get_drvdata(dev);
  1289. struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
  1290. clk_prepare_enable(sdd->src_clk);
  1291. clk_prepare_enable(sdd->clk);
  1292. return 0;
  1293. }
  1294. #endif /* CONFIG_PM_RUNTIME */
  1295. static const struct dev_pm_ops s3c64xx_spi_pm = {
  1296. SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
  1297. SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
  1298. s3c64xx_spi_runtime_resume, NULL)
  1299. };
  1300. static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
  1301. .fifo_lvl_mask = { 0x7f },
  1302. .rx_lvl_offset = 13,
  1303. .tx_st_done = 21,
  1304. .high_speed = true,
  1305. };
  1306. static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
  1307. .fifo_lvl_mask = { 0x7f, 0x7F },
  1308. .rx_lvl_offset = 13,
  1309. .tx_st_done = 21,
  1310. };
  1311. static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
  1312. .fifo_lvl_mask = { 0x1ff, 0x7F },
  1313. .rx_lvl_offset = 15,
  1314. .tx_st_done = 25,
  1315. };
  1316. static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
  1317. .fifo_lvl_mask = { 0x7f, 0x7F },
  1318. .rx_lvl_offset = 13,
  1319. .tx_st_done = 21,
  1320. .high_speed = true,
  1321. };
  1322. static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
  1323. .fifo_lvl_mask = { 0x1ff, 0x7F },
  1324. .rx_lvl_offset = 15,
  1325. .tx_st_done = 25,
  1326. .high_speed = true,
  1327. };
  1328. static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
  1329. .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
  1330. .rx_lvl_offset = 15,
  1331. .tx_st_done = 25,
  1332. .high_speed = true,
  1333. .clk_from_cmu = true,
  1334. };
  1335. static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
  1336. .fifo_lvl_mask = { 0x1ff },
  1337. .rx_lvl_offset = 15,
  1338. .tx_st_done = 25,
  1339. .high_speed = true,
  1340. .clk_from_cmu = true,
  1341. .quirks = S3C64XX_SPI_QUIRK_POLL,
  1342. };
  1343. static struct platform_device_id s3c64xx_spi_driver_ids[] = {
  1344. {
  1345. .name = "s3c2443-spi",
  1346. .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
  1347. }, {
  1348. .name = "s3c6410-spi",
  1349. .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
  1350. }, {
  1351. .name = "s5p64x0-spi",
  1352. .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
  1353. }, {
  1354. .name = "s5pc100-spi",
  1355. .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
  1356. }, {
  1357. .name = "s5pv210-spi",
  1358. .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
  1359. }, {
  1360. .name = "exynos4210-spi",
  1361. .driver_data = (kernel_ulong_t)&exynos4_spi_port_config,
  1362. },
  1363. { },
  1364. };
  1365. static const struct of_device_id s3c64xx_spi_dt_match[] = {
  1366. { .compatible = "samsung,exynos4210-spi",
  1367. .data = (void *)&exynos4_spi_port_config,
  1368. },
  1369. { .compatible = "samsung,exynos5440-spi",
  1370. .data = (void *)&exynos5440_spi_port_config,
  1371. },
  1372. { },
  1373. };
  1374. MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
  1375. static struct platform_driver s3c64xx_spi_driver = {
  1376. .driver = {
  1377. .name = "s3c64xx-spi",
  1378. .owner = THIS_MODULE,
  1379. .pm = &s3c64xx_spi_pm,
  1380. .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
  1381. },
  1382. .remove = s3c64xx_spi_remove,
  1383. .id_table = s3c64xx_spi_driver_ids,
  1384. };
  1385. MODULE_ALIAS("platform:s3c64xx-spi");
  1386. static int __init s3c64xx_spi_init(void)
  1387. {
  1388. return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
  1389. }
  1390. subsys_initcall(s3c64xx_spi_init);
  1391. static void __exit s3c64xx_spi_exit(void)
  1392. {
  1393. platform_driver_unregister(&s3c64xx_spi_driver);
  1394. }
  1395. module_exit(s3c64xx_spi_exit);
  1396. MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
  1397. MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
  1398. MODULE_LICENSE("GPL");