falcon_xmac.c 12 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/delay.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "falcon.h"
  14. #include "regs.h"
  15. #include "io.h"
  16. #include "mac.h"
  17. #include "mdio_10g.h"
  18. #include "phy.h"
  19. #include "workarounds.h"
  20. /**************************************************************************
  21. *
  22. * MAC operations
  23. *
  24. *************************************************************************/
  25. /* Configure the XAUI driver that is an output from Falcon */
  26. static void falcon_setup_xaui(struct efx_nic *efx)
  27. {
  28. efx_oword_t sdctl, txdrv;
  29. /* Move the XAUI into low power, unless there is no PHY, in
  30. * which case the XAUI will have to drive a cable. */
  31. if (efx->phy_type == PHY_TYPE_NONE)
  32. return;
  33. efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
  34. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  35. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
  36. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  37. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
  38. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  39. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
  40. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  41. EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
  42. efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
  43. EFX_POPULATE_OWORD_8(txdrv,
  44. FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
  45. FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
  46. FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
  47. FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
  48. FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
  49. FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
  50. FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
  51. FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
  52. efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
  53. }
  54. int falcon_reset_xaui(struct efx_nic *efx)
  55. {
  56. efx_oword_t reg;
  57. int count;
  58. /* Start reset sequence */
  59. EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
  60. efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
  61. /* Wait up to 10 ms for completion, then reinitialise */
  62. for (count = 0; count < 1000; count++) {
  63. efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
  64. if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
  65. EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
  66. falcon_setup_xaui(efx);
  67. return 0;
  68. }
  69. udelay(10);
  70. }
  71. EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
  72. return -ETIMEDOUT;
  73. }
  74. static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
  75. {
  76. efx_oword_t reg;
  77. if ((falcon_rev(efx) != FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
  78. return;
  79. /* We expect xgmii faults if the wireside link is up */
  80. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
  81. return;
  82. /* We can only use this interrupt to signal the negative edge of
  83. * xaui_align [we have to poll the positive edge]. */
  84. if (!efx->mac_up)
  85. return;
  86. /* Flush the ISR */
  87. if (enable)
  88. efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
  89. EFX_POPULATE_OWORD_2(reg,
  90. FRF_AB_XM_MSK_RMTFLT, !enable,
  91. FRF_AB_XM_MSK_LCLFLT, !enable);
  92. efx_writeo(efx, &reg, FR_AB_XM_MGT_INT_MASK);
  93. }
  94. /* Get status of XAUI link */
  95. bool falcon_xaui_link_ok(struct efx_nic *efx)
  96. {
  97. efx_oword_t reg;
  98. bool align_done, link_ok = false;
  99. int sync_status;
  100. if (LOOPBACK_INTERNAL(efx))
  101. return true;
  102. /* Read link status */
  103. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  104. align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
  105. sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
  106. if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
  107. link_ok = true;
  108. /* Clear link status ready for next read */
  109. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
  110. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
  111. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
  112. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  113. /* If the link is up, then check the phy side of the xaui link */
  114. if (efx->link_state.up && link_ok)
  115. if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
  116. link_ok = efx_mdio_phyxgxs_lane_sync(efx);
  117. return link_ok;
  118. }
  119. static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  120. {
  121. unsigned int max_frame_len;
  122. efx_oword_t reg;
  123. bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
  124. /* Configure MAC - cut-thru mode is hard wired on */
  125. EFX_POPULATE_DWORD_3(reg,
  126. FRF_AB_XM_RX_JUMBO_MODE, 1,
  127. FRF_AB_XM_TX_STAT_EN, 1,
  128. FRF_AB_XM_RX_STAT_EN, 1);
  129. efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
  130. /* Configure TX */
  131. EFX_POPULATE_DWORD_6(reg,
  132. FRF_AB_XM_TXEN, 1,
  133. FRF_AB_XM_TX_PRMBL, 1,
  134. FRF_AB_XM_AUTO_PAD, 1,
  135. FRF_AB_XM_TXCRC, 1,
  136. FRF_AB_XM_FCNTL, 1,
  137. FRF_AB_XM_IPG, 0x3);
  138. efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
  139. /* Configure RX */
  140. EFX_POPULATE_DWORD_5(reg,
  141. FRF_AB_XM_RXEN, 1,
  142. FRF_AB_XM_AUTO_DEPAD, 0,
  143. FRF_AB_XM_ACPT_ALL_MCAST, 1,
  144. FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
  145. FRF_AB_XM_PASS_CRC_ERR, 1);
  146. efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
  147. /* Set frame length */
  148. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  149. EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
  150. efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
  151. EFX_POPULATE_DWORD_2(reg,
  152. FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
  153. FRF_AB_XM_TX_JUMBO_MODE, 1);
  154. efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
  155. EFX_POPULATE_DWORD_2(reg,
  156. FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  157. FRF_AB_XM_DIS_FCNTL, !rx_fc);
  158. efx_writeo(efx, &reg, FR_AB_XM_FC);
  159. /* Set MAC address */
  160. memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
  161. efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
  162. memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
  163. efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
  164. }
  165. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  166. {
  167. efx_oword_t reg;
  168. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  169. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  170. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  171. /* XGXS block is flaky and will need to be reset if moving
  172. * into our out of XGMII, XGXS or XAUI loopbacks. */
  173. if (EFX_WORKAROUND_5147(efx)) {
  174. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  175. bool reset_xgxs;
  176. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  177. old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
  178. old_xgmii_loopback =
  179. EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
  180. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  181. old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
  182. /* The PHY driver may have turned XAUI off */
  183. reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
  184. (xaui_loopback != old_xaui_loopback) ||
  185. (xgmii_loopback != old_xgmii_loopback));
  186. if (reset_xgxs)
  187. falcon_reset_xaui(efx);
  188. }
  189. efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
  190. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
  191. (xgxs_loopback || xaui_loopback) ?
  192. FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
  193. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
  194. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
  195. efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
  196. efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
  197. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
  198. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
  199. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
  200. EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
  201. efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
  202. }
  203. /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
  204. * to come back up. Bash it until it comes back up */
  205. static void falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
  206. {
  207. efx->mac_up = falcon_xaui_link_ok(efx);
  208. if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
  209. efx_phy_mode_disabled(efx->phy_mode))
  210. /* XAUI link is expected to be down */
  211. return;
  212. while (!efx->mac_up && tries) {
  213. EFX_LOG(efx, "bashing xaui\n");
  214. falcon_reset_xaui(efx);
  215. udelay(200);
  216. efx->mac_up = falcon_xaui_link_ok(efx);
  217. --tries;
  218. }
  219. }
  220. static void falcon_reconfigure_xmac(struct efx_nic *efx)
  221. {
  222. falcon_mask_status_intr(efx, false);
  223. falcon_reconfigure_xgxs_core(efx);
  224. falcon_reconfigure_xmac_core(efx);
  225. falcon_reconfigure_mac_wrapper(efx);
  226. falcon_check_xaui_link_up(efx, 5);
  227. falcon_mask_status_intr(efx, true);
  228. }
  229. static void falcon_update_stats_xmac(struct efx_nic *efx)
  230. {
  231. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  232. int rc;
  233. rc = falcon_dma_stats(efx, XgDmaDone_offset);
  234. if (rc)
  235. return;
  236. /* Update MAC stats from DMAed values */
  237. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  238. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  239. FALCON_STAT(efx, XgRxPkts, rx_packets);
  240. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  241. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  242. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  243. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  244. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  245. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  246. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  247. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  248. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  249. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  250. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  251. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  252. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  253. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  254. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  255. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  256. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  257. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  258. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  259. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  260. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  261. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  262. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  263. FALCON_STAT(efx, XgTxPkts, tx_packets);
  264. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  265. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  266. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  267. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  268. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  269. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  270. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  271. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  272. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  273. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  274. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  275. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  276. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  277. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  278. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  279. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  280. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  281. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  282. /* Update derived statistics */
  283. mac_stats->tx_good_bytes =
  284. (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  285. mac_stats->tx_control * 64);
  286. mac_stats->rx_bad_bytes =
  287. (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  288. mac_stats->rx_control * 64);
  289. }
  290. static void falcon_xmac_irq(struct efx_nic *efx)
  291. {
  292. /* The XGMII link has a transient fault, which indicates either:
  293. * - there's a transient xgmii fault
  294. * - falcon's end of the xaui link may need a kick
  295. * - the wire-side link may have gone down, but the lasi/poll()
  296. * hasn't noticed yet.
  297. *
  298. * We only want to even bother polling XAUI if we're confident it's
  299. * not (1) or (3). In both cases, the only reliable way to spot this
  300. * is to wait a bit. We do this here by forcing the mac link state
  301. * to down, and waiting for the mac poll to come round and check
  302. */
  303. efx->mac_up = false;
  304. }
  305. static void falcon_poll_xmac(struct efx_nic *efx)
  306. {
  307. if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up || efx->mac_up)
  308. return;
  309. falcon_mask_status_intr(efx, false);
  310. falcon_check_xaui_link_up(efx, 1);
  311. falcon_mask_status_intr(efx, true);
  312. }
  313. struct efx_mac_operations falcon_xmac_operations = {
  314. .reconfigure = falcon_reconfigure_xmac,
  315. .update_stats = falcon_update_stats_xmac,
  316. .irq = falcon_xmac_irq,
  317. .poll = falcon_poll_xmac,
  318. };