cnic.c 118 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2009 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/list.h>
  16. #include <linux/slab.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/uio_driver.h>
  21. #include <linux/in.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/delay.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/if_vlan.h>
  26. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  27. #define BCM_VLAN 1
  28. #endif
  29. #include <net/ip.h>
  30. #include <net/tcp.h>
  31. #include <net/route.h>
  32. #include <net/ipv6.h>
  33. #include <net/ip6_route.h>
  34. #include <net/ip6_checksum.h>
  35. #include <scsi/iscsi_if.h>
  36. #include "cnic_if.h"
  37. #include "bnx2.h"
  38. #include "bnx2x_reg.h"
  39. #include "bnx2x_fw_defs.h"
  40. #include "bnx2x_hsi.h"
  41. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  43. #include "cnic.h"
  44. #include "cnic_defs.h"
  45. #define DRV_MODULE_NAME "cnic"
  46. #define PFX DRV_MODULE_NAME ": "
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = DRV_CTL_COMPLETION_CMD;
  207. info.data.comp.comp_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. csk = &cp->csk_tbl[l5_cid];
  274. csk_hold(csk);
  275. if (cnic_in_use(csk)) {
  276. memcpy(csk->ha, path_resp->mac_addr, 6);
  277. if (test_bit(SK_F_IPV6, &csk->flags))
  278. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  279. sizeof(struct in6_addr));
  280. else
  281. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  282. sizeof(struct in_addr));
  283. if (is_valid_ether_addr(csk->ha))
  284. cnic_cm_set_pg(csk);
  285. }
  286. csk_put(csk);
  287. rc = 0;
  288. }
  289. }
  290. return rc;
  291. }
  292. static int cnic_offld_prep(struct cnic_sock *csk)
  293. {
  294. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  295. return 0;
  296. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  297. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  298. return 0;
  299. }
  300. return 1;
  301. }
  302. static int cnic_close_prep(struct cnic_sock *csk)
  303. {
  304. clear_bit(SK_F_CONNECT_START, &csk->flags);
  305. smp_mb__after_clear_bit();
  306. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  307. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  308. msleep(1);
  309. return 1;
  310. }
  311. return 0;
  312. }
  313. static int cnic_abort_prep(struct cnic_sock *csk)
  314. {
  315. clear_bit(SK_F_CONNECT_START, &csk->flags);
  316. smp_mb__after_clear_bit();
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  320. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  321. return 1;
  322. }
  323. return 0;
  324. }
  325. static void cnic_uio_stop(void)
  326. {
  327. struct cnic_dev *dev;
  328. read_lock(&cnic_dev_lock);
  329. list_for_each_entry(dev, &cnic_dev_list, list) {
  330. struct cnic_local *cp = dev->cnic_priv;
  331. if (cp->cnic_uinfo)
  332. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  333. }
  334. read_unlock(&cnic_dev_lock);
  335. }
  336. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  337. {
  338. struct cnic_dev *dev;
  339. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  340. printk(KERN_ERR PFX "cnic_register_driver: Bad type %d\n",
  341. ulp_type);
  342. return -EINVAL;
  343. }
  344. mutex_lock(&cnic_lock);
  345. if (cnic_ulp_tbl[ulp_type]) {
  346. printk(KERN_ERR PFX "cnic_register_driver: Type %d has already "
  347. "been registered\n", ulp_type);
  348. mutex_unlock(&cnic_lock);
  349. return -EBUSY;
  350. }
  351. read_lock(&cnic_dev_lock);
  352. list_for_each_entry(dev, &cnic_dev_list, list) {
  353. struct cnic_local *cp = dev->cnic_priv;
  354. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  355. }
  356. read_unlock(&cnic_dev_lock);
  357. atomic_set(&ulp_ops->ref_count, 0);
  358. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  359. mutex_unlock(&cnic_lock);
  360. /* Prevent race conditions with netdev_event */
  361. rtnl_lock();
  362. read_lock(&cnic_dev_lock);
  363. list_for_each_entry(dev, &cnic_dev_list, list) {
  364. struct cnic_local *cp = dev->cnic_priv;
  365. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  366. ulp_ops->cnic_init(dev);
  367. }
  368. read_unlock(&cnic_dev_lock);
  369. rtnl_unlock();
  370. return 0;
  371. }
  372. int cnic_unregister_driver(int ulp_type)
  373. {
  374. struct cnic_dev *dev;
  375. struct cnic_ulp_ops *ulp_ops;
  376. int i = 0;
  377. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  378. printk(KERN_ERR PFX "cnic_unregister_driver: Bad type %d\n",
  379. ulp_type);
  380. return -EINVAL;
  381. }
  382. mutex_lock(&cnic_lock);
  383. ulp_ops = cnic_ulp_tbl[ulp_type];
  384. if (!ulp_ops) {
  385. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d has not "
  386. "been registered\n", ulp_type);
  387. goto out_unlock;
  388. }
  389. read_lock(&cnic_dev_lock);
  390. list_for_each_entry(dev, &cnic_dev_list, list) {
  391. struct cnic_local *cp = dev->cnic_priv;
  392. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  393. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d "
  394. "still has devices registered\n", ulp_type);
  395. read_unlock(&cnic_dev_lock);
  396. goto out_unlock;
  397. }
  398. }
  399. read_unlock(&cnic_dev_lock);
  400. if (ulp_type == CNIC_ULP_ISCSI)
  401. cnic_uio_stop();
  402. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  403. mutex_unlock(&cnic_lock);
  404. synchronize_rcu();
  405. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  406. msleep(100);
  407. i++;
  408. }
  409. if (atomic_read(&ulp_ops->ref_count) != 0)
  410. printk(KERN_WARNING PFX "%s: Failed waiting for ref count to go"
  411. " to zero.\n", dev->netdev->name);
  412. return 0;
  413. out_unlock:
  414. mutex_unlock(&cnic_lock);
  415. return -EINVAL;
  416. }
  417. static int cnic_start_hw(struct cnic_dev *);
  418. static void cnic_stop_hw(struct cnic_dev *);
  419. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  420. void *ulp_ctx)
  421. {
  422. struct cnic_local *cp = dev->cnic_priv;
  423. struct cnic_ulp_ops *ulp_ops;
  424. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  425. printk(KERN_ERR PFX "cnic_register_device: Bad type %d\n",
  426. ulp_type);
  427. return -EINVAL;
  428. }
  429. mutex_lock(&cnic_lock);
  430. if (cnic_ulp_tbl[ulp_type] == NULL) {
  431. printk(KERN_ERR PFX "cnic_register_device: Driver with type %d "
  432. "has not been registered\n", ulp_type);
  433. mutex_unlock(&cnic_lock);
  434. return -EAGAIN;
  435. }
  436. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  437. printk(KERN_ERR PFX "cnic_register_device: Type %d has already "
  438. "been registered to this device\n", ulp_type);
  439. mutex_unlock(&cnic_lock);
  440. return -EBUSY;
  441. }
  442. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  443. cp->ulp_handle[ulp_type] = ulp_ctx;
  444. ulp_ops = cnic_ulp_tbl[ulp_type];
  445. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  446. cnic_hold(dev);
  447. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  448. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  449. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  450. mutex_unlock(&cnic_lock);
  451. return 0;
  452. }
  453. EXPORT_SYMBOL(cnic_register_driver);
  454. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  455. {
  456. struct cnic_local *cp = dev->cnic_priv;
  457. int i = 0;
  458. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  459. printk(KERN_ERR PFX "cnic_unregister_device: Bad type %d\n",
  460. ulp_type);
  461. return -EINVAL;
  462. }
  463. mutex_lock(&cnic_lock);
  464. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  465. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  466. cnic_put(dev);
  467. } else {
  468. printk(KERN_ERR PFX "cnic_unregister_device: device not "
  469. "registered to this ulp type %d\n", ulp_type);
  470. mutex_unlock(&cnic_lock);
  471. return -EINVAL;
  472. }
  473. mutex_unlock(&cnic_lock);
  474. synchronize_rcu();
  475. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  476. i < 20) {
  477. msleep(100);
  478. i++;
  479. }
  480. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  481. printk(KERN_WARNING PFX "%s: Failed waiting for ULP up call"
  482. " to complete.\n", dev->netdev->name);
  483. return 0;
  484. }
  485. EXPORT_SYMBOL(cnic_unregister_driver);
  486. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  487. {
  488. id_tbl->start = start_id;
  489. id_tbl->max = size;
  490. id_tbl->next = 0;
  491. spin_lock_init(&id_tbl->lock);
  492. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  493. if (!id_tbl->table)
  494. return -ENOMEM;
  495. return 0;
  496. }
  497. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  498. {
  499. kfree(id_tbl->table);
  500. id_tbl->table = NULL;
  501. }
  502. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  503. {
  504. int ret = -1;
  505. id -= id_tbl->start;
  506. if (id >= id_tbl->max)
  507. return ret;
  508. spin_lock(&id_tbl->lock);
  509. if (!test_bit(id, id_tbl->table)) {
  510. set_bit(id, id_tbl->table);
  511. ret = 0;
  512. }
  513. spin_unlock(&id_tbl->lock);
  514. return ret;
  515. }
  516. /* Returns -1 if not successful */
  517. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  518. {
  519. u32 id;
  520. spin_lock(&id_tbl->lock);
  521. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  522. if (id >= id_tbl->max) {
  523. id = -1;
  524. if (id_tbl->next != 0) {
  525. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  526. if (id >= id_tbl->next)
  527. id = -1;
  528. }
  529. }
  530. if (id < id_tbl->max) {
  531. set_bit(id, id_tbl->table);
  532. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  533. id += id_tbl->start;
  534. }
  535. spin_unlock(&id_tbl->lock);
  536. return id;
  537. }
  538. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  539. {
  540. if (id == -1)
  541. return;
  542. id -= id_tbl->start;
  543. if (id >= id_tbl->max)
  544. return;
  545. clear_bit(id, id_tbl->table);
  546. }
  547. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  548. {
  549. int i;
  550. if (!dma->pg_arr)
  551. return;
  552. for (i = 0; i < dma->num_pages; i++) {
  553. if (dma->pg_arr[i]) {
  554. pci_free_consistent(dev->pcidev, BCM_PAGE_SIZE,
  555. dma->pg_arr[i], dma->pg_map_arr[i]);
  556. dma->pg_arr[i] = NULL;
  557. }
  558. }
  559. if (dma->pgtbl) {
  560. pci_free_consistent(dev->pcidev, dma->pgtbl_size,
  561. dma->pgtbl, dma->pgtbl_map);
  562. dma->pgtbl = NULL;
  563. }
  564. kfree(dma->pg_arr);
  565. dma->pg_arr = NULL;
  566. dma->num_pages = 0;
  567. }
  568. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  569. {
  570. int i;
  571. u32 *page_table = dma->pgtbl;
  572. for (i = 0; i < dma->num_pages; i++) {
  573. /* Each entry needs to be in big endian format. */
  574. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  575. page_table++;
  576. *page_table = (u32) dma->pg_map_arr[i];
  577. page_table++;
  578. }
  579. }
  580. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  581. {
  582. int i;
  583. u32 *page_table = dma->pgtbl;
  584. for (i = 0; i < dma->num_pages; i++) {
  585. /* Each entry needs to be in little endian format. */
  586. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  587. page_table++;
  588. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  589. page_table++;
  590. }
  591. }
  592. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  593. int pages, int use_pg_tbl)
  594. {
  595. int i, size;
  596. struct cnic_local *cp = dev->cnic_priv;
  597. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  598. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  599. if (dma->pg_arr == NULL)
  600. return -ENOMEM;
  601. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  602. dma->num_pages = pages;
  603. for (i = 0; i < pages; i++) {
  604. dma->pg_arr[i] = pci_alloc_consistent(dev->pcidev,
  605. BCM_PAGE_SIZE,
  606. &dma->pg_map_arr[i]);
  607. if (dma->pg_arr[i] == NULL)
  608. goto error;
  609. }
  610. if (!use_pg_tbl)
  611. return 0;
  612. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  613. ~(BCM_PAGE_SIZE - 1);
  614. dma->pgtbl = pci_alloc_consistent(dev->pcidev, dma->pgtbl_size,
  615. &dma->pgtbl_map);
  616. if (dma->pgtbl == NULL)
  617. goto error;
  618. cp->setup_pgtbl(dev, dma);
  619. return 0;
  620. error:
  621. cnic_free_dma(dev, dma);
  622. return -ENOMEM;
  623. }
  624. static void cnic_free_context(struct cnic_dev *dev)
  625. {
  626. struct cnic_local *cp = dev->cnic_priv;
  627. int i;
  628. for (i = 0; i < cp->ctx_blks; i++) {
  629. if (cp->ctx_arr[i].ctx) {
  630. pci_free_consistent(dev->pcidev, cp->ctx_blk_size,
  631. cp->ctx_arr[i].ctx,
  632. cp->ctx_arr[i].mapping);
  633. cp->ctx_arr[i].ctx = NULL;
  634. }
  635. }
  636. }
  637. static void cnic_free_resc(struct cnic_dev *dev)
  638. {
  639. struct cnic_local *cp = dev->cnic_priv;
  640. int i = 0;
  641. if (cp->cnic_uinfo) {
  642. while (cp->uio_dev != -1 && i < 15) {
  643. msleep(100);
  644. i++;
  645. }
  646. uio_unregister_device(cp->cnic_uinfo);
  647. kfree(cp->cnic_uinfo);
  648. cp->cnic_uinfo = NULL;
  649. }
  650. if (cp->l2_buf) {
  651. pci_free_consistent(dev->pcidev, cp->l2_buf_size,
  652. cp->l2_buf, cp->l2_buf_map);
  653. cp->l2_buf = NULL;
  654. }
  655. if (cp->l2_ring) {
  656. pci_free_consistent(dev->pcidev, cp->l2_ring_size,
  657. cp->l2_ring, cp->l2_ring_map);
  658. cp->l2_ring = NULL;
  659. }
  660. cnic_free_context(dev);
  661. kfree(cp->ctx_arr);
  662. cp->ctx_arr = NULL;
  663. cp->ctx_blks = 0;
  664. cnic_free_dma(dev, &cp->gbl_buf_info);
  665. cnic_free_dma(dev, &cp->conn_buf_info);
  666. cnic_free_dma(dev, &cp->kwq_info);
  667. cnic_free_dma(dev, &cp->kwq_16_data_info);
  668. cnic_free_dma(dev, &cp->kcq_info);
  669. kfree(cp->iscsi_tbl);
  670. cp->iscsi_tbl = NULL;
  671. kfree(cp->ctx_tbl);
  672. cp->ctx_tbl = NULL;
  673. cnic_free_id_tbl(&cp->cid_tbl);
  674. }
  675. static int cnic_alloc_context(struct cnic_dev *dev)
  676. {
  677. struct cnic_local *cp = dev->cnic_priv;
  678. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  679. int i, k, arr_size;
  680. cp->ctx_blk_size = BCM_PAGE_SIZE;
  681. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  682. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  683. sizeof(struct cnic_ctx);
  684. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  685. if (cp->ctx_arr == NULL)
  686. return -ENOMEM;
  687. k = 0;
  688. for (i = 0; i < 2; i++) {
  689. u32 j, reg, off, lo, hi;
  690. if (i == 0)
  691. off = BNX2_PG_CTX_MAP;
  692. else
  693. off = BNX2_ISCSI_CTX_MAP;
  694. reg = cnic_reg_rd_ind(dev, off);
  695. lo = reg >> 16;
  696. hi = reg & 0xffff;
  697. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  698. cp->ctx_arr[k].cid = j;
  699. }
  700. cp->ctx_blks = k;
  701. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  702. cp->ctx_blks = 0;
  703. return -ENOMEM;
  704. }
  705. for (i = 0; i < cp->ctx_blks; i++) {
  706. cp->ctx_arr[i].ctx =
  707. pci_alloc_consistent(dev->pcidev, BCM_PAGE_SIZE,
  708. &cp->ctx_arr[i].mapping);
  709. if (cp->ctx_arr[i].ctx == NULL)
  710. return -ENOMEM;
  711. }
  712. }
  713. return 0;
  714. }
  715. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  716. {
  717. struct cnic_local *cp = dev->cnic_priv;
  718. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  719. cp->l2_ring = pci_alloc_consistent(dev->pcidev, cp->l2_ring_size,
  720. &cp->l2_ring_map);
  721. if (!cp->l2_ring)
  722. return -ENOMEM;
  723. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  724. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  725. cp->l2_buf = pci_alloc_consistent(dev->pcidev, cp->l2_buf_size,
  726. &cp->l2_buf_map);
  727. if (!cp->l2_buf)
  728. return -ENOMEM;
  729. return 0;
  730. }
  731. static int cnic_alloc_uio(struct cnic_dev *dev) {
  732. struct cnic_local *cp = dev->cnic_priv;
  733. struct uio_info *uinfo;
  734. int ret;
  735. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  736. if (!uinfo)
  737. return -ENOMEM;
  738. uinfo->mem[0].addr = dev->netdev->base_addr;
  739. uinfo->mem[0].internal_addr = dev->regview;
  740. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  741. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  742. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  743. uinfo->mem[1].addr = (unsigned long) cp->status_blk & PAGE_MASK;
  744. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  745. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  746. else
  747. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  748. uinfo->name = "bnx2_cnic";
  749. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  750. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  751. PAGE_MASK;
  752. uinfo->mem[1].size = sizeof(struct host_def_status_block);
  753. uinfo->name = "bnx2x_cnic";
  754. }
  755. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  756. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  757. uinfo->mem[2].size = cp->l2_ring_size;
  758. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  759. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  760. uinfo->mem[3].size = cp->l2_buf_size;
  761. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  762. uinfo->version = CNIC_MODULE_VERSION;
  763. uinfo->irq = UIO_IRQ_CUSTOM;
  764. uinfo->open = cnic_uio_open;
  765. uinfo->release = cnic_uio_close;
  766. uinfo->priv = dev;
  767. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  768. if (ret) {
  769. kfree(uinfo);
  770. return ret;
  771. }
  772. cp->cnic_uinfo = uinfo;
  773. return 0;
  774. }
  775. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  776. {
  777. struct cnic_local *cp = dev->cnic_priv;
  778. int ret;
  779. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  780. if (ret)
  781. goto error;
  782. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  783. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
  784. if (ret)
  785. goto error;
  786. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  787. ret = cnic_alloc_context(dev);
  788. if (ret)
  789. goto error;
  790. ret = cnic_alloc_l2_rings(dev, 2);
  791. if (ret)
  792. goto error;
  793. ret = cnic_alloc_uio(dev);
  794. if (ret)
  795. goto error;
  796. return 0;
  797. error:
  798. cnic_free_resc(dev);
  799. return ret;
  800. }
  801. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  802. {
  803. struct cnic_local *cp = dev->cnic_priv;
  804. struct cnic_eth_dev *ethdev = cp->ethdev;
  805. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  806. int total_mem, blks, i, cid_space;
  807. if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
  808. return -EINVAL;
  809. cid_space = MAX_ISCSI_TBL_SZ +
  810. (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
  811. total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
  812. blks = total_mem / ctx_blk_size;
  813. if (total_mem % ctx_blk_size)
  814. blks++;
  815. if (blks > cp->ethdev->ctx_tbl_len)
  816. return -ENOMEM;
  817. cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
  818. if (cp->ctx_arr == NULL)
  819. return -ENOMEM;
  820. cp->ctx_blks = blks;
  821. cp->ctx_blk_size = ctx_blk_size;
  822. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  823. cp->ctx_align = 0;
  824. else
  825. cp->ctx_align = ctx_blk_size;
  826. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  827. for (i = 0; i < blks; i++) {
  828. cp->ctx_arr[i].ctx =
  829. pci_alloc_consistent(dev->pcidev, cp->ctx_blk_size,
  830. &cp->ctx_arr[i].mapping);
  831. if (cp->ctx_arr[i].ctx == NULL)
  832. return -ENOMEM;
  833. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  834. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  835. cnic_free_context(dev);
  836. cp->ctx_blk_size += cp->ctx_align;
  837. i = -1;
  838. continue;
  839. }
  840. }
  841. }
  842. return 0;
  843. }
  844. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  845. {
  846. struct cnic_local *cp = dev->cnic_priv;
  847. int i, j, n, ret, pages;
  848. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  849. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  850. GFP_KERNEL);
  851. if (!cp->iscsi_tbl)
  852. goto error;
  853. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  854. MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
  855. if (!cp->ctx_tbl)
  856. goto error;
  857. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  858. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  859. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  860. }
  861. pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
  862. PAGE_SIZE;
  863. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  864. if (ret)
  865. return -ENOMEM;
  866. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  867. for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  868. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  869. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  870. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  871. off;
  872. if ((i % n) == (n - 1))
  873. j++;
  874. }
  875. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
  876. if (ret)
  877. goto error;
  878. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  879. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  880. struct bnx2x_bd_chain_next *next =
  881. (struct bnx2x_bd_chain_next *)
  882. &cp->kcq[i][MAX_KCQE_CNT];
  883. int j = i + 1;
  884. if (j >= KCQ_PAGE_CNT)
  885. j = 0;
  886. next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
  887. next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
  888. }
  889. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  890. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  891. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  892. if (ret)
  893. goto error;
  894. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  895. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  896. if (ret)
  897. goto error;
  898. ret = cnic_alloc_bnx2x_context(dev);
  899. if (ret)
  900. goto error;
  901. cp->bnx2x_status_blk = cp->status_blk;
  902. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  903. cp->l2_rx_ring_size = 15;
  904. ret = cnic_alloc_l2_rings(dev, 4);
  905. if (ret)
  906. goto error;
  907. ret = cnic_alloc_uio(dev);
  908. if (ret)
  909. goto error;
  910. return 0;
  911. error:
  912. cnic_free_resc(dev);
  913. return -ENOMEM;
  914. }
  915. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  916. {
  917. return cp->max_kwq_idx -
  918. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  919. }
  920. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  921. u32 num_wqes)
  922. {
  923. struct cnic_local *cp = dev->cnic_priv;
  924. struct kwqe *prod_qe;
  925. u16 prod, sw_prod, i;
  926. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  927. return -EAGAIN; /* bnx2 is down */
  928. spin_lock_bh(&cp->cnic_ulp_lock);
  929. if (num_wqes > cnic_kwq_avail(cp) &&
  930. !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
  931. spin_unlock_bh(&cp->cnic_ulp_lock);
  932. return -EAGAIN;
  933. }
  934. cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
  935. prod = cp->kwq_prod_idx;
  936. sw_prod = prod & MAX_KWQ_IDX;
  937. for (i = 0; i < num_wqes; i++) {
  938. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  939. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  940. prod++;
  941. sw_prod = prod & MAX_KWQ_IDX;
  942. }
  943. cp->kwq_prod_idx = prod;
  944. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  945. spin_unlock_bh(&cp->cnic_ulp_lock);
  946. return 0;
  947. }
  948. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  949. union l5cm_specific_data *l5_data)
  950. {
  951. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  952. dma_addr_t map;
  953. map = ctx->kwqe_data_mapping;
  954. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  955. l5_data->phy_address.hi = (u64) map >> 32;
  956. return ctx->kwqe_data;
  957. }
  958. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  959. u32 type, union l5cm_specific_data *l5_data)
  960. {
  961. struct cnic_local *cp = dev->cnic_priv;
  962. struct l5cm_spe kwqe;
  963. struct kwqe_16 *kwq[1];
  964. int ret;
  965. kwqe.hdr.conn_and_cmd_data =
  966. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  967. BNX2X_HW_CID(cid, cp->func)));
  968. kwqe.hdr.type = cpu_to_le16(type);
  969. kwqe.hdr.reserved = 0;
  970. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  971. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  972. kwq[0] = (struct kwqe_16 *) &kwqe;
  973. spin_lock_bh(&cp->cnic_ulp_lock);
  974. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  975. spin_unlock_bh(&cp->cnic_ulp_lock);
  976. if (ret == 1)
  977. return 0;
  978. return -EBUSY;
  979. }
  980. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  981. struct kcqe *cqes[], u32 num_cqes)
  982. {
  983. struct cnic_local *cp = dev->cnic_priv;
  984. struct cnic_ulp_ops *ulp_ops;
  985. rcu_read_lock();
  986. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  987. if (likely(ulp_ops)) {
  988. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  989. cqes, num_cqes);
  990. }
  991. rcu_read_unlock();
  992. }
  993. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  994. {
  995. struct cnic_local *cp = dev->cnic_priv;
  996. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  997. int func = cp->func, pages;
  998. int hq_bds;
  999. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1000. cp->num_ccells = req1->num_ccells_per_conn;
  1001. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1002. cp->num_iscsi_tasks;
  1003. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1004. BNX2X_ISCSI_R2TQE_SIZE;
  1005. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1006. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1007. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1008. cp->num_cqs = req1->num_cqs;
  1009. if (!dev->max_iscsi_conn)
  1010. return 0;
  1011. /* init Tstorm RAM */
  1012. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1013. req1->rq_num_wqes);
  1014. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1015. PAGE_SIZE);
  1016. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1017. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1018. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1019. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1020. req1->num_tasks_per_conn);
  1021. /* init Ustorm RAM */
  1022. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1023. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
  1024. req1->rq_buffer_size);
  1025. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1026. PAGE_SIZE);
  1027. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1028. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1029. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1030. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1031. req1->num_tasks_per_conn);
  1032. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1033. req1->rq_num_wqes);
  1034. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1035. req1->cq_num_wqes);
  1036. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1037. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1038. /* init Xstorm RAM */
  1039. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1040. PAGE_SIZE);
  1041. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1042. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1043. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1044. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1045. req1->num_tasks_per_conn);
  1046. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1047. hq_bds);
  1048. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
  1049. req1->num_tasks_per_conn);
  1050. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1051. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1052. /* init Cstorm RAM */
  1053. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1054. PAGE_SIZE);
  1055. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1056. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1057. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1058. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1059. req1->num_tasks_per_conn);
  1060. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1061. req1->cq_num_wqes);
  1062. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1063. hq_bds);
  1064. return 0;
  1065. }
  1066. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1067. {
  1068. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1069. struct cnic_local *cp = dev->cnic_priv;
  1070. int func = cp->func;
  1071. struct iscsi_kcqe kcqe;
  1072. struct kcqe *cqes[1];
  1073. memset(&kcqe, 0, sizeof(kcqe));
  1074. if (!dev->max_iscsi_conn) {
  1075. kcqe.completion_status =
  1076. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1077. goto done;
  1078. }
  1079. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1080. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1081. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1082. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1083. req2->error_bit_map[1]);
  1084. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1085. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1086. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1087. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1088. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1089. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1090. req2->error_bit_map[1]);
  1091. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1092. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1093. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1094. done:
  1095. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1096. cqes[0] = (struct kcqe *) &kcqe;
  1097. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1098. return 0;
  1099. }
  1100. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1101. {
  1102. struct cnic_local *cp = dev->cnic_priv;
  1103. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1104. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1105. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1106. cnic_free_dma(dev, &iscsi->hq_info);
  1107. cnic_free_dma(dev, &iscsi->r2tq_info);
  1108. cnic_free_dma(dev, &iscsi->task_array_info);
  1109. }
  1110. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1111. ctx->cid = 0;
  1112. }
  1113. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1114. {
  1115. u32 cid;
  1116. int ret, pages;
  1117. struct cnic_local *cp = dev->cnic_priv;
  1118. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1119. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1120. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1121. if (cid == -1) {
  1122. ret = -ENOMEM;
  1123. goto error;
  1124. }
  1125. ctx->cid = cid;
  1126. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1127. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1128. if (ret)
  1129. goto error;
  1130. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1131. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1132. if (ret)
  1133. goto error;
  1134. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1135. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1136. if (ret)
  1137. goto error;
  1138. return 0;
  1139. error:
  1140. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1141. return ret;
  1142. }
  1143. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1144. struct regpair *ctx_addr)
  1145. {
  1146. struct cnic_local *cp = dev->cnic_priv;
  1147. struct cnic_eth_dev *ethdev = cp->ethdev;
  1148. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1149. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1150. unsigned long align_off = 0;
  1151. dma_addr_t ctx_map;
  1152. void *ctx;
  1153. if (cp->ctx_align) {
  1154. unsigned long mask = cp->ctx_align - 1;
  1155. if (cp->ctx_arr[blk].mapping & mask)
  1156. align_off = cp->ctx_align -
  1157. (cp->ctx_arr[blk].mapping & mask);
  1158. }
  1159. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1160. (off * BNX2X_CONTEXT_MEM_SIZE);
  1161. ctx = cp->ctx_arr[blk].ctx + align_off +
  1162. (off * BNX2X_CONTEXT_MEM_SIZE);
  1163. if (init)
  1164. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1165. ctx_addr->lo = ctx_map & 0xffffffff;
  1166. ctx_addr->hi = (u64) ctx_map >> 32;
  1167. return ctx;
  1168. }
  1169. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1170. u32 num)
  1171. {
  1172. struct cnic_local *cp = dev->cnic_priv;
  1173. struct iscsi_kwqe_conn_offload1 *req1 =
  1174. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1175. struct iscsi_kwqe_conn_offload2 *req2 =
  1176. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1177. struct iscsi_kwqe_conn_offload3 *req3;
  1178. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1179. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1180. u32 cid = ctx->cid;
  1181. u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
  1182. struct iscsi_context *ictx;
  1183. struct regpair context_addr;
  1184. int i, j, n = 2, n_max;
  1185. ctx->ctx_flags = 0;
  1186. if (!req2->num_additional_wqes)
  1187. return -EINVAL;
  1188. n_max = req2->num_additional_wqes + 2;
  1189. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1190. if (ictx == NULL)
  1191. return -ENOMEM;
  1192. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1193. ictx->xstorm_ag_context.hq_prod = 1;
  1194. ictx->xstorm_st_context.iscsi.first_burst_length =
  1195. ISCSI_DEF_FIRST_BURST_LEN;
  1196. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1197. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1198. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1199. req1->sq_page_table_addr_lo;
  1200. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1201. req1->sq_page_table_addr_hi;
  1202. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1203. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1204. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1205. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1206. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1207. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1208. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1209. iscsi->hq_info.pgtbl[0];
  1210. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1211. iscsi->hq_info.pgtbl[1];
  1212. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1213. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1214. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1215. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1216. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1217. iscsi->r2tq_info.pgtbl[0];
  1218. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1219. iscsi->r2tq_info.pgtbl[1];
  1220. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1221. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1222. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1223. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1224. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1225. BNX2X_ISCSI_PBL_NOT_CACHED;
  1226. ictx->xstorm_st_context.iscsi.flags.flags |=
  1227. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1228. ictx->xstorm_st_context.iscsi.flags.flags |=
  1229. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1230. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1231. /* TSTORM requires the base address of RQ DB & not PTE */
  1232. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1233. req2->rq_page_table_addr_lo & PAGE_MASK;
  1234. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1235. req2->rq_page_table_addr_hi;
  1236. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1237. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1238. ictx->tstorm_st_context.tcp.flags2 |=
  1239. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1240. ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1241. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1242. req2->rq_page_table_addr_lo & 0xffffffff;
  1243. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1244. (u64) req2->rq_page_table_addr_hi >> 32;
  1245. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1246. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1247. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1248. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1249. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1250. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1251. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1252. iscsi->r2tq_info.pgtbl[0];
  1253. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1254. iscsi->r2tq_info.pgtbl[1];
  1255. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1256. req1->cq_page_table_addr_lo;
  1257. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1258. req1->cq_page_table_addr_hi;
  1259. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1260. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1261. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1262. ictx->ustorm_st_context.task_pbe_cache_index =
  1263. BNX2X_ISCSI_PBL_NOT_CACHED;
  1264. ictx->ustorm_st_context.task_pdu_cache_index =
  1265. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1266. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1267. if (j == 3) {
  1268. if (n >= n_max)
  1269. break;
  1270. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1271. j = 0;
  1272. }
  1273. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1274. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1275. req3->qp_first_pte[j].hi;
  1276. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1277. req3->qp_first_pte[j].lo;
  1278. }
  1279. ictx->ustorm_st_context.task_pbl_base.lo =
  1280. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1281. ictx->ustorm_st_context.task_pbl_base.hi =
  1282. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1283. ictx->ustorm_st_context.tce_phy_addr.lo =
  1284. iscsi->task_array_info.pgtbl[0];
  1285. ictx->ustorm_st_context.tce_phy_addr.hi =
  1286. iscsi->task_array_info.pgtbl[1];
  1287. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1288. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1289. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1290. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1291. ISCSI_DEF_MAX_BURST_LEN;
  1292. ictx->ustorm_st_context.negotiated_rx |=
  1293. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1294. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1295. ictx->cstorm_st_context.hq_pbl_base.lo =
  1296. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1297. ictx->cstorm_st_context.hq_pbl_base.hi =
  1298. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1299. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1300. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1301. ictx->cstorm_st_context.task_pbl_base.lo =
  1302. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1303. ictx->cstorm_st_context.task_pbl_base.hi =
  1304. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1305. /* CSTORM and USTORM initialization is different, CSTORM requires
  1306. * CQ DB base & not PTE addr */
  1307. ictx->cstorm_st_context.cq_db_base.lo =
  1308. req1->cq_page_table_addr_lo & PAGE_MASK;
  1309. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1310. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1311. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1312. for (i = 0; i < cp->num_cqs; i++) {
  1313. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1314. ISCSI_INITIAL_SN;
  1315. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1316. ISCSI_INITIAL_SN;
  1317. }
  1318. ictx->xstorm_ag_context.cdu_reserved =
  1319. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1320. ISCSI_CONNECTION_TYPE);
  1321. ictx->ustorm_ag_context.cdu_usage =
  1322. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1323. ISCSI_CONNECTION_TYPE);
  1324. return 0;
  1325. }
  1326. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1327. u32 num, int *work)
  1328. {
  1329. struct iscsi_kwqe_conn_offload1 *req1;
  1330. struct iscsi_kwqe_conn_offload2 *req2;
  1331. struct cnic_local *cp = dev->cnic_priv;
  1332. struct iscsi_kcqe kcqe;
  1333. struct kcqe *cqes[1];
  1334. u32 l5_cid;
  1335. int ret;
  1336. if (num < 2) {
  1337. *work = num;
  1338. return -EINVAL;
  1339. }
  1340. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1341. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1342. if ((num - 2) < req2->num_additional_wqes) {
  1343. *work = num;
  1344. return -EINVAL;
  1345. }
  1346. *work = 2 + req2->num_additional_wqes;;
  1347. l5_cid = req1->iscsi_conn_id;
  1348. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1349. return -EINVAL;
  1350. memset(&kcqe, 0, sizeof(kcqe));
  1351. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1352. kcqe.iscsi_conn_id = l5_cid;
  1353. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1354. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1355. atomic_dec(&cp->iscsi_conn);
  1356. ret = 0;
  1357. goto done;
  1358. }
  1359. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1360. if (ret) {
  1361. atomic_dec(&cp->iscsi_conn);
  1362. ret = 0;
  1363. goto done;
  1364. }
  1365. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1366. if (ret < 0) {
  1367. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1368. atomic_dec(&cp->iscsi_conn);
  1369. goto done;
  1370. }
  1371. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1372. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
  1373. cp->func);
  1374. done:
  1375. cqes[0] = (struct kcqe *) &kcqe;
  1376. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1377. return ret;
  1378. }
  1379. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1380. {
  1381. struct cnic_local *cp = dev->cnic_priv;
  1382. struct iscsi_kwqe_conn_update *req =
  1383. (struct iscsi_kwqe_conn_update *) kwqe;
  1384. void *data;
  1385. union l5cm_specific_data l5_data;
  1386. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1387. int ret;
  1388. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1389. return -EINVAL;
  1390. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1391. if (!data)
  1392. return -ENOMEM;
  1393. memcpy(data, kwqe, sizeof(struct kwqe));
  1394. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1395. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1396. return ret;
  1397. }
  1398. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1399. {
  1400. struct cnic_local *cp = dev->cnic_priv;
  1401. struct iscsi_kwqe_conn_destroy *req =
  1402. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1403. union l5cm_specific_data l5_data;
  1404. u32 l5_cid = req->reserved0;
  1405. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1406. int ret = 0;
  1407. struct iscsi_kcqe kcqe;
  1408. struct kcqe *cqes[1];
  1409. if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
  1410. goto skip_cfc_delete;
  1411. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1412. msleep(250);
  1413. init_waitqueue_head(&ctx->waitq);
  1414. ctx->wait_cond = 0;
  1415. memset(&l5_data, 0, sizeof(l5_data));
  1416. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  1417. req->context_id,
  1418. ETH_CONNECTION_TYPE |
  1419. (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
  1420. &l5_data);
  1421. if (ret == 0)
  1422. wait_event(ctx->waitq, ctx->wait_cond);
  1423. skip_cfc_delete:
  1424. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1425. atomic_dec(&cp->iscsi_conn);
  1426. memset(&kcqe, 0, sizeof(kcqe));
  1427. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1428. kcqe.iscsi_conn_id = l5_cid;
  1429. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1430. kcqe.iscsi_conn_context_id = req->context_id;
  1431. cqes[0] = (struct kcqe *) &kcqe;
  1432. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1433. return ret;
  1434. }
  1435. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1436. struct l4_kwq_connect_req1 *kwqe1,
  1437. struct l4_kwq_connect_req3 *kwqe3,
  1438. struct l5cm_active_conn_buffer *conn_buf)
  1439. {
  1440. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1441. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1442. &conn_buf->xstorm_conn_buffer;
  1443. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1444. &conn_buf->tstorm_conn_buffer;
  1445. struct regpair context_addr;
  1446. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1447. struct in6_addr src_ip, dst_ip;
  1448. int i;
  1449. u32 *addrp;
  1450. addrp = (u32 *) &conn_addr->local_ip_addr;
  1451. for (i = 0; i < 4; i++, addrp++)
  1452. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1453. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1454. for (i = 0; i < 4; i++, addrp++)
  1455. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1456. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1457. xstorm_buf->context_addr.hi = context_addr.hi;
  1458. xstorm_buf->context_addr.lo = context_addr.lo;
  1459. xstorm_buf->mss = 0xffff;
  1460. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1461. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1462. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1463. xstorm_buf->pseudo_header_checksum =
  1464. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1465. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1466. tstorm_buf->params |=
  1467. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1468. if (kwqe3->ka_timeout) {
  1469. tstorm_buf->ka_enable = 1;
  1470. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1471. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1472. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1473. }
  1474. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1475. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1476. tstorm_buf->max_rt_time = 0xffffffff;
  1477. }
  1478. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1479. {
  1480. struct cnic_local *cp = dev->cnic_priv;
  1481. int func = CNIC_FUNC(cp);
  1482. u8 *mac = dev->mac_addr;
  1483. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1484. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
  1485. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1486. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
  1487. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1488. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
  1489. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1490. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
  1491. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1492. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
  1493. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1494. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
  1495. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1496. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
  1497. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1498. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1499. mac[4]);
  1500. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1501. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
  1502. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1503. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1504. mac[2]);
  1505. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1506. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
  1507. mac[1]);
  1508. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1509. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
  1510. mac[0]);
  1511. }
  1512. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1513. {
  1514. struct cnic_local *cp = dev->cnic_priv;
  1515. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1516. u16 tstorm_flags = 0;
  1517. if (tcp_ts) {
  1518. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1519. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1520. }
  1521. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1522. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
  1523. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1524. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
  1525. }
  1526. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1527. u32 num, int *work)
  1528. {
  1529. struct cnic_local *cp = dev->cnic_priv;
  1530. struct l4_kwq_connect_req1 *kwqe1 =
  1531. (struct l4_kwq_connect_req1 *) wqes[0];
  1532. struct l4_kwq_connect_req3 *kwqe3;
  1533. struct l5cm_active_conn_buffer *conn_buf;
  1534. struct l5cm_conn_addr_params *conn_addr;
  1535. union l5cm_specific_data l5_data;
  1536. u32 l5_cid = kwqe1->pg_cid;
  1537. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1538. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1539. int ret;
  1540. if (num < 2) {
  1541. *work = num;
  1542. return -EINVAL;
  1543. }
  1544. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1545. *work = 3;
  1546. else
  1547. *work = 2;
  1548. if (num < *work) {
  1549. *work = num;
  1550. return -EINVAL;
  1551. }
  1552. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1553. printk(KERN_ERR PFX "%s: conn_buf size too big\n",
  1554. dev->netdev->name);
  1555. return -ENOMEM;
  1556. }
  1557. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1558. if (!conn_buf)
  1559. return -ENOMEM;
  1560. memset(conn_buf, 0, sizeof(*conn_buf));
  1561. conn_addr = &conn_buf->conn_addr_buf;
  1562. conn_addr->remote_addr_0 = csk->ha[0];
  1563. conn_addr->remote_addr_1 = csk->ha[1];
  1564. conn_addr->remote_addr_2 = csk->ha[2];
  1565. conn_addr->remote_addr_3 = csk->ha[3];
  1566. conn_addr->remote_addr_4 = csk->ha[4];
  1567. conn_addr->remote_addr_5 = csk->ha[5];
  1568. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1569. struct l4_kwq_connect_req2 *kwqe2 =
  1570. (struct l4_kwq_connect_req2 *) wqes[1];
  1571. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1572. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1573. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1574. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1575. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1576. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1577. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1578. }
  1579. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1580. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1581. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1582. conn_addr->local_tcp_port = kwqe1->src_port;
  1583. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1584. conn_addr->pmtu = kwqe3->pmtu;
  1585. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1586. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1587. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
  1588. cnic_bnx2x_set_tcp_timestamp(dev,
  1589. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1590. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1591. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1592. if (!ret)
  1593. ctx->ctx_flags |= CTX_FL_OFFLD_START;
  1594. return ret;
  1595. }
  1596. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1597. {
  1598. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1599. union l5cm_specific_data l5_data;
  1600. int ret;
  1601. memset(&l5_data, 0, sizeof(l5_data));
  1602. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1603. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1604. return ret;
  1605. }
  1606. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1607. {
  1608. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1609. union l5cm_specific_data l5_data;
  1610. int ret;
  1611. memset(&l5_data, 0, sizeof(l5_data));
  1612. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1613. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1614. return ret;
  1615. }
  1616. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1617. {
  1618. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1619. struct l4_kcq kcqe;
  1620. struct kcqe *cqes[1];
  1621. memset(&kcqe, 0, sizeof(kcqe));
  1622. kcqe.pg_host_opaque = req->host_opaque;
  1623. kcqe.pg_cid = req->host_opaque;
  1624. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1625. cqes[0] = (struct kcqe *) &kcqe;
  1626. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1627. return 0;
  1628. }
  1629. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1630. {
  1631. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1632. struct l4_kcq kcqe;
  1633. struct kcqe *cqes[1];
  1634. memset(&kcqe, 0, sizeof(kcqe));
  1635. kcqe.pg_host_opaque = req->pg_host_opaque;
  1636. kcqe.pg_cid = req->pg_cid;
  1637. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1638. cqes[0] = (struct kcqe *) &kcqe;
  1639. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1640. return 0;
  1641. }
  1642. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1643. u32 num_wqes)
  1644. {
  1645. int i, work, ret;
  1646. u32 opcode;
  1647. struct kwqe *kwqe;
  1648. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1649. return -EAGAIN; /* bnx2 is down */
  1650. for (i = 0; i < num_wqes; ) {
  1651. kwqe = wqes[i];
  1652. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1653. work = 1;
  1654. switch (opcode) {
  1655. case ISCSI_KWQE_OPCODE_INIT1:
  1656. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1657. break;
  1658. case ISCSI_KWQE_OPCODE_INIT2:
  1659. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1660. break;
  1661. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1662. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1663. num_wqes - i, &work);
  1664. break;
  1665. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1666. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1667. break;
  1668. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1669. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1670. break;
  1671. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1672. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1673. &work);
  1674. break;
  1675. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1676. ret = cnic_bnx2x_close(dev, kwqe);
  1677. break;
  1678. case L4_KWQE_OPCODE_VALUE_RESET:
  1679. ret = cnic_bnx2x_reset(dev, kwqe);
  1680. break;
  1681. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1682. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1683. break;
  1684. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1685. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1686. break;
  1687. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1688. ret = 0;
  1689. break;
  1690. default:
  1691. ret = 0;
  1692. printk(KERN_ERR PFX "%s: Unknown type of KWQE(0x%x)\n",
  1693. dev->netdev->name, opcode);
  1694. break;
  1695. }
  1696. if (ret < 0)
  1697. printk(KERN_ERR PFX "%s: KWQE(0x%x) failed\n",
  1698. dev->netdev->name, opcode);
  1699. i += work;
  1700. }
  1701. return 0;
  1702. }
  1703. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1704. {
  1705. struct cnic_local *cp = dev->cnic_priv;
  1706. int i, j;
  1707. i = 0;
  1708. j = 1;
  1709. while (num_cqes) {
  1710. struct cnic_ulp_ops *ulp_ops;
  1711. int ulp_type;
  1712. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1713. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1714. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1715. cnic_kwq_completion(dev, 1);
  1716. while (j < num_cqes) {
  1717. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1718. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1719. break;
  1720. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1721. cnic_kwq_completion(dev, 1);
  1722. j++;
  1723. }
  1724. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1725. ulp_type = CNIC_ULP_RDMA;
  1726. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1727. ulp_type = CNIC_ULP_ISCSI;
  1728. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1729. ulp_type = CNIC_ULP_L4;
  1730. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1731. goto end;
  1732. else {
  1733. printk(KERN_ERR PFX "%s: Unknown type of KCQE(0x%x)\n",
  1734. dev->netdev->name, kcqe_op_flag);
  1735. goto end;
  1736. }
  1737. rcu_read_lock();
  1738. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1739. if (likely(ulp_ops)) {
  1740. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1741. cp->completed_kcq + i, j);
  1742. }
  1743. rcu_read_unlock();
  1744. end:
  1745. num_cqes -= j;
  1746. i += j;
  1747. j = 1;
  1748. }
  1749. return;
  1750. }
  1751. static u16 cnic_bnx2_next_idx(u16 idx)
  1752. {
  1753. return idx + 1;
  1754. }
  1755. static u16 cnic_bnx2_hw_idx(u16 idx)
  1756. {
  1757. return idx;
  1758. }
  1759. static u16 cnic_bnx2x_next_idx(u16 idx)
  1760. {
  1761. idx++;
  1762. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1763. idx++;
  1764. return idx;
  1765. }
  1766. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1767. {
  1768. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1769. idx++;
  1770. return idx;
  1771. }
  1772. static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
  1773. {
  1774. struct cnic_local *cp = dev->cnic_priv;
  1775. u16 i, ri, last;
  1776. struct kcqe *kcqe;
  1777. int kcqe_cnt = 0, last_cnt = 0;
  1778. i = ri = last = *sw_prod;
  1779. ri &= MAX_KCQ_IDX;
  1780. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1781. kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1782. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1783. i = cp->next_idx(i);
  1784. ri = i & MAX_KCQ_IDX;
  1785. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1786. last_cnt = kcqe_cnt;
  1787. last = i;
  1788. }
  1789. }
  1790. *sw_prod = last;
  1791. return last_cnt;
  1792. }
  1793. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1794. {
  1795. u16 rx_cons = *cp->rx_cons_ptr;
  1796. u16 tx_cons = *cp->tx_cons_ptr;
  1797. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1798. cp->tx_cons = tx_cons;
  1799. cp->rx_cons = rx_cons;
  1800. uio_event_notify(cp->cnic_uinfo);
  1801. }
  1802. }
  1803. static int cnic_service_bnx2(void *data, void *status_blk)
  1804. {
  1805. struct cnic_dev *dev = data;
  1806. struct status_block *sblk = status_blk;
  1807. struct cnic_local *cp = dev->cnic_priv;
  1808. u32 status_idx = sblk->status_idx;
  1809. u16 hw_prod, sw_prod;
  1810. int kcqe_cnt;
  1811. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1812. return status_idx;
  1813. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1814. hw_prod = sblk->status_completion_producer_index;
  1815. sw_prod = cp->kcq_prod_idx;
  1816. while (sw_prod != hw_prod) {
  1817. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1818. if (kcqe_cnt == 0)
  1819. goto done;
  1820. service_kcqes(dev, kcqe_cnt);
  1821. /* Tell compiler that status_blk fields can change. */
  1822. barrier();
  1823. if (status_idx != sblk->status_idx) {
  1824. status_idx = sblk->status_idx;
  1825. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1826. hw_prod = sblk->status_completion_producer_index;
  1827. } else
  1828. break;
  1829. }
  1830. done:
  1831. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1832. cp->kcq_prod_idx = sw_prod;
  1833. cnic_chk_pkt_rings(cp);
  1834. return status_idx;
  1835. }
  1836. static void cnic_service_bnx2_msix(unsigned long data)
  1837. {
  1838. struct cnic_dev *dev = (struct cnic_dev *) data;
  1839. struct cnic_local *cp = dev->cnic_priv;
  1840. struct status_block_msix *status_blk = cp->bnx2_status_blk;
  1841. u32 status_idx = status_blk->status_idx;
  1842. u16 hw_prod, sw_prod;
  1843. int kcqe_cnt;
  1844. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1845. hw_prod = status_blk->status_completion_producer_index;
  1846. sw_prod = cp->kcq_prod_idx;
  1847. while (sw_prod != hw_prod) {
  1848. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1849. if (kcqe_cnt == 0)
  1850. goto done;
  1851. service_kcqes(dev, kcqe_cnt);
  1852. /* Tell compiler that status_blk fields can change. */
  1853. barrier();
  1854. if (status_idx != status_blk->status_idx) {
  1855. status_idx = status_blk->status_idx;
  1856. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1857. hw_prod = status_blk->status_completion_producer_index;
  1858. } else
  1859. break;
  1860. }
  1861. done:
  1862. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1863. cp->kcq_prod_idx = sw_prod;
  1864. cnic_chk_pkt_rings(cp);
  1865. cp->last_status_idx = status_idx;
  1866. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1867. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1868. }
  1869. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1870. {
  1871. struct cnic_dev *dev = dev_instance;
  1872. struct cnic_local *cp = dev->cnic_priv;
  1873. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1874. if (cp->ack_int)
  1875. cp->ack_int(dev);
  1876. prefetch(cp->status_blk);
  1877. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1878. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1879. tasklet_schedule(&cp->cnic_irq_task);
  1880. return IRQ_HANDLED;
  1881. }
  1882. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1883. u16 index, u8 op, u8 update)
  1884. {
  1885. struct cnic_local *cp = dev->cnic_priv;
  1886. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1887. COMMAND_REG_INT_ACK);
  1888. struct igu_ack_register igu_ack;
  1889. igu_ack.status_block_index = index;
  1890. igu_ack.sb_id_and_flags =
  1891. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1892. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1893. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1894. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1895. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1896. }
  1897. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1898. {
  1899. struct cnic_local *cp = dev->cnic_priv;
  1900. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
  1901. IGU_INT_DISABLE, 0);
  1902. }
  1903. static void cnic_service_bnx2x_bh(unsigned long data)
  1904. {
  1905. struct cnic_dev *dev = (struct cnic_dev *) data;
  1906. struct cnic_local *cp = dev->cnic_priv;
  1907. u16 hw_prod, sw_prod;
  1908. struct cstorm_status_block_c *sblk =
  1909. &cp->bnx2x_status_blk->c_status_block;
  1910. u32 status_idx = sblk->status_block_index;
  1911. int kcqe_cnt;
  1912. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1913. return;
  1914. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1915. hw_prod = cp->hw_idx(hw_prod);
  1916. sw_prod = cp->kcq_prod_idx;
  1917. while (sw_prod != hw_prod) {
  1918. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1919. if (kcqe_cnt == 0)
  1920. goto done;
  1921. service_kcqes(dev, kcqe_cnt);
  1922. /* Tell compiler that sblk fields can change. */
  1923. barrier();
  1924. if (status_idx == sblk->status_block_index)
  1925. break;
  1926. status_idx = sblk->status_block_index;
  1927. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1928. hw_prod = cp->hw_idx(hw_prod);
  1929. }
  1930. done:
  1931. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
  1932. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
  1933. status_idx, IGU_INT_ENABLE, 1);
  1934. cp->kcq_prod_idx = sw_prod;
  1935. return;
  1936. }
  1937. static int cnic_service_bnx2x(void *data, void *status_blk)
  1938. {
  1939. struct cnic_dev *dev = data;
  1940. struct cnic_local *cp = dev->cnic_priv;
  1941. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1942. prefetch(cp->status_blk);
  1943. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1944. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1945. tasklet_schedule(&cp->cnic_irq_task);
  1946. cnic_chk_pkt_rings(cp);
  1947. return 0;
  1948. }
  1949. static void cnic_ulp_stop(struct cnic_dev *dev)
  1950. {
  1951. struct cnic_local *cp = dev->cnic_priv;
  1952. int if_type;
  1953. if (cp->cnic_uinfo)
  1954. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1955. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1956. struct cnic_ulp_ops *ulp_ops;
  1957. mutex_lock(&cnic_lock);
  1958. ulp_ops = cp->ulp_ops[if_type];
  1959. if (!ulp_ops) {
  1960. mutex_unlock(&cnic_lock);
  1961. continue;
  1962. }
  1963. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1964. mutex_unlock(&cnic_lock);
  1965. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1966. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  1967. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1968. }
  1969. }
  1970. static void cnic_ulp_start(struct cnic_dev *dev)
  1971. {
  1972. struct cnic_local *cp = dev->cnic_priv;
  1973. int if_type;
  1974. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1975. struct cnic_ulp_ops *ulp_ops;
  1976. mutex_lock(&cnic_lock);
  1977. ulp_ops = cp->ulp_ops[if_type];
  1978. if (!ulp_ops || !ulp_ops->cnic_start) {
  1979. mutex_unlock(&cnic_lock);
  1980. continue;
  1981. }
  1982. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1983. mutex_unlock(&cnic_lock);
  1984. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1985. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  1986. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1987. }
  1988. }
  1989. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  1990. {
  1991. struct cnic_dev *dev = data;
  1992. switch (info->cmd) {
  1993. case CNIC_CTL_STOP_CMD:
  1994. cnic_hold(dev);
  1995. cnic_ulp_stop(dev);
  1996. cnic_stop_hw(dev);
  1997. cnic_put(dev);
  1998. break;
  1999. case CNIC_CTL_START_CMD:
  2000. cnic_hold(dev);
  2001. if (!cnic_start_hw(dev))
  2002. cnic_ulp_start(dev);
  2003. cnic_put(dev);
  2004. break;
  2005. case CNIC_CTL_COMPLETION_CMD: {
  2006. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2007. u32 l5_cid;
  2008. struct cnic_local *cp = dev->cnic_priv;
  2009. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2010. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2011. ctx->wait_cond = 1;
  2012. wake_up(&ctx->waitq);
  2013. }
  2014. break;
  2015. }
  2016. default:
  2017. return -EINVAL;
  2018. }
  2019. return 0;
  2020. }
  2021. static void cnic_ulp_init(struct cnic_dev *dev)
  2022. {
  2023. int i;
  2024. struct cnic_local *cp = dev->cnic_priv;
  2025. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2026. struct cnic_ulp_ops *ulp_ops;
  2027. mutex_lock(&cnic_lock);
  2028. ulp_ops = cnic_ulp_tbl[i];
  2029. if (!ulp_ops || !ulp_ops->cnic_init) {
  2030. mutex_unlock(&cnic_lock);
  2031. continue;
  2032. }
  2033. ulp_get(ulp_ops);
  2034. mutex_unlock(&cnic_lock);
  2035. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2036. ulp_ops->cnic_init(dev);
  2037. ulp_put(ulp_ops);
  2038. }
  2039. }
  2040. static void cnic_ulp_exit(struct cnic_dev *dev)
  2041. {
  2042. int i;
  2043. struct cnic_local *cp = dev->cnic_priv;
  2044. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2045. struct cnic_ulp_ops *ulp_ops;
  2046. mutex_lock(&cnic_lock);
  2047. ulp_ops = cnic_ulp_tbl[i];
  2048. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2049. mutex_unlock(&cnic_lock);
  2050. continue;
  2051. }
  2052. ulp_get(ulp_ops);
  2053. mutex_unlock(&cnic_lock);
  2054. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2055. ulp_ops->cnic_exit(dev);
  2056. ulp_put(ulp_ops);
  2057. }
  2058. }
  2059. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2060. {
  2061. struct cnic_dev *dev = csk->dev;
  2062. struct l4_kwq_offload_pg *l4kwqe;
  2063. struct kwqe *wqes[1];
  2064. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2065. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2066. wqes[0] = (struct kwqe *) l4kwqe;
  2067. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2068. l4kwqe->flags =
  2069. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2070. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2071. l4kwqe->da0 = csk->ha[0];
  2072. l4kwqe->da1 = csk->ha[1];
  2073. l4kwqe->da2 = csk->ha[2];
  2074. l4kwqe->da3 = csk->ha[3];
  2075. l4kwqe->da4 = csk->ha[4];
  2076. l4kwqe->da5 = csk->ha[5];
  2077. l4kwqe->sa0 = dev->mac_addr[0];
  2078. l4kwqe->sa1 = dev->mac_addr[1];
  2079. l4kwqe->sa2 = dev->mac_addr[2];
  2080. l4kwqe->sa3 = dev->mac_addr[3];
  2081. l4kwqe->sa4 = dev->mac_addr[4];
  2082. l4kwqe->sa5 = dev->mac_addr[5];
  2083. l4kwqe->etype = ETH_P_IP;
  2084. l4kwqe->ipid_count = DEF_IPID_COUNT;
  2085. l4kwqe->host_opaque = csk->l5_cid;
  2086. if (csk->vlan_id) {
  2087. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2088. l4kwqe->vlan_tag = csk->vlan_id;
  2089. l4kwqe->l2hdr_nbytes += 4;
  2090. }
  2091. return dev->submit_kwqes(dev, wqes, 1);
  2092. }
  2093. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2094. {
  2095. struct cnic_dev *dev = csk->dev;
  2096. struct l4_kwq_update_pg *l4kwqe;
  2097. struct kwqe *wqes[1];
  2098. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2099. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2100. wqes[0] = (struct kwqe *) l4kwqe;
  2101. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2102. l4kwqe->flags =
  2103. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2104. l4kwqe->pg_cid = csk->pg_cid;
  2105. l4kwqe->da0 = csk->ha[0];
  2106. l4kwqe->da1 = csk->ha[1];
  2107. l4kwqe->da2 = csk->ha[2];
  2108. l4kwqe->da3 = csk->ha[3];
  2109. l4kwqe->da4 = csk->ha[4];
  2110. l4kwqe->da5 = csk->ha[5];
  2111. l4kwqe->pg_host_opaque = csk->l5_cid;
  2112. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2113. return dev->submit_kwqes(dev, wqes, 1);
  2114. }
  2115. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2116. {
  2117. struct cnic_dev *dev = csk->dev;
  2118. struct l4_kwq_upload *l4kwqe;
  2119. struct kwqe *wqes[1];
  2120. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2121. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2122. wqes[0] = (struct kwqe *) l4kwqe;
  2123. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2124. l4kwqe->flags =
  2125. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2126. l4kwqe->cid = csk->pg_cid;
  2127. return dev->submit_kwqes(dev, wqes, 1);
  2128. }
  2129. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2130. {
  2131. struct cnic_dev *dev = csk->dev;
  2132. struct l4_kwq_connect_req1 *l4kwqe1;
  2133. struct l4_kwq_connect_req2 *l4kwqe2;
  2134. struct l4_kwq_connect_req3 *l4kwqe3;
  2135. struct kwqe *wqes[3];
  2136. u8 tcp_flags = 0;
  2137. int num_wqes = 2;
  2138. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2139. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2140. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2141. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2142. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2143. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2144. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2145. l4kwqe3->flags =
  2146. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2147. l4kwqe3->ka_timeout = csk->ka_timeout;
  2148. l4kwqe3->ka_interval = csk->ka_interval;
  2149. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2150. l4kwqe3->tos = csk->tos;
  2151. l4kwqe3->ttl = csk->ttl;
  2152. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2153. l4kwqe3->pmtu = csk->mtu;
  2154. l4kwqe3->rcv_buf = csk->rcv_buf;
  2155. l4kwqe3->snd_buf = csk->snd_buf;
  2156. l4kwqe3->seed = csk->seed;
  2157. wqes[0] = (struct kwqe *) l4kwqe1;
  2158. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2159. wqes[1] = (struct kwqe *) l4kwqe2;
  2160. wqes[2] = (struct kwqe *) l4kwqe3;
  2161. num_wqes = 3;
  2162. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2163. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2164. l4kwqe2->flags =
  2165. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2166. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2167. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2168. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2169. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2170. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2171. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2172. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2173. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2174. sizeof(struct tcphdr);
  2175. } else {
  2176. wqes[1] = (struct kwqe *) l4kwqe3;
  2177. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2178. sizeof(struct tcphdr);
  2179. }
  2180. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2181. l4kwqe1->flags =
  2182. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2183. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2184. l4kwqe1->cid = csk->cid;
  2185. l4kwqe1->pg_cid = csk->pg_cid;
  2186. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2187. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2188. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2189. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2190. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2191. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2192. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2193. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2194. if (csk->tcp_flags & SK_TCP_NAGLE)
  2195. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2196. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2197. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2198. if (csk->tcp_flags & SK_TCP_SACK)
  2199. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2200. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2201. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2202. l4kwqe1->tcp_flags = tcp_flags;
  2203. return dev->submit_kwqes(dev, wqes, num_wqes);
  2204. }
  2205. static int cnic_cm_close_req(struct cnic_sock *csk)
  2206. {
  2207. struct cnic_dev *dev = csk->dev;
  2208. struct l4_kwq_close_req *l4kwqe;
  2209. struct kwqe *wqes[1];
  2210. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2211. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2212. wqes[0] = (struct kwqe *) l4kwqe;
  2213. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2214. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2215. l4kwqe->cid = csk->cid;
  2216. return dev->submit_kwqes(dev, wqes, 1);
  2217. }
  2218. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2219. {
  2220. struct cnic_dev *dev = csk->dev;
  2221. struct l4_kwq_reset_req *l4kwqe;
  2222. struct kwqe *wqes[1];
  2223. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2224. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2225. wqes[0] = (struct kwqe *) l4kwqe;
  2226. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2227. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2228. l4kwqe->cid = csk->cid;
  2229. return dev->submit_kwqes(dev, wqes, 1);
  2230. }
  2231. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2232. u32 l5_cid, struct cnic_sock **csk, void *context)
  2233. {
  2234. struct cnic_local *cp = dev->cnic_priv;
  2235. struct cnic_sock *csk1;
  2236. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2237. return -EINVAL;
  2238. csk1 = &cp->csk_tbl[l5_cid];
  2239. if (atomic_read(&csk1->ref_count))
  2240. return -EAGAIN;
  2241. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2242. return -EBUSY;
  2243. csk1->dev = dev;
  2244. csk1->cid = cid;
  2245. csk1->l5_cid = l5_cid;
  2246. csk1->ulp_type = ulp_type;
  2247. csk1->context = context;
  2248. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2249. csk1->ka_interval = DEF_KA_INTERVAL;
  2250. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2251. csk1->tos = DEF_TOS;
  2252. csk1->ttl = DEF_TTL;
  2253. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2254. csk1->rcv_buf = DEF_RCV_BUF;
  2255. csk1->snd_buf = DEF_SND_BUF;
  2256. csk1->seed = DEF_SEED;
  2257. *csk = csk1;
  2258. return 0;
  2259. }
  2260. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2261. {
  2262. if (csk->src_port) {
  2263. struct cnic_dev *dev = csk->dev;
  2264. struct cnic_local *cp = dev->cnic_priv;
  2265. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2266. csk->src_port = 0;
  2267. }
  2268. }
  2269. static void cnic_close_conn(struct cnic_sock *csk)
  2270. {
  2271. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2272. cnic_cm_upload_pg(csk);
  2273. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2274. }
  2275. cnic_cm_cleanup(csk);
  2276. }
  2277. static int cnic_cm_destroy(struct cnic_sock *csk)
  2278. {
  2279. if (!cnic_in_use(csk))
  2280. return -EINVAL;
  2281. csk_hold(csk);
  2282. clear_bit(SK_F_INUSE, &csk->flags);
  2283. smp_mb__after_clear_bit();
  2284. while (atomic_read(&csk->ref_count) != 1)
  2285. msleep(1);
  2286. cnic_cm_cleanup(csk);
  2287. csk->flags = 0;
  2288. csk_put(csk);
  2289. return 0;
  2290. }
  2291. static inline u16 cnic_get_vlan(struct net_device *dev,
  2292. struct net_device **vlan_dev)
  2293. {
  2294. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2295. *vlan_dev = vlan_dev_real_dev(dev);
  2296. return vlan_dev_vlan_id(dev);
  2297. }
  2298. *vlan_dev = dev;
  2299. return 0;
  2300. }
  2301. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2302. struct dst_entry **dst)
  2303. {
  2304. #if defined(CONFIG_INET)
  2305. struct flowi fl;
  2306. int err;
  2307. struct rtable *rt;
  2308. memset(&fl, 0, sizeof(fl));
  2309. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2310. err = ip_route_output_key(&init_net, &rt, &fl);
  2311. if (!err)
  2312. *dst = &rt->u.dst;
  2313. return err;
  2314. #else
  2315. return -ENETUNREACH;
  2316. #endif
  2317. }
  2318. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2319. struct dst_entry **dst)
  2320. {
  2321. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2322. struct flowi fl;
  2323. memset(&fl, 0, sizeof(fl));
  2324. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2325. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2326. fl.oif = dst_addr->sin6_scope_id;
  2327. *dst = ip6_route_output(&init_net, NULL, &fl);
  2328. if (*dst)
  2329. return 0;
  2330. #endif
  2331. return -ENETUNREACH;
  2332. }
  2333. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2334. int ulp_type)
  2335. {
  2336. struct cnic_dev *dev = NULL;
  2337. struct dst_entry *dst;
  2338. struct net_device *netdev = NULL;
  2339. int err = -ENETUNREACH;
  2340. if (dst_addr->sin_family == AF_INET)
  2341. err = cnic_get_v4_route(dst_addr, &dst);
  2342. else if (dst_addr->sin_family == AF_INET6) {
  2343. struct sockaddr_in6 *dst_addr6 =
  2344. (struct sockaddr_in6 *) dst_addr;
  2345. err = cnic_get_v6_route(dst_addr6, &dst);
  2346. } else
  2347. return NULL;
  2348. if (err)
  2349. return NULL;
  2350. if (!dst->dev)
  2351. goto done;
  2352. cnic_get_vlan(dst->dev, &netdev);
  2353. dev = cnic_from_netdev(netdev);
  2354. done:
  2355. dst_release(dst);
  2356. if (dev)
  2357. cnic_put(dev);
  2358. return dev;
  2359. }
  2360. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2361. {
  2362. struct cnic_dev *dev = csk->dev;
  2363. struct cnic_local *cp = dev->cnic_priv;
  2364. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2365. }
  2366. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2367. {
  2368. struct cnic_dev *dev = csk->dev;
  2369. struct cnic_local *cp = dev->cnic_priv;
  2370. int is_v6, err, rc = -ENETUNREACH;
  2371. struct dst_entry *dst;
  2372. struct net_device *realdev;
  2373. u32 local_port;
  2374. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2375. saddr->remote.v6.sin6_family == AF_INET6)
  2376. is_v6 = 1;
  2377. else if (saddr->local.v4.sin_family == AF_INET &&
  2378. saddr->remote.v4.sin_family == AF_INET)
  2379. is_v6 = 0;
  2380. else
  2381. return -EINVAL;
  2382. clear_bit(SK_F_IPV6, &csk->flags);
  2383. if (is_v6) {
  2384. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2385. set_bit(SK_F_IPV6, &csk->flags);
  2386. err = cnic_get_v6_route(&saddr->remote.v6, &dst);
  2387. if (err)
  2388. return err;
  2389. if (!dst || dst->error || !dst->dev)
  2390. goto err_out;
  2391. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2392. sizeof(struct in6_addr));
  2393. csk->dst_port = saddr->remote.v6.sin6_port;
  2394. local_port = saddr->local.v6.sin6_port;
  2395. #else
  2396. return rc;
  2397. #endif
  2398. } else {
  2399. err = cnic_get_v4_route(&saddr->remote.v4, &dst);
  2400. if (err)
  2401. return err;
  2402. if (!dst || dst->error || !dst->dev)
  2403. goto err_out;
  2404. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2405. csk->dst_port = saddr->remote.v4.sin_port;
  2406. local_port = saddr->local.v4.sin_port;
  2407. }
  2408. csk->vlan_id = cnic_get_vlan(dst->dev, &realdev);
  2409. if (realdev != dev->netdev)
  2410. goto err_out;
  2411. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2412. local_port < CNIC_LOCAL_PORT_MAX) {
  2413. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2414. local_port = 0;
  2415. } else
  2416. local_port = 0;
  2417. if (!local_port) {
  2418. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2419. if (local_port == -1) {
  2420. rc = -ENOMEM;
  2421. goto err_out;
  2422. }
  2423. }
  2424. csk->src_port = local_port;
  2425. csk->mtu = dst_mtu(dst);
  2426. rc = 0;
  2427. err_out:
  2428. dst_release(dst);
  2429. return rc;
  2430. }
  2431. static void cnic_init_csk_state(struct cnic_sock *csk)
  2432. {
  2433. csk->state = 0;
  2434. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2435. clear_bit(SK_F_CLOSING, &csk->flags);
  2436. }
  2437. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2438. {
  2439. int err = 0;
  2440. if (!cnic_in_use(csk))
  2441. return -EINVAL;
  2442. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2443. return -EINVAL;
  2444. cnic_init_csk_state(csk);
  2445. err = cnic_get_route(csk, saddr);
  2446. if (err)
  2447. goto err_out;
  2448. err = cnic_resolve_addr(csk, saddr);
  2449. if (!err)
  2450. return 0;
  2451. err_out:
  2452. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2453. return err;
  2454. }
  2455. static int cnic_cm_abort(struct cnic_sock *csk)
  2456. {
  2457. struct cnic_local *cp = csk->dev->cnic_priv;
  2458. u32 opcode;
  2459. if (!cnic_in_use(csk))
  2460. return -EINVAL;
  2461. if (cnic_abort_prep(csk))
  2462. return cnic_cm_abort_req(csk);
  2463. /* Getting here means that we haven't started connect, or
  2464. * connect was not successful.
  2465. */
  2466. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2467. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2468. opcode = csk->state;
  2469. else
  2470. opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2471. cp->close_conn(csk, opcode);
  2472. return 0;
  2473. }
  2474. static int cnic_cm_close(struct cnic_sock *csk)
  2475. {
  2476. if (!cnic_in_use(csk))
  2477. return -EINVAL;
  2478. if (cnic_close_prep(csk)) {
  2479. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2480. return cnic_cm_close_req(csk);
  2481. }
  2482. return 0;
  2483. }
  2484. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2485. u8 opcode)
  2486. {
  2487. struct cnic_ulp_ops *ulp_ops;
  2488. int ulp_type = csk->ulp_type;
  2489. rcu_read_lock();
  2490. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2491. if (ulp_ops) {
  2492. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2493. ulp_ops->cm_connect_complete(csk);
  2494. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2495. ulp_ops->cm_close_complete(csk);
  2496. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2497. ulp_ops->cm_remote_abort(csk);
  2498. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2499. ulp_ops->cm_abort_complete(csk);
  2500. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2501. ulp_ops->cm_remote_close(csk);
  2502. }
  2503. rcu_read_unlock();
  2504. }
  2505. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2506. {
  2507. if (cnic_offld_prep(csk)) {
  2508. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2509. cnic_cm_update_pg(csk);
  2510. else
  2511. cnic_cm_offload_pg(csk);
  2512. }
  2513. return 0;
  2514. }
  2515. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2516. {
  2517. struct cnic_local *cp = dev->cnic_priv;
  2518. u32 l5_cid = kcqe->pg_host_opaque;
  2519. u8 opcode = kcqe->op_code;
  2520. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2521. csk_hold(csk);
  2522. if (!cnic_in_use(csk))
  2523. goto done;
  2524. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2525. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2526. goto done;
  2527. }
  2528. csk->pg_cid = kcqe->pg_cid;
  2529. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2530. cnic_cm_conn_req(csk);
  2531. done:
  2532. csk_put(csk);
  2533. }
  2534. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2535. {
  2536. struct cnic_local *cp = dev->cnic_priv;
  2537. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2538. u8 opcode = l4kcqe->op_code;
  2539. u32 l5_cid;
  2540. struct cnic_sock *csk;
  2541. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2542. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2543. cnic_cm_process_offld_pg(dev, l4kcqe);
  2544. return;
  2545. }
  2546. l5_cid = l4kcqe->conn_id;
  2547. if (opcode & 0x80)
  2548. l5_cid = l4kcqe->cid;
  2549. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2550. return;
  2551. csk = &cp->csk_tbl[l5_cid];
  2552. csk_hold(csk);
  2553. if (!cnic_in_use(csk)) {
  2554. csk_put(csk);
  2555. return;
  2556. }
  2557. switch (opcode) {
  2558. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2559. if (l4kcqe->status == 0)
  2560. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2561. smp_mb__before_clear_bit();
  2562. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2563. cnic_cm_upcall(cp, csk, opcode);
  2564. break;
  2565. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2566. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
  2567. csk->state = opcode;
  2568. /* fall through */
  2569. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2570. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2571. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2572. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2573. cp->close_conn(csk, opcode);
  2574. break;
  2575. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2576. cnic_cm_upcall(cp, csk, opcode);
  2577. break;
  2578. }
  2579. csk_put(csk);
  2580. }
  2581. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2582. {
  2583. struct cnic_dev *dev = data;
  2584. int i;
  2585. for (i = 0; i < num; i++)
  2586. cnic_cm_process_kcqe(dev, kcqe[i]);
  2587. }
  2588. static struct cnic_ulp_ops cm_ulp_ops = {
  2589. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2590. };
  2591. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2592. {
  2593. struct cnic_local *cp = dev->cnic_priv;
  2594. kfree(cp->csk_tbl);
  2595. cp->csk_tbl = NULL;
  2596. cnic_free_id_tbl(&cp->csk_port_tbl);
  2597. }
  2598. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2599. {
  2600. struct cnic_local *cp = dev->cnic_priv;
  2601. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2602. GFP_KERNEL);
  2603. if (!cp->csk_tbl)
  2604. return -ENOMEM;
  2605. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2606. CNIC_LOCAL_PORT_MIN)) {
  2607. cnic_cm_free_mem(dev);
  2608. return -ENOMEM;
  2609. }
  2610. return 0;
  2611. }
  2612. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2613. {
  2614. if ((opcode == csk->state) ||
  2615. (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
  2616. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
  2617. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
  2618. return 1;
  2619. }
  2620. return 0;
  2621. }
  2622. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2623. {
  2624. struct cnic_dev *dev = csk->dev;
  2625. struct cnic_local *cp = dev->cnic_priv;
  2626. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2627. if (cnic_ready_to_close(csk, opcode)) {
  2628. cnic_close_conn(csk);
  2629. cnic_cm_upcall(cp, csk, opcode);
  2630. }
  2631. }
  2632. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2633. {
  2634. }
  2635. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2636. {
  2637. u32 seed;
  2638. get_random_bytes(&seed, 4);
  2639. cnic_ctx_wr(dev, 45, 0, seed);
  2640. return 0;
  2641. }
  2642. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2643. {
  2644. struct cnic_dev *dev = csk->dev;
  2645. struct cnic_local *cp = dev->cnic_priv;
  2646. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2647. union l5cm_specific_data l5_data;
  2648. u32 cmd = 0;
  2649. int close_complete = 0;
  2650. switch (opcode) {
  2651. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2652. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2653. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2654. if (cnic_ready_to_close(csk, opcode))
  2655. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2656. break;
  2657. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2658. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2659. break;
  2660. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2661. close_complete = 1;
  2662. break;
  2663. }
  2664. if (cmd) {
  2665. memset(&l5_data, 0, sizeof(l5_data));
  2666. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2667. &l5_data);
  2668. } else if (close_complete) {
  2669. ctx->timestamp = jiffies;
  2670. cnic_close_conn(csk);
  2671. cnic_cm_upcall(cp, csk, csk->state);
  2672. }
  2673. }
  2674. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2675. {
  2676. }
  2677. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2678. {
  2679. struct cnic_local *cp = dev->cnic_priv;
  2680. int func = CNIC_FUNC(cp);
  2681. cnic_init_bnx2x_mac(dev);
  2682. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2683. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2684. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
  2685. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2686. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
  2687. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2688. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
  2689. DEF_MAX_DA_COUNT);
  2690. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2691. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
  2692. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2693. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
  2694. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2695. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
  2696. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2697. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
  2698. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
  2699. DEF_MAX_CWND);
  2700. return 0;
  2701. }
  2702. static int cnic_cm_open(struct cnic_dev *dev)
  2703. {
  2704. struct cnic_local *cp = dev->cnic_priv;
  2705. int err;
  2706. err = cnic_cm_alloc_mem(dev);
  2707. if (err)
  2708. return err;
  2709. err = cp->start_cm(dev);
  2710. if (err)
  2711. goto err_out;
  2712. dev->cm_create = cnic_cm_create;
  2713. dev->cm_destroy = cnic_cm_destroy;
  2714. dev->cm_connect = cnic_cm_connect;
  2715. dev->cm_abort = cnic_cm_abort;
  2716. dev->cm_close = cnic_cm_close;
  2717. dev->cm_select_dev = cnic_cm_select_dev;
  2718. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2719. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2720. return 0;
  2721. err_out:
  2722. cnic_cm_free_mem(dev);
  2723. return err;
  2724. }
  2725. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2726. {
  2727. struct cnic_local *cp = dev->cnic_priv;
  2728. int i;
  2729. cp->stop_cm(dev);
  2730. if (!cp->csk_tbl)
  2731. return 0;
  2732. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2733. struct cnic_sock *csk = &cp->csk_tbl[i];
  2734. clear_bit(SK_F_INUSE, &csk->flags);
  2735. cnic_cm_cleanup(csk);
  2736. }
  2737. cnic_cm_free_mem(dev);
  2738. return 0;
  2739. }
  2740. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2741. {
  2742. struct cnic_local *cp = dev->cnic_priv;
  2743. u32 cid_addr;
  2744. int i;
  2745. if (CHIP_NUM(cp) == CHIP_NUM_5709)
  2746. return;
  2747. cid_addr = GET_CID_ADDR(cid);
  2748. for (i = 0; i < CTX_SIZE; i += 4)
  2749. cnic_ctx_wr(dev, cid_addr, i, 0);
  2750. }
  2751. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2752. {
  2753. struct cnic_local *cp = dev->cnic_priv;
  2754. int ret = 0, i;
  2755. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2756. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2757. return 0;
  2758. for (i = 0; i < cp->ctx_blks; i++) {
  2759. int j;
  2760. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2761. u32 val;
  2762. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2763. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2764. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2765. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2766. (u64) cp->ctx_arr[i].mapping >> 32);
  2767. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2768. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2769. for (j = 0; j < 10; j++) {
  2770. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2771. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2772. break;
  2773. udelay(5);
  2774. }
  2775. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2776. ret = -EBUSY;
  2777. break;
  2778. }
  2779. }
  2780. return ret;
  2781. }
  2782. static void cnic_free_irq(struct cnic_dev *dev)
  2783. {
  2784. struct cnic_local *cp = dev->cnic_priv;
  2785. struct cnic_eth_dev *ethdev = cp->ethdev;
  2786. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2787. cp->disable_int_sync(dev);
  2788. tasklet_disable(&cp->cnic_irq_task);
  2789. free_irq(ethdev->irq_arr[0].vector, dev);
  2790. }
  2791. }
  2792. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2793. {
  2794. struct cnic_local *cp = dev->cnic_priv;
  2795. struct cnic_eth_dev *ethdev = cp->ethdev;
  2796. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2797. int err, i = 0;
  2798. int sblk_num = cp->status_blk_num;
  2799. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2800. BNX2_HC_SB_CONFIG_1;
  2801. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2802. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2803. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2804. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2805. cp->bnx2_status_blk = cp->status_blk;
  2806. cp->last_status_idx = cp->bnx2_status_blk->status_idx;
  2807. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2808. (unsigned long) dev);
  2809. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  2810. "cnic", dev);
  2811. if (err) {
  2812. tasklet_disable(&cp->cnic_irq_task);
  2813. return err;
  2814. }
  2815. while (cp->bnx2_status_blk->status_completion_producer_index &&
  2816. i < 10) {
  2817. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2818. 1 << (11 + sblk_num));
  2819. udelay(10);
  2820. i++;
  2821. barrier();
  2822. }
  2823. if (cp->bnx2_status_blk->status_completion_producer_index) {
  2824. cnic_free_irq(dev);
  2825. goto failed;
  2826. }
  2827. } else {
  2828. struct status_block *sblk = cp->status_blk;
  2829. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2830. int i = 0;
  2831. while (sblk->status_completion_producer_index && i < 10) {
  2832. CNIC_WR(dev, BNX2_HC_COMMAND,
  2833. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2834. udelay(10);
  2835. i++;
  2836. barrier();
  2837. }
  2838. if (sblk->status_completion_producer_index)
  2839. goto failed;
  2840. }
  2841. return 0;
  2842. failed:
  2843. printk(KERN_ERR PFX "%s: " "KCQ index not resetting to 0.\n",
  2844. dev->netdev->name);
  2845. return -EBUSY;
  2846. }
  2847. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2848. {
  2849. struct cnic_local *cp = dev->cnic_priv;
  2850. struct cnic_eth_dev *ethdev = cp->ethdev;
  2851. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2852. return;
  2853. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2854. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2855. }
  2856. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2857. {
  2858. struct cnic_local *cp = dev->cnic_priv;
  2859. struct cnic_eth_dev *ethdev = cp->ethdev;
  2860. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2861. return;
  2862. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2863. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2864. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2865. synchronize_irq(ethdev->irq_arr[0].vector);
  2866. }
  2867. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2868. {
  2869. struct cnic_local *cp = dev->cnic_priv;
  2870. struct cnic_eth_dev *ethdev = cp->ethdev;
  2871. u32 cid_addr, tx_cid, sb_id;
  2872. u32 val, offset0, offset1, offset2, offset3;
  2873. int i;
  2874. struct tx_bd *txbd;
  2875. dma_addr_t buf_map;
  2876. struct status_block *s_blk = cp->status_blk;
  2877. sb_id = cp->status_blk_num;
  2878. tx_cid = 20;
  2879. cnic_init_context(dev, tx_cid);
  2880. cnic_init_context(dev, tx_cid + 1);
  2881. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2882. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2883. struct status_block_msix *sblk = cp->status_blk;
  2884. tx_cid = TX_TSS_CID + sb_id - 1;
  2885. cnic_init_context(dev, tx_cid);
  2886. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2887. (TX_TSS_CID << 7));
  2888. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2889. }
  2890. cp->tx_cons = *cp->tx_cons_ptr;
  2891. cid_addr = GET_CID_ADDR(tx_cid);
  2892. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2893. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2894. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2895. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2896. offset0 = BNX2_L2CTX_TYPE_XI;
  2897. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2898. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2899. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2900. } else {
  2901. offset0 = BNX2_L2CTX_TYPE;
  2902. offset1 = BNX2_L2CTX_CMD_TYPE;
  2903. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2904. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2905. }
  2906. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2907. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2908. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2909. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2910. txbd = (struct tx_bd *) cp->l2_ring;
  2911. buf_map = cp->l2_buf_map;
  2912. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2913. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2914. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2915. }
  2916. val = (u64) cp->l2_ring_map >> 32;
  2917. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2918. txbd->tx_bd_haddr_hi = val;
  2919. val = (u64) cp->l2_ring_map & 0xffffffff;
  2920. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2921. txbd->tx_bd_haddr_lo = val;
  2922. }
  2923. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2924. {
  2925. struct cnic_local *cp = dev->cnic_priv;
  2926. struct cnic_eth_dev *ethdev = cp->ethdev;
  2927. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2928. int i;
  2929. struct rx_bd *rxbd;
  2930. struct status_block *s_blk = cp->status_blk;
  2931. sb_id = cp->status_blk_num;
  2932. cnic_init_context(dev, 2);
  2933. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2934. coal_reg = BNX2_HC_COMMAND;
  2935. coal_val = CNIC_RD(dev, coal_reg);
  2936. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2937. struct status_block_msix *sblk = cp->status_blk;
  2938. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  2939. coal_reg = BNX2_HC_COALESCE_NOW;
  2940. coal_val = 1 << (11 + sb_id);
  2941. }
  2942. i = 0;
  2943. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  2944. CNIC_WR(dev, coal_reg, coal_val);
  2945. udelay(10);
  2946. i++;
  2947. barrier();
  2948. }
  2949. cp->rx_cons = *cp->rx_cons_ptr;
  2950. cid_addr = GET_CID_ADDR(2);
  2951. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  2952. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  2953. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  2954. if (sb_id == 0)
  2955. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  2956. else
  2957. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  2958. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  2959. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  2960. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  2961. dma_addr_t buf_map;
  2962. int n = (i % cp->l2_rx_ring_size) + 1;
  2963. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  2964. rxbd->rx_bd_len = cp->l2_single_buf_size;
  2965. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  2966. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  2967. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2968. }
  2969. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  2970. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  2971. rxbd->rx_bd_haddr_hi = val;
  2972. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  2973. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  2974. rxbd->rx_bd_haddr_lo = val;
  2975. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  2976. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  2977. }
  2978. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  2979. {
  2980. struct kwqe *wqes[1], l2kwqe;
  2981. memset(&l2kwqe, 0, sizeof(l2kwqe));
  2982. wqes[0] = &l2kwqe;
  2983. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  2984. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  2985. KWQE_OPCODE_SHIFT) | 2;
  2986. dev->submit_kwqes(dev, wqes, 1);
  2987. }
  2988. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  2989. {
  2990. struct cnic_local *cp = dev->cnic_priv;
  2991. u32 val;
  2992. val = cp->func << 2;
  2993. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  2994. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  2995. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  2996. dev->mac_addr[0] = (u8) (val >> 8);
  2997. dev->mac_addr[1] = (u8) val;
  2998. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  2999. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3000. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3001. dev->mac_addr[2] = (u8) (val >> 24);
  3002. dev->mac_addr[3] = (u8) (val >> 16);
  3003. dev->mac_addr[4] = (u8) (val >> 8);
  3004. dev->mac_addr[5] = (u8) val;
  3005. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3006. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3007. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3008. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3009. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3010. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3011. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3012. }
  3013. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3014. {
  3015. struct cnic_local *cp = dev->cnic_priv;
  3016. struct cnic_eth_dev *ethdev = cp->ethdev;
  3017. struct status_block *sblk = cp->status_blk;
  3018. u32 val;
  3019. int err;
  3020. cnic_set_bnx2_mac(dev);
  3021. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3022. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3023. if (BCM_PAGE_BITS > 12)
  3024. val |= (12 - 8) << 4;
  3025. else
  3026. val |= (BCM_PAGE_BITS - 8) << 4;
  3027. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3028. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3029. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3030. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3031. err = cnic_setup_5709_context(dev, 1);
  3032. if (err)
  3033. return err;
  3034. cnic_init_context(dev, KWQ_CID);
  3035. cnic_init_context(dev, KCQ_CID);
  3036. cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3037. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3038. cp->max_kwq_idx = MAX_KWQ_IDX;
  3039. cp->kwq_prod_idx = 0;
  3040. cp->kwq_con_idx = 0;
  3041. cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
  3042. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3043. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3044. else
  3045. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3046. /* Initialize the kernel work queue context. */
  3047. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3048. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3049. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3050. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3051. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3052. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3053. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3054. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3055. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3056. val = (u32) cp->kwq_info.pgtbl_map;
  3057. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3058. cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3059. cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3060. cp->kcq_prod_idx = 0;
  3061. /* Initialize the kernel complete queue context. */
  3062. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3063. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3064. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3065. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3066. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3067. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3068. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3069. val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
  3070. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3071. val = (u32) cp->kcq_info.pgtbl_map;
  3072. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3073. cp->int_num = 0;
  3074. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3075. u32 sb_id = cp->status_blk_num;
  3076. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3077. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3078. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3079. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3080. }
  3081. /* Enable Commnad Scheduler notification when we write to the
  3082. * host producer index of the kernel contexts. */
  3083. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3084. /* Enable Command Scheduler notification when we write to either
  3085. * the Send Queue or Receive Queue producer indexes of the kernel
  3086. * bypass contexts. */
  3087. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3088. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3089. /* Notify COM when the driver post an application buffer. */
  3090. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3091. /* Set the CP and COM doorbells. These two processors polls the
  3092. * doorbell for a non zero value before running. This must be done
  3093. * after setting up the kernel queue contexts. */
  3094. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3095. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3096. cnic_init_bnx2_tx_ring(dev);
  3097. cnic_init_bnx2_rx_ring(dev);
  3098. err = cnic_init_bnx2_irq(dev);
  3099. if (err) {
  3100. printk(KERN_ERR PFX "%s: cnic_init_irq failed\n",
  3101. dev->netdev->name);
  3102. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3103. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3104. return err;
  3105. }
  3106. return 0;
  3107. }
  3108. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3109. {
  3110. struct cnic_local *cp = dev->cnic_priv;
  3111. struct cnic_eth_dev *ethdev = cp->ethdev;
  3112. u32 start_offset = ethdev->ctx_tbl_offset;
  3113. int i;
  3114. for (i = 0; i < cp->ctx_blks; i++) {
  3115. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3116. dma_addr_t map = ctx->mapping;
  3117. if (cp->ctx_align) {
  3118. unsigned long mask = cp->ctx_align - 1;
  3119. map = (map + mask) & ~mask;
  3120. }
  3121. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3122. }
  3123. }
  3124. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3125. {
  3126. struct cnic_local *cp = dev->cnic_priv;
  3127. struct cnic_eth_dev *ethdev = cp->ethdev;
  3128. int err = 0;
  3129. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3130. (unsigned long) dev);
  3131. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3132. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  3133. "cnic", dev);
  3134. if (err)
  3135. tasklet_disable(&cp->cnic_irq_task);
  3136. }
  3137. return err;
  3138. }
  3139. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3140. {
  3141. struct cnic_local *cp = dev->cnic_priv;
  3142. u8 sb_id = cp->status_blk_num;
  3143. int port = CNIC_PORT(cp);
  3144. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3145. CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
  3146. HC_INDEX_C_ISCSI_EQ_CONS),
  3147. 64 / 12);
  3148. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3149. CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
  3150. HC_INDEX_C_ISCSI_EQ_CONS), 0);
  3151. }
  3152. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3153. {
  3154. }
  3155. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
  3156. {
  3157. struct cnic_local *cp = dev->cnic_priv;
  3158. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3159. struct eth_context *context;
  3160. struct regpair context_addr;
  3161. dma_addr_t buf_map;
  3162. int func = CNIC_FUNC(cp);
  3163. int port = CNIC_PORT(cp);
  3164. int i;
  3165. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3166. u32 val;
  3167. memset(txbd, 0, BCM_PAGE_SIZE);
  3168. buf_map = cp->l2_buf_map;
  3169. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3170. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3171. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3172. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3173. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3174. reg_bd->addr_hi = start_bd->addr_hi;
  3175. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3176. start_bd->nbytes = cpu_to_le16(0x10);
  3177. start_bd->nbd = cpu_to_le16(3);
  3178. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3179. start_bd->general_data = (UNICAST_ADDRESS <<
  3180. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3181. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3182. }
  3183. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
  3184. val = (u64) cp->l2_ring_map >> 32;
  3185. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3186. context->xstorm_st_context.tx_bd_page_base_hi = val;
  3187. val = (u64) cp->l2_ring_map & 0xffffffff;
  3188. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3189. context->xstorm_st_context.tx_bd_page_base_lo = val;
  3190. context->cstorm_st_context.sb_index_number =
  3191. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
  3192. context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
  3193. context->xstorm_st_context.statistics_data = (cli |
  3194. XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
  3195. context->xstorm_ag_context.cdu_reserved =
  3196. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3197. CDU_REGION_NUMBER_XCM_AG,
  3198. ETH_CONNECTION_TYPE);
  3199. /* reset xstorm per client statistics */
  3200. val = BAR_XSTRORM_INTMEM +
  3201. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3202. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3203. CNIC_WR(dev, val + i * 4, 0);
  3204. cp->tx_cons_ptr =
  3205. &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
  3206. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
  3207. }
  3208. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
  3209. {
  3210. struct cnic_local *cp = dev->cnic_priv;
  3211. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3212. BCM_PAGE_SIZE);
  3213. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3214. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3215. struct eth_context *context;
  3216. struct regpair context_addr;
  3217. int i;
  3218. int port = CNIC_PORT(cp);
  3219. int func = CNIC_FUNC(cp);
  3220. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3221. u32 val;
  3222. struct tstorm_eth_client_config tstorm_client = {0};
  3223. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3224. dma_addr_t buf_map;
  3225. int n = (i % cp->l2_rx_ring_size) + 1;
  3226. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3227. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3228. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3229. }
  3230. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
  3231. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3232. rxbd->addr_hi = cpu_to_le32(val);
  3233. context->ustorm_st_context.common.bd_page_base_hi = val;
  3234. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3235. rxbd->addr_lo = cpu_to_le32(val);
  3236. context->ustorm_st_context.common.bd_page_base_lo = val;
  3237. context->ustorm_st_context.common.sb_index_numbers =
  3238. BNX2X_ISCSI_RX_SB_INDEX_NUM;
  3239. context->ustorm_st_context.common.clientId = cli;
  3240. context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
  3241. context->ustorm_st_context.common.flags =
  3242. USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
  3243. context->ustorm_st_context.common.statistics_counter_id = cli;
  3244. context->ustorm_st_context.common.mc_alignment_log_size = 0;
  3245. context->ustorm_st_context.common.bd_buff_size =
  3246. cp->l2_single_buf_size;
  3247. context->ustorm_ag_context.cdu_usage =
  3248. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3249. CDU_REGION_NUMBER_UCM_AG,
  3250. ETH_CONNECTION_TYPE);
  3251. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3252. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3253. rxcqe->addr_hi = cpu_to_le32(val);
  3254. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3255. USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
  3256. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3257. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
  3258. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3259. rxcqe->addr_lo = cpu_to_le32(val);
  3260. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3261. USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
  3262. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3263. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
  3264. /* client tstorm info */
  3265. tstorm_client.mtu = cp->l2_single_buf_size - 14;
  3266. tstorm_client.config_flags =
  3267. (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
  3268. TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
  3269. tstorm_client.statistics_counter_id = cli;
  3270. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3271. TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
  3272. ((u32 *)&tstorm_client)[0]);
  3273. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3274. TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
  3275. ((u32 *)&tstorm_client)[1]);
  3276. /* reset tstorm per client statistics */
  3277. val = BAR_TSTRORM_INTMEM +
  3278. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3279. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3280. CNIC_WR(dev, val + i * 4, 0);
  3281. /* reset ustorm per client statistics */
  3282. val = BAR_USTRORM_INTMEM +
  3283. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3284. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3285. CNIC_WR(dev, val + i * 4, 0);
  3286. cp->rx_cons_ptr =
  3287. &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
  3288. HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
  3289. }
  3290. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3291. {
  3292. struct cnic_local *cp = dev->cnic_priv;
  3293. u32 base, addr, val;
  3294. int port = CNIC_PORT(cp);
  3295. dev->max_iscsi_conn = 0;
  3296. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3297. if (base < 0xa0000 || base >= 0xc0000)
  3298. return;
  3299. val = BNX2X_SHMEM_ADDR(base,
  3300. dev_info.port_hw_config[port].iscsi_mac_upper);
  3301. dev->mac_addr[0] = (u8) (val >> 8);
  3302. dev->mac_addr[1] = (u8) val;
  3303. val = BNX2X_SHMEM_ADDR(base,
  3304. dev_info.port_hw_config[port].iscsi_mac_lower);
  3305. dev->mac_addr[2] = (u8) (val >> 24);
  3306. dev->mac_addr[3] = (u8) (val >> 16);
  3307. dev->mac_addr[4] = (u8) (val >> 8);
  3308. dev->mac_addr[5] = (u8) val;
  3309. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3310. val = CNIC_RD(dev, addr);
  3311. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3312. u16 val16;
  3313. addr = BNX2X_SHMEM_ADDR(base,
  3314. drv_lic_key[port].max_iscsi_init_conn);
  3315. val16 = CNIC_RD16(dev, addr);
  3316. if (val16)
  3317. val16 ^= 0x1e1e;
  3318. dev->max_iscsi_conn = val16;
  3319. }
  3320. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3321. int func = CNIC_FUNC(cp);
  3322. addr = BNX2X_SHMEM_ADDR(base,
  3323. mf_cfg.func_mf_config[func].e1hov_tag);
  3324. val = CNIC_RD(dev, addr);
  3325. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3326. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3327. addr = BNX2X_SHMEM_ADDR(base,
  3328. mf_cfg.func_mf_config[func].config);
  3329. val = CNIC_RD(dev, addr);
  3330. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3331. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3332. dev->max_iscsi_conn = 0;
  3333. }
  3334. }
  3335. }
  3336. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3337. {
  3338. struct cnic_local *cp = dev->cnic_priv;
  3339. int func = CNIC_FUNC(cp), ret, i;
  3340. int port = CNIC_PORT(cp);
  3341. u16 eq_idx;
  3342. u8 sb_id = cp->status_blk_num;
  3343. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3344. BNX2X_ISCSI_START_CID);
  3345. if (ret)
  3346. return -ENOMEM;
  3347. cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
  3348. CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
  3349. cp->kcq_prod_idx = 0;
  3350. cnic_get_bnx2x_iscsi_info(dev);
  3351. /* Only 1 EQ */
  3352. CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
  3353. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3354. CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
  3355. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3356. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
  3357. cp->kcq_info.pg_map_arr[1] & 0xffffffff);
  3358. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3359. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
  3360. (u64) cp->kcq_info.pg_map_arr[1] >> 32);
  3361. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3362. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
  3363. cp->kcq_info.pg_map_arr[0] & 0xffffffff);
  3364. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3365. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
  3366. (u64) cp->kcq_info.pg_map_arr[0] >> 32);
  3367. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3368. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
  3369. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3370. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
  3371. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3372. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
  3373. HC_INDEX_C_ISCSI_EQ_CONS);
  3374. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3375. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3376. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
  3377. cp->conn_buf_info.pgtbl[2 * i]);
  3378. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3379. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
  3380. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3381. }
  3382. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3383. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
  3384. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3385. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3386. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
  3387. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3388. cnic_setup_bnx2x_context(dev);
  3389. eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
  3390. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3391. offsetof(struct cstorm_status_block_c,
  3392. index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
  3393. if (eq_idx != 0) {
  3394. printk(KERN_ERR PFX "%s: EQ cons index %x != 0\n",
  3395. dev->netdev->name, eq_idx);
  3396. return -EBUSY;
  3397. }
  3398. ret = cnic_init_bnx2x_irq(dev);
  3399. if (ret)
  3400. return ret;
  3401. cnic_init_bnx2x_tx_ring(dev);
  3402. cnic_init_bnx2x_rx_ring(dev);
  3403. return 0;
  3404. }
  3405. static void cnic_init_rings(struct cnic_dev *dev)
  3406. {
  3407. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3408. cnic_init_bnx2_tx_ring(dev);
  3409. cnic_init_bnx2_rx_ring(dev);
  3410. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3411. struct cnic_local *cp = dev->cnic_priv;
  3412. struct cnic_eth_dev *ethdev = cp->ethdev;
  3413. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3414. union l5cm_specific_data l5_data;
  3415. struct ustorm_eth_rx_producers rx_prods = {0};
  3416. void __iomem *doorbell;
  3417. int i;
  3418. rx_prods.bd_prod = 0;
  3419. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3420. barrier();
  3421. doorbell = ethdev->io_base2 + BAR_USTRORM_INTMEM +
  3422. USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
  3423. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3424. writel(((u32 *) &rx_prods)[i], doorbell + i * 4);
  3425. cnic_init_bnx2x_tx_ring(dev);
  3426. cnic_init_bnx2x_rx_ring(dev);
  3427. l5_data.phy_address.lo = cli;
  3428. l5_data.phy_address.hi = 0;
  3429. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3430. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3431. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3432. }
  3433. }
  3434. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3435. {
  3436. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3437. cnic_shutdown_bnx2_rx_ring(dev);
  3438. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3439. struct cnic_local *cp = dev->cnic_priv;
  3440. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3441. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3442. }
  3443. }
  3444. static int cnic_register_netdev(struct cnic_dev *dev)
  3445. {
  3446. struct cnic_local *cp = dev->cnic_priv;
  3447. struct cnic_eth_dev *ethdev = cp->ethdev;
  3448. int err;
  3449. if (!ethdev)
  3450. return -ENODEV;
  3451. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3452. return 0;
  3453. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3454. if (err)
  3455. printk(KERN_ERR PFX "%s: register_cnic failed\n",
  3456. dev->netdev->name);
  3457. return err;
  3458. }
  3459. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3460. {
  3461. struct cnic_local *cp = dev->cnic_priv;
  3462. struct cnic_eth_dev *ethdev = cp->ethdev;
  3463. if (!ethdev)
  3464. return;
  3465. ethdev->drv_unregister_cnic(dev->netdev);
  3466. }
  3467. static int cnic_start_hw(struct cnic_dev *dev)
  3468. {
  3469. struct cnic_local *cp = dev->cnic_priv;
  3470. struct cnic_eth_dev *ethdev = cp->ethdev;
  3471. int err;
  3472. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3473. return -EALREADY;
  3474. dev->regview = ethdev->io_base;
  3475. cp->chip_id = ethdev->chip_id;
  3476. pci_dev_get(dev->pcidev);
  3477. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3478. cp->status_blk = ethdev->irq_arr[0].status_blk;
  3479. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3480. err = cp->alloc_resc(dev);
  3481. if (err) {
  3482. printk(KERN_ERR PFX "%s: allocate resource failure\n",
  3483. dev->netdev->name);
  3484. goto err1;
  3485. }
  3486. err = cp->start_hw(dev);
  3487. if (err)
  3488. goto err1;
  3489. err = cnic_cm_open(dev);
  3490. if (err)
  3491. goto err1;
  3492. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3493. cp->enable_int(dev);
  3494. return 0;
  3495. err1:
  3496. cp->free_resc(dev);
  3497. pci_dev_put(dev->pcidev);
  3498. return err;
  3499. }
  3500. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3501. {
  3502. cnic_disable_bnx2_int_sync(dev);
  3503. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3504. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3505. cnic_init_context(dev, KWQ_CID);
  3506. cnic_init_context(dev, KCQ_CID);
  3507. cnic_setup_5709_context(dev, 0);
  3508. cnic_free_irq(dev);
  3509. cnic_free_resc(dev);
  3510. }
  3511. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3512. {
  3513. struct cnic_local *cp = dev->cnic_priv;
  3514. u8 sb_id = cp->status_blk_num;
  3515. int port = CNIC_PORT(cp);
  3516. cnic_free_irq(dev);
  3517. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3518. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3519. offsetof(struct cstorm_status_block_c,
  3520. index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
  3521. 0);
  3522. cnic_free_resc(dev);
  3523. }
  3524. static void cnic_stop_hw(struct cnic_dev *dev)
  3525. {
  3526. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3527. struct cnic_local *cp = dev->cnic_priv;
  3528. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3529. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3530. synchronize_rcu();
  3531. cnic_cm_shutdown(dev);
  3532. cp->stop_hw(dev);
  3533. pci_dev_put(dev->pcidev);
  3534. }
  3535. }
  3536. static void cnic_free_dev(struct cnic_dev *dev)
  3537. {
  3538. int i = 0;
  3539. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3540. msleep(100);
  3541. i++;
  3542. }
  3543. if (atomic_read(&dev->ref_count) != 0)
  3544. printk(KERN_ERR PFX "%s: Failed waiting for ref count to go"
  3545. " to zero.\n", dev->netdev->name);
  3546. printk(KERN_INFO PFX "Removed CNIC device: %s\n", dev->netdev->name);
  3547. dev_put(dev->netdev);
  3548. kfree(dev);
  3549. }
  3550. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3551. struct pci_dev *pdev)
  3552. {
  3553. struct cnic_dev *cdev;
  3554. struct cnic_local *cp;
  3555. int alloc_size;
  3556. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3557. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3558. if (cdev == NULL) {
  3559. printk(KERN_ERR PFX "%s: allocate dev struct failure\n",
  3560. dev->name);
  3561. return NULL;
  3562. }
  3563. cdev->netdev = dev;
  3564. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3565. cdev->register_device = cnic_register_device;
  3566. cdev->unregister_device = cnic_unregister_device;
  3567. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3568. cp = cdev->cnic_priv;
  3569. cp->dev = cdev;
  3570. cp->uio_dev = -1;
  3571. cp->l2_single_buf_size = 0x400;
  3572. cp->l2_rx_ring_size = 3;
  3573. spin_lock_init(&cp->cnic_ulp_lock);
  3574. printk(KERN_INFO PFX "Added CNIC device: %s\n", dev->name);
  3575. return cdev;
  3576. }
  3577. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3578. {
  3579. struct pci_dev *pdev;
  3580. struct cnic_dev *cdev;
  3581. struct cnic_local *cp;
  3582. struct cnic_eth_dev *ethdev = NULL;
  3583. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3584. probe = symbol_get(bnx2_cnic_probe);
  3585. if (probe) {
  3586. ethdev = (*probe)(dev);
  3587. symbol_put(bnx2_cnic_probe);
  3588. }
  3589. if (!ethdev)
  3590. return NULL;
  3591. pdev = ethdev->pdev;
  3592. if (!pdev)
  3593. return NULL;
  3594. dev_hold(dev);
  3595. pci_dev_get(pdev);
  3596. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3597. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3598. u8 rev;
  3599. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3600. if (rev < 0x10) {
  3601. pci_dev_put(pdev);
  3602. goto cnic_err;
  3603. }
  3604. }
  3605. pci_dev_put(pdev);
  3606. cdev = cnic_alloc_dev(dev, pdev);
  3607. if (cdev == NULL)
  3608. goto cnic_err;
  3609. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3610. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3611. cp = cdev->cnic_priv;
  3612. cp->ethdev = ethdev;
  3613. cdev->pcidev = pdev;
  3614. cp->cnic_ops = &cnic_bnx2_ops;
  3615. cp->start_hw = cnic_start_bnx2_hw;
  3616. cp->stop_hw = cnic_stop_bnx2_hw;
  3617. cp->setup_pgtbl = cnic_setup_page_tbl;
  3618. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3619. cp->free_resc = cnic_free_resc;
  3620. cp->start_cm = cnic_cm_init_bnx2_hw;
  3621. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3622. cp->enable_int = cnic_enable_bnx2_int;
  3623. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3624. cp->close_conn = cnic_close_bnx2_conn;
  3625. cp->next_idx = cnic_bnx2_next_idx;
  3626. cp->hw_idx = cnic_bnx2_hw_idx;
  3627. return cdev;
  3628. cnic_err:
  3629. dev_put(dev);
  3630. return NULL;
  3631. }
  3632. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3633. {
  3634. struct pci_dev *pdev;
  3635. struct cnic_dev *cdev;
  3636. struct cnic_local *cp;
  3637. struct cnic_eth_dev *ethdev = NULL;
  3638. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3639. probe = symbol_get(bnx2x_cnic_probe);
  3640. if (probe) {
  3641. ethdev = (*probe)(dev);
  3642. symbol_put(bnx2x_cnic_probe);
  3643. }
  3644. if (!ethdev)
  3645. return NULL;
  3646. pdev = ethdev->pdev;
  3647. if (!pdev)
  3648. return NULL;
  3649. dev_hold(dev);
  3650. cdev = cnic_alloc_dev(dev, pdev);
  3651. if (cdev == NULL) {
  3652. dev_put(dev);
  3653. return NULL;
  3654. }
  3655. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3656. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3657. cp = cdev->cnic_priv;
  3658. cp->ethdev = ethdev;
  3659. cdev->pcidev = pdev;
  3660. cp->cnic_ops = &cnic_bnx2x_ops;
  3661. cp->start_hw = cnic_start_bnx2x_hw;
  3662. cp->stop_hw = cnic_stop_bnx2x_hw;
  3663. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3664. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3665. cp->free_resc = cnic_free_resc;
  3666. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3667. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3668. cp->enable_int = cnic_enable_bnx2x_int;
  3669. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3670. cp->ack_int = cnic_ack_bnx2x_msix;
  3671. cp->close_conn = cnic_close_bnx2x_conn;
  3672. cp->next_idx = cnic_bnx2x_next_idx;
  3673. cp->hw_idx = cnic_bnx2x_hw_idx;
  3674. return cdev;
  3675. }
  3676. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3677. {
  3678. struct ethtool_drvinfo drvinfo;
  3679. struct cnic_dev *cdev = NULL;
  3680. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3681. memset(&drvinfo, 0, sizeof(drvinfo));
  3682. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3683. if (!strcmp(drvinfo.driver, "bnx2"))
  3684. cdev = init_bnx2_cnic(dev);
  3685. if (!strcmp(drvinfo.driver, "bnx2x"))
  3686. cdev = init_bnx2x_cnic(dev);
  3687. if (cdev) {
  3688. write_lock(&cnic_dev_lock);
  3689. list_add(&cdev->list, &cnic_dev_list);
  3690. write_unlock(&cnic_dev_lock);
  3691. }
  3692. }
  3693. return cdev;
  3694. }
  3695. /**
  3696. * netdev event handler
  3697. */
  3698. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3699. void *ptr)
  3700. {
  3701. struct net_device *netdev = ptr;
  3702. struct cnic_dev *dev;
  3703. int if_type;
  3704. int new_dev = 0;
  3705. dev = cnic_from_netdev(netdev);
  3706. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3707. /* Check for the hot-plug device */
  3708. dev = is_cnic_dev(netdev);
  3709. if (dev) {
  3710. new_dev = 1;
  3711. cnic_hold(dev);
  3712. }
  3713. }
  3714. if (dev) {
  3715. struct cnic_local *cp = dev->cnic_priv;
  3716. if (new_dev)
  3717. cnic_ulp_init(dev);
  3718. else if (event == NETDEV_UNREGISTER)
  3719. cnic_ulp_exit(dev);
  3720. if (event == NETDEV_UP) {
  3721. if (cnic_register_netdev(dev) != 0) {
  3722. cnic_put(dev);
  3723. goto done;
  3724. }
  3725. if (!cnic_start_hw(dev))
  3726. cnic_ulp_start(dev);
  3727. }
  3728. rcu_read_lock();
  3729. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3730. struct cnic_ulp_ops *ulp_ops;
  3731. void *ctx;
  3732. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3733. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3734. continue;
  3735. ctx = cp->ulp_handle[if_type];
  3736. ulp_ops->indicate_netevent(ctx, event);
  3737. }
  3738. rcu_read_unlock();
  3739. if (event == NETDEV_GOING_DOWN) {
  3740. cnic_ulp_stop(dev);
  3741. cnic_stop_hw(dev);
  3742. cnic_unregister_netdev(dev);
  3743. } else if (event == NETDEV_UNREGISTER) {
  3744. write_lock(&cnic_dev_lock);
  3745. list_del_init(&dev->list);
  3746. write_unlock(&cnic_dev_lock);
  3747. cnic_put(dev);
  3748. cnic_free_dev(dev);
  3749. goto done;
  3750. }
  3751. cnic_put(dev);
  3752. }
  3753. done:
  3754. return NOTIFY_DONE;
  3755. }
  3756. static struct notifier_block cnic_netdev_notifier = {
  3757. .notifier_call = cnic_netdev_event
  3758. };
  3759. static void cnic_release(void)
  3760. {
  3761. struct cnic_dev *dev;
  3762. while (!list_empty(&cnic_dev_list)) {
  3763. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3764. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3765. cnic_ulp_stop(dev);
  3766. cnic_stop_hw(dev);
  3767. }
  3768. cnic_ulp_exit(dev);
  3769. cnic_unregister_netdev(dev);
  3770. list_del_init(&dev->list);
  3771. cnic_free_dev(dev);
  3772. }
  3773. }
  3774. static int __init cnic_init(void)
  3775. {
  3776. int rc = 0;
  3777. printk(KERN_INFO "%s", version);
  3778. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3779. if (rc) {
  3780. cnic_release();
  3781. return rc;
  3782. }
  3783. return 0;
  3784. }
  3785. static void __exit cnic_exit(void)
  3786. {
  3787. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3788. cnic_release();
  3789. return;
  3790. }
  3791. module_init(cnic_init);
  3792. module_exit(cnic_exit);