qla_os.c 109 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/moduleparam.h>
  9. #include <linux/vmalloc.h>
  10. #include <linux/delay.h>
  11. #include <linux/kthread.h>
  12. #include <linux/mutex.h>
  13. #include <linux/kobject.h>
  14. #include <linux/slab.h>
  15. #include <scsi/scsi_tcq.h>
  16. #include <scsi/scsicam.h>
  17. #include <scsi/scsi_transport.h>
  18. #include <scsi/scsi_transport_fc.h>
  19. /*
  20. * Driver version
  21. */
  22. char qla2x00_version_str[40];
  23. static int apidev_major;
  24. /*
  25. * SRB allocation cache
  26. */
  27. static struct kmem_cache *srb_cachep;
  28. /*
  29. * CT6 CTX allocation cache
  30. */
  31. static struct kmem_cache *ctx_cachep;
  32. int ql2xlogintimeout = 20;
  33. module_param(ql2xlogintimeout, int, S_IRUGO);
  34. MODULE_PARM_DESC(ql2xlogintimeout,
  35. "Login timeout value in seconds.");
  36. int qlport_down_retry;
  37. module_param(qlport_down_retry, int, S_IRUGO);
  38. MODULE_PARM_DESC(qlport_down_retry,
  39. "Maximum number of command retries to a port that returns "
  40. "a PORT-DOWN status.");
  41. int ql2xplogiabsentdevice;
  42. module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
  43. MODULE_PARM_DESC(ql2xplogiabsentdevice,
  44. "Option to enable PLOGI to devices that are not present after "
  45. "a Fabric scan. This is needed for several broken switches. "
  46. "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
  47. int ql2xloginretrycount = 0;
  48. module_param(ql2xloginretrycount, int, S_IRUGO);
  49. MODULE_PARM_DESC(ql2xloginretrycount,
  50. "Specify an alternate value for the NVRAM login retry count.");
  51. int ql2xallocfwdump = 1;
  52. module_param(ql2xallocfwdump, int, S_IRUGO);
  53. MODULE_PARM_DESC(ql2xallocfwdump,
  54. "Option to enable allocation of memory for a firmware dump "
  55. "during HBA initialization. Memory allocation requirements "
  56. "vary by ISP type. Default is 1 - allocate memory.");
  57. int ql2xextended_error_logging;
  58. module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
  59. MODULE_PARM_DESC(ql2xextended_error_logging,
  60. "Option to enable extended error logging, "
  61. "Default is 0 - no logging. 1 - log errors.");
  62. int ql2xshiftctondsd = 6;
  63. module_param(ql2xshiftctondsd, int, S_IRUGO);
  64. MODULE_PARM_DESC(ql2xshiftctondsd,
  65. "Set to control shifting of command type processing "
  66. "based on total number of SG elements.");
  67. static void qla2x00_free_device(scsi_qla_host_t *);
  68. int ql2xfdmienable=1;
  69. module_param(ql2xfdmienable, int, S_IRUGO);
  70. MODULE_PARM_DESC(ql2xfdmienable,
  71. "Enables FDMI registrations. "
  72. "0 - no FDMI. Default is 1 - perform FDMI.");
  73. #define MAX_Q_DEPTH 32
  74. static int ql2xmaxqdepth = MAX_Q_DEPTH;
  75. module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
  76. MODULE_PARM_DESC(ql2xmaxqdepth,
  77. "Maximum queue depth to report for target devices.");
  78. /* Do not change the value of this after module load */
  79. int ql2xenabledif = 1;
  80. module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
  81. MODULE_PARM_DESC(ql2xenabledif,
  82. " Enable T10-CRC-DIF "
  83. " Default is 0 - No DIF Support. 1 - Enable it");
  84. int ql2xenablehba_err_chk;
  85. module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
  86. MODULE_PARM_DESC(ql2xenablehba_err_chk,
  87. " Enable T10-CRC-DIF Error isolation by HBA"
  88. " Default is 0 - Error isolation disabled, 1 - Enable it");
  89. int ql2xiidmaenable=1;
  90. module_param(ql2xiidmaenable, int, S_IRUGO);
  91. MODULE_PARM_DESC(ql2xiidmaenable,
  92. "Enables iIDMA settings "
  93. "Default is 1 - perform iIDMA. 0 - no iIDMA.");
  94. int ql2xmaxqueues = 1;
  95. module_param(ql2xmaxqueues, int, S_IRUGO);
  96. MODULE_PARM_DESC(ql2xmaxqueues,
  97. "Enables MQ settings "
  98. "Default is 1 for single queue. Set it to number "
  99. "of queues in MQ mode.");
  100. int ql2xmultique_tag;
  101. module_param(ql2xmultique_tag, int, S_IRUGO);
  102. MODULE_PARM_DESC(ql2xmultique_tag,
  103. "Enables CPU affinity settings for the driver "
  104. "Default is 0 for no affinity of request and response IO. "
  105. "Set it to 1 to turn on the cpu affinity.");
  106. int ql2xfwloadbin;
  107. module_param(ql2xfwloadbin, int, S_IRUGO);
  108. MODULE_PARM_DESC(ql2xfwloadbin,
  109. "Option to specify location from which to load ISP firmware:\n"
  110. " 2 -- load firmware via the request_firmware() (hotplug)\n"
  111. " interface.\n"
  112. " 1 -- load firmware from flash.\n"
  113. " 0 -- use default semantics.\n");
  114. int ql2xetsenable;
  115. module_param(ql2xetsenable, int, S_IRUGO);
  116. MODULE_PARM_DESC(ql2xetsenable,
  117. "Enables firmware ETS burst."
  118. "Default is 0 - skip ETS enablement.");
  119. int ql2xdbwr = 1;
  120. module_param(ql2xdbwr, int, S_IRUGO);
  121. MODULE_PARM_DESC(ql2xdbwr,
  122. "Option to specify scheme for request queue posting\n"
  123. " 0 -- Regular doorbell.\n"
  124. " 1 -- CAMRAM doorbell (faster).\n");
  125. int ql2xtargetreset = 1;
  126. module_param(ql2xtargetreset, int, S_IRUGO);
  127. MODULE_PARM_DESC(ql2xtargetreset,
  128. "Enable target reset."
  129. "Default is 1 - use hw defaults.");
  130. int ql2xgffidenable;
  131. module_param(ql2xgffidenable, int, S_IRUGO);
  132. MODULE_PARM_DESC(ql2xgffidenable,
  133. "Enables GFF_ID checks of port type. "
  134. "Default is 0 - Do not use GFF_ID information.");
  135. int ql2xasynctmfenable;
  136. module_param(ql2xasynctmfenable, int, S_IRUGO);
  137. MODULE_PARM_DESC(ql2xasynctmfenable,
  138. "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
  139. "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
  140. /*
  141. * SCSI host template entry points
  142. */
  143. static int qla2xxx_slave_configure(struct scsi_device * device);
  144. static int qla2xxx_slave_alloc(struct scsi_device *);
  145. static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
  146. static void qla2xxx_scan_start(struct Scsi_Host *);
  147. static void qla2xxx_slave_destroy(struct scsi_device *);
  148. static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  149. static int qla2xxx_eh_abort(struct scsi_cmnd *);
  150. static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
  151. static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
  152. static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
  153. static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
  154. static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
  155. static int qla2x00_change_queue_type(struct scsi_device *, int);
  156. struct scsi_host_template qla2xxx_driver_template = {
  157. .module = THIS_MODULE,
  158. .name = QLA2XXX_DRIVER_NAME,
  159. .queuecommand = qla2xxx_queuecommand,
  160. .eh_abort_handler = qla2xxx_eh_abort,
  161. .eh_device_reset_handler = qla2xxx_eh_device_reset,
  162. .eh_target_reset_handler = qla2xxx_eh_target_reset,
  163. .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
  164. .eh_host_reset_handler = qla2xxx_eh_host_reset,
  165. .slave_configure = qla2xxx_slave_configure,
  166. .slave_alloc = qla2xxx_slave_alloc,
  167. .slave_destroy = qla2xxx_slave_destroy,
  168. .scan_finished = qla2xxx_scan_finished,
  169. .scan_start = qla2xxx_scan_start,
  170. .change_queue_depth = qla2x00_change_queue_depth,
  171. .change_queue_type = qla2x00_change_queue_type,
  172. .this_id = -1,
  173. .cmd_per_lun = 3,
  174. .use_clustering = ENABLE_CLUSTERING,
  175. .sg_tablesize = SG_ALL,
  176. .max_sectors = 0xFFFF,
  177. .shost_attrs = qla2x00_host_attrs,
  178. };
  179. static struct scsi_transport_template *qla2xxx_transport_template = NULL;
  180. struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
  181. /* TODO Convert to inlines
  182. *
  183. * Timer routines
  184. */
  185. __inline__ void
  186. qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
  187. {
  188. init_timer(&vha->timer);
  189. vha->timer.expires = jiffies + interval * HZ;
  190. vha->timer.data = (unsigned long)vha;
  191. vha->timer.function = (void (*)(unsigned long))func;
  192. add_timer(&vha->timer);
  193. vha->timer_active = 1;
  194. }
  195. static inline void
  196. qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
  197. {
  198. /* Currently used for 82XX only. */
  199. if (vha->device_flags & DFLG_DEV_FAILED)
  200. return;
  201. mod_timer(&vha->timer, jiffies + interval * HZ);
  202. }
  203. static __inline__ void
  204. qla2x00_stop_timer(scsi_qla_host_t *vha)
  205. {
  206. del_timer_sync(&vha->timer);
  207. vha->timer_active = 0;
  208. }
  209. static int qla2x00_do_dpc(void *data);
  210. static void qla2x00_rst_aen(scsi_qla_host_t *);
  211. static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
  212. struct req_que **, struct rsp_que **);
  213. static void qla2x00_free_fw_dump(struct qla_hw_data *);
  214. static void qla2x00_mem_free(struct qla_hw_data *);
  215. static void qla2x00_sp_free_dma(srb_t *);
  216. /* -------------------------------------------------------------------------- */
  217. static int qla2x00_alloc_queues(struct qla_hw_data *ha)
  218. {
  219. ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
  220. GFP_KERNEL);
  221. if (!ha->req_q_map) {
  222. qla_printk(KERN_WARNING, ha,
  223. "Unable to allocate memory for request queue ptrs\n");
  224. goto fail_req_map;
  225. }
  226. ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
  227. GFP_KERNEL);
  228. if (!ha->rsp_q_map) {
  229. qla_printk(KERN_WARNING, ha,
  230. "Unable to allocate memory for response queue ptrs\n");
  231. goto fail_rsp_map;
  232. }
  233. set_bit(0, ha->rsp_qid_map);
  234. set_bit(0, ha->req_qid_map);
  235. return 1;
  236. fail_rsp_map:
  237. kfree(ha->req_q_map);
  238. ha->req_q_map = NULL;
  239. fail_req_map:
  240. return -ENOMEM;
  241. }
  242. static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
  243. {
  244. if (req && req->ring)
  245. dma_free_coherent(&ha->pdev->dev,
  246. (req->length + 1) * sizeof(request_t),
  247. req->ring, req->dma);
  248. kfree(req);
  249. req = NULL;
  250. }
  251. static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
  252. {
  253. if (rsp && rsp->ring)
  254. dma_free_coherent(&ha->pdev->dev,
  255. (rsp->length + 1) * sizeof(response_t),
  256. rsp->ring, rsp->dma);
  257. kfree(rsp);
  258. rsp = NULL;
  259. }
  260. static void qla2x00_free_queues(struct qla_hw_data *ha)
  261. {
  262. struct req_que *req;
  263. struct rsp_que *rsp;
  264. int cnt;
  265. for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
  266. req = ha->req_q_map[cnt];
  267. qla2x00_free_req_que(ha, req);
  268. }
  269. kfree(ha->req_q_map);
  270. ha->req_q_map = NULL;
  271. for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
  272. rsp = ha->rsp_q_map[cnt];
  273. qla2x00_free_rsp_que(ha, rsp);
  274. }
  275. kfree(ha->rsp_q_map);
  276. ha->rsp_q_map = NULL;
  277. }
  278. static int qla25xx_setup_mode(struct scsi_qla_host *vha)
  279. {
  280. uint16_t options = 0;
  281. int ques, req, ret;
  282. struct qla_hw_data *ha = vha->hw;
  283. if (!(ha->fw_attributes & BIT_6)) {
  284. qla_printk(KERN_INFO, ha,
  285. "Firmware is not multi-queue capable\n");
  286. goto fail;
  287. }
  288. if (ql2xmultique_tag) {
  289. /* create a request queue for IO */
  290. options |= BIT_7;
  291. req = qla25xx_create_req_que(ha, options, 0, 0, -1,
  292. QLA_DEFAULT_QUE_QOS);
  293. if (!req) {
  294. qla_printk(KERN_WARNING, ha,
  295. "Can't create request queue\n");
  296. goto fail;
  297. }
  298. ha->wq = create_workqueue("qla2xxx_wq");
  299. vha->req = ha->req_q_map[req];
  300. options |= BIT_1;
  301. for (ques = 1; ques < ha->max_rsp_queues; ques++) {
  302. ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
  303. if (!ret) {
  304. qla_printk(KERN_WARNING, ha,
  305. "Response Queue create failed\n");
  306. goto fail2;
  307. }
  308. }
  309. ha->flags.cpu_affinity_enabled = 1;
  310. DEBUG2(qla_printk(KERN_INFO, ha,
  311. "CPU affinity mode enabled, no. of response"
  312. " queues:%d, no. of request queues:%d\n",
  313. ha->max_rsp_queues, ha->max_req_queues));
  314. }
  315. return 0;
  316. fail2:
  317. qla25xx_delete_queues(vha);
  318. destroy_workqueue(ha->wq);
  319. ha->wq = NULL;
  320. fail:
  321. ha->mqenable = 0;
  322. kfree(ha->req_q_map);
  323. kfree(ha->rsp_q_map);
  324. ha->max_req_queues = ha->max_rsp_queues = 1;
  325. return 1;
  326. }
  327. static char *
  328. qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
  329. {
  330. struct qla_hw_data *ha = vha->hw;
  331. static char *pci_bus_modes[] = {
  332. "33", "66", "100", "133",
  333. };
  334. uint16_t pci_bus;
  335. strcpy(str, "PCI");
  336. pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
  337. if (pci_bus) {
  338. strcat(str, "-X (");
  339. strcat(str, pci_bus_modes[pci_bus]);
  340. } else {
  341. pci_bus = (ha->pci_attr & BIT_8) >> 8;
  342. strcat(str, " (");
  343. strcat(str, pci_bus_modes[pci_bus]);
  344. }
  345. strcat(str, " MHz)");
  346. return (str);
  347. }
  348. static char *
  349. qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
  350. {
  351. static char *pci_bus_modes[] = { "33", "66", "100", "133", };
  352. struct qla_hw_data *ha = vha->hw;
  353. uint32_t pci_bus;
  354. int pcie_reg;
  355. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  356. if (pcie_reg) {
  357. char lwstr[6];
  358. uint16_t pcie_lstat, lspeed, lwidth;
  359. pcie_reg += 0x12;
  360. pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
  361. lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
  362. lwidth = (pcie_lstat &
  363. (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
  364. strcpy(str, "PCIe (");
  365. if (lspeed == 1)
  366. strcat(str, "2.5GT/s ");
  367. else if (lspeed == 2)
  368. strcat(str, "5.0GT/s ");
  369. else
  370. strcat(str, "<unknown> ");
  371. snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
  372. strcat(str, lwstr);
  373. return str;
  374. }
  375. strcpy(str, "PCI");
  376. pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
  377. if (pci_bus == 0 || pci_bus == 8) {
  378. strcat(str, " (");
  379. strcat(str, pci_bus_modes[pci_bus >> 3]);
  380. } else {
  381. strcat(str, "-X ");
  382. if (pci_bus & BIT_2)
  383. strcat(str, "Mode 2");
  384. else
  385. strcat(str, "Mode 1");
  386. strcat(str, " (");
  387. strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
  388. }
  389. strcat(str, " MHz)");
  390. return str;
  391. }
  392. static char *
  393. qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
  394. {
  395. char un_str[10];
  396. struct qla_hw_data *ha = vha->hw;
  397. sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
  398. ha->fw_minor_version,
  399. ha->fw_subminor_version);
  400. if (ha->fw_attributes & BIT_9) {
  401. strcat(str, "FLX");
  402. return (str);
  403. }
  404. switch (ha->fw_attributes & 0xFF) {
  405. case 0x7:
  406. strcat(str, "EF");
  407. break;
  408. case 0x17:
  409. strcat(str, "TP");
  410. break;
  411. case 0x37:
  412. strcat(str, "IP");
  413. break;
  414. case 0x77:
  415. strcat(str, "VI");
  416. break;
  417. default:
  418. sprintf(un_str, "(%x)", ha->fw_attributes);
  419. strcat(str, un_str);
  420. break;
  421. }
  422. if (ha->fw_attributes & 0x100)
  423. strcat(str, "X");
  424. return (str);
  425. }
  426. static char *
  427. qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
  428. {
  429. struct qla_hw_data *ha = vha->hw;
  430. sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
  431. ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
  432. return str;
  433. }
  434. static inline srb_t *
  435. qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
  436. struct scsi_cmnd *cmd)
  437. {
  438. srb_t *sp;
  439. struct qla_hw_data *ha = vha->hw;
  440. sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
  441. if (!sp)
  442. return sp;
  443. atomic_set(&sp->ref_count, 1);
  444. sp->fcport = fcport;
  445. sp->cmd = cmd;
  446. sp->flags = 0;
  447. CMD_SP(cmd) = (void *)sp;
  448. sp->ctx = NULL;
  449. return sp;
  450. }
  451. static int
  452. qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  453. {
  454. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  455. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  456. struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
  457. struct qla_hw_data *ha = vha->hw;
  458. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  459. srb_t *sp;
  460. int rval;
  461. if (ha->flags.eeh_busy) {
  462. if (ha->flags.pci_channel_io_perm_failure)
  463. cmd->result = DID_NO_CONNECT << 16;
  464. else
  465. cmd->result = DID_REQUEUE << 16;
  466. goto qc24_fail_command;
  467. }
  468. rval = fc_remote_port_chkready(rport);
  469. if (rval) {
  470. cmd->result = rval;
  471. goto qc24_fail_command;
  472. }
  473. if (!vha->flags.difdix_supported &&
  474. scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
  475. DEBUG2(qla_printk(KERN_ERR, ha,
  476. "DIF Cap Not Reg, fail DIF capable cmd's:%x\n",
  477. cmd->cmnd[0]));
  478. cmd->result = DID_NO_CONNECT << 16;
  479. goto qc24_fail_command;
  480. }
  481. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  482. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
  483. atomic_read(&fcport->state) == FCS_DEVICE_LOST ||
  484. atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  485. cmd->result = DID_NO_CONNECT << 16;
  486. goto qc24_fail_command;
  487. }
  488. goto qc24_target_busy;
  489. }
  490. sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
  491. if (!sp)
  492. goto qc24_host_busy;
  493. rval = ha->isp_ops->start_scsi(sp);
  494. if (rval != QLA_SUCCESS)
  495. goto qc24_host_busy_free_sp;
  496. return 0;
  497. qc24_host_busy_free_sp:
  498. qla2x00_sp_free_dma(sp);
  499. mempool_free(sp, ha->srb_mempool);
  500. qc24_host_busy:
  501. return SCSI_MLQUEUE_HOST_BUSY;
  502. qc24_target_busy:
  503. return SCSI_MLQUEUE_TARGET_BUSY;
  504. qc24_fail_command:
  505. cmd->scsi_done(cmd);
  506. return 0;
  507. }
  508. /*
  509. * qla2x00_eh_wait_on_command
  510. * Waits for the command to be returned by the Firmware for some
  511. * max time.
  512. *
  513. * Input:
  514. * cmd = Scsi Command to wait on.
  515. *
  516. * Return:
  517. * Not Found : 0
  518. * Found : 1
  519. */
  520. static int
  521. qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
  522. {
  523. #define ABORT_POLLING_PERIOD 1000
  524. #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
  525. unsigned long wait_iter = ABORT_WAIT_ITER;
  526. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  527. struct qla_hw_data *ha = vha->hw;
  528. int ret = QLA_SUCCESS;
  529. if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
  530. DEBUG17(qla_printk(KERN_WARNING, ha, "return:eh_wait\n"));
  531. return ret;
  532. }
  533. while (CMD_SP(cmd) && wait_iter--) {
  534. msleep(ABORT_POLLING_PERIOD);
  535. }
  536. if (CMD_SP(cmd))
  537. ret = QLA_FUNCTION_FAILED;
  538. return ret;
  539. }
  540. /*
  541. * qla2x00_wait_for_hba_online
  542. * Wait till the HBA is online after going through
  543. * <= MAX_RETRIES_OF_ISP_ABORT or
  544. * finally HBA is disabled ie marked offline
  545. *
  546. * Input:
  547. * ha - pointer to host adapter structure
  548. *
  549. * Note:
  550. * Does context switching-Release SPIN_LOCK
  551. * (if any) before calling this routine.
  552. *
  553. * Return:
  554. * Success (Adapter is online) : 0
  555. * Failed (Adapter is offline/disabled) : 1
  556. */
  557. int
  558. qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
  559. {
  560. int return_status;
  561. unsigned long wait_online;
  562. struct qla_hw_data *ha = vha->hw;
  563. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  564. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  565. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  566. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  567. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  568. ha->dpc_active) && time_before(jiffies, wait_online)) {
  569. msleep(1000);
  570. }
  571. if (base_vha->flags.online)
  572. return_status = QLA_SUCCESS;
  573. else
  574. return_status = QLA_FUNCTION_FAILED;
  575. return (return_status);
  576. }
  577. /*
  578. * qla2x00_wait_for_reset_ready
  579. * Wait till the HBA is online after going through
  580. * <= MAX_RETRIES_OF_ISP_ABORT or
  581. * finally HBA is disabled ie marked offline or flash
  582. * operations are in progress.
  583. *
  584. * Input:
  585. * ha - pointer to host adapter structure
  586. *
  587. * Note:
  588. * Does context switching-Release SPIN_LOCK
  589. * (if any) before calling this routine.
  590. *
  591. * Return:
  592. * Success (Adapter is online/no flash ops) : 0
  593. * Failed (Adapter is offline/disabled/flash ops in progress) : 1
  594. */
  595. static int
  596. qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
  597. {
  598. int return_status;
  599. unsigned long wait_online;
  600. struct qla_hw_data *ha = vha->hw;
  601. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  602. wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  603. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  604. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  605. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  606. ha->optrom_state != QLA_SWAITING ||
  607. ha->dpc_active) && time_before(jiffies, wait_online))
  608. msleep(1000);
  609. if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
  610. return_status = QLA_SUCCESS;
  611. else
  612. return_status = QLA_FUNCTION_FAILED;
  613. DEBUG2(printk("%s return_status=%d\n", __func__, return_status));
  614. return return_status;
  615. }
  616. int
  617. qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
  618. {
  619. int return_status;
  620. unsigned long wait_reset;
  621. struct qla_hw_data *ha = vha->hw;
  622. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  623. wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  624. while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
  625. test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
  626. test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
  627. ha->dpc_active) && time_before(jiffies, wait_reset)) {
  628. msleep(1000);
  629. if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
  630. ha->flags.chip_reset_done)
  631. break;
  632. }
  633. if (ha->flags.chip_reset_done)
  634. return_status = QLA_SUCCESS;
  635. else
  636. return_status = QLA_FUNCTION_FAILED;
  637. return return_status;
  638. }
  639. /*
  640. * qla2x00_wait_for_loop_ready
  641. * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
  642. * to be in LOOP_READY state.
  643. * Input:
  644. * ha - pointer to host adapter structure
  645. *
  646. * Note:
  647. * Does context switching-Release SPIN_LOCK
  648. * (if any) before calling this routine.
  649. *
  650. *
  651. * Return:
  652. * Success (LOOP_READY) : 0
  653. * Failed (LOOP_NOT_READY) : 1
  654. */
  655. static inline int
  656. qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
  657. {
  658. int return_status = QLA_SUCCESS;
  659. unsigned long loop_timeout ;
  660. struct qla_hw_data *ha = vha->hw;
  661. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  662. /* wait for 5 min at the max for loop to be ready */
  663. loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
  664. while ((!atomic_read(&base_vha->loop_down_timer) &&
  665. atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
  666. atomic_read(&base_vha->loop_state) != LOOP_READY) {
  667. if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
  668. return_status = QLA_FUNCTION_FAILED;
  669. break;
  670. }
  671. msleep(1000);
  672. if (time_after_eq(jiffies, loop_timeout)) {
  673. return_status = QLA_FUNCTION_FAILED;
  674. break;
  675. }
  676. }
  677. return (return_status);
  678. }
  679. static void
  680. sp_get(struct srb *sp)
  681. {
  682. atomic_inc(&sp->ref_count);
  683. }
  684. /**************************************************************************
  685. * qla2xxx_eh_abort
  686. *
  687. * Description:
  688. * The abort function will abort the specified command.
  689. *
  690. * Input:
  691. * cmd = Linux SCSI command packet to be aborted.
  692. *
  693. * Returns:
  694. * Either SUCCESS or FAILED.
  695. *
  696. * Note:
  697. * Only return FAILED if command not returned by firmware.
  698. **************************************************************************/
  699. static int
  700. qla2xxx_eh_abort(struct scsi_cmnd *cmd)
  701. {
  702. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  703. srb_t *sp;
  704. int ret = SUCCESS;
  705. unsigned int id, lun;
  706. unsigned long flags;
  707. int wait = 0;
  708. struct qla_hw_data *ha = vha->hw;
  709. fc_block_scsi_eh(cmd);
  710. if (!CMD_SP(cmd))
  711. return SUCCESS;
  712. id = cmd->device->id;
  713. lun = cmd->device->lun;
  714. spin_lock_irqsave(&ha->hardware_lock, flags);
  715. sp = (srb_t *) CMD_SP(cmd);
  716. if (!sp) {
  717. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  718. return SUCCESS;
  719. }
  720. DEBUG2(printk("%s(%ld): aborting sp %p from RISC.",
  721. __func__, vha->host_no, sp));
  722. /* Get a reference to the sp and drop the lock.*/
  723. sp_get(sp);
  724. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  725. if (ha->isp_ops->abort_command(sp)) {
  726. DEBUG2(printk("%s(%ld): abort_command "
  727. "mbx failed.\n", __func__, vha->host_no));
  728. ret = FAILED;
  729. } else {
  730. DEBUG3(printk("%s(%ld): abort_command "
  731. "mbx success.\n", __func__, vha->host_no));
  732. wait = 1;
  733. }
  734. qla2x00_sp_compl(ha, sp);
  735. /* Wait for the command to be returned. */
  736. if (wait) {
  737. if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
  738. qla_printk(KERN_ERR, ha,
  739. "scsi(%ld:%d:%d): Abort handler timed out -- %x.\n",
  740. vha->host_no, id, lun, ret);
  741. ret = FAILED;
  742. }
  743. }
  744. qla_printk(KERN_INFO, ha,
  745. "scsi(%ld:%d:%d): Abort command issued -- %d %x.\n",
  746. vha->host_no, id, lun, wait, ret);
  747. return ret;
  748. }
  749. int
  750. qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
  751. unsigned int l, enum nexus_wait_type type)
  752. {
  753. int cnt, match, status;
  754. unsigned long flags;
  755. struct qla_hw_data *ha = vha->hw;
  756. struct req_que *req;
  757. srb_t *sp;
  758. status = QLA_SUCCESS;
  759. spin_lock_irqsave(&ha->hardware_lock, flags);
  760. req = vha->req;
  761. for (cnt = 1; status == QLA_SUCCESS &&
  762. cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  763. sp = req->outstanding_cmds[cnt];
  764. if (!sp)
  765. continue;
  766. if ((sp->ctx) && !IS_PROT_IO(sp))
  767. continue;
  768. if (vha->vp_idx != sp->fcport->vha->vp_idx)
  769. continue;
  770. match = 0;
  771. switch (type) {
  772. case WAIT_HOST:
  773. match = 1;
  774. break;
  775. case WAIT_TARGET:
  776. match = sp->cmd->device->id == t;
  777. break;
  778. case WAIT_LUN:
  779. match = (sp->cmd->device->id == t &&
  780. sp->cmd->device->lun == l);
  781. break;
  782. }
  783. if (!match)
  784. continue;
  785. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  786. status = qla2x00_eh_wait_on_command(sp->cmd);
  787. spin_lock_irqsave(&ha->hardware_lock, flags);
  788. }
  789. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  790. return status;
  791. }
  792. static char *reset_errors[] = {
  793. "HBA not online",
  794. "HBA not ready",
  795. "Task management failed",
  796. "Waiting for command completions",
  797. };
  798. static int
  799. __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
  800. struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
  801. {
  802. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  803. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  804. int err;
  805. fc_block_scsi_eh(cmd);
  806. if (!fcport)
  807. return FAILED;
  808. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET ISSUED.\n",
  809. vha->host_no, cmd->device->id, cmd->device->lun, name);
  810. err = 0;
  811. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  812. goto eh_reset_failed;
  813. err = 1;
  814. if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS)
  815. goto eh_reset_failed;
  816. err = 2;
  817. if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
  818. != QLA_SUCCESS)
  819. goto eh_reset_failed;
  820. err = 3;
  821. if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
  822. cmd->device->lun, type) != QLA_SUCCESS)
  823. goto eh_reset_failed;
  824. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET SUCCEEDED.\n",
  825. vha->host_no, cmd->device->id, cmd->device->lun, name);
  826. return SUCCESS;
  827. eh_reset_failed:
  828. qla_printk(KERN_INFO, vha->hw, "scsi(%ld:%d:%d): %s RESET FAILED: %s.\n"
  829. , vha->host_no, cmd->device->id, cmd->device->lun, name,
  830. reset_errors[err]);
  831. return FAILED;
  832. }
  833. static int
  834. qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
  835. {
  836. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  837. struct qla_hw_data *ha = vha->hw;
  838. return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
  839. ha->isp_ops->lun_reset);
  840. }
  841. static int
  842. qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
  843. {
  844. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  845. struct qla_hw_data *ha = vha->hw;
  846. return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
  847. ha->isp_ops->target_reset);
  848. }
  849. /**************************************************************************
  850. * qla2xxx_eh_bus_reset
  851. *
  852. * Description:
  853. * The bus reset function will reset the bus and abort any executing
  854. * commands.
  855. *
  856. * Input:
  857. * cmd = Linux SCSI command packet of the command that cause the
  858. * bus reset.
  859. *
  860. * Returns:
  861. * SUCCESS/FAILURE (defined as macro in scsi.h).
  862. *
  863. **************************************************************************/
  864. static int
  865. qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
  866. {
  867. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  868. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  869. int ret = FAILED;
  870. unsigned int id, lun;
  871. fc_block_scsi_eh(cmd);
  872. id = cmd->device->id;
  873. lun = cmd->device->lun;
  874. if (!fcport)
  875. return ret;
  876. qla_printk(KERN_INFO, vha->hw,
  877. "scsi(%ld:%d:%d): BUS RESET ISSUED.\n", vha->host_no, id, lun);
  878. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
  879. DEBUG2(printk("%s failed:board disabled\n",__func__));
  880. goto eh_bus_reset_done;
  881. }
  882. if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
  883. if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
  884. ret = SUCCESS;
  885. }
  886. if (ret == FAILED)
  887. goto eh_bus_reset_done;
  888. /* Flush outstanding commands. */
  889. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
  890. QLA_SUCCESS)
  891. ret = FAILED;
  892. eh_bus_reset_done:
  893. qla_printk(KERN_INFO, vha->hw, "%s: reset %s\n", __func__,
  894. (ret == FAILED) ? "failed" : "succeded");
  895. return ret;
  896. }
  897. /**************************************************************************
  898. * qla2xxx_eh_host_reset
  899. *
  900. * Description:
  901. * The reset function will reset the Adapter.
  902. *
  903. * Input:
  904. * cmd = Linux SCSI command packet of the command that cause the
  905. * adapter reset.
  906. *
  907. * Returns:
  908. * Either SUCCESS or FAILED.
  909. *
  910. * Note:
  911. **************************************************************************/
  912. static int
  913. qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
  914. {
  915. scsi_qla_host_t *vha = shost_priv(cmd->device->host);
  916. fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
  917. struct qla_hw_data *ha = vha->hw;
  918. int ret = FAILED;
  919. unsigned int id, lun;
  920. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  921. fc_block_scsi_eh(cmd);
  922. id = cmd->device->id;
  923. lun = cmd->device->lun;
  924. if (!fcport)
  925. return ret;
  926. qla_printk(KERN_INFO, ha,
  927. "scsi(%ld:%d:%d): ADAPTER RESET ISSUED.\n", vha->host_no, id, lun);
  928. if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
  929. goto eh_host_reset_lock;
  930. /*
  931. * Fixme-may be dpc thread is active and processing
  932. * loop_resync,so wait a while for it to
  933. * be completed and then issue big hammer.Otherwise
  934. * it may cause I/O failure as big hammer marks the
  935. * devices as lost kicking of the port_down_timer
  936. * while dpc is stuck for the mailbox to complete.
  937. */
  938. qla2x00_wait_for_loop_ready(vha);
  939. if (vha != base_vha) {
  940. if (qla2x00_vp_abort_isp(vha))
  941. goto eh_host_reset_lock;
  942. } else {
  943. if (IS_QLA82XX(vha->hw)) {
  944. if (!qla82xx_fcoe_ctx_reset(vha)) {
  945. /* Ctx reset success */
  946. ret = SUCCESS;
  947. goto eh_host_reset_lock;
  948. }
  949. /* fall thru if ctx reset failed */
  950. }
  951. if (ha->wq)
  952. flush_workqueue(ha->wq);
  953. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  954. if (ha->isp_ops->abort_isp(base_vha)) {
  955. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  956. /* failed. schedule dpc to try */
  957. set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
  958. if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS)
  959. goto eh_host_reset_lock;
  960. }
  961. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  962. }
  963. /* Waiting for command to be returned to OS.*/
  964. if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
  965. QLA_SUCCESS)
  966. ret = SUCCESS;
  967. eh_host_reset_lock:
  968. qla_printk(KERN_INFO, ha, "%s: reset %s\n", __func__,
  969. (ret == FAILED) ? "failed" : "succeded");
  970. return ret;
  971. }
  972. /*
  973. * qla2x00_loop_reset
  974. * Issue loop reset.
  975. *
  976. * Input:
  977. * ha = adapter block pointer.
  978. *
  979. * Returns:
  980. * 0 = success
  981. */
  982. int
  983. qla2x00_loop_reset(scsi_qla_host_t *vha)
  984. {
  985. int ret;
  986. struct fc_port *fcport;
  987. struct qla_hw_data *ha = vha->hw;
  988. if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
  989. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  990. if (fcport->port_type != FCT_TARGET)
  991. continue;
  992. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  993. if (ret != QLA_SUCCESS) {
  994. DEBUG2_3(printk("%s(%ld): bus_reset failed: "
  995. "target_reset=%d d_id=%x.\n", __func__,
  996. vha->host_no, ret, fcport->d_id.b24));
  997. }
  998. }
  999. }
  1000. if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
  1001. ret = qla2x00_full_login_lip(vha);
  1002. if (ret != QLA_SUCCESS) {
  1003. DEBUG2_3(printk("%s(%ld): failed: "
  1004. "full_login_lip=%d.\n", __func__, vha->host_no,
  1005. ret));
  1006. }
  1007. atomic_set(&vha->loop_state, LOOP_DOWN);
  1008. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1009. qla2x00_mark_all_devices_lost(vha, 0);
  1010. qla2x00_wait_for_loop_ready(vha);
  1011. }
  1012. if (ha->flags.enable_lip_reset) {
  1013. ret = qla2x00_lip_reset(vha);
  1014. if (ret != QLA_SUCCESS) {
  1015. DEBUG2_3(printk("%s(%ld): failed: "
  1016. "lip_reset=%d.\n", __func__, vha->host_no, ret));
  1017. } else
  1018. qla2x00_wait_for_loop_ready(vha);
  1019. }
  1020. /* Issue marker command only when we are going to start the I/O */
  1021. vha->marker_needed = 1;
  1022. return QLA_SUCCESS;
  1023. }
  1024. void
  1025. qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
  1026. {
  1027. int que, cnt;
  1028. unsigned long flags;
  1029. srb_t *sp;
  1030. struct srb_ctx *ctx;
  1031. struct qla_hw_data *ha = vha->hw;
  1032. struct req_que *req;
  1033. spin_lock_irqsave(&ha->hardware_lock, flags);
  1034. for (que = 0; que < ha->max_req_queues; que++) {
  1035. req = ha->req_q_map[que];
  1036. if (!req)
  1037. continue;
  1038. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
  1039. sp = req->outstanding_cmds[cnt];
  1040. if (sp) {
  1041. req->outstanding_cmds[cnt] = NULL;
  1042. if (!sp->ctx ||
  1043. (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
  1044. IS_PROT_IO(sp)) {
  1045. sp->cmd->result = res;
  1046. qla2x00_sp_compl(ha, sp);
  1047. } else {
  1048. ctx = sp->ctx;
  1049. if (ctx->type == SRB_LOGIN_CMD ||
  1050. ctx->type == SRB_LOGOUT_CMD) {
  1051. ctx->u.iocb_cmd->free(sp);
  1052. } else {
  1053. struct fc_bsg_job *bsg_job =
  1054. ctx->u.bsg_job;
  1055. if (bsg_job->request->msgcode
  1056. == FC_BSG_HST_CT)
  1057. kfree(sp->fcport);
  1058. bsg_job->req->errors = 0;
  1059. bsg_job->reply->result = res;
  1060. bsg_job->job_done(bsg_job);
  1061. kfree(sp->ctx);
  1062. mempool_free(sp,
  1063. ha->srb_mempool);
  1064. }
  1065. }
  1066. }
  1067. }
  1068. }
  1069. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1070. }
  1071. static int
  1072. qla2xxx_slave_alloc(struct scsi_device *sdev)
  1073. {
  1074. struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
  1075. if (!rport || fc_remote_port_chkready(rport))
  1076. return -ENXIO;
  1077. sdev->hostdata = *(fc_port_t **)rport->dd_data;
  1078. return 0;
  1079. }
  1080. static int
  1081. qla2xxx_slave_configure(struct scsi_device *sdev)
  1082. {
  1083. scsi_qla_host_t *vha = shost_priv(sdev->host);
  1084. struct req_que *req = vha->req;
  1085. if (sdev->tagged_supported)
  1086. scsi_activate_tcq(sdev, req->max_q_depth);
  1087. else
  1088. scsi_deactivate_tcq(sdev, req->max_q_depth);
  1089. return 0;
  1090. }
  1091. static void
  1092. qla2xxx_slave_destroy(struct scsi_device *sdev)
  1093. {
  1094. sdev->hostdata = NULL;
  1095. }
  1096. static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
  1097. {
  1098. fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
  1099. if (!scsi_track_queue_full(sdev, qdepth))
  1100. return;
  1101. DEBUG2(qla_printk(KERN_INFO, fcport->vha->hw,
  1102. "scsi(%ld:%d:%d:%d): Queue depth adjusted-down to %d.\n",
  1103. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1104. sdev->queue_depth));
  1105. }
  1106. static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
  1107. {
  1108. fc_port_t *fcport = sdev->hostdata;
  1109. struct scsi_qla_host *vha = fcport->vha;
  1110. struct qla_hw_data *ha = vha->hw;
  1111. struct req_que *req = NULL;
  1112. req = vha->req;
  1113. if (!req)
  1114. return;
  1115. if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
  1116. return;
  1117. if (sdev->ordered_tags)
  1118. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
  1119. else
  1120. scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
  1121. DEBUG2(qla_printk(KERN_INFO, ha,
  1122. "scsi(%ld:%d:%d:%d): Queue depth adjusted-up to %d.\n",
  1123. fcport->vha->host_no, sdev->channel, sdev->id, sdev->lun,
  1124. sdev->queue_depth));
  1125. }
  1126. static int
  1127. qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
  1128. {
  1129. switch (reason) {
  1130. case SCSI_QDEPTH_DEFAULT:
  1131. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
  1132. break;
  1133. case SCSI_QDEPTH_QFULL:
  1134. qla2x00_handle_queue_full(sdev, qdepth);
  1135. break;
  1136. case SCSI_QDEPTH_RAMP_UP:
  1137. qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
  1138. break;
  1139. default:
  1140. return -EOPNOTSUPP;
  1141. }
  1142. return sdev->queue_depth;
  1143. }
  1144. static int
  1145. qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
  1146. {
  1147. if (sdev->tagged_supported) {
  1148. scsi_set_tag_type(sdev, tag_type);
  1149. if (tag_type)
  1150. scsi_activate_tcq(sdev, sdev->queue_depth);
  1151. else
  1152. scsi_deactivate_tcq(sdev, sdev->queue_depth);
  1153. } else
  1154. tag_type = 0;
  1155. return tag_type;
  1156. }
  1157. /**
  1158. * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
  1159. * @ha: HA context
  1160. *
  1161. * At exit, the @ha's flags.enable_64bit_addressing set to indicated
  1162. * supported addressing method.
  1163. */
  1164. static void
  1165. qla2x00_config_dma_addressing(struct qla_hw_data *ha)
  1166. {
  1167. /* Assume a 32bit DMA mask. */
  1168. ha->flags.enable_64bit_addressing = 0;
  1169. if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
  1170. /* Any upper-dword bits set? */
  1171. if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
  1172. !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
  1173. /* Ok, a 64bit DMA mask is applicable. */
  1174. ha->flags.enable_64bit_addressing = 1;
  1175. ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
  1176. ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
  1177. return;
  1178. }
  1179. }
  1180. dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
  1181. pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
  1182. }
  1183. static void
  1184. qla2x00_enable_intrs(struct qla_hw_data *ha)
  1185. {
  1186. unsigned long flags = 0;
  1187. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1188. spin_lock_irqsave(&ha->hardware_lock, flags);
  1189. ha->interrupts_on = 1;
  1190. /* enable risc and host interrupts */
  1191. WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
  1192. RD_REG_WORD(&reg->ictrl);
  1193. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1194. }
  1195. static void
  1196. qla2x00_disable_intrs(struct qla_hw_data *ha)
  1197. {
  1198. unsigned long flags = 0;
  1199. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1200. spin_lock_irqsave(&ha->hardware_lock, flags);
  1201. ha->interrupts_on = 0;
  1202. /* disable risc and host interrupts */
  1203. WRT_REG_WORD(&reg->ictrl, 0);
  1204. RD_REG_WORD(&reg->ictrl);
  1205. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1206. }
  1207. static void
  1208. qla24xx_enable_intrs(struct qla_hw_data *ha)
  1209. {
  1210. unsigned long flags = 0;
  1211. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1212. spin_lock_irqsave(&ha->hardware_lock, flags);
  1213. ha->interrupts_on = 1;
  1214. WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
  1215. RD_REG_DWORD(&reg->ictrl);
  1216. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1217. }
  1218. static void
  1219. qla24xx_disable_intrs(struct qla_hw_data *ha)
  1220. {
  1221. unsigned long flags = 0;
  1222. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  1223. if (IS_NOPOLLING_TYPE(ha))
  1224. return;
  1225. spin_lock_irqsave(&ha->hardware_lock, flags);
  1226. ha->interrupts_on = 0;
  1227. WRT_REG_DWORD(&reg->ictrl, 0);
  1228. RD_REG_DWORD(&reg->ictrl);
  1229. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1230. }
  1231. static struct isp_operations qla2100_isp_ops = {
  1232. .pci_config = qla2100_pci_config,
  1233. .reset_chip = qla2x00_reset_chip,
  1234. .chip_diag = qla2x00_chip_diag,
  1235. .config_rings = qla2x00_config_rings,
  1236. .reset_adapter = qla2x00_reset_adapter,
  1237. .nvram_config = qla2x00_nvram_config,
  1238. .update_fw_options = qla2x00_update_fw_options,
  1239. .load_risc = qla2x00_load_risc,
  1240. .pci_info_str = qla2x00_pci_info_str,
  1241. .fw_version_str = qla2x00_fw_version_str,
  1242. .intr_handler = qla2100_intr_handler,
  1243. .enable_intrs = qla2x00_enable_intrs,
  1244. .disable_intrs = qla2x00_disable_intrs,
  1245. .abort_command = qla2x00_abort_command,
  1246. .target_reset = qla2x00_abort_target,
  1247. .lun_reset = qla2x00_lun_reset,
  1248. .fabric_login = qla2x00_login_fabric,
  1249. .fabric_logout = qla2x00_fabric_logout,
  1250. .calc_req_entries = qla2x00_calc_iocbs_32,
  1251. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1252. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1253. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1254. .read_nvram = qla2x00_read_nvram_data,
  1255. .write_nvram = qla2x00_write_nvram_data,
  1256. .fw_dump = qla2100_fw_dump,
  1257. .beacon_on = NULL,
  1258. .beacon_off = NULL,
  1259. .beacon_blink = NULL,
  1260. .read_optrom = qla2x00_read_optrom_data,
  1261. .write_optrom = qla2x00_write_optrom_data,
  1262. .get_flash_version = qla2x00_get_flash_version,
  1263. .start_scsi = qla2x00_start_scsi,
  1264. .abort_isp = qla2x00_abort_isp,
  1265. };
  1266. static struct isp_operations qla2300_isp_ops = {
  1267. .pci_config = qla2300_pci_config,
  1268. .reset_chip = qla2x00_reset_chip,
  1269. .chip_diag = qla2x00_chip_diag,
  1270. .config_rings = qla2x00_config_rings,
  1271. .reset_adapter = qla2x00_reset_adapter,
  1272. .nvram_config = qla2x00_nvram_config,
  1273. .update_fw_options = qla2x00_update_fw_options,
  1274. .load_risc = qla2x00_load_risc,
  1275. .pci_info_str = qla2x00_pci_info_str,
  1276. .fw_version_str = qla2x00_fw_version_str,
  1277. .intr_handler = qla2300_intr_handler,
  1278. .enable_intrs = qla2x00_enable_intrs,
  1279. .disable_intrs = qla2x00_disable_intrs,
  1280. .abort_command = qla2x00_abort_command,
  1281. .target_reset = qla2x00_abort_target,
  1282. .lun_reset = qla2x00_lun_reset,
  1283. .fabric_login = qla2x00_login_fabric,
  1284. .fabric_logout = qla2x00_fabric_logout,
  1285. .calc_req_entries = qla2x00_calc_iocbs_32,
  1286. .build_iocbs = qla2x00_build_scsi_iocbs_32,
  1287. .prep_ms_iocb = qla2x00_prep_ms_iocb,
  1288. .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
  1289. .read_nvram = qla2x00_read_nvram_data,
  1290. .write_nvram = qla2x00_write_nvram_data,
  1291. .fw_dump = qla2300_fw_dump,
  1292. .beacon_on = qla2x00_beacon_on,
  1293. .beacon_off = qla2x00_beacon_off,
  1294. .beacon_blink = qla2x00_beacon_blink,
  1295. .read_optrom = qla2x00_read_optrom_data,
  1296. .write_optrom = qla2x00_write_optrom_data,
  1297. .get_flash_version = qla2x00_get_flash_version,
  1298. .start_scsi = qla2x00_start_scsi,
  1299. .abort_isp = qla2x00_abort_isp,
  1300. };
  1301. static struct isp_operations qla24xx_isp_ops = {
  1302. .pci_config = qla24xx_pci_config,
  1303. .reset_chip = qla24xx_reset_chip,
  1304. .chip_diag = qla24xx_chip_diag,
  1305. .config_rings = qla24xx_config_rings,
  1306. .reset_adapter = qla24xx_reset_adapter,
  1307. .nvram_config = qla24xx_nvram_config,
  1308. .update_fw_options = qla24xx_update_fw_options,
  1309. .load_risc = qla24xx_load_risc,
  1310. .pci_info_str = qla24xx_pci_info_str,
  1311. .fw_version_str = qla24xx_fw_version_str,
  1312. .intr_handler = qla24xx_intr_handler,
  1313. .enable_intrs = qla24xx_enable_intrs,
  1314. .disable_intrs = qla24xx_disable_intrs,
  1315. .abort_command = qla24xx_abort_command,
  1316. .target_reset = qla24xx_abort_target,
  1317. .lun_reset = qla24xx_lun_reset,
  1318. .fabric_login = qla24xx_login_fabric,
  1319. .fabric_logout = qla24xx_fabric_logout,
  1320. .calc_req_entries = NULL,
  1321. .build_iocbs = NULL,
  1322. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1323. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1324. .read_nvram = qla24xx_read_nvram_data,
  1325. .write_nvram = qla24xx_write_nvram_data,
  1326. .fw_dump = qla24xx_fw_dump,
  1327. .beacon_on = qla24xx_beacon_on,
  1328. .beacon_off = qla24xx_beacon_off,
  1329. .beacon_blink = qla24xx_beacon_blink,
  1330. .read_optrom = qla24xx_read_optrom_data,
  1331. .write_optrom = qla24xx_write_optrom_data,
  1332. .get_flash_version = qla24xx_get_flash_version,
  1333. .start_scsi = qla24xx_start_scsi,
  1334. .abort_isp = qla2x00_abort_isp,
  1335. };
  1336. static struct isp_operations qla25xx_isp_ops = {
  1337. .pci_config = qla25xx_pci_config,
  1338. .reset_chip = qla24xx_reset_chip,
  1339. .chip_diag = qla24xx_chip_diag,
  1340. .config_rings = qla24xx_config_rings,
  1341. .reset_adapter = qla24xx_reset_adapter,
  1342. .nvram_config = qla24xx_nvram_config,
  1343. .update_fw_options = qla24xx_update_fw_options,
  1344. .load_risc = qla24xx_load_risc,
  1345. .pci_info_str = qla24xx_pci_info_str,
  1346. .fw_version_str = qla24xx_fw_version_str,
  1347. .intr_handler = qla24xx_intr_handler,
  1348. .enable_intrs = qla24xx_enable_intrs,
  1349. .disable_intrs = qla24xx_disable_intrs,
  1350. .abort_command = qla24xx_abort_command,
  1351. .target_reset = qla24xx_abort_target,
  1352. .lun_reset = qla24xx_lun_reset,
  1353. .fabric_login = qla24xx_login_fabric,
  1354. .fabric_logout = qla24xx_fabric_logout,
  1355. .calc_req_entries = NULL,
  1356. .build_iocbs = NULL,
  1357. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1358. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1359. .read_nvram = qla25xx_read_nvram_data,
  1360. .write_nvram = qla25xx_write_nvram_data,
  1361. .fw_dump = qla25xx_fw_dump,
  1362. .beacon_on = qla24xx_beacon_on,
  1363. .beacon_off = qla24xx_beacon_off,
  1364. .beacon_blink = qla24xx_beacon_blink,
  1365. .read_optrom = qla25xx_read_optrom_data,
  1366. .write_optrom = qla24xx_write_optrom_data,
  1367. .get_flash_version = qla24xx_get_flash_version,
  1368. .start_scsi = qla24xx_dif_start_scsi,
  1369. .abort_isp = qla2x00_abort_isp,
  1370. };
  1371. static struct isp_operations qla81xx_isp_ops = {
  1372. .pci_config = qla25xx_pci_config,
  1373. .reset_chip = qla24xx_reset_chip,
  1374. .chip_diag = qla24xx_chip_diag,
  1375. .config_rings = qla24xx_config_rings,
  1376. .reset_adapter = qla24xx_reset_adapter,
  1377. .nvram_config = qla81xx_nvram_config,
  1378. .update_fw_options = qla81xx_update_fw_options,
  1379. .load_risc = qla81xx_load_risc,
  1380. .pci_info_str = qla24xx_pci_info_str,
  1381. .fw_version_str = qla24xx_fw_version_str,
  1382. .intr_handler = qla24xx_intr_handler,
  1383. .enable_intrs = qla24xx_enable_intrs,
  1384. .disable_intrs = qla24xx_disable_intrs,
  1385. .abort_command = qla24xx_abort_command,
  1386. .target_reset = qla24xx_abort_target,
  1387. .lun_reset = qla24xx_lun_reset,
  1388. .fabric_login = qla24xx_login_fabric,
  1389. .fabric_logout = qla24xx_fabric_logout,
  1390. .calc_req_entries = NULL,
  1391. .build_iocbs = NULL,
  1392. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1393. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1394. .read_nvram = NULL,
  1395. .write_nvram = NULL,
  1396. .fw_dump = qla81xx_fw_dump,
  1397. .beacon_on = qla24xx_beacon_on,
  1398. .beacon_off = qla24xx_beacon_off,
  1399. .beacon_blink = qla24xx_beacon_blink,
  1400. .read_optrom = qla25xx_read_optrom_data,
  1401. .write_optrom = qla24xx_write_optrom_data,
  1402. .get_flash_version = qla24xx_get_flash_version,
  1403. .start_scsi = qla24xx_dif_start_scsi,
  1404. .abort_isp = qla2x00_abort_isp,
  1405. };
  1406. static struct isp_operations qla82xx_isp_ops = {
  1407. .pci_config = qla82xx_pci_config,
  1408. .reset_chip = qla82xx_reset_chip,
  1409. .chip_diag = qla24xx_chip_diag,
  1410. .config_rings = qla82xx_config_rings,
  1411. .reset_adapter = qla24xx_reset_adapter,
  1412. .nvram_config = qla81xx_nvram_config,
  1413. .update_fw_options = qla24xx_update_fw_options,
  1414. .load_risc = qla82xx_load_risc,
  1415. .pci_info_str = qla82xx_pci_info_str,
  1416. .fw_version_str = qla24xx_fw_version_str,
  1417. .intr_handler = qla82xx_intr_handler,
  1418. .enable_intrs = qla82xx_enable_intrs,
  1419. .disable_intrs = qla82xx_disable_intrs,
  1420. .abort_command = qla24xx_abort_command,
  1421. .target_reset = qla24xx_abort_target,
  1422. .lun_reset = qla24xx_lun_reset,
  1423. .fabric_login = qla24xx_login_fabric,
  1424. .fabric_logout = qla24xx_fabric_logout,
  1425. .calc_req_entries = NULL,
  1426. .build_iocbs = NULL,
  1427. .prep_ms_iocb = qla24xx_prep_ms_iocb,
  1428. .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
  1429. .read_nvram = qla24xx_read_nvram_data,
  1430. .write_nvram = qla24xx_write_nvram_data,
  1431. .fw_dump = qla24xx_fw_dump,
  1432. .beacon_on = qla24xx_beacon_on,
  1433. .beacon_off = qla24xx_beacon_off,
  1434. .beacon_blink = qla24xx_beacon_blink,
  1435. .read_optrom = qla82xx_read_optrom_data,
  1436. .write_optrom = qla82xx_write_optrom_data,
  1437. .get_flash_version = qla24xx_get_flash_version,
  1438. .start_scsi = qla82xx_start_scsi,
  1439. .abort_isp = qla82xx_abort_isp,
  1440. };
  1441. static inline void
  1442. qla2x00_set_isp_flags(struct qla_hw_data *ha)
  1443. {
  1444. ha->device_type = DT_EXTENDED_IDS;
  1445. switch (ha->pdev->device) {
  1446. case PCI_DEVICE_ID_QLOGIC_ISP2100:
  1447. ha->device_type |= DT_ISP2100;
  1448. ha->device_type &= ~DT_EXTENDED_IDS;
  1449. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1450. break;
  1451. case PCI_DEVICE_ID_QLOGIC_ISP2200:
  1452. ha->device_type |= DT_ISP2200;
  1453. ha->device_type &= ~DT_EXTENDED_IDS;
  1454. ha->fw_srisc_address = RISC_START_ADDRESS_2100;
  1455. break;
  1456. case PCI_DEVICE_ID_QLOGIC_ISP2300:
  1457. ha->device_type |= DT_ISP2300;
  1458. ha->device_type |= DT_ZIO_SUPPORTED;
  1459. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1460. break;
  1461. case PCI_DEVICE_ID_QLOGIC_ISP2312:
  1462. ha->device_type |= DT_ISP2312;
  1463. ha->device_type |= DT_ZIO_SUPPORTED;
  1464. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1465. break;
  1466. case PCI_DEVICE_ID_QLOGIC_ISP2322:
  1467. ha->device_type |= DT_ISP2322;
  1468. ha->device_type |= DT_ZIO_SUPPORTED;
  1469. if (ha->pdev->subsystem_vendor == 0x1028 &&
  1470. ha->pdev->subsystem_device == 0x0170)
  1471. ha->device_type |= DT_OEM_001;
  1472. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1473. break;
  1474. case PCI_DEVICE_ID_QLOGIC_ISP6312:
  1475. ha->device_type |= DT_ISP6312;
  1476. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1477. break;
  1478. case PCI_DEVICE_ID_QLOGIC_ISP6322:
  1479. ha->device_type |= DT_ISP6322;
  1480. ha->fw_srisc_address = RISC_START_ADDRESS_2300;
  1481. break;
  1482. case PCI_DEVICE_ID_QLOGIC_ISP2422:
  1483. ha->device_type |= DT_ISP2422;
  1484. ha->device_type |= DT_ZIO_SUPPORTED;
  1485. ha->device_type |= DT_FWI2;
  1486. ha->device_type |= DT_IIDMA;
  1487. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1488. break;
  1489. case PCI_DEVICE_ID_QLOGIC_ISP2432:
  1490. ha->device_type |= DT_ISP2432;
  1491. ha->device_type |= DT_ZIO_SUPPORTED;
  1492. ha->device_type |= DT_FWI2;
  1493. ha->device_type |= DT_IIDMA;
  1494. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1495. break;
  1496. case PCI_DEVICE_ID_QLOGIC_ISP8432:
  1497. ha->device_type |= DT_ISP8432;
  1498. ha->device_type |= DT_ZIO_SUPPORTED;
  1499. ha->device_type |= DT_FWI2;
  1500. ha->device_type |= DT_IIDMA;
  1501. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1502. break;
  1503. case PCI_DEVICE_ID_QLOGIC_ISP5422:
  1504. ha->device_type |= DT_ISP5422;
  1505. ha->device_type |= DT_FWI2;
  1506. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1507. break;
  1508. case PCI_DEVICE_ID_QLOGIC_ISP5432:
  1509. ha->device_type |= DT_ISP5432;
  1510. ha->device_type |= DT_FWI2;
  1511. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1512. break;
  1513. case PCI_DEVICE_ID_QLOGIC_ISP2532:
  1514. ha->device_type |= DT_ISP2532;
  1515. ha->device_type |= DT_ZIO_SUPPORTED;
  1516. ha->device_type |= DT_FWI2;
  1517. ha->device_type |= DT_IIDMA;
  1518. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1519. break;
  1520. case PCI_DEVICE_ID_QLOGIC_ISP8001:
  1521. ha->device_type |= DT_ISP8001;
  1522. ha->device_type |= DT_ZIO_SUPPORTED;
  1523. ha->device_type |= DT_FWI2;
  1524. ha->device_type |= DT_IIDMA;
  1525. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1526. break;
  1527. case PCI_DEVICE_ID_QLOGIC_ISP8021:
  1528. ha->device_type |= DT_ISP8021;
  1529. ha->device_type |= DT_ZIO_SUPPORTED;
  1530. ha->device_type |= DT_FWI2;
  1531. ha->fw_srisc_address = RISC_START_ADDRESS_2400;
  1532. /* Initialize 82XX ISP flags */
  1533. qla82xx_init_flags(ha);
  1534. break;
  1535. }
  1536. if (IS_QLA82XX(ha))
  1537. ha->port_no = !(ha->portnum & 1);
  1538. else
  1539. /* Get adapter physical port no from interrupt pin register. */
  1540. pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
  1541. if (ha->port_no & 1)
  1542. ha->flags.port0 = 1;
  1543. else
  1544. ha->flags.port0 = 0;
  1545. }
  1546. static int
  1547. qla2x00_iospace_config(struct qla_hw_data *ha)
  1548. {
  1549. resource_size_t pio;
  1550. uint16_t msix;
  1551. int cpus;
  1552. if (IS_QLA82XX(ha))
  1553. return qla82xx_iospace_config(ha);
  1554. if (pci_request_selected_regions(ha->pdev, ha->bars,
  1555. QLA2XXX_DRIVER_NAME)) {
  1556. qla_printk(KERN_WARNING, ha,
  1557. "Failed to reserve PIO/MMIO regions (%s)\n",
  1558. pci_name(ha->pdev));
  1559. goto iospace_error_exit;
  1560. }
  1561. if (!(ha->bars & 1))
  1562. goto skip_pio;
  1563. /* We only need PIO for Flash operations on ISP2312 v2 chips. */
  1564. pio = pci_resource_start(ha->pdev, 0);
  1565. if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
  1566. if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
  1567. qla_printk(KERN_WARNING, ha,
  1568. "Invalid PCI I/O region size (%s)...\n",
  1569. pci_name(ha->pdev));
  1570. pio = 0;
  1571. }
  1572. } else {
  1573. qla_printk(KERN_WARNING, ha,
  1574. "region #0 not a PIO resource (%s)...\n",
  1575. pci_name(ha->pdev));
  1576. pio = 0;
  1577. }
  1578. ha->pio_address = pio;
  1579. skip_pio:
  1580. /* Use MMIO operations for all accesses. */
  1581. if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
  1582. qla_printk(KERN_ERR, ha,
  1583. "region #1 not an MMIO resource (%s), aborting\n",
  1584. pci_name(ha->pdev));
  1585. goto iospace_error_exit;
  1586. }
  1587. if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
  1588. qla_printk(KERN_ERR, ha,
  1589. "Invalid PCI mem region size (%s), aborting\n",
  1590. pci_name(ha->pdev));
  1591. goto iospace_error_exit;
  1592. }
  1593. ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
  1594. if (!ha->iobase) {
  1595. qla_printk(KERN_ERR, ha,
  1596. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  1597. goto iospace_error_exit;
  1598. }
  1599. /* Determine queue resources */
  1600. ha->max_req_queues = ha->max_rsp_queues = 1;
  1601. if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
  1602. (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
  1603. (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
  1604. goto mqiobase_exit;
  1605. ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
  1606. pci_resource_len(ha->pdev, 3));
  1607. if (ha->mqiobase) {
  1608. /* Read MSIX vector size of the board */
  1609. pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
  1610. ha->msix_count = msix;
  1611. /* Max queues are bounded by available msix vectors */
  1612. /* queue 0 uses two msix vectors */
  1613. if (ql2xmultique_tag) {
  1614. cpus = num_online_cpus();
  1615. ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
  1616. (cpus + 1) : (ha->msix_count - 1);
  1617. ha->max_req_queues = 2;
  1618. } else if (ql2xmaxqueues > 1) {
  1619. ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
  1620. QLA_MQ_SIZE : ql2xmaxqueues;
  1621. DEBUG2(qla_printk(KERN_INFO, ha, "QoS mode set, max no"
  1622. " of request queues:%d\n", ha->max_req_queues));
  1623. }
  1624. qla_printk(KERN_INFO, ha,
  1625. "MSI-X vector count: %d\n", msix);
  1626. } else
  1627. qla_printk(KERN_INFO, ha, "BAR 3 not enabled\n");
  1628. mqiobase_exit:
  1629. ha->msix_count = ha->max_rsp_queues + 1;
  1630. return (0);
  1631. iospace_error_exit:
  1632. return (-ENOMEM);
  1633. }
  1634. static void
  1635. qla2xxx_scan_start(struct Scsi_Host *shost)
  1636. {
  1637. scsi_qla_host_t *vha = shost_priv(shost);
  1638. if (vha->hw->flags.running_gold_fw)
  1639. return;
  1640. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1641. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  1642. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  1643. set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
  1644. }
  1645. static int
  1646. qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
  1647. {
  1648. scsi_qla_host_t *vha = shost_priv(shost);
  1649. if (!vha->host)
  1650. return 1;
  1651. if (time > vha->hw->loop_reset_delay * HZ)
  1652. return 1;
  1653. return atomic_read(&vha->loop_state) == LOOP_READY;
  1654. }
  1655. /*
  1656. * PCI driver interface
  1657. */
  1658. static int __devinit
  1659. qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1660. {
  1661. int ret = -ENODEV;
  1662. struct Scsi_Host *host;
  1663. scsi_qla_host_t *base_vha = NULL;
  1664. struct qla_hw_data *ha;
  1665. char pci_info[30];
  1666. char fw_str[30];
  1667. struct scsi_host_template *sht;
  1668. int bars, max_id, mem_only = 0;
  1669. uint16_t req_length = 0, rsp_length = 0;
  1670. struct req_que *req = NULL;
  1671. struct rsp_que *rsp = NULL;
  1672. bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
  1673. sht = &qla2xxx_driver_template;
  1674. if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
  1675. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
  1676. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
  1677. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
  1678. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
  1679. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
  1680. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
  1681. pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
  1682. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1683. mem_only = 1;
  1684. }
  1685. if (mem_only) {
  1686. if (pci_enable_device_mem(pdev))
  1687. goto probe_out;
  1688. } else {
  1689. if (pci_enable_device(pdev))
  1690. goto probe_out;
  1691. }
  1692. /* This may fail but that's ok */
  1693. pci_enable_pcie_error_reporting(pdev);
  1694. ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
  1695. if (!ha) {
  1696. DEBUG(printk("Unable to allocate memory for ha\n"));
  1697. goto probe_out;
  1698. }
  1699. ha->pdev = pdev;
  1700. /* Clear our data area */
  1701. ha->bars = bars;
  1702. ha->mem_only = mem_only;
  1703. spin_lock_init(&ha->hardware_lock);
  1704. spin_lock_init(&ha->vport_slock);
  1705. /* Set ISP-type information. */
  1706. qla2x00_set_isp_flags(ha);
  1707. /* Set EEH reset type to fundamental if required by hba */
  1708. if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
  1709. pdev->needs_freset = 1;
  1710. }
  1711. /* Configure PCI I/O space */
  1712. ret = qla2x00_iospace_config(ha);
  1713. if (ret)
  1714. goto probe_hw_failed;
  1715. qla_printk(KERN_INFO, ha,
  1716. "Found an ISP%04X, irq %d, iobase 0x%p\n", pdev->device, pdev->irq,
  1717. ha->iobase);
  1718. ha->prev_topology = 0;
  1719. ha->init_cb_size = sizeof(init_cb_t);
  1720. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  1721. ha->optrom_size = OPTROM_SIZE_2300;
  1722. /* Assign ISP specific operations. */
  1723. max_id = MAX_TARGETS_2200;
  1724. if (IS_QLA2100(ha)) {
  1725. max_id = MAX_TARGETS_2100;
  1726. ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
  1727. req_length = REQUEST_ENTRY_CNT_2100;
  1728. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1729. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1730. ha->gid_list_info_size = 4;
  1731. ha->flash_conf_off = ~0;
  1732. ha->flash_data_off = ~0;
  1733. ha->nvram_conf_off = ~0;
  1734. ha->nvram_data_off = ~0;
  1735. ha->isp_ops = &qla2100_isp_ops;
  1736. } else if (IS_QLA2200(ha)) {
  1737. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1738. req_length = REQUEST_ENTRY_CNT_2200;
  1739. rsp_length = RESPONSE_ENTRY_CNT_2100;
  1740. ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
  1741. ha->gid_list_info_size = 4;
  1742. ha->flash_conf_off = ~0;
  1743. ha->flash_data_off = ~0;
  1744. ha->nvram_conf_off = ~0;
  1745. ha->nvram_data_off = ~0;
  1746. ha->isp_ops = &qla2100_isp_ops;
  1747. } else if (IS_QLA23XX(ha)) {
  1748. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1749. req_length = REQUEST_ENTRY_CNT_2200;
  1750. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1751. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1752. ha->gid_list_info_size = 6;
  1753. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1754. ha->optrom_size = OPTROM_SIZE_2322;
  1755. ha->flash_conf_off = ~0;
  1756. ha->flash_data_off = ~0;
  1757. ha->nvram_conf_off = ~0;
  1758. ha->nvram_data_off = ~0;
  1759. ha->isp_ops = &qla2300_isp_ops;
  1760. } else if (IS_QLA24XX_TYPE(ha)) {
  1761. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1762. req_length = REQUEST_ENTRY_CNT_24XX;
  1763. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1764. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1765. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1766. ha->gid_list_info_size = 8;
  1767. ha->optrom_size = OPTROM_SIZE_24XX;
  1768. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
  1769. ha->isp_ops = &qla24xx_isp_ops;
  1770. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1771. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1772. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1773. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1774. } else if (IS_QLA25XX(ha)) {
  1775. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1776. req_length = REQUEST_ENTRY_CNT_24XX;
  1777. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1778. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1779. ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
  1780. ha->gid_list_info_size = 8;
  1781. ha->optrom_size = OPTROM_SIZE_25XX;
  1782. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1783. ha->isp_ops = &qla25xx_isp_ops;
  1784. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1785. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1786. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1787. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1788. } else if (IS_QLA81XX(ha)) {
  1789. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1790. req_length = REQUEST_ENTRY_CNT_24XX;
  1791. rsp_length = RESPONSE_ENTRY_CNT_2300;
  1792. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1793. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1794. ha->gid_list_info_size = 8;
  1795. ha->optrom_size = OPTROM_SIZE_81XX;
  1796. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1797. ha->isp_ops = &qla81xx_isp_ops;
  1798. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
  1799. ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
  1800. ha->nvram_conf_off = ~0;
  1801. ha->nvram_data_off = ~0;
  1802. } else if (IS_QLA82XX(ha)) {
  1803. ha->mbx_count = MAILBOX_REGISTER_COUNT;
  1804. req_length = REQUEST_ENTRY_CNT_82XX;
  1805. rsp_length = RESPONSE_ENTRY_CNT_82XX;
  1806. ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
  1807. ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
  1808. ha->gid_list_info_size = 8;
  1809. ha->optrom_size = OPTROM_SIZE_82XX;
  1810. ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
  1811. ha->isp_ops = &qla82xx_isp_ops;
  1812. ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
  1813. ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
  1814. ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
  1815. ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
  1816. }
  1817. mutex_init(&ha->vport_lock);
  1818. init_completion(&ha->mbx_cmd_comp);
  1819. complete(&ha->mbx_cmd_comp);
  1820. init_completion(&ha->mbx_intr_comp);
  1821. init_completion(&ha->dcbx_comp);
  1822. set_bit(0, (unsigned long *) ha->vp_idx_map);
  1823. qla2x00_config_dma_addressing(ha);
  1824. ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
  1825. if (!ret) {
  1826. qla_printk(KERN_WARNING, ha,
  1827. "[ERROR] Failed to allocate memory for adapter\n");
  1828. goto probe_hw_failed;
  1829. }
  1830. req->max_q_depth = MAX_Q_DEPTH;
  1831. if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
  1832. req->max_q_depth = ql2xmaxqdepth;
  1833. base_vha = qla2x00_create_host(sht, ha);
  1834. if (!base_vha) {
  1835. qla_printk(KERN_WARNING, ha,
  1836. "[ERROR] Failed to allocate memory for scsi_host\n");
  1837. ret = -ENOMEM;
  1838. qla2x00_mem_free(ha);
  1839. qla2x00_free_req_que(ha, req);
  1840. qla2x00_free_rsp_que(ha, rsp);
  1841. goto probe_hw_failed;
  1842. }
  1843. pci_set_drvdata(pdev, base_vha);
  1844. host = base_vha->host;
  1845. base_vha->req = req;
  1846. host->can_queue = req->length + 128;
  1847. if (IS_QLA2XXX_MIDTYPE(ha))
  1848. base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
  1849. else
  1850. base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
  1851. base_vha->vp_idx;
  1852. /* Set the SG table size based on ISP type */
  1853. if (!IS_FWI2_CAPABLE(ha)) {
  1854. if (IS_QLA2100(ha))
  1855. host->sg_tablesize = 32;
  1856. } else {
  1857. if (!IS_QLA82XX(ha))
  1858. host->sg_tablesize = QLA_SG_ALL;
  1859. }
  1860. host->max_id = max_id;
  1861. host->this_id = 255;
  1862. host->cmd_per_lun = 3;
  1863. host->unique_id = host->host_no;
  1864. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif)
  1865. host->max_cmd_len = 32;
  1866. else
  1867. host->max_cmd_len = MAX_CMDSZ;
  1868. host->max_channel = MAX_BUSES - 1;
  1869. host->max_lun = MAX_LUNS;
  1870. host->transportt = qla2xxx_transport_template;
  1871. sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
  1872. /* Set up the irqs */
  1873. ret = qla2x00_request_irqs(ha, rsp);
  1874. if (ret)
  1875. goto probe_init_failed;
  1876. pci_save_state(pdev);
  1877. /* Alloc arrays of request and response ring ptrs */
  1878. que_init:
  1879. if (!qla2x00_alloc_queues(ha)) {
  1880. qla_printk(KERN_WARNING, ha,
  1881. "[ERROR] Failed to allocate memory for queue"
  1882. " pointers\n");
  1883. goto probe_init_failed;
  1884. }
  1885. ha->rsp_q_map[0] = rsp;
  1886. ha->req_q_map[0] = req;
  1887. rsp->req = req;
  1888. req->rsp = rsp;
  1889. set_bit(0, ha->req_qid_map);
  1890. set_bit(0, ha->rsp_qid_map);
  1891. /* FWI2-capable only. */
  1892. req->req_q_in = &ha->iobase->isp24.req_q_in;
  1893. req->req_q_out = &ha->iobase->isp24.req_q_out;
  1894. rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
  1895. rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
  1896. if (ha->mqenable) {
  1897. req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
  1898. req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
  1899. rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
  1900. rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
  1901. }
  1902. if (IS_QLA82XX(ha)) {
  1903. req->req_q_out = &ha->iobase->isp82.req_q_out[0];
  1904. rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
  1905. rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
  1906. }
  1907. if (qla2x00_initialize_adapter(base_vha)) {
  1908. qla_printk(KERN_WARNING, ha,
  1909. "Failed to initialize adapter\n");
  1910. DEBUG2(printk("scsi(%ld): Failed to initialize adapter - "
  1911. "Adapter flags %x.\n",
  1912. base_vha->host_no, base_vha->device_flags));
  1913. if (IS_QLA82XX(ha)) {
  1914. qla82xx_idc_lock(ha);
  1915. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  1916. QLA82XX_DEV_FAILED);
  1917. qla82xx_idc_unlock(ha);
  1918. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  1919. }
  1920. ret = -ENODEV;
  1921. goto probe_failed;
  1922. }
  1923. if (ha->mqenable) {
  1924. if (qla25xx_setup_mode(base_vha)) {
  1925. qla_printk(KERN_WARNING, ha,
  1926. "Can't create queues, falling back to single"
  1927. " queue mode\n");
  1928. goto que_init;
  1929. }
  1930. }
  1931. if (ha->flags.running_gold_fw)
  1932. goto skip_dpc;
  1933. /*
  1934. * Startup the kernel thread for this host adapter
  1935. */
  1936. ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
  1937. "%s_dpc", base_vha->host_str);
  1938. if (IS_ERR(ha->dpc_thread)) {
  1939. qla_printk(KERN_WARNING, ha,
  1940. "Unable to start DPC thread!\n");
  1941. ret = PTR_ERR(ha->dpc_thread);
  1942. goto probe_failed;
  1943. }
  1944. skip_dpc:
  1945. list_add_tail(&base_vha->list, &ha->vp_list);
  1946. base_vha->host->irq = ha->pdev->irq;
  1947. /* Initialized the timer */
  1948. qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
  1949. DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n",
  1950. base_vha->host_no, ha));
  1951. if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && ql2xenabledif) {
  1952. if (ha->fw_attributes & BIT_4) {
  1953. base_vha->flags.difdix_supported = 1;
  1954. DEBUG18(qla_printk(KERN_INFO, ha,
  1955. "Registering for DIF/DIX type 1 and 3"
  1956. " protection.\n"));
  1957. scsi_host_set_prot(host,
  1958. SHOST_DIF_TYPE1_PROTECTION
  1959. | SHOST_DIF_TYPE2_PROTECTION
  1960. | SHOST_DIF_TYPE3_PROTECTION
  1961. | SHOST_DIX_TYPE1_PROTECTION
  1962. | SHOST_DIX_TYPE2_PROTECTION
  1963. | SHOST_DIX_TYPE3_PROTECTION);
  1964. scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
  1965. } else
  1966. base_vha->flags.difdix_supported = 0;
  1967. }
  1968. ha->isp_ops->enable_intrs(ha);
  1969. ret = scsi_add_host(host, &pdev->dev);
  1970. if (ret)
  1971. goto probe_failed;
  1972. base_vha->flags.init_done = 1;
  1973. base_vha->flags.online = 1;
  1974. scsi_scan_host(host);
  1975. qla2x00_alloc_sysfs_attr(base_vha);
  1976. qla2x00_init_host_attr(base_vha);
  1977. qla2x00_dfs_setup(base_vha);
  1978. qla_printk(KERN_INFO, ha, "\n"
  1979. " QLogic Fibre Channel HBA Driver: %s\n"
  1980. " QLogic %s - %s\n"
  1981. " ISP%04X: %s @ %s hdma%c, host#=%ld, fw=%s\n",
  1982. qla2x00_version_str, ha->model_number,
  1983. ha->model_desc ? ha->model_desc : "", pdev->device,
  1984. ha->isp_ops->pci_info_str(base_vha, pci_info), pci_name(pdev),
  1985. ha->flags.enable_64bit_addressing ? '+' : '-', base_vha->host_no,
  1986. ha->isp_ops->fw_version_str(base_vha, fw_str));
  1987. return 0;
  1988. probe_init_failed:
  1989. qla2x00_free_req_que(ha, req);
  1990. qla2x00_free_rsp_que(ha, rsp);
  1991. ha->max_req_queues = ha->max_rsp_queues = 0;
  1992. probe_failed:
  1993. if (base_vha->timer_active)
  1994. qla2x00_stop_timer(base_vha);
  1995. base_vha->flags.online = 0;
  1996. if (ha->dpc_thread) {
  1997. struct task_struct *t = ha->dpc_thread;
  1998. ha->dpc_thread = NULL;
  1999. kthread_stop(t);
  2000. }
  2001. qla2x00_free_device(base_vha);
  2002. scsi_host_put(base_vha->host);
  2003. probe_hw_failed:
  2004. if (IS_QLA82XX(ha)) {
  2005. qla82xx_idc_lock(ha);
  2006. qla82xx_clear_drv_active(ha);
  2007. qla82xx_idc_unlock(ha);
  2008. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2009. if (!ql2xdbwr)
  2010. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2011. } else {
  2012. if (ha->iobase)
  2013. iounmap(ha->iobase);
  2014. }
  2015. pci_release_selected_regions(ha->pdev, ha->bars);
  2016. kfree(ha);
  2017. ha = NULL;
  2018. probe_out:
  2019. pci_disable_device(pdev);
  2020. return ret;
  2021. }
  2022. static void
  2023. qla2x00_shutdown(struct pci_dev *pdev)
  2024. {
  2025. scsi_qla_host_t *vha;
  2026. struct qla_hw_data *ha;
  2027. vha = pci_get_drvdata(pdev);
  2028. ha = vha->hw;
  2029. /* Turn-off FCE trace */
  2030. if (ha->flags.fce_enabled) {
  2031. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2032. ha->flags.fce_enabled = 0;
  2033. }
  2034. /* Turn-off EFT trace */
  2035. if (ha->eft)
  2036. qla2x00_disable_eft_trace(vha);
  2037. /* Stop currently executing firmware. */
  2038. qla2x00_try_to_stop_firmware(vha);
  2039. /* Turn adapter off line */
  2040. vha->flags.online = 0;
  2041. /* turn-off interrupts on the card */
  2042. if (ha->interrupts_on) {
  2043. vha->flags.init_done = 0;
  2044. ha->isp_ops->disable_intrs(ha);
  2045. }
  2046. qla2x00_free_irqs(vha);
  2047. qla2x00_free_fw_dump(ha);
  2048. }
  2049. static void
  2050. qla2x00_remove_one(struct pci_dev *pdev)
  2051. {
  2052. scsi_qla_host_t *base_vha, *vha;
  2053. struct qla_hw_data *ha;
  2054. unsigned long flags;
  2055. base_vha = pci_get_drvdata(pdev);
  2056. ha = base_vha->hw;
  2057. spin_lock_irqsave(&ha->vport_slock, flags);
  2058. list_for_each_entry(vha, &ha->vp_list, list) {
  2059. atomic_inc(&vha->vref_count);
  2060. if (vha->fc_vport) {
  2061. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2062. fc_vport_terminate(vha->fc_vport);
  2063. spin_lock_irqsave(&ha->vport_slock, flags);
  2064. }
  2065. atomic_dec(&vha->vref_count);
  2066. }
  2067. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2068. set_bit(UNLOADING, &base_vha->dpc_flags);
  2069. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2070. qla2x00_dfs_remove(base_vha);
  2071. qla84xx_put_chip(base_vha);
  2072. /* Disable timer */
  2073. if (base_vha->timer_active)
  2074. qla2x00_stop_timer(base_vha);
  2075. base_vha->flags.online = 0;
  2076. /* Flush the work queue and remove it */
  2077. if (ha->wq) {
  2078. flush_workqueue(ha->wq);
  2079. destroy_workqueue(ha->wq);
  2080. ha->wq = NULL;
  2081. }
  2082. /* Kill the kernel thread for this host */
  2083. if (ha->dpc_thread) {
  2084. struct task_struct *t = ha->dpc_thread;
  2085. /*
  2086. * qla2xxx_wake_dpc checks for ->dpc_thread
  2087. * so we need to zero it out.
  2088. */
  2089. ha->dpc_thread = NULL;
  2090. kthread_stop(t);
  2091. }
  2092. qla2x00_free_sysfs_attr(base_vha);
  2093. fc_remove_host(base_vha->host);
  2094. scsi_remove_host(base_vha->host);
  2095. qla2x00_free_device(base_vha);
  2096. scsi_host_put(base_vha->host);
  2097. if (IS_QLA82XX(ha)) {
  2098. qla82xx_idc_lock(ha);
  2099. qla82xx_clear_drv_active(ha);
  2100. qla82xx_idc_unlock(ha);
  2101. iounmap((device_reg_t __iomem *)ha->nx_pcibase);
  2102. if (!ql2xdbwr)
  2103. iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
  2104. } else {
  2105. if (ha->iobase)
  2106. iounmap(ha->iobase);
  2107. if (ha->mqiobase)
  2108. iounmap(ha->mqiobase);
  2109. }
  2110. pci_release_selected_regions(ha->pdev, ha->bars);
  2111. kfree(ha);
  2112. ha = NULL;
  2113. pci_disable_pcie_error_reporting(pdev);
  2114. pci_disable_device(pdev);
  2115. pci_set_drvdata(pdev, NULL);
  2116. }
  2117. static void
  2118. qla2x00_free_device(scsi_qla_host_t *vha)
  2119. {
  2120. struct qla_hw_data *ha = vha->hw;
  2121. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  2122. /* Disable timer */
  2123. if (vha->timer_active)
  2124. qla2x00_stop_timer(vha);
  2125. /* Kill the kernel thread for this host */
  2126. if (ha->dpc_thread) {
  2127. struct task_struct *t = ha->dpc_thread;
  2128. /*
  2129. * qla2xxx_wake_dpc checks for ->dpc_thread
  2130. * so we need to zero it out.
  2131. */
  2132. ha->dpc_thread = NULL;
  2133. kthread_stop(t);
  2134. }
  2135. qla25xx_delete_queues(vha);
  2136. if (ha->flags.fce_enabled)
  2137. qla2x00_disable_fce_trace(vha, NULL, NULL);
  2138. if (ha->eft)
  2139. qla2x00_disable_eft_trace(vha);
  2140. /* Stop currently executing firmware. */
  2141. qla2x00_try_to_stop_firmware(vha);
  2142. vha->flags.online = 0;
  2143. /* turn-off interrupts on the card */
  2144. if (ha->interrupts_on) {
  2145. vha->flags.init_done = 0;
  2146. ha->isp_ops->disable_intrs(ha);
  2147. }
  2148. qla2x00_free_irqs(vha);
  2149. qla2x00_free_fcports(vha);
  2150. qla2x00_mem_free(ha);
  2151. qla2x00_free_queues(ha);
  2152. }
  2153. void qla2x00_free_fcports(struct scsi_qla_host *vha)
  2154. {
  2155. fc_port_t *fcport, *tfcport;
  2156. list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
  2157. list_del(&fcport->list);
  2158. kfree(fcport);
  2159. fcport = NULL;
  2160. }
  2161. }
  2162. static inline void
  2163. qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
  2164. int defer)
  2165. {
  2166. struct fc_rport *rport;
  2167. scsi_qla_host_t *base_vha;
  2168. if (!fcport->rport)
  2169. return;
  2170. rport = fcport->rport;
  2171. if (defer) {
  2172. base_vha = pci_get_drvdata(vha->hw->pdev);
  2173. spin_lock_irq(vha->host->host_lock);
  2174. fcport->drport = rport;
  2175. spin_unlock_irq(vha->host->host_lock);
  2176. set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2177. qla2xxx_wake_dpc(base_vha);
  2178. } else
  2179. fc_remote_port_delete(rport);
  2180. }
  2181. /*
  2182. * qla2x00_mark_device_lost Updates fcport state when device goes offline.
  2183. *
  2184. * Input: ha = adapter block pointer. fcport = port structure pointer.
  2185. *
  2186. * Return: None.
  2187. *
  2188. * Context:
  2189. */
  2190. void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
  2191. int do_login, int defer)
  2192. {
  2193. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2194. vha->vp_idx == fcport->vp_idx) {
  2195. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2196. qla2x00_schedule_rport_del(vha, fcport, defer);
  2197. }
  2198. /*
  2199. * We may need to retry the login, so don't change the state of the
  2200. * port but do the retries.
  2201. */
  2202. if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
  2203. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2204. if (!do_login)
  2205. return;
  2206. if (fcport->login_retry == 0) {
  2207. fcport->login_retry = vha->hw->login_retry_count;
  2208. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2209. DEBUG(printk("scsi(%ld): Port login retry: "
  2210. "%02x%02x%02x%02x%02x%02x%02x%02x, "
  2211. "id = 0x%04x retry cnt=%d\n",
  2212. vha->host_no,
  2213. fcport->port_name[0],
  2214. fcport->port_name[1],
  2215. fcport->port_name[2],
  2216. fcport->port_name[3],
  2217. fcport->port_name[4],
  2218. fcport->port_name[5],
  2219. fcport->port_name[6],
  2220. fcport->port_name[7],
  2221. fcport->loop_id,
  2222. fcport->login_retry));
  2223. }
  2224. }
  2225. /*
  2226. * qla2x00_mark_all_devices_lost
  2227. * Updates fcport state when device goes offline.
  2228. *
  2229. * Input:
  2230. * ha = adapter block pointer.
  2231. * fcport = port structure pointer.
  2232. *
  2233. * Return:
  2234. * None.
  2235. *
  2236. * Context:
  2237. */
  2238. void
  2239. qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
  2240. {
  2241. fc_port_t *fcport;
  2242. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2243. if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
  2244. continue;
  2245. /*
  2246. * No point in marking the device as lost, if the device is
  2247. * already DEAD.
  2248. */
  2249. if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
  2250. continue;
  2251. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  2252. atomic_set(&fcport->state, FCS_DEVICE_LOST);
  2253. if (defer)
  2254. qla2x00_schedule_rport_del(vha, fcport, defer);
  2255. else if (vha->vp_idx == fcport->vp_idx)
  2256. qla2x00_schedule_rport_del(vha, fcport, defer);
  2257. }
  2258. }
  2259. }
  2260. /*
  2261. * qla2x00_mem_alloc
  2262. * Allocates adapter memory.
  2263. *
  2264. * Returns:
  2265. * 0 = success.
  2266. * !0 = failure.
  2267. */
  2268. static int
  2269. qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
  2270. struct req_que **req, struct rsp_que **rsp)
  2271. {
  2272. char name[16];
  2273. ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
  2274. &ha->init_cb_dma, GFP_KERNEL);
  2275. if (!ha->init_cb)
  2276. goto fail;
  2277. ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
  2278. &ha->gid_list_dma, GFP_KERNEL);
  2279. if (!ha->gid_list)
  2280. goto fail_free_init_cb;
  2281. ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
  2282. if (!ha->srb_mempool)
  2283. goto fail_free_gid_list;
  2284. if (IS_QLA82XX(ha)) {
  2285. /* Allocate cache for CT6 Ctx. */
  2286. if (!ctx_cachep) {
  2287. ctx_cachep = kmem_cache_create("qla2xxx_ctx",
  2288. sizeof(struct ct6_dsd), 0,
  2289. SLAB_HWCACHE_ALIGN, NULL);
  2290. if (!ctx_cachep)
  2291. goto fail_free_gid_list;
  2292. }
  2293. ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
  2294. ctx_cachep);
  2295. if (!ha->ctx_mempool)
  2296. goto fail_free_srb_mempool;
  2297. }
  2298. /* Get memory for cached NVRAM */
  2299. ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
  2300. if (!ha->nvram)
  2301. goto fail_free_ctx_mempool;
  2302. snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
  2303. ha->pdev->device);
  2304. ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2305. DMA_POOL_SIZE, 8, 0);
  2306. if (!ha->s_dma_pool)
  2307. goto fail_free_nvram;
  2308. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2309. ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2310. DSD_LIST_DMA_POOL_SIZE, 8, 0);
  2311. if (!ha->dl_dma_pool) {
  2312. qla_printk(KERN_WARNING, ha,
  2313. "Memory Allocation failed - dl_dma_pool\n");
  2314. goto fail_s_dma_pool;
  2315. }
  2316. ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
  2317. FCP_CMND_DMA_POOL_SIZE, 8, 0);
  2318. if (!ha->fcp_cmnd_dma_pool) {
  2319. qla_printk(KERN_WARNING, ha,
  2320. "Memory Allocation failed - fcp_cmnd_dma_pool\n");
  2321. goto fail_dl_dma_pool;
  2322. }
  2323. }
  2324. /* Allocate memory for SNS commands */
  2325. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2326. /* Get consistent memory allocated for SNS commands */
  2327. ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
  2328. sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
  2329. if (!ha->sns_cmd)
  2330. goto fail_dma_pool;
  2331. } else {
  2332. /* Get consistent memory allocated for MS IOCB */
  2333. ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2334. &ha->ms_iocb_dma);
  2335. if (!ha->ms_iocb)
  2336. goto fail_dma_pool;
  2337. /* Get consistent memory allocated for CT SNS commands */
  2338. ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
  2339. sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
  2340. if (!ha->ct_sns)
  2341. goto fail_free_ms_iocb;
  2342. }
  2343. /* Allocate memory for request ring */
  2344. *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
  2345. if (!*req) {
  2346. DEBUG(printk("Unable to allocate memory for req\n"));
  2347. goto fail_req;
  2348. }
  2349. (*req)->length = req_len;
  2350. (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2351. ((*req)->length + 1) * sizeof(request_t),
  2352. &(*req)->dma, GFP_KERNEL);
  2353. if (!(*req)->ring) {
  2354. DEBUG(printk("Unable to allocate memory for req_ring\n"));
  2355. goto fail_req_ring;
  2356. }
  2357. /* Allocate memory for response ring */
  2358. *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
  2359. if (!*rsp) {
  2360. qla_printk(KERN_WARNING, ha,
  2361. "Unable to allocate memory for rsp\n");
  2362. goto fail_rsp;
  2363. }
  2364. (*rsp)->hw = ha;
  2365. (*rsp)->length = rsp_len;
  2366. (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
  2367. ((*rsp)->length + 1) * sizeof(response_t),
  2368. &(*rsp)->dma, GFP_KERNEL);
  2369. if (!(*rsp)->ring) {
  2370. qla_printk(KERN_WARNING, ha,
  2371. "Unable to allocate memory for rsp_ring\n");
  2372. goto fail_rsp_ring;
  2373. }
  2374. (*req)->rsp = *rsp;
  2375. (*rsp)->req = *req;
  2376. /* Allocate memory for NVRAM data for vports */
  2377. if (ha->nvram_npiv_size) {
  2378. ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
  2379. ha->nvram_npiv_size, GFP_KERNEL);
  2380. if (!ha->npiv_info) {
  2381. qla_printk(KERN_WARNING, ha,
  2382. "Unable to allocate memory for npiv info\n");
  2383. goto fail_npiv_info;
  2384. }
  2385. } else
  2386. ha->npiv_info = NULL;
  2387. /* Get consistent memory allocated for EX-INIT-CB. */
  2388. if (IS_QLA8XXX_TYPE(ha)) {
  2389. ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2390. &ha->ex_init_cb_dma);
  2391. if (!ha->ex_init_cb)
  2392. goto fail_ex_init_cb;
  2393. }
  2394. INIT_LIST_HEAD(&ha->gbl_dsd_list);
  2395. /* Get consistent memory allocated for Async Port-Database. */
  2396. if (!IS_FWI2_CAPABLE(ha)) {
  2397. ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
  2398. &ha->async_pd_dma);
  2399. if (!ha->async_pd)
  2400. goto fail_async_pd;
  2401. }
  2402. INIT_LIST_HEAD(&ha->vp_list);
  2403. return 1;
  2404. fail_async_pd:
  2405. dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
  2406. fail_ex_init_cb:
  2407. kfree(ha->npiv_info);
  2408. fail_npiv_info:
  2409. dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
  2410. sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
  2411. (*rsp)->ring = NULL;
  2412. (*rsp)->dma = 0;
  2413. fail_rsp_ring:
  2414. kfree(*rsp);
  2415. fail_rsp:
  2416. dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
  2417. sizeof(request_t), (*req)->ring, (*req)->dma);
  2418. (*req)->ring = NULL;
  2419. (*req)->dma = 0;
  2420. fail_req_ring:
  2421. kfree(*req);
  2422. fail_req:
  2423. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2424. ha->ct_sns, ha->ct_sns_dma);
  2425. ha->ct_sns = NULL;
  2426. ha->ct_sns_dma = 0;
  2427. fail_free_ms_iocb:
  2428. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2429. ha->ms_iocb = NULL;
  2430. ha->ms_iocb_dma = 0;
  2431. fail_dma_pool:
  2432. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2433. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2434. ha->fcp_cmnd_dma_pool = NULL;
  2435. }
  2436. fail_dl_dma_pool:
  2437. if (IS_QLA82XX(ha) || ql2xenabledif) {
  2438. dma_pool_destroy(ha->dl_dma_pool);
  2439. ha->dl_dma_pool = NULL;
  2440. }
  2441. fail_s_dma_pool:
  2442. dma_pool_destroy(ha->s_dma_pool);
  2443. ha->s_dma_pool = NULL;
  2444. fail_free_nvram:
  2445. kfree(ha->nvram);
  2446. ha->nvram = NULL;
  2447. fail_free_ctx_mempool:
  2448. mempool_destroy(ha->ctx_mempool);
  2449. ha->ctx_mempool = NULL;
  2450. fail_free_srb_mempool:
  2451. mempool_destroy(ha->srb_mempool);
  2452. ha->srb_mempool = NULL;
  2453. fail_free_gid_list:
  2454. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2455. ha->gid_list_dma);
  2456. ha->gid_list = NULL;
  2457. ha->gid_list_dma = 0;
  2458. fail_free_init_cb:
  2459. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
  2460. ha->init_cb_dma);
  2461. ha->init_cb = NULL;
  2462. ha->init_cb_dma = 0;
  2463. fail:
  2464. DEBUG(printk("%s: Memory allocation failure\n", __func__));
  2465. return -ENOMEM;
  2466. }
  2467. /*
  2468. * qla2x00_free_fw_dump
  2469. * Frees fw dump stuff.
  2470. *
  2471. * Input:
  2472. * ha = adapter block pointer.
  2473. */
  2474. static void
  2475. qla2x00_free_fw_dump(struct qla_hw_data *ha)
  2476. {
  2477. if (ha->fce)
  2478. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  2479. ha->fce_dma);
  2480. if (ha->fw_dump) {
  2481. if (ha->eft)
  2482. dma_free_coherent(&ha->pdev->dev,
  2483. ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
  2484. vfree(ha->fw_dump);
  2485. }
  2486. ha->fce = NULL;
  2487. ha->fce_dma = 0;
  2488. ha->eft = NULL;
  2489. ha->eft_dma = 0;
  2490. ha->fw_dump = NULL;
  2491. ha->fw_dumped = 0;
  2492. ha->fw_dump_reading = 0;
  2493. }
  2494. /*
  2495. * qla2x00_mem_free
  2496. * Frees all adapter allocated memory.
  2497. *
  2498. * Input:
  2499. * ha = adapter block pointer.
  2500. */
  2501. static void
  2502. qla2x00_mem_free(struct qla_hw_data *ha)
  2503. {
  2504. qla2x00_free_fw_dump(ha);
  2505. if (ha->srb_mempool)
  2506. mempool_destroy(ha->srb_mempool);
  2507. if (ha->dcbx_tlv)
  2508. dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
  2509. ha->dcbx_tlv, ha->dcbx_tlv_dma);
  2510. if (ha->xgmac_data)
  2511. dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
  2512. ha->xgmac_data, ha->xgmac_data_dma);
  2513. if (ha->sns_cmd)
  2514. dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
  2515. ha->sns_cmd, ha->sns_cmd_dma);
  2516. if (ha->ct_sns)
  2517. dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
  2518. ha->ct_sns, ha->ct_sns_dma);
  2519. if (ha->sfp_data)
  2520. dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
  2521. if (ha->edc_data)
  2522. dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
  2523. if (ha->ms_iocb)
  2524. dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
  2525. if (ha->ex_init_cb)
  2526. dma_pool_free(ha->s_dma_pool,
  2527. ha->ex_init_cb, ha->ex_init_cb_dma);
  2528. if (ha->async_pd)
  2529. dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
  2530. if (ha->s_dma_pool)
  2531. dma_pool_destroy(ha->s_dma_pool);
  2532. if (ha->gid_list)
  2533. dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
  2534. ha->gid_list_dma);
  2535. if (IS_QLA82XX(ha)) {
  2536. if (!list_empty(&ha->gbl_dsd_list)) {
  2537. struct dsd_dma *dsd_ptr, *tdsd_ptr;
  2538. /* clean up allocated prev pool */
  2539. list_for_each_entry_safe(dsd_ptr,
  2540. tdsd_ptr, &ha->gbl_dsd_list, list) {
  2541. dma_pool_free(ha->dl_dma_pool,
  2542. dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
  2543. list_del(&dsd_ptr->list);
  2544. kfree(dsd_ptr);
  2545. }
  2546. }
  2547. }
  2548. if (ha->dl_dma_pool)
  2549. dma_pool_destroy(ha->dl_dma_pool);
  2550. if (ha->fcp_cmnd_dma_pool)
  2551. dma_pool_destroy(ha->fcp_cmnd_dma_pool);
  2552. if (ha->ctx_mempool)
  2553. mempool_destroy(ha->ctx_mempool);
  2554. if (ha->init_cb)
  2555. dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
  2556. ha->init_cb, ha->init_cb_dma);
  2557. vfree(ha->optrom_buffer);
  2558. kfree(ha->nvram);
  2559. kfree(ha->npiv_info);
  2560. ha->srb_mempool = NULL;
  2561. ha->ctx_mempool = NULL;
  2562. ha->sns_cmd = NULL;
  2563. ha->sns_cmd_dma = 0;
  2564. ha->ct_sns = NULL;
  2565. ha->ct_sns_dma = 0;
  2566. ha->ms_iocb = NULL;
  2567. ha->ms_iocb_dma = 0;
  2568. ha->init_cb = NULL;
  2569. ha->init_cb_dma = 0;
  2570. ha->ex_init_cb = NULL;
  2571. ha->ex_init_cb_dma = 0;
  2572. ha->async_pd = NULL;
  2573. ha->async_pd_dma = 0;
  2574. ha->s_dma_pool = NULL;
  2575. ha->dl_dma_pool = NULL;
  2576. ha->fcp_cmnd_dma_pool = NULL;
  2577. ha->gid_list = NULL;
  2578. ha->gid_list_dma = 0;
  2579. }
  2580. struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
  2581. struct qla_hw_data *ha)
  2582. {
  2583. struct Scsi_Host *host;
  2584. struct scsi_qla_host *vha = NULL;
  2585. host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
  2586. if (host == NULL) {
  2587. printk(KERN_WARNING
  2588. "qla2xxx: Couldn't allocate host from scsi layer!\n");
  2589. goto fail;
  2590. }
  2591. /* Clear our data area */
  2592. vha = shost_priv(host);
  2593. memset(vha, 0, sizeof(scsi_qla_host_t));
  2594. vha->host = host;
  2595. vha->host_no = host->host_no;
  2596. vha->hw = ha;
  2597. INIT_LIST_HEAD(&vha->vp_fcports);
  2598. INIT_LIST_HEAD(&vha->work_list);
  2599. INIT_LIST_HEAD(&vha->list);
  2600. spin_lock_init(&vha->work_lock);
  2601. sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
  2602. return vha;
  2603. fail:
  2604. return vha;
  2605. }
  2606. static struct qla_work_evt *
  2607. qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
  2608. {
  2609. struct qla_work_evt *e;
  2610. uint8_t bail;
  2611. QLA_VHA_MARK_BUSY(vha, bail);
  2612. if (bail)
  2613. return NULL;
  2614. e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
  2615. if (!e) {
  2616. QLA_VHA_MARK_NOT_BUSY(vha);
  2617. return NULL;
  2618. }
  2619. INIT_LIST_HEAD(&e->list);
  2620. e->type = type;
  2621. e->flags = QLA_EVT_FLAG_FREE;
  2622. return e;
  2623. }
  2624. static int
  2625. qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
  2626. {
  2627. unsigned long flags;
  2628. spin_lock_irqsave(&vha->work_lock, flags);
  2629. list_add_tail(&e->list, &vha->work_list);
  2630. spin_unlock_irqrestore(&vha->work_lock, flags);
  2631. qla2xxx_wake_dpc(vha);
  2632. return QLA_SUCCESS;
  2633. }
  2634. int
  2635. qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
  2636. u32 data)
  2637. {
  2638. struct qla_work_evt *e;
  2639. e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
  2640. if (!e)
  2641. return QLA_FUNCTION_FAILED;
  2642. e->u.aen.code = code;
  2643. e->u.aen.data = data;
  2644. return qla2x00_post_work(vha, e);
  2645. }
  2646. int
  2647. qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
  2648. {
  2649. struct qla_work_evt *e;
  2650. e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
  2651. if (!e)
  2652. return QLA_FUNCTION_FAILED;
  2653. memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  2654. return qla2x00_post_work(vha, e);
  2655. }
  2656. #define qla2x00_post_async_work(name, type) \
  2657. int qla2x00_post_async_##name##_work( \
  2658. struct scsi_qla_host *vha, \
  2659. fc_port_t *fcport, uint16_t *data) \
  2660. { \
  2661. struct qla_work_evt *e; \
  2662. \
  2663. e = qla2x00_alloc_work(vha, type); \
  2664. if (!e) \
  2665. return QLA_FUNCTION_FAILED; \
  2666. \
  2667. e->u.logio.fcport = fcport; \
  2668. if (data) { \
  2669. e->u.logio.data[0] = data[0]; \
  2670. e->u.logio.data[1] = data[1]; \
  2671. } \
  2672. return qla2x00_post_work(vha, e); \
  2673. }
  2674. qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
  2675. qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
  2676. qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
  2677. qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
  2678. qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
  2679. qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
  2680. int
  2681. qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
  2682. {
  2683. struct qla_work_evt *e;
  2684. e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
  2685. if (!e)
  2686. return QLA_FUNCTION_FAILED;
  2687. e->u.uevent.code = code;
  2688. return qla2x00_post_work(vha, e);
  2689. }
  2690. static void
  2691. qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
  2692. {
  2693. char event_string[40];
  2694. char *envp[] = { event_string, NULL };
  2695. switch (code) {
  2696. case QLA_UEVENT_CODE_FW_DUMP:
  2697. snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
  2698. vha->host_no);
  2699. break;
  2700. default:
  2701. /* do nothing */
  2702. break;
  2703. }
  2704. kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
  2705. }
  2706. void
  2707. qla2x00_do_work(struct scsi_qla_host *vha)
  2708. {
  2709. struct qla_work_evt *e, *tmp;
  2710. unsigned long flags;
  2711. LIST_HEAD(work);
  2712. spin_lock_irqsave(&vha->work_lock, flags);
  2713. list_splice_init(&vha->work_list, &work);
  2714. spin_unlock_irqrestore(&vha->work_lock, flags);
  2715. list_for_each_entry_safe(e, tmp, &work, list) {
  2716. list_del_init(&e->list);
  2717. switch (e->type) {
  2718. case QLA_EVT_AEN:
  2719. fc_host_post_event(vha->host, fc_get_event_number(),
  2720. e->u.aen.code, e->u.aen.data);
  2721. break;
  2722. case QLA_EVT_IDC_ACK:
  2723. qla81xx_idc_ack(vha, e->u.idc_ack.mb);
  2724. break;
  2725. case QLA_EVT_ASYNC_LOGIN:
  2726. qla2x00_async_login(vha, e->u.logio.fcport,
  2727. e->u.logio.data);
  2728. break;
  2729. case QLA_EVT_ASYNC_LOGIN_DONE:
  2730. qla2x00_async_login_done(vha, e->u.logio.fcport,
  2731. e->u.logio.data);
  2732. break;
  2733. case QLA_EVT_ASYNC_LOGOUT:
  2734. qla2x00_async_logout(vha, e->u.logio.fcport);
  2735. break;
  2736. case QLA_EVT_ASYNC_LOGOUT_DONE:
  2737. qla2x00_async_logout_done(vha, e->u.logio.fcport,
  2738. e->u.logio.data);
  2739. break;
  2740. case QLA_EVT_ASYNC_ADISC:
  2741. qla2x00_async_adisc(vha, e->u.logio.fcport,
  2742. e->u.logio.data);
  2743. break;
  2744. case QLA_EVT_ASYNC_ADISC_DONE:
  2745. qla2x00_async_adisc_done(vha, e->u.logio.fcport,
  2746. e->u.logio.data);
  2747. break;
  2748. case QLA_EVT_UEVENT:
  2749. qla2x00_uevent_emit(vha, e->u.uevent.code);
  2750. break;
  2751. }
  2752. if (e->flags & QLA_EVT_FLAG_FREE)
  2753. kfree(e);
  2754. /* For each work completed decrement vha ref count */
  2755. QLA_VHA_MARK_NOT_BUSY(vha);
  2756. }
  2757. }
  2758. /* Relogins all the fcports of a vport
  2759. * Context: dpc thread
  2760. */
  2761. void qla2x00_relogin(struct scsi_qla_host *vha)
  2762. {
  2763. fc_port_t *fcport;
  2764. int status;
  2765. uint16_t next_loopid = 0;
  2766. struct qla_hw_data *ha = vha->hw;
  2767. uint16_t data[2];
  2768. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2769. /*
  2770. * If the port is not ONLINE then try to login
  2771. * to it if we haven't run out of retries.
  2772. */
  2773. if (atomic_read(&fcport->state) != FCS_ONLINE &&
  2774. fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
  2775. fcport->login_retry--;
  2776. if (fcport->flags & FCF_FABRIC_DEVICE) {
  2777. if (fcport->flags & FCF_FCP2_DEVICE)
  2778. ha->isp_ops->fabric_logout(vha,
  2779. fcport->loop_id,
  2780. fcport->d_id.b.domain,
  2781. fcport->d_id.b.area,
  2782. fcport->d_id.b.al_pa);
  2783. if (IS_ALOGIO_CAPABLE(ha)) {
  2784. fcport->flags |= FCF_ASYNC_SENT;
  2785. data[0] = 0;
  2786. data[1] = QLA_LOGIO_LOGIN_RETRIED;
  2787. status = qla2x00_post_async_login_work(
  2788. vha, fcport, data);
  2789. if (status == QLA_SUCCESS)
  2790. continue;
  2791. /* Attempt a retry. */
  2792. status = 1;
  2793. } else
  2794. status = qla2x00_fabric_login(vha,
  2795. fcport, &next_loopid);
  2796. } else
  2797. status = qla2x00_local_device_login(vha,
  2798. fcport);
  2799. if (status == QLA_SUCCESS) {
  2800. fcport->old_loop_id = fcport->loop_id;
  2801. DEBUG(printk("scsi(%ld): port login OK: logged "
  2802. "in ID 0x%x\n", vha->host_no, fcport->loop_id));
  2803. qla2x00_update_fcport(vha, fcport);
  2804. } else if (status == 1) {
  2805. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  2806. /* retry the login again */
  2807. DEBUG(printk("scsi(%ld): Retrying"
  2808. " %d login again loop_id 0x%x\n",
  2809. vha->host_no, fcport->login_retry,
  2810. fcport->loop_id));
  2811. } else {
  2812. fcport->login_retry = 0;
  2813. }
  2814. if (fcport->login_retry == 0 && status != QLA_SUCCESS)
  2815. fcport->loop_id = FC_NO_LOOP_ID;
  2816. }
  2817. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2818. break;
  2819. }
  2820. }
  2821. /**************************************************************************
  2822. * qla2x00_do_dpc
  2823. * This kernel thread is a task that is schedule by the interrupt handler
  2824. * to perform the background processing for interrupts.
  2825. *
  2826. * Notes:
  2827. * This task always run in the context of a kernel thread. It
  2828. * is kick-off by the driver's detect code and starts up
  2829. * up one per adapter. It immediately goes to sleep and waits for
  2830. * some fibre event. When either the interrupt handler or
  2831. * the timer routine detects a event it will one of the task
  2832. * bits then wake us up.
  2833. **************************************************************************/
  2834. static int
  2835. qla2x00_do_dpc(void *data)
  2836. {
  2837. int rval;
  2838. scsi_qla_host_t *base_vha;
  2839. struct qla_hw_data *ha;
  2840. ha = (struct qla_hw_data *)data;
  2841. base_vha = pci_get_drvdata(ha->pdev);
  2842. set_user_nice(current, -20);
  2843. while (!kthread_should_stop()) {
  2844. DEBUG3(printk("qla2x00: DPC handler sleeping\n"));
  2845. set_current_state(TASK_INTERRUPTIBLE);
  2846. schedule();
  2847. __set_current_state(TASK_RUNNING);
  2848. DEBUG3(printk("qla2x00: DPC handler waking up\n"));
  2849. /* Initialization not yet finished. Don't do anything yet. */
  2850. if (!base_vha->flags.init_done)
  2851. continue;
  2852. if (ha->flags.eeh_busy) {
  2853. DEBUG17(qla_printk(KERN_WARNING, ha,
  2854. "qla2x00_do_dpc: dpc_flags: %lx\n",
  2855. base_vha->dpc_flags));
  2856. continue;
  2857. }
  2858. DEBUG3(printk("scsi(%ld): DPC handler\n", base_vha->host_no));
  2859. ha->dpc_active = 1;
  2860. if (ha->flags.mbox_busy) {
  2861. ha->dpc_active = 0;
  2862. continue;
  2863. }
  2864. qla2x00_do_work(base_vha);
  2865. if (IS_QLA82XX(ha)) {
  2866. if (test_and_clear_bit(ISP_UNRECOVERABLE,
  2867. &base_vha->dpc_flags)) {
  2868. qla82xx_idc_lock(ha);
  2869. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  2870. QLA82XX_DEV_FAILED);
  2871. qla82xx_idc_unlock(ha);
  2872. qla_printk(KERN_INFO, ha,
  2873. "HW State: FAILED\n");
  2874. qla82xx_device_state_handler(base_vha);
  2875. continue;
  2876. }
  2877. if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
  2878. &base_vha->dpc_flags)) {
  2879. DEBUG(printk(KERN_INFO
  2880. "scsi(%ld): dpc: sched "
  2881. "qla82xx_fcoe_ctx_reset ha = %p\n",
  2882. base_vha->host_no, ha));
  2883. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2884. &base_vha->dpc_flags))) {
  2885. if (qla82xx_fcoe_ctx_reset(base_vha)) {
  2886. /* FCoE-ctx reset failed.
  2887. * Escalate to chip-reset
  2888. */
  2889. set_bit(ISP_ABORT_NEEDED,
  2890. &base_vha->dpc_flags);
  2891. }
  2892. clear_bit(ABORT_ISP_ACTIVE,
  2893. &base_vha->dpc_flags);
  2894. }
  2895. DEBUG(printk("scsi(%ld): dpc:"
  2896. " qla82xx_fcoe_ctx_reset end\n",
  2897. base_vha->host_no));
  2898. }
  2899. }
  2900. if (test_and_clear_bit(ISP_ABORT_NEEDED,
  2901. &base_vha->dpc_flags)) {
  2902. DEBUG(printk("scsi(%ld): dpc: sched "
  2903. "qla2x00_abort_isp ha = %p\n",
  2904. base_vha->host_no, ha));
  2905. if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
  2906. &base_vha->dpc_flags))) {
  2907. if (ha->isp_ops->abort_isp(base_vha)) {
  2908. /* failed. retry later */
  2909. set_bit(ISP_ABORT_NEEDED,
  2910. &base_vha->dpc_flags);
  2911. }
  2912. clear_bit(ABORT_ISP_ACTIVE,
  2913. &base_vha->dpc_flags);
  2914. }
  2915. DEBUG(printk("scsi(%ld): dpc: qla2x00_abort_isp end\n",
  2916. base_vha->host_no));
  2917. }
  2918. if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
  2919. qla2x00_update_fcports(base_vha);
  2920. clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
  2921. }
  2922. if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
  2923. DEBUG(printk(KERN_INFO "scsi(%ld): dpc: sched "
  2924. "qla2x00_quiesce_needed ha = %p\n",
  2925. base_vha->host_no, ha));
  2926. qla82xx_device_state_handler(base_vha);
  2927. clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
  2928. if (!ha->flags.quiesce_owner) {
  2929. qla2x00_perform_loop_resync(base_vha);
  2930. qla82xx_idc_lock(ha);
  2931. qla82xx_clear_qsnt_ready(base_vha);
  2932. qla82xx_idc_unlock(ha);
  2933. }
  2934. }
  2935. if (test_and_clear_bit(RESET_MARKER_NEEDED,
  2936. &base_vha->dpc_flags) &&
  2937. (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
  2938. DEBUG(printk("scsi(%ld): qla2x00_reset_marker()\n",
  2939. base_vha->host_no));
  2940. qla2x00_rst_aen(base_vha);
  2941. clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
  2942. }
  2943. /* Retry each device up to login retry count */
  2944. if ((test_and_clear_bit(RELOGIN_NEEDED,
  2945. &base_vha->dpc_flags)) &&
  2946. !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
  2947. atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
  2948. DEBUG(printk("scsi(%ld): qla2x00_port_login()\n",
  2949. base_vha->host_no));
  2950. qla2x00_relogin(base_vha);
  2951. DEBUG(printk("scsi(%ld): qla2x00_port_login - end\n",
  2952. base_vha->host_no));
  2953. }
  2954. if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
  2955. &base_vha->dpc_flags)) {
  2956. DEBUG(printk("scsi(%ld): qla2x00_loop_resync()\n",
  2957. base_vha->host_no));
  2958. if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
  2959. &base_vha->dpc_flags))) {
  2960. rval = qla2x00_loop_resync(base_vha);
  2961. clear_bit(LOOP_RESYNC_ACTIVE,
  2962. &base_vha->dpc_flags);
  2963. }
  2964. DEBUG(printk("scsi(%ld): qla2x00_loop_resync - end\n",
  2965. base_vha->host_no));
  2966. }
  2967. if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
  2968. atomic_read(&base_vha->loop_state) == LOOP_READY) {
  2969. clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
  2970. qla2xxx_flash_npiv_conf(base_vha);
  2971. }
  2972. if (!ha->interrupts_on)
  2973. ha->isp_ops->enable_intrs(ha);
  2974. if (test_and_clear_bit(BEACON_BLINK_NEEDED,
  2975. &base_vha->dpc_flags))
  2976. ha->isp_ops->beacon_blink(base_vha);
  2977. qla2x00_do_dpc_all_vps(base_vha);
  2978. ha->dpc_active = 0;
  2979. } /* End of while(1) */
  2980. DEBUG(printk("scsi(%ld): DPC handler exiting\n", base_vha->host_no));
  2981. /*
  2982. * Make sure that nobody tries to wake us up again.
  2983. */
  2984. ha->dpc_active = 0;
  2985. /* Cleanup any residual CTX SRBs. */
  2986. qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
  2987. return 0;
  2988. }
  2989. void
  2990. qla2xxx_wake_dpc(struct scsi_qla_host *vha)
  2991. {
  2992. struct qla_hw_data *ha = vha->hw;
  2993. struct task_struct *t = ha->dpc_thread;
  2994. if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
  2995. wake_up_process(t);
  2996. }
  2997. /*
  2998. * qla2x00_rst_aen
  2999. * Processes asynchronous reset.
  3000. *
  3001. * Input:
  3002. * ha = adapter block pointer.
  3003. */
  3004. static void
  3005. qla2x00_rst_aen(scsi_qla_host_t *vha)
  3006. {
  3007. if (vha->flags.online && !vha->flags.reset_active &&
  3008. !atomic_read(&vha->loop_down_timer) &&
  3009. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
  3010. do {
  3011. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3012. /*
  3013. * Issue marker command only when we are going to start
  3014. * the I/O.
  3015. */
  3016. vha->marker_needed = 1;
  3017. } while (!atomic_read(&vha->loop_down_timer) &&
  3018. (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
  3019. }
  3020. }
  3021. static void
  3022. qla2x00_sp_free_dma(srb_t *sp)
  3023. {
  3024. struct scsi_cmnd *cmd = sp->cmd;
  3025. struct qla_hw_data *ha = sp->fcport->vha->hw;
  3026. if (sp->flags & SRB_DMA_VALID) {
  3027. scsi_dma_unmap(cmd);
  3028. sp->flags &= ~SRB_DMA_VALID;
  3029. }
  3030. if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
  3031. dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
  3032. scsi_prot_sg_count(cmd), cmd->sc_data_direction);
  3033. sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
  3034. }
  3035. if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
  3036. /* List assured to be having elements */
  3037. qla2x00_clean_dsd_pool(ha, sp);
  3038. sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
  3039. }
  3040. if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
  3041. dma_pool_free(ha->dl_dma_pool, sp->ctx,
  3042. ((struct crc_context *)sp->ctx)->crc_ctx_dma);
  3043. sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
  3044. }
  3045. CMD_SP(cmd) = NULL;
  3046. }
  3047. static void
  3048. qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
  3049. {
  3050. struct scsi_cmnd *cmd = sp->cmd;
  3051. qla2x00_sp_free_dma(sp);
  3052. if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
  3053. struct ct6_dsd *ctx = sp->ctx;
  3054. dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
  3055. ctx->fcp_cmnd_dma);
  3056. list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
  3057. ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
  3058. ha->gbl_dsd_avail += ctx->dsd_use_cnt;
  3059. mempool_free(sp->ctx, ha->ctx_mempool);
  3060. sp->ctx = NULL;
  3061. }
  3062. mempool_free(sp, ha->srb_mempool);
  3063. cmd->scsi_done(cmd);
  3064. }
  3065. void
  3066. qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
  3067. {
  3068. if (atomic_read(&sp->ref_count) == 0) {
  3069. DEBUG2(qla_printk(KERN_WARNING, ha,
  3070. "SP reference-count to ZERO -- sp=%p\n", sp));
  3071. DEBUG2(BUG());
  3072. return;
  3073. }
  3074. if (!atomic_dec_and_test(&sp->ref_count))
  3075. return;
  3076. qla2x00_sp_final_compl(ha, sp);
  3077. }
  3078. /**************************************************************************
  3079. * qla2x00_timer
  3080. *
  3081. * Description:
  3082. * One second timer
  3083. *
  3084. * Context: Interrupt
  3085. ***************************************************************************/
  3086. void
  3087. qla2x00_timer(scsi_qla_host_t *vha)
  3088. {
  3089. unsigned long cpu_flags = 0;
  3090. int start_dpc = 0;
  3091. int index;
  3092. srb_t *sp;
  3093. uint16_t w;
  3094. struct qla_hw_data *ha = vha->hw;
  3095. struct req_que *req;
  3096. if (ha->flags.eeh_busy) {
  3097. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3098. return;
  3099. }
  3100. /* Hardware read to raise pending EEH errors during mailbox waits. */
  3101. if (!pci_channel_offline(ha->pdev))
  3102. pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
  3103. if (IS_QLA82XX(ha)) {
  3104. if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
  3105. start_dpc++;
  3106. qla82xx_watchdog(vha);
  3107. }
  3108. /* Loop down handler. */
  3109. if (atomic_read(&vha->loop_down_timer) > 0 &&
  3110. !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
  3111. && vha->flags.online) {
  3112. if (atomic_read(&vha->loop_down_timer) ==
  3113. vha->loop_down_abort_time) {
  3114. DEBUG(printk("scsi(%ld): Loop Down - aborting the "
  3115. "queues before time expire\n",
  3116. vha->host_no));
  3117. if (!IS_QLA2100(ha) && vha->link_down_timeout)
  3118. atomic_set(&vha->loop_state, LOOP_DEAD);
  3119. /*
  3120. * Schedule an ISP abort to return any FCP2-device
  3121. * commands.
  3122. */
  3123. /* NPIV - scan physical port only */
  3124. if (!vha->vp_idx) {
  3125. spin_lock_irqsave(&ha->hardware_lock,
  3126. cpu_flags);
  3127. req = ha->req_q_map[0];
  3128. for (index = 1;
  3129. index < MAX_OUTSTANDING_COMMANDS;
  3130. index++) {
  3131. fc_port_t *sfcp;
  3132. sp = req->outstanding_cmds[index];
  3133. if (!sp)
  3134. continue;
  3135. if (sp->ctx && !IS_PROT_IO(sp))
  3136. continue;
  3137. sfcp = sp->fcport;
  3138. if (!(sfcp->flags & FCF_FCP2_DEVICE))
  3139. continue;
  3140. set_bit(ISP_ABORT_NEEDED,
  3141. &vha->dpc_flags);
  3142. break;
  3143. }
  3144. spin_unlock_irqrestore(&ha->hardware_lock,
  3145. cpu_flags);
  3146. }
  3147. start_dpc++;
  3148. }
  3149. /* if the loop has been down for 4 minutes, reinit adapter */
  3150. if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
  3151. if (!(vha->device_flags & DFLG_NO_CABLE)) {
  3152. DEBUG(printk("scsi(%ld): Loop down - "
  3153. "aborting ISP.\n",
  3154. vha->host_no));
  3155. qla_printk(KERN_WARNING, ha,
  3156. "Loop down - aborting ISP.\n");
  3157. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3158. }
  3159. }
  3160. DEBUG3(printk("scsi(%ld): Loop Down - seconds remaining %d\n",
  3161. vha->host_no,
  3162. atomic_read(&vha->loop_down_timer)));
  3163. }
  3164. /* Check if beacon LED needs to be blinked */
  3165. if (ha->beacon_blink_led == 1) {
  3166. set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
  3167. start_dpc++;
  3168. }
  3169. /* Process any deferred work. */
  3170. if (!list_empty(&vha->work_list))
  3171. start_dpc++;
  3172. /* Schedule the DPC routine if needed */
  3173. if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
  3174. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
  3175. test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
  3176. start_dpc ||
  3177. test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
  3178. test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
  3179. test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
  3180. test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
  3181. test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
  3182. test_bit(RELOGIN_NEEDED, &vha->dpc_flags)))
  3183. qla2xxx_wake_dpc(vha);
  3184. qla2x00_restart_timer(vha, WATCH_INTERVAL);
  3185. }
  3186. /* Firmware interface routines. */
  3187. #define FW_BLOBS 8
  3188. #define FW_ISP21XX 0
  3189. #define FW_ISP22XX 1
  3190. #define FW_ISP2300 2
  3191. #define FW_ISP2322 3
  3192. #define FW_ISP24XX 4
  3193. #define FW_ISP25XX 5
  3194. #define FW_ISP81XX 6
  3195. #define FW_ISP82XX 7
  3196. #define FW_FILE_ISP21XX "ql2100_fw.bin"
  3197. #define FW_FILE_ISP22XX "ql2200_fw.bin"
  3198. #define FW_FILE_ISP2300 "ql2300_fw.bin"
  3199. #define FW_FILE_ISP2322 "ql2322_fw.bin"
  3200. #define FW_FILE_ISP24XX "ql2400_fw.bin"
  3201. #define FW_FILE_ISP25XX "ql2500_fw.bin"
  3202. #define FW_FILE_ISP81XX "ql8100_fw.bin"
  3203. #define FW_FILE_ISP82XX "ql8200_fw.bin"
  3204. static DEFINE_MUTEX(qla_fw_lock);
  3205. static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
  3206. { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
  3207. { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
  3208. { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
  3209. { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
  3210. { .name = FW_FILE_ISP24XX, },
  3211. { .name = FW_FILE_ISP25XX, },
  3212. { .name = FW_FILE_ISP81XX, },
  3213. { .name = FW_FILE_ISP82XX, },
  3214. };
  3215. struct fw_blob *
  3216. qla2x00_request_firmware(scsi_qla_host_t *vha)
  3217. {
  3218. struct qla_hw_data *ha = vha->hw;
  3219. struct fw_blob *blob;
  3220. blob = NULL;
  3221. if (IS_QLA2100(ha)) {
  3222. blob = &qla_fw_blobs[FW_ISP21XX];
  3223. } else if (IS_QLA2200(ha)) {
  3224. blob = &qla_fw_blobs[FW_ISP22XX];
  3225. } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  3226. blob = &qla_fw_blobs[FW_ISP2300];
  3227. } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  3228. blob = &qla_fw_blobs[FW_ISP2322];
  3229. } else if (IS_QLA24XX_TYPE(ha)) {
  3230. blob = &qla_fw_blobs[FW_ISP24XX];
  3231. } else if (IS_QLA25XX(ha)) {
  3232. blob = &qla_fw_blobs[FW_ISP25XX];
  3233. } else if (IS_QLA81XX(ha)) {
  3234. blob = &qla_fw_blobs[FW_ISP81XX];
  3235. } else if (IS_QLA82XX(ha)) {
  3236. blob = &qla_fw_blobs[FW_ISP82XX];
  3237. }
  3238. mutex_lock(&qla_fw_lock);
  3239. if (blob->fw)
  3240. goto out;
  3241. if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
  3242. DEBUG2(printk("scsi(%ld): Failed to load firmware image "
  3243. "(%s).\n", vha->host_no, blob->name));
  3244. blob->fw = NULL;
  3245. blob = NULL;
  3246. goto out;
  3247. }
  3248. out:
  3249. mutex_unlock(&qla_fw_lock);
  3250. return blob;
  3251. }
  3252. static void
  3253. qla2x00_release_firmware(void)
  3254. {
  3255. int idx;
  3256. mutex_lock(&qla_fw_lock);
  3257. for (idx = 0; idx < FW_BLOBS; idx++)
  3258. if (qla_fw_blobs[idx].fw)
  3259. release_firmware(qla_fw_blobs[idx].fw);
  3260. mutex_unlock(&qla_fw_lock);
  3261. }
  3262. static pci_ers_result_t
  3263. qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
  3264. {
  3265. scsi_qla_host_t *vha = pci_get_drvdata(pdev);
  3266. struct qla_hw_data *ha = vha->hw;
  3267. DEBUG2(qla_printk(KERN_WARNING, ha, "error_detected:state %x\n",
  3268. state));
  3269. switch (state) {
  3270. case pci_channel_io_normal:
  3271. ha->flags.eeh_busy = 0;
  3272. return PCI_ERS_RESULT_CAN_RECOVER;
  3273. case pci_channel_io_frozen:
  3274. ha->flags.eeh_busy = 1;
  3275. /* For ISP82XX complete any pending mailbox cmd */
  3276. if (IS_QLA82XX(ha)) {
  3277. ha->flags.fw_hung = 1;
  3278. if (ha->flags.mbox_busy) {
  3279. ha->flags.mbox_int = 1;
  3280. DEBUG2(qla_printk(KERN_ERR, ha,
  3281. "Due to pci channel io frozen, doing premature "
  3282. "completion of mbx command\n"));
  3283. complete(&ha->mbx_intr_comp);
  3284. }
  3285. }
  3286. qla2x00_free_irqs(vha);
  3287. pci_disable_device(pdev);
  3288. /* Return back all IOs */
  3289. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3290. return PCI_ERS_RESULT_NEED_RESET;
  3291. case pci_channel_io_perm_failure:
  3292. ha->flags.pci_channel_io_perm_failure = 1;
  3293. qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
  3294. return PCI_ERS_RESULT_DISCONNECT;
  3295. }
  3296. return PCI_ERS_RESULT_NEED_RESET;
  3297. }
  3298. static pci_ers_result_t
  3299. qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
  3300. {
  3301. int risc_paused = 0;
  3302. uint32_t stat;
  3303. unsigned long flags;
  3304. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3305. struct qla_hw_data *ha = base_vha->hw;
  3306. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3307. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  3308. if (IS_QLA82XX(ha))
  3309. return PCI_ERS_RESULT_RECOVERED;
  3310. spin_lock_irqsave(&ha->hardware_lock, flags);
  3311. if (IS_QLA2100(ha) || IS_QLA2200(ha)){
  3312. stat = RD_REG_DWORD(&reg->hccr);
  3313. if (stat & HCCR_RISC_PAUSE)
  3314. risc_paused = 1;
  3315. } else if (IS_QLA23XX(ha)) {
  3316. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  3317. if (stat & HSR_RISC_PAUSED)
  3318. risc_paused = 1;
  3319. } else if (IS_FWI2_CAPABLE(ha)) {
  3320. stat = RD_REG_DWORD(&reg24->host_status);
  3321. if (stat & HSRX_RISC_PAUSED)
  3322. risc_paused = 1;
  3323. }
  3324. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3325. if (risc_paused) {
  3326. qla_printk(KERN_INFO, ha, "RISC paused -- mmio_enabled, "
  3327. "Dumping firmware!\n");
  3328. ha->isp_ops->fw_dump(base_vha, 0);
  3329. return PCI_ERS_RESULT_NEED_RESET;
  3330. } else
  3331. return PCI_ERS_RESULT_RECOVERED;
  3332. }
  3333. uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
  3334. {
  3335. uint32_t rval = QLA_FUNCTION_FAILED;
  3336. uint32_t drv_active = 0;
  3337. struct qla_hw_data *ha = base_vha->hw;
  3338. int fn;
  3339. struct pci_dev *other_pdev = NULL;
  3340. DEBUG17(qla_printk(KERN_INFO, ha,
  3341. "scsi(%ld): In qla82xx_error_recovery\n", base_vha->host_no));
  3342. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3343. if (base_vha->flags.online) {
  3344. /* Abort all outstanding commands,
  3345. * so as to be requeued later */
  3346. qla2x00_abort_isp_cleanup(base_vha);
  3347. }
  3348. fn = PCI_FUNC(ha->pdev->devfn);
  3349. while (fn > 0) {
  3350. fn--;
  3351. DEBUG17(qla_printk(KERN_INFO, ha,
  3352. "Finding pci device at function = 0x%x\n", fn));
  3353. other_pdev =
  3354. pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
  3355. ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
  3356. fn));
  3357. if (!other_pdev)
  3358. continue;
  3359. if (atomic_read(&other_pdev->enable_cnt)) {
  3360. DEBUG17(qla_printk(KERN_INFO, ha,
  3361. "Found PCI func availabe and enabled at 0x%x\n",
  3362. fn));
  3363. pci_dev_put(other_pdev);
  3364. break;
  3365. }
  3366. pci_dev_put(other_pdev);
  3367. }
  3368. if (!fn) {
  3369. /* Reset owner */
  3370. DEBUG17(qla_printk(KERN_INFO, ha,
  3371. "This devfn is reset owner = 0x%x\n", ha->pdev->devfn));
  3372. qla82xx_idc_lock(ha);
  3373. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3374. QLA82XX_DEV_INITIALIZING);
  3375. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
  3376. QLA82XX_IDC_VERSION);
  3377. drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
  3378. DEBUG17(qla_printk(KERN_INFO, ha,
  3379. "drv_active = 0x%x\n", drv_active));
  3380. qla82xx_idc_unlock(ha);
  3381. /* Reset if device is not already reset
  3382. * drv_active would be 0 if a reset has already been done
  3383. */
  3384. if (drv_active)
  3385. rval = qla82xx_start_firmware(base_vha);
  3386. else
  3387. rval = QLA_SUCCESS;
  3388. qla82xx_idc_lock(ha);
  3389. if (rval != QLA_SUCCESS) {
  3390. qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
  3391. qla82xx_clear_drv_active(ha);
  3392. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3393. QLA82XX_DEV_FAILED);
  3394. } else {
  3395. qla_printk(KERN_INFO, ha, "HW State: READY\n");
  3396. qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
  3397. QLA82XX_DEV_READY);
  3398. qla82xx_idc_unlock(ha);
  3399. ha->flags.fw_hung = 0;
  3400. rval = qla82xx_restart_isp(base_vha);
  3401. qla82xx_idc_lock(ha);
  3402. /* Clear driver state register */
  3403. qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
  3404. qla82xx_set_drv_active(base_vha);
  3405. }
  3406. qla82xx_idc_unlock(ha);
  3407. } else {
  3408. DEBUG17(qla_printk(KERN_INFO, ha,
  3409. "This devfn is not reset owner = 0x%x\n", ha->pdev->devfn));
  3410. if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
  3411. QLA82XX_DEV_READY)) {
  3412. ha->flags.fw_hung = 0;
  3413. rval = qla82xx_restart_isp(base_vha);
  3414. qla82xx_idc_lock(ha);
  3415. qla82xx_set_drv_active(base_vha);
  3416. qla82xx_idc_unlock(ha);
  3417. }
  3418. }
  3419. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3420. return rval;
  3421. }
  3422. static pci_ers_result_t
  3423. qla2xxx_pci_slot_reset(struct pci_dev *pdev)
  3424. {
  3425. pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
  3426. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3427. struct qla_hw_data *ha = base_vha->hw;
  3428. struct rsp_que *rsp;
  3429. int rc, retries = 10;
  3430. DEBUG17(qla_printk(KERN_WARNING, ha, "slot_reset\n"));
  3431. /* Workaround: qla2xxx driver which access hardware earlier
  3432. * needs error state to be pci_channel_io_online.
  3433. * Otherwise mailbox command timesout.
  3434. */
  3435. pdev->error_state = pci_channel_io_normal;
  3436. pci_restore_state(pdev);
  3437. /* pci_restore_state() clears the saved_state flag of the device
  3438. * save restored state which resets saved_state flag
  3439. */
  3440. pci_save_state(pdev);
  3441. if (ha->mem_only)
  3442. rc = pci_enable_device_mem(pdev);
  3443. else
  3444. rc = pci_enable_device(pdev);
  3445. if (rc) {
  3446. qla_printk(KERN_WARNING, ha,
  3447. "Can't re-enable PCI device after reset.\n");
  3448. goto exit_slot_reset;
  3449. }
  3450. rsp = ha->rsp_q_map[0];
  3451. if (qla2x00_request_irqs(ha, rsp))
  3452. goto exit_slot_reset;
  3453. if (ha->isp_ops->pci_config(base_vha))
  3454. goto exit_slot_reset;
  3455. if (IS_QLA82XX(ha)) {
  3456. if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
  3457. ret = PCI_ERS_RESULT_RECOVERED;
  3458. goto exit_slot_reset;
  3459. } else
  3460. goto exit_slot_reset;
  3461. }
  3462. while (ha->flags.mbox_busy && retries--)
  3463. msleep(1000);
  3464. set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3465. if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
  3466. ret = PCI_ERS_RESULT_RECOVERED;
  3467. clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  3468. exit_slot_reset:
  3469. DEBUG17(qla_printk(KERN_WARNING, ha,
  3470. "slot_reset-return:ret=%x\n", ret));
  3471. return ret;
  3472. }
  3473. static void
  3474. qla2xxx_pci_resume(struct pci_dev *pdev)
  3475. {
  3476. scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
  3477. struct qla_hw_data *ha = base_vha->hw;
  3478. int ret;
  3479. DEBUG17(qla_printk(KERN_WARNING, ha, "pci_resume\n"));
  3480. ret = qla2x00_wait_for_hba_online(base_vha);
  3481. if (ret != QLA_SUCCESS) {
  3482. qla_printk(KERN_ERR, ha,
  3483. "the device failed to resume I/O "
  3484. "from slot/link_reset");
  3485. }
  3486. pci_cleanup_aer_uncorrect_error_status(pdev);
  3487. ha->flags.eeh_busy = 0;
  3488. }
  3489. static struct pci_error_handlers qla2xxx_err_handler = {
  3490. .error_detected = qla2xxx_pci_error_detected,
  3491. .mmio_enabled = qla2xxx_pci_mmio_enabled,
  3492. .slot_reset = qla2xxx_pci_slot_reset,
  3493. .resume = qla2xxx_pci_resume,
  3494. };
  3495. static struct pci_device_id qla2xxx_pci_tbl[] = {
  3496. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
  3497. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
  3498. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
  3499. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
  3500. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
  3501. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
  3502. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
  3503. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
  3504. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
  3505. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
  3506. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
  3507. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
  3508. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
  3509. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
  3510. { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
  3511. { 0 },
  3512. };
  3513. MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
  3514. static struct pci_driver qla2xxx_pci_driver = {
  3515. .name = QLA2XXX_DRIVER_NAME,
  3516. .driver = {
  3517. .owner = THIS_MODULE,
  3518. },
  3519. .id_table = qla2xxx_pci_tbl,
  3520. .probe = qla2x00_probe_one,
  3521. .remove = qla2x00_remove_one,
  3522. .shutdown = qla2x00_shutdown,
  3523. .err_handler = &qla2xxx_err_handler,
  3524. };
  3525. static struct file_operations apidev_fops = {
  3526. .owner = THIS_MODULE,
  3527. .llseek = noop_llseek,
  3528. };
  3529. /**
  3530. * qla2x00_module_init - Module initialization.
  3531. **/
  3532. static int __init
  3533. qla2x00_module_init(void)
  3534. {
  3535. int ret = 0;
  3536. /* Allocate cache for SRBs. */
  3537. srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
  3538. SLAB_HWCACHE_ALIGN, NULL);
  3539. if (srb_cachep == NULL) {
  3540. printk(KERN_ERR
  3541. "qla2xxx: Unable to allocate SRB cache...Failing load!\n");
  3542. return -ENOMEM;
  3543. }
  3544. /* Derive version string. */
  3545. strcpy(qla2x00_version_str, QLA2XXX_VERSION);
  3546. if (ql2xextended_error_logging)
  3547. strcat(qla2x00_version_str, "-debug");
  3548. qla2xxx_transport_template =
  3549. fc_attach_transport(&qla2xxx_transport_functions);
  3550. if (!qla2xxx_transport_template) {
  3551. kmem_cache_destroy(srb_cachep);
  3552. return -ENODEV;
  3553. }
  3554. apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
  3555. if (apidev_major < 0) {
  3556. printk(KERN_WARNING "qla2xxx: Unable to register char device "
  3557. "%s\n", QLA2XXX_APIDEV);
  3558. }
  3559. qla2xxx_transport_vport_template =
  3560. fc_attach_transport(&qla2xxx_transport_vport_functions);
  3561. if (!qla2xxx_transport_vport_template) {
  3562. kmem_cache_destroy(srb_cachep);
  3563. fc_release_transport(qla2xxx_transport_template);
  3564. return -ENODEV;
  3565. }
  3566. printk(KERN_INFO "QLogic Fibre Channel HBA Driver: %s\n",
  3567. qla2x00_version_str);
  3568. ret = pci_register_driver(&qla2xxx_pci_driver);
  3569. if (ret) {
  3570. kmem_cache_destroy(srb_cachep);
  3571. fc_release_transport(qla2xxx_transport_template);
  3572. fc_release_transport(qla2xxx_transport_vport_template);
  3573. }
  3574. return ret;
  3575. }
  3576. /**
  3577. * qla2x00_module_exit - Module cleanup.
  3578. **/
  3579. static void __exit
  3580. qla2x00_module_exit(void)
  3581. {
  3582. unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
  3583. pci_unregister_driver(&qla2xxx_pci_driver);
  3584. qla2x00_release_firmware();
  3585. kmem_cache_destroy(srb_cachep);
  3586. if (ctx_cachep)
  3587. kmem_cache_destroy(ctx_cachep);
  3588. fc_release_transport(qla2xxx_transport_template);
  3589. fc_release_transport(qla2xxx_transport_vport_template);
  3590. }
  3591. module_init(qla2x00_module_init);
  3592. module_exit(qla2x00_module_exit);
  3593. MODULE_AUTHOR("QLogic Corporation");
  3594. MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
  3595. MODULE_LICENSE("GPL");
  3596. MODULE_VERSION(QLA2XXX_VERSION);
  3597. MODULE_FIRMWARE(FW_FILE_ISP21XX);
  3598. MODULE_FIRMWARE(FW_FILE_ISP22XX);
  3599. MODULE_FIRMWARE(FW_FILE_ISP2300);
  3600. MODULE_FIRMWARE(FW_FILE_ISP2322);
  3601. MODULE_FIRMWARE(FW_FILE_ISP24XX);
  3602. MODULE_FIRMWARE(FW_FILE_ISP25XX);