i915_dma.c 61 KB

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  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc_helper.h"
  31. #include "drm_fb_helper.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include <linux/vgaarb.h>
  37. #include <linux/acpi.h>
  38. #include <linux/pnp.h>
  39. #include <linux/vga_switcheroo.h>
  40. #include <linux/slab.h>
  41. /**
  42. * Sets up the hardware status page for devices that need a physical address
  43. * in the register.
  44. */
  45. static int i915_init_phys_hws(struct drm_device *dev)
  46. {
  47. drm_i915_private_t *dev_priv = dev->dev_private;
  48. /* Program Hardware Status Page */
  49. dev_priv->status_page_dmah =
  50. drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  51. if (!dev_priv->status_page_dmah) {
  52. DRM_ERROR("Can not allocate hardware status page\n");
  53. return -ENOMEM;
  54. }
  55. dev_priv->render_ring.status_page.page_addr
  56. = dev_priv->status_page_dmah->vaddr;
  57. dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  58. memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  59. if (IS_I965G(dev))
  60. dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  61. 0xf0;
  62. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  63. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  64. return 0;
  65. }
  66. /**
  67. * Frees the hardware status page, whether it's a physical address or a virtual
  68. * address set up by the X Server.
  69. */
  70. static void i915_free_hws(struct drm_device *dev)
  71. {
  72. drm_i915_private_t *dev_priv = dev->dev_private;
  73. if (dev_priv->status_page_dmah) {
  74. drm_pci_free(dev, dev_priv->status_page_dmah);
  75. dev_priv->status_page_dmah = NULL;
  76. }
  77. if (dev_priv->render_ring.status_page.gfx_addr) {
  78. dev_priv->render_ring.status_page.gfx_addr = 0;
  79. drm_core_ioremapfree(&dev_priv->hws_map, dev);
  80. }
  81. /* Need to rewrite hardware status page */
  82. I915_WRITE(HWS_PGA, 0x1ffff000);
  83. }
  84. void i915_kernel_lost_context(struct drm_device * dev)
  85. {
  86. drm_i915_private_t *dev_priv = dev->dev_private;
  87. struct drm_i915_master_private *master_priv;
  88. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  89. /*
  90. * We should never lose context on the ring with modesetting
  91. * as we don't expose it to userspace
  92. */
  93. if (drm_core_check_feature(dev, DRIVER_MODESET))
  94. return;
  95. ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
  96. ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
  97. ring->space = ring->head - (ring->tail + 8);
  98. if (ring->space < 0)
  99. ring->space += ring->size;
  100. if (!dev->primary->master)
  101. return;
  102. master_priv = dev->primary->master->driver_priv;
  103. if (ring->head == ring->tail && master_priv->sarea_priv)
  104. master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  105. }
  106. static int i915_dma_cleanup(struct drm_device * dev)
  107. {
  108. drm_i915_private_t *dev_priv = dev->dev_private;
  109. /* Make sure interrupts are disabled here because the uninstall ioctl
  110. * may not have been called from userspace and after dev_private
  111. * is freed, it's too late.
  112. */
  113. if (dev->irq_enabled)
  114. drm_irq_uninstall(dev);
  115. intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
  116. if (HAS_BSD(dev))
  117. intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
  118. /* Clear the HWS virtual address at teardown */
  119. if (I915_NEED_GFX_HWS(dev))
  120. i915_free_hws(dev);
  121. return 0;
  122. }
  123. static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
  124. {
  125. drm_i915_private_t *dev_priv = dev->dev_private;
  126. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  127. master_priv->sarea = drm_getsarea(dev);
  128. if (master_priv->sarea) {
  129. master_priv->sarea_priv = (drm_i915_sarea_t *)
  130. ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
  131. } else {
  132. DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
  133. }
  134. if (init->ring_size != 0) {
  135. if (dev_priv->render_ring.gem_object != NULL) {
  136. i915_dma_cleanup(dev);
  137. DRM_ERROR("Client tried to initialize ringbuffer in "
  138. "GEM mode\n");
  139. return -EINVAL;
  140. }
  141. dev_priv->render_ring.size = init->ring_size;
  142. dev_priv->render_ring.map.offset = init->ring_start;
  143. dev_priv->render_ring.map.size = init->ring_size;
  144. dev_priv->render_ring.map.type = 0;
  145. dev_priv->render_ring.map.flags = 0;
  146. dev_priv->render_ring.map.mtrr = 0;
  147. drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
  148. if (dev_priv->render_ring.map.handle == NULL) {
  149. i915_dma_cleanup(dev);
  150. DRM_ERROR("can not ioremap virtual address for"
  151. " ring buffer\n");
  152. return -ENOMEM;
  153. }
  154. }
  155. dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
  156. dev_priv->cpp = init->cpp;
  157. dev_priv->back_offset = init->back_offset;
  158. dev_priv->front_offset = init->front_offset;
  159. dev_priv->current_page = 0;
  160. if (master_priv->sarea_priv)
  161. master_priv->sarea_priv->pf_current_page = 0;
  162. /* Allow hardware batchbuffers unless told otherwise.
  163. */
  164. dev_priv->allow_batchbuffer = 1;
  165. return 0;
  166. }
  167. static int i915_dma_resume(struct drm_device * dev)
  168. {
  169. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  170. struct intel_ring_buffer *ring;
  171. DRM_DEBUG_DRIVER("%s\n", __func__);
  172. ring = &dev_priv->render_ring;
  173. if (ring->map.handle == NULL) {
  174. DRM_ERROR("can not ioremap virtual address for"
  175. " ring buffer\n");
  176. return -ENOMEM;
  177. }
  178. /* Program Hardware Status Page */
  179. if (!ring->status_page.page_addr) {
  180. DRM_ERROR("Can not find hardware status page\n");
  181. return -EINVAL;
  182. }
  183. DRM_DEBUG_DRIVER("hw status page @ %p\n",
  184. ring->status_page.page_addr);
  185. if (ring->status_page.gfx_addr != 0)
  186. ring->setup_status_page(dev, ring);
  187. else
  188. I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  189. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  190. return 0;
  191. }
  192. static int i915_dma_init(struct drm_device *dev, void *data,
  193. struct drm_file *file_priv)
  194. {
  195. drm_i915_init_t *init = data;
  196. int retcode = 0;
  197. switch (init->func) {
  198. case I915_INIT_DMA:
  199. retcode = i915_initialize(dev, init);
  200. break;
  201. case I915_CLEANUP_DMA:
  202. retcode = i915_dma_cleanup(dev);
  203. break;
  204. case I915_RESUME_DMA:
  205. retcode = i915_dma_resume(dev);
  206. break;
  207. default:
  208. retcode = -EINVAL;
  209. break;
  210. }
  211. return retcode;
  212. }
  213. /* Implement basically the same security restrictions as hardware does
  214. * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
  215. *
  216. * Most of the calculations below involve calculating the size of a
  217. * particular instruction. It's important to get the size right as
  218. * that tells us where the next instruction to check is. Any illegal
  219. * instruction detected will be given a size of zero, which is a
  220. * signal to abort the rest of the buffer.
  221. */
  222. static int do_validate_cmd(int cmd)
  223. {
  224. switch (((cmd >> 29) & 0x7)) {
  225. case 0x0:
  226. switch ((cmd >> 23) & 0x3f) {
  227. case 0x0:
  228. return 1; /* MI_NOOP */
  229. case 0x4:
  230. return 1; /* MI_FLUSH */
  231. default:
  232. return 0; /* disallow everything else */
  233. }
  234. break;
  235. case 0x1:
  236. return 0; /* reserved */
  237. case 0x2:
  238. return (cmd & 0xff) + 2; /* 2d commands */
  239. case 0x3:
  240. if (((cmd >> 24) & 0x1f) <= 0x18)
  241. return 1;
  242. switch ((cmd >> 24) & 0x1f) {
  243. case 0x1c:
  244. return 1;
  245. case 0x1d:
  246. switch ((cmd >> 16) & 0xff) {
  247. case 0x3:
  248. return (cmd & 0x1f) + 2;
  249. case 0x4:
  250. return (cmd & 0xf) + 2;
  251. default:
  252. return (cmd & 0xffff) + 2;
  253. }
  254. case 0x1e:
  255. if (cmd & (1 << 23))
  256. return (cmd & 0xffff) + 1;
  257. else
  258. return 1;
  259. case 0x1f:
  260. if ((cmd & (1 << 23)) == 0) /* inline vertices */
  261. return (cmd & 0x1ffff) + 2;
  262. else if (cmd & (1 << 17)) /* indirect random */
  263. if ((cmd & 0xffff) == 0)
  264. return 0; /* unknown length, too hard */
  265. else
  266. return (((cmd & 0xffff) + 1) / 2) + 1;
  267. else
  268. return 2; /* indirect sequential */
  269. default:
  270. return 0;
  271. }
  272. default:
  273. return 0;
  274. }
  275. return 0;
  276. }
  277. static int validate_cmd(int cmd)
  278. {
  279. int ret = do_validate_cmd(cmd);
  280. /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
  281. return ret;
  282. }
  283. static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
  284. {
  285. drm_i915_private_t *dev_priv = dev->dev_private;
  286. int i;
  287. if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
  288. return -EINVAL;
  289. BEGIN_LP_RING((dwords+1)&~1);
  290. for (i = 0; i < dwords;) {
  291. int cmd, sz;
  292. cmd = buffer[i];
  293. if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
  294. return -EINVAL;
  295. OUT_RING(cmd);
  296. while (++i, --sz) {
  297. OUT_RING(buffer[i]);
  298. }
  299. }
  300. if (dwords & 1)
  301. OUT_RING(0);
  302. ADVANCE_LP_RING();
  303. return 0;
  304. }
  305. int
  306. i915_emit_box(struct drm_device *dev,
  307. struct drm_clip_rect *boxes,
  308. int i, int DR1, int DR4)
  309. {
  310. struct drm_clip_rect box = boxes[i];
  311. if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
  312. DRM_ERROR("Bad box %d,%d..%d,%d\n",
  313. box.x1, box.y1, box.x2, box.y2);
  314. return -EINVAL;
  315. }
  316. if (IS_I965G(dev)) {
  317. BEGIN_LP_RING(4);
  318. OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
  319. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  320. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  321. OUT_RING(DR4);
  322. ADVANCE_LP_RING();
  323. } else {
  324. BEGIN_LP_RING(6);
  325. OUT_RING(GFX_OP_DRAWRECT_INFO);
  326. OUT_RING(DR1);
  327. OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
  328. OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
  329. OUT_RING(DR4);
  330. OUT_RING(0);
  331. ADVANCE_LP_RING();
  332. }
  333. return 0;
  334. }
  335. /* XXX: Emitting the counter should really be moved to part of the IRQ
  336. * emit. For now, do it in both places:
  337. */
  338. static void i915_emit_breadcrumb(struct drm_device *dev)
  339. {
  340. drm_i915_private_t *dev_priv = dev->dev_private;
  341. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  342. dev_priv->counter++;
  343. if (dev_priv->counter > 0x7FFFFFFFUL)
  344. dev_priv->counter = 0;
  345. if (master_priv->sarea_priv)
  346. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  347. BEGIN_LP_RING(4);
  348. OUT_RING(MI_STORE_DWORD_INDEX);
  349. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  350. OUT_RING(dev_priv->counter);
  351. OUT_RING(0);
  352. ADVANCE_LP_RING();
  353. }
  354. static int i915_dispatch_cmdbuffer(struct drm_device * dev,
  355. drm_i915_cmdbuffer_t *cmd,
  356. struct drm_clip_rect *cliprects,
  357. void *cmdbuf)
  358. {
  359. int nbox = cmd->num_cliprects;
  360. int i = 0, count, ret;
  361. if (cmd->sz & 0x3) {
  362. DRM_ERROR("alignment");
  363. return -EINVAL;
  364. }
  365. i915_kernel_lost_context(dev);
  366. count = nbox ? nbox : 1;
  367. for (i = 0; i < count; i++) {
  368. if (i < nbox) {
  369. ret = i915_emit_box(dev, cliprects, i,
  370. cmd->DR1, cmd->DR4);
  371. if (ret)
  372. return ret;
  373. }
  374. ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
  375. if (ret)
  376. return ret;
  377. }
  378. i915_emit_breadcrumb(dev);
  379. return 0;
  380. }
  381. static int i915_dispatch_batchbuffer(struct drm_device * dev,
  382. drm_i915_batchbuffer_t * batch,
  383. struct drm_clip_rect *cliprects)
  384. {
  385. int nbox = batch->num_cliprects;
  386. int i = 0, count;
  387. if ((batch->start | batch->used) & 0x7) {
  388. DRM_ERROR("alignment");
  389. return -EINVAL;
  390. }
  391. i915_kernel_lost_context(dev);
  392. count = nbox ? nbox : 1;
  393. for (i = 0; i < count; i++) {
  394. if (i < nbox) {
  395. int ret = i915_emit_box(dev, cliprects, i,
  396. batch->DR1, batch->DR4);
  397. if (ret)
  398. return ret;
  399. }
  400. if (!IS_I830(dev) && !IS_845G(dev)) {
  401. BEGIN_LP_RING(2);
  402. if (IS_I965G(dev)) {
  403. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
  404. OUT_RING(batch->start);
  405. } else {
  406. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
  407. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  408. }
  409. ADVANCE_LP_RING();
  410. } else {
  411. BEGIN_LP_RING(4);
  412. OUT_RING(MI_BATCH_BUFFER);
  413. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  414. OUT_RING(batch->start + batch->used - 4);
  415. OUT_RING(0);
  416. ADVANCE_LP_RING();
  417. }
  418. }
  419. i915_emit_breadcrumb(dev);
  420. return 0;
  421. }
  422. static int i915_dispatch_flip(struct drm_device * dev)
  423. {
  424. drm_i915_private_t *dev_priv = dev->dev_private;
  425. struct drm_i915_master_private *master_priv =
  426. dev->primary->master->driver_priv;
  427. if (!master_priv->sarea_priv)
  428. return -EINVAL;
  429. DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
  430. __func__,
  431. dev_priv->current_page,
  432. master_priv->sarea_priv->pf_current_page);
  433. i915_kernel_lost_context(dev);
  434. BEGIN_LP_RING(2);
  435. OUT_RING(MI_FLUSH | MI_READ_FLUSH);
  436. OUT_RING(0);
  437. ADVANCE_LP_RING();
  438. BEGIN_LP_RING(6);
  439. OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
  440. OUT_RING(0);
  441. if (dev_priv->current_page == 0) {
  442. OUT_RING(dev_priv->back_offset);
  443. dev_priv->current_page = 1;
  444. } else {
  445. OUT_RING(dev_priv->front_offset);
  446. dev_priv->current_page = 0;
  447. }
  448. OUT_RING(0);
  449. ADVANCE_LP_RING();
  450. BEGIN_LP_RING(2);
  451. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
  452. OUT_RING(0);
  453. ADVANCE_LP_RING();
  454. master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
  455. BEGIN_LP_RING(4);
  456. OUT_RING(MI_STORE_DWORD_INDEX);
  457. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  458. OUT_RING(dev_priv->counter);
  459. OUT_RING(0);
  460. ADVANCE_LP_RING();
  461. master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  462. return 0;
  463. }
  464. static int i915_quiescent(struct drm_device * dev)
  465. {
  466. drm_i915_private_t *dev_priv = dev->dev_private;
  467. i915_kernel_lost_context(dev);
  468. return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
  469. dev_priv->render_ring.size - 8);
  470. }
  471. static int i915_flush_ioctl(struct drm_device *dev, void *data,
  472. struct drm_file *file_priv)
  473. {
  474. int ret;
  475. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  476. mutex_lock(&dev->struct_mutex);
  477. ret = i915_quiescent(dev);
  478. mutex_unlock(&dev->struct_mutex);
  479. return ret;
  480. }
  481. static int i915_batchbuffer(struct drm_device *dev, void *data,
  482. struct drm_file *file_priv)
  483. {
  484. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  485. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  486. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  487. master_priv->sarea_priv;
  488. drm_i915_batchbuffer_t *batch = data;
  489. int ret;
  490. struct drm_clip_rect *cliprects = NULL;
  491. if (!dev_priv->allow_batchbuffer) {
  492. DRM_ERROR("Batchbuffer ioctl disabled\n");
  493. return -EINVAL;
  494. }
  495. DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
  496. batch->start, batch->used, batch->num_cliprects);
  497. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  498. if (batch->num_cliprects < 0)
  499. return -EINVAL;
  500. if (batch->num_cliprects) {
  501. cliprects = kcalloc(batch->num_cliprects,
  502. sizeof(struct drm_clip_rect),
  503. GFP_KERNEL);
  504. if (cliprects == NULL)
  505. return -ENOMEM;
  506. ret = copy_from_user(cliprects, batch->cliprects,
  507. batch->num_cliprects *
  508. sizeof(struct drm_clip_rect));
  509. if (ret != 0)
  510. goto fail_free;
  511. }
  512. mutex_lock(&dev->struct_mutex);
  513. ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
  514. mutex_unlock(&dev->struct_mutex);
  515. if (sarea_priv)
  516. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  517. fail_free:
  518. kfree(cliprects);
  519. return ret;
  520. }
  521. static int i915_cmdbuffer(struct drm_device *dev, void *data,
  522. struct drm_file *file_priv)
  523. {
  524. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  525. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  526. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  527. master_priv->sarea_priv;
  528. drm_i915_cmdbuffer_t *cmdbuf = data;
  529. struct drm_clip_rect *cliprects = NULL;
  530. void *batch_data;
  531. int ret;
  532. DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
  533. cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
  534. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  535. if (cmdbuf->num_cliprects < 0)
  536. return -EINVAL;
  537. batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
  538. if (batch_data == NULL)
  539. return -ENOMEM;
  540. ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
  541. if (ret != 0)
  542. goto fail_batch_free;
  543. if (cmdbuf->num_cliprects) {
  544. cliprects = kcalloc(cmdbuf->num_cliprects,
  545. sizeof(struct drm_clip_rect), GFP_KERNEL);
  546. if (cliprects == NULL) {
  547. ret = -ENOMEM;
  548. goto fail_batch_free;
  549. }
  550. ret = copy_from_user(cliprects, cmdbuf->cliprects,
  551. cmdbuf->num_cliprects *
  552. sizeof(struct drm_clip_rect));
  553. if (ret != 0)
  554. goto fail_clip_free;
  555. }
  556. mutex_lock(&dev->struct_mutex);
  557. ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
  558. mutex_unlock(&dev->struct_mutex);
  559. if (ret) {
  560. DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
  561. goto fail_clip_free;
  562. }
  563. if (sarea_priv)
  564. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  565. fail_clip_free:
  566. kfree(cliprects);
  567. fail_batch_free:
  568. kfree(batch_data);
  569. return ret;
  570. }
  571. static int i915_flip_bufs(struct drm_device *dev, void *data,
  572. struct drm_file *file_priv)
  573. {
  574. int ret;
  575. DRM_DEBUG_DRIVER("%s\n", __func__);
  576. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  577. mutex_lock(&dev->struct_mutex);
  578. ret = i915_dispatch_flip(dev);
  579. mutex_unlock(&dev->struct_mutex);
  580. return ret;
  581. }
  582. static int i915_getparam(struct drm_device *dev, void *data,
  583. struct drm_file *file_priv)
  584. {
  585. drm_i915_private_t *dev_priv = dev->dev_private;
  586. drm_i915_getparam_t *param = data;
  587. int value;
  588. if (!dev_priv) {
  589. DRM_ERROR("called with no initialization\n");
  590. return -EINVAL;
  591. }
  592. switch (param->param) {
  593. case I915_PARAM_IRQ_ACTIVE:
  594. value = dev->pdev->irq ? 1 : 0;
  595. break;
  596. case I915_PARAM_ALLOW_BATCHBUFFER:
  597. value = dev_priv->allow_batchbuffer ? 1 : 0;
  598. break;
  599. case I915_PARAM_LAST_DISPATCH:
  600. value = READ_BREADCRUMB(dev_priv);
  601. break;
  602. case I915_PARAM_CHIPSET_ID:
  603. value = dev->pci_device;
  604. break;
  605. case I915_PARAM_HAS_GEM:
  606. value = dev_priv->has_gem;
  607. break;
  608. case I915_PARAM_NUM_FENCES_AVAIL:
  609. value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  610. break;
  611. case I915_PARAM_HAS_OVERLAY:
  612. value = dev_priv->overlay ? 1 : 0;
  613. break;
  614. case I915_PARAM_HAS_PAGEFLIPPING:
  615. value = 1;
  616. break;
  617. case I915_PARAM_HAS_EXECBUF2:
  618. /* depends on GEM */
  619. value = dev_priv->has_gem;
  620. break;
  621. case I915_PARAM_HAS_BSD:
  622. value = HAS_BSD(dev);
  623. break;
  624. default:
  625. DRM_DEBUG_DRIVER("Unknown parameter %d\n",
  626. param->param);
  627. return -EINVAL;
  628. }
  629. if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
  630. DRM_ERROR("DRM_COPY_TO_USER failed\n");
  631. return -EFAULT;
  632. }
  633. return 0;
  634. }
  635. static int i915_setparam(struct drm_device *dev, void *data,
  636. struct drm_file *file_priv)
  637. {
  638. drm_i915_private_t *dev_priv = dev->dev_private;
  639. drm_i915_setparam_t *param = data;
  640. if (!dev_priv) {
  641. DRM_ERROR("called with no initialization\n");
  642. return -EINVAL;
  643. }
  644. switch (param->param) {
  645. case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
  646. break;
  647. case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
  648. dev_priv->tex_lru_log_granularity = param->value;
  649. break;
  650. case I915_SETPARAM_ALLOW_BATCHBUFFER:
  651. dev_priv->allow_batchbuffer = param->value;
  652. break;
  653. case I915_SETPARAM_NUM_USED_FENCES:
  654. if (param->value > dev_priv->num_fence_regs ||
  655. param->value < 0)
  656. return -EINVAL;
  657. /* Userspace can use first N regs */
  658. dev_priv->fence_reg_start = param->value;
  659. break;
  660. default:
  661. DRM_DEBUG_DRIVER("unknown parameter %d\n",
  662. param->param);
  663. return -EINVAL;
  664. }
  665. return 0;
  666. }
  667. static int i915_set_status_page(struct drm_device *dev, void *data,
  668. struct drm_file *file_priv)
  669. {
  670. drm_i915_private_t *dev_priv = dev->dev_private;
  671. drm_i915_hws_addr_t *hws = data;
  672. struct intel_ring_buffer *ring = &dev_priv->render_ring;
  673. if (!I915_NEED_GFX_HWS(dev))
  674. return -EINVAL;
  675. if (!dev_priv) {
  676. DRM_ERROR("called with no initialization\n");
  677. return -EINVAL;
  678. }
  679. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  680. WARN(1, "tried to set status page when mode setting active\n");
  681. return 0;
  682. }
  683. DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
  684. ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
  685. dev_priv->hws_map.offset = dev->agp->base + hws->addr;
  686. dev_priv->hws_map.size = 4*1024;
  687. dev_priv->hws_map.type = 0;
  688. dev_priv->hws_map.flags = 0;
  689. dev_priv->hws_map.mtrr = 0;
  690. drm_core_ioremap_wc(&dev_priv->hws_map, dev);
  691. if (dev_priv->hws_map.handle == NULL) {
  692. i915_dma_cleanup(dev);
  693. ring->status_page.gfx_addr = 0;
  694. DRM_ERROR("can not ioremap virtual address for"
  695. " G33 hw status page\n");
  696. return -ENOMEM;
  697. }
  698. ring->status_page.page_addr = dev_priv->hws_map.handle;
  699. memset(ring->status_page.page_addr, 0, PAGE_SIZE);
  700. I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
  701. DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
  702. ring->status_page.gfx_addr);
  703. DRM_DEBUG_DRIVER("load hws at %p\n",
  704. ring->status_page.page_addr);
  705. return 0;
  706. }
  707. static int i915_get_bridge_dev(struct drm_device *dev)
  708. {
  709. struct drm_i915_private *dev_priv = dev->dev_private;
  710. dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  711. if (!dev_priv->bridge_dev) {
  712. DRM_ERROR("bridge device not found\n");
  713. return -1;
  714. }
  715. return 0;
  716. }
  717. #define MCHBAR_I915 0x44
  718. #define MCHBAR_I965 0x48
  719. #define MCHBAR_SIZE (4*4096)
  720. #define DEVEN_REG 0x54
  721. #define DEVEN_MCHBAR_EN (1 << 28)
  722. /* Allocate space for the MCH regs if needed, return nonzero on error */
  723. static int
  724. intel_alloc_mchbar_resource(struct drm_device *dev)
  725. {
  726. drm_i915_private_t *dev_priv = dev->dev_private;
  727. int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  728. u32 temp_lo, temp_hi = 0;
  729. u64 mchbar_addr;
  730. int ret = 0;
  731. if (IS_I965G(dev))
  732. pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
  733. pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
  734. mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
  735. /* If ACPI doesn't have it, assume we need to allocate it ourselves */
  736. #ifdef CONFIG_PNP
  737. if (mchbar_addr &&
  738. pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
  739. ret = 0;
  740. goto out;
  741. }
  742. #endif
  743. /* Get some space for it */
  744. ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
  745. MCHBAR_SIZE, MCHBAR_SIZE,
  746. PCIBIOS_MIN_MEM,
  747. 0, pcibios_align_resource,
  748. dev_priv->bridge_dev);
  749. if (ret) {
  750. DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
  751. dev_priv->mch_res.start = 0;
  752. goto out;
  753. }
  754. if (IS_I965G(dev))
  755. pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
  756. upper_32_bits(dev_priv->mch_res.start));
  757. pci_write_config_dword(dev_priv->bridge_dev, reg,
  758. lower_32_bits(dev_priv->mch_res.start));
  759. out:
  760. return ret;
  761. }
  762. /* Setup MCHBAR if possible, return true if we should disable it again */
  763. static void
  764. intel_setup_mchbar(struct drm_device *dev)
  765. {
  766. drm_i915_private_t *dev_priv = dev->dev_private;
  767. int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  768. u32 temp;
  769. bool enabled;
  770. dev_priv->mchbar_need_disable = false;
  771. if (IS_I915G(dev) || IS_I915GM(dev)) {
  772. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  773. enabled = !!(temp & DEVEN_MCHBAR_EN);
  774. } else {
  775. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  776. enabled = temp & 1;
  777. }
  778. /* If it's already enabled, don't have to do anything */
  779. if (enabled)
  780. return;
  781. if (intel_alloc_mchbar_resource(dev))
  782. return;
  783. dev_priv->mchbar_need_disable = true;
  784. /* Space is allocated or reserved, so enable it. */
  785. if (IS_I915G(dev) || IS_I915GM(dev)) {
  786. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
  787. temp | DEVEN_MCHBAR_EN);
  788. } else {
  789. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  790. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
  791. }
  792. }
  793. static void
  794. intel_teardown_mchbar(struct drm_device *dev)
  795. {
  796. drm_i915_private_t *dev_priv = dev->dev_private;
  797. int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
  798. u32 temp;
  799. if (dev_priv->mchbar_need_disable) {
  800. if (IS_I915G(dev) || IS_I915GM(dev)) {
  801. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  802. temp &= ~DEVEN_MCHBAR_EN;
  803. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
  804. } else {
  805. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  806. temp &= ~1;
  807. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
  808. }
  809. }
  810. if (dev_priv->mch_res.start)
  811. release_resource(&dev_priv->mch_res);
  812. }
  813. /**
  814. * i915_probe_agp - get AGP bootup configuration
  815. * @pdev: PCI device
  816. * @aperture_size: returns AGP aperture configured size
  817. * @preallocated_size: returns size of BIOS preallocated AGP space
  818. *
  819. * Since Intel integrated graphics are UMA, the BIOS has to set aside
  820. * some RAM for the framebuffer at early boot. This code figures out
  821. * how much was set aside so we can use it for our own purposes.
  822. */
  823. static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
  824. uint32_t *preallocated_size,
  825. uint32_t *start)
  826. {
  827. struct drm_i915_private *dev_priv = dev->dev_private;
  828. u16 tmp = 0;
  829. unsigned long overhead;
  830. unsigned long stolen;
  831. /* Get the fb aperture size and "stolen" memory amount. */
  832. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
  833. *aperture_size = 1024 * 1024;
  834. *preallocated_size = 1024 * 1024;
  835. switch (dev->pdev->device) {
  836. case PCI_DEVICE_ID_INTEL_82830_CGC:
  837. case PCI_DEVICE_ID_INTEL_82845G_IG:
  838. case PCI_DEVICE_ID_INTEL_82855GM_IG:
  839. case PCI_DEVICE_ID_INTEL_82865_IG:
  840. if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  841. *aperture_size *= 64;
  842. else
  843. *aperture_size *= 128;
  844. break;
  845. default:
  846. /* 9xx supports large sizes, just look at the length */
  847. *aperture_size = pci_resource_len(dev->pdev, 2);
  848. break;
  849. }
  850. /*
  851. * Some of the preallocated space is taken by the GTT
  852. * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
  853. */
  854. if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
  855. overhead = 4096;
  856. else
  857. overhead = (*aperture_size / 1024) + 4096;
  858. if (IS_GEN6(dev)) {
  859. /* SNB has memory control reg at 0x50.w */
  860. pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
  861. switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
  862. case INTEL_855_GMCH_GMS_DISABLED:
  863. DRM_ERROR("video memory is disabled\n");
  864. return -1;
  865. case SNB_GMCH_GMS_STOLEN_32M:
  866. stolen = 32 * 1024 * 1024;
  867. break;
  868. case SNB_GMCH_GMS_STOLEN_64M:
  869. stolen = 64 * 1024 * 1024;
  870. break;
  871. case SNB_GMCH_GMS_STOLEN_96M:
  872. stolen = 96 * 1024 * 1024;
  873. break;
  874. case SNB_GMCH_GMS_STOLEN_128M:
  875. stolen = 128 * 1024 * 1024;
  876. break;
  877. case SNB_GMCH_GMS_STOLEN_160M:
  878. stolen = 160 * 1024 * 1024;
  879. break;
  880. case SNB_GMCH_GMS_STOLEN_192M:
  881. stolen = 192 * 1024 * 1024;
  882. break;
  883. case SNB_GMCH_GMS_STOLEN_224M:
  884. stolen = 224 * 1024 * 1024;
  885. break;
  886. case SNB_GMCH_GMS_STOLEN_256M:
  887. stolen = 256 * 1024 * 1024;
  888. break;
  889. case SNB_GMCH_GMS_STOLEN_288M:
  890. stolen = 288 * 1024 * 1024;
  891. break;
  892. case SNB_GMCH_GMS_STOLEN_320M:
  893. stolen = 320 * 1024 * 1024;
  894. break;
  895. case SNB_GMCH_GMS_STOLEN_352M:
  896. stolen = 352 * 1024 * 1024;
  897. break;
  898. case SNB_GMCH_GMS_STOLEN_384M:
  899. stolen = 384 * 1024 * 1024;
  900. break;
  901. case SNB_GMCH_GMS_STOLEN_416M:
  902. stolen = 416 * 1024 * 1024;
  903. break;
  904. case SNB_GMCH_GMS_STOLEN_448M:
  905. stolen = 448 * 1024 * 1024;
  906. break;
  907. case SNB_GMCH_GMS_STOLEN_480M:
  908. stolen = 480 * 1024 * 1024;
  909. break;
  910. case SNB_GMCH_GMS_STOLEN_512M:
  911. stolen = 512 * 1024 * 1024;
  912. break;
  913. default:
  914. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  915. tmp & SNB_GMCH_GMS_STOLEN_MASK);
  916. return -1;
  917. }
  918. } else {
  919. switch (tmp & INTEL_GMCH_GMS_MASK) {
  920. case INTEL_855_GMCH_GMS_DISABLED:
  921. DRM_ERROR("video memory is disabled\n");
  922. return -1;
  923. case INTEL_855_GMCH_GMS_STOLEN_1M:
  924. stolen = 1 * 1024 * 1024;
  925. break;
  926. case INTEL_855_GMCH_GMS_STOLEN_4M:
  927. stolen = 4 * 1024 * 1024;
  928. break;
  929. case INTEL_855_GMCH_GMS_STOLEN_8M:
  930. stolen = 8 * 1024 * 1024;
  931. break;
  932. case INTEL_855_GMCH_GMS_STOLEN_16M:
  933. stolen = 16 * 1024 * 1024;
  934. break;
  935. case INTEL_855_GMCH_GMS_STOLEN_32M:
  936. stolen = 32 * 1024 * 1024;
  937. break;
  938. case INTEL_915G_GMCH_GMS_STOLEN_48M:
  939. stolen = 48 * 1024 * 1024;
  940. break;
  941. case INTEL_915G_GMCH_GMS_STOLEN_64M:
  942. stolen = 64 * 1024 * 1024;
  943. break;
  944. case INTEL_GMCH_GMS_STOLEN_128M:
  945. stolen = 128 * 1024 * 1024;
  946. break;
  947. case INTEL_GMCH_GMS_STOLEN_256M:
  948. stolen = 256 * 1024 * 1024;
  949. break;
  950. case INTEL_GMCH_GMS_STOLEN_96M:
  951. stolen = 96 * 1024 * 1024;
  952. break;
  953. case INTEL_GMCH_GMS_STOLEN_160M:
  954. stolen = 160 * 1024 * 1024;
  955. break;
  956. case INTEL_GMCH_GMS_STOLEN_224M:
  957. stolen = 224 * 1024 * 1024;
  958. break;
  959. case INTEL_GMCH_GMS_STOLEN_352M:
  960. stolen = 352 * 1024 * 1024;
  961. break;
  962. default:
  963. DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  964. tmp & INTEL_GMCH_GMS_MASK);
  965. return -1;
  966. }
  967. }
  968. *preallocated_size = stolen - overhead;
  969. *start = overhead;
  970. return 0;
  971. }
  972. #define PTE_ADDRESS_MASK 0xfffff000
  973. #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
  974. #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
  975. #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
  976. #define PTE_MAPPING_TYPE_CACHED (3 << 1)
  977. #define PTE_MAPPING_TYPE_MASK (3 << 1)
  978. #define PTE_VALID (1 << 0)
  979. /**
  980. * i915_gtt_to_phys - take a GTT address and turn it into a physical one
  981. * @dev: drm device
  982. * @gtt_addr: address to translate
  983. *
  984. * Some chip functions require allocations from stolen space but need the
  985. * physical address of the memory in question. We use this routine
  986. * to get a physical address suitable for register programming from a given
  987. * GTT address.
  988. */
  989. static unsigned long i915_gtt_to_phys(struct drm_device *dev,
  990. unsigned long gtt_addr)
  991. {
  992. unsigned long *gtt;
  993. unsigned long entry, phys;
  994. int gtt_bar = IS_I9XX(dev) ? 0 : 1;
  995. int gtt_offset, gtt_size;
  996. if (IS_I965G(dev)) {
  997. if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
  998. gtt_offset = 2*1024*1024;
  999. gtt_size = 2*1024*1024;
  1000. } else {
  1001. gtt_offset = 512*1024;
  1002. gtt_size = 512*1024;
  1003. }
  1004. } else {
  1005. gtt_bar = 3;
  1006. gtt_offset = 0;
  1007. gtt_size = pci_resource_len(dev->pdev, gtt_bar);
  1008. }
  1009. gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
  1010. gtt_size);
  1011. if (!gtt) {
  1012. DRM_ERROR("ioremap of GTT failed\n");
  1013. return 0;
  1014. }
  1015. entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
  1016. DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
  1017. /* Mask out these reserved bits on this hardware. */
  1018. if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
  1019. IS_I945G(dev) || IS_I945GM(dev)) {
  1020. entry &= ~PTE_ADDRESS_MASK_HIGH;
  1021. }
  1022. /* If it's not a mapping type we know, then bail. */
  1023. if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
  1024. (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
  1025. iounmap(gtt);
  1026. return 0;
  1027. }
  1028. if (!(entry & PTE_VALID)) {
  1029. DRM_ERROR("bad GTT entry in stolen space\n");
  1030. iounmap(gtt);
  1031. return 0;
  1032. }
  1033. iounmap(gtt);
  1034. phys =(entry & PTE_ADDRESS_MASK) |
  1035. ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
  1036. DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
  1037. return phys;
  1038. }
  1039. static void i915_warn_stolen(struct drm_device *dev)
  1040. {
  1041. DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
  1042. DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
  1043. }
  1044. static void i915_setup_compression(struct drm_device *dev, int size)
  1045. {
  1046. struct drm_i915_private *dev_priv = dev->dev_private;
  1047. struct drm_mm_node *compressed_fb, *compressed_llb;
  1048. unsigned long cfb_base;
  1049. unsigned long ll_base = 0;
  1050. /* Leave 1M for line length buffer & misc. */
  1051. compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
  1052. if (!compressed_fb) {
  1053. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1054. i915_warn_stolen(dev);
  1055. return;
  1056. }
  1057. compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
  1058. if (!compressed_fb) {
  1059. i915_warn_stolen(dev);
  1060. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1061. return;
  1062. }
  1063. cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
  1064. if (!cfb_base) {
  1065. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  1066. drm_mm_put_block(compressed_fb);
  1067. }
  1068. if (!IS_GM45(dev)) {
  1069. compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
  1070. 4096, 0);
  1071. if (!compressed_llb) {
  1072. i915_warn_stolen(dev);
  1073. return;
  1074. }
  1075. compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
  1076. if (!compressed_llb) {
  1077. i915_warn_stolen(dev);
  1078. return;
  1079. }
  1080. ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
  1081. if (!ll_base) {
  1082. DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
  1083. drm_mm_put_block(compressed_fb);
  1084. drm_mm_put_block(compressed_llb);
  1085. }
  1086. }
  1087. dev_priv->cfb_size = size;
  1088. intel_disable_fbc(dev);
  1089. dev_priv->compressed_fb = compressed_fb;
  1090. if (IS_GM45(dev)) {
  1091. I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
  1092. } else {
  1093. I915_WRITE(FBC_CFB_BASE, cfb_base);
  1094. I915_WRITE(FBC_LL_BASE, ll_base);
  1095. dev_priv->compressed_llb = compressed_llb;
  1096. }
  1097. DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
  1098. ll_base, size >> 20);
  1099. }
  1100. static void i915_cleanup_compression(struct drm_device *dev)
  1101. {
  1102. struct drm_i915_private *dev_priv = dev->dev_private;
  1103. drm_mm_put_block(dev_priv->compressed_fb);
  1104. if (!IS_GM45(dev))
  1105. drm_mm_put_block(dev_priv->compressed_llb);
  1106. }
  1107. /* true = enable decode, false = disable decoder */
  1108. static unsigned int i915_vga_set_decode(void *cookie, bool state)
  1109. {
  1110. struct drm_device *dev = cookie;
  1111. intel_modeset_vga_set_state(dev, state);
  1112. if (state)
  1113. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  1114. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1115. else
  1116. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1117. }
  1118. static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  1119. {
  1120. struct drm_device *dev = pci_get_drvdata(pdev);
  1121. pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
  1122. if (state == VGA_SWITCHEROO_ON) {
  1123. printk(KERN_INFO "i915: switched on\n");
  1124. /* i915 resume handler doesn't set to D0 */
  1125. pci_set_power_state(dev->pdev, PCI_D0);
  1126. i915_resume(dev);
  1127. drm_kms_helper_poll_enable(dev);
  1128. } else {
  1129. printk(KERN_ERR "i915: switched off\n");
  1130. drm_kms_helper_poll_disable(dev);
  1131. i915_suspend(dev, pmm);
  1132. }
  1133. }
  1134. static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
  1135. {
  1136. struct drm_device *dev = pci_get_drvdata(pdev);
  1137. bool can_switch;
  1138. spin_lock(&dev->count_lock);
  1139. can_switch = (dev->open_count == 0);
  1140. spin_unlock(&dev->count_lock);
  1141. return can_switch;
  1142. }
  1143. static int i915_load_modeset_init(struct drm_device *dev,
  1144. unsigned long prealloc_start,
  1145. unsigned long prealloc_size,
  1146. unsigned long agp_size)
  1147. {
  1148. struct drm_i915_private *dev_priv = dev->dev_private;
  1149. int fb_bar = IS_I9XX(dev) ? 2 : 0;
  1150. int ret = 0;
  1151. dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
  1152. 0xff000000;
  1153. /* Basic memrange allocator for stolen space (aka vram) */
  1154. drm_mm_init(&dev_priv->vram, 0, prealloc_size);
  1155. DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
  1156. /* We're off and running w/KMS */
  1157. dev_priv->mm.suspended = 0;
  1158. /* Let GEM Manage from end of prealloc space to end of aperture.
  1159. *
  1160. * However, leave one page at the end still bound to the scratch page.
  1161. * There are a number of places where the hardware apparently
  1162. * prefetches past the end of the object, and we've seen multiple
  1163. * hangs with the GPU head pointer stuck in a batchbuffer bound
  1164. * at the last page of the aperture. One page should be enough to
  1165. * keep any prefetching inside of the aperture.
  1166. */
  1167. i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
  1168. mutex_lock(&dev->struct_mutex);
  1169. ret = i915_gem_init_ringbuffer(dev);
  1170. mutex_unlock(&dev->struct_mutex);
  1171. if (ret)
  1172. goto out;
  1173. /* Try to set up FBC with a reasonable compressed buffer size */
  1174. if (I915_HAS_FBC(dev) && i915_powersave) {
  1175. int cfb_size;
  1176. /* Try to get an 8M buffer... */
  1177. if (prealloc_size > (9*1024*1024))
  1178. cfb_size = 8*1024*1024;
  1179. else /* fall back to 7/8 of the stolen space */
  1180. cfb_size = prealloc_size * 7 / 8;
  1181. i915_setup_compression(dev, cfb_size);
  1182. }
  1183. /* Allow hardware batchbuffers unless told otherwise.
  1184. */
  1185. dev_priv->allow_batchbuffer = 1;
  1186. ret = intel_init_bios(dev);
  1187. if (ret)
  1188. DRM_INFO("failed to find VBIOS tables\n");
  1189. /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  1190. ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
  1191. if (ret)
  1192. goto cleanup_ringbuffer;
  1193. ret = vga_switcheroo_register_client(dev->pdev,
  1194. i915_switcheroo_set_state,
  1195. i915_switcheroo_can_switch);
  1196. if (ret)
  1197. goto cleanup_vga_client;
  1198. intel_modeset_init(dev);
  1199. ret = drm_irq_install(dev);
  1200. if (ret)
  1201. goto cleanup_vga_switcheroo;
  1202. /* Always safe in the mode setting case. */
  1203. /* FIXME: do pre/post-mode set stuff in core KMS code */
  1204. dev->vblank_disable_allowed = 1;
  1205. /*
  1206. * Initialize the hardware status page IRQ location.
  1207. */
  1208. I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
  1209. ret = intel_fbdev_init(dev);
  1210. if (ret)
  1211. goto cleanup_irq;
  1212. drm_kms_helper_poll_init(dev);
  1213. return 0;
  1214. cleanup_irq:
  1215. drm_irq_uninstall(dev);
  1216. cleanup_vga_switcheroo:
  1217. vga_switcheroo_unregister_client(dev->pdev);
  1218. cleanup_vga_client:
  1219. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1220. cleanup_ringbuffer:
  1221. mutex_lock(&dev->struct_mutex);
  1222. i915_gem_cleanup_ringbuffer(dev);
  1223. mutex_unlock(&dev->struct_mutex);
  1224. out:
  1225. return ret;
  1226. }
  1227. int i915_master_create(struct drm_device *dev, struct drm_master *master)
  1228. {
  1229. struct drm_i915_master_private *master_priv;
  1230. master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
  1231. if (!master_priv)
  1232. return -ENOMEM;
  1233. master->driver_priv = master_priv;
  1234. return 0;
  1235. }
  1236. void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
  1237. {
  1238. struct drm_i915_master_private *master_priv = master->driver_priv;
  1239. if (!master_priv)
  1240. return;
  1241. kfree(master_priv);
  1242. master->driver_priv = NULL;
  1243. }
  1244. static void i915_pineview_get_mem_freq(struct drm_device *dev)
  1245. {
  1246. drm_i915_private_t *dev_priv = dev->dev_private;
  1247. u32 tmp;
  1248. tmp = I915_READ(CLKCFG);
  1249. switch (tmp & CLKCFG_FSB_MASK) {
  1250. case CLKCFG_FSB_533:
  1251. dev_priv->fsb_freq = 533; /* 133*4 */
  1252. break;
  1253. case CLKCFG_FSB_800:
  1254. dev_priv->fsb_freq = 800; /* 200*4 */
  1255. break;
  1256. case CLKCFG_FSB_667:
  1257. dev_priv->fsb_freq = 667; /* 167*4 */
  1258. break;
  1259. case CLKCFG_FSB_400:
  1260. dev_priv->fsb_freq = 400; /* 100*4 */
  1261. break;
  1262. }
  1263. switch (tmp & CLKCFG_MEM_MASK) {
  1264. case CLKCFG_MEM_533:
  1265. dev_priv->mem_freq = 533;
  1266. break;
  1267. case CLKCFG_MEM_667:
  1268. dev_priv->mem_freq = 667;
  1269. break;
  1270. case CLKCFG_MEM_800:
  1271. dev_priv->mem_freq = 800;
  1272. break;
  1273. }
  1274. /* detect pineview DDR3 setting */
  1275. tmp = I915_READ(CSHRDDR3CTL);
  1276. dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
  1277. }
  1278. static void i915_ironlake_get_mem_freq(struct drm_device *dev)
  1279. {
  1280. drm_i915_private_t *dev_priv = dev->dev_private;
  1281. u16 ddrpll, csipll;
  1282. ddrpll = I915_READ16(DDRMPLL1);
  1283. csipll = I915_READ16(CSIPLL0);
  1284. switch (ddrpll & 0xff) {
  1285. case 0xc:
  1286. dev_priv->mem_freq = 800;
  1287. break;
  1288. case 0x10:
  1289. dev_priv->mem_freq = 1066;
  1290. break;
  1291. case 0x14:
  1292. dev_priv->mem_freq = 1333;
  1293. break;
  1294. case 0x18:
  1295. dev_priv->mem_freq = 1600;
  1296. break;
  1297. default:
  1298. DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
  1299. ddrpll & 0xff);
  1300. dev_priv->mem_freq = 0;
  1301. break;
  1302. }
  1303. dev_priv->r_t = dev_priv->mem_freq;
  1304. switch (csipll & 0x3ff) {
  1305. case 0x00c:
  1306. dev_priv->fsb_freq = 3200;
  1307. break;
  1308. case 0x00e:
  1309. dev_priv->fsb_freq = 3733;
  1310. break;
  1311. case 0x010:
  1312. dev_priv->fsb_freq = 4266;
  1313. break;
  1314. case 0x012:
  1315. dev_priv->fsb_freq = 4800;
  1316. break;
  1317. case 0x014:
  1318. dev_priv->fsb_freq = 5333;
  1319. break;
  1320. case 0x016:
  1321. dev_priv->fsb_freq = 5866;
  1322. break;
  1323. case 0x018:
  1324. dev_priv->fsb_freq = 6400;
  1325. break;
  1326. default:
  1327. DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
  1328. csipll & 0x3ff);
  1329. dev_priv->fsb_freq = 0;
  1330. break;
  1331. }
  1332. if (dev_priv->fsb_freq == 3200) {
  1333. dev_priv->c_m = 0;
  1334. } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
  1335. dev_priv->c_m = 1;
  1336. } else {
  1337. dev_priv->c_m = 2;
  1338. }
  1339. }
  1340. struct v_table {
  1341. u8 vid;
  1342. unsigned long vd; /* in .1 mil */
  1343. unsigned long vm; /* in .1 mil */
  1344. u8 pvid;
  1345. };
  1346. static struct v_table v_table[] = {
  1347. { 0, 16125, 15000, 0x7f, },
  1348. { 1, 16000, 14875, 0x7e, },
  1349. { 2, 15875, 14750, 0x7d, },
  1350. { 3, 15750, 14625, 0x7c, },
  1351. { 4, 15625, 14500, 0x7b, },
  1352. { 5, 15500, 14375, 0x7a, },
  1353. { 6, 15375, 14250, 0x79, },
  1354. { 7, 15250, 14125, 0x78, },
  1355. { 8, 15125, 14000, 0x77, },
  1356. { 9, 15000, 13875, 0x76, },
  1357. { 10, 14875, 13750, 0x75, },
  1358. { 11, 14750, 13625, 0x74, },
  1359. { 12, 14625, 13500, 0x73, },
  1360. { 13, 14500, 13375, 0x72, },
  1361. { 14, 14375, 13250, 0x71, },
  1362. { 15, 14250, 13125, 0x70, },
  1363. { 16, 14125, 13000, 0x6f, },
  1364. { 17, 14000, 12875, 0x6e, },
  1365. { 18, 13875, 12750, 0x6d, },
  1366. { 19, 13750, 12625, 0x6c, },
  1367. { 20, 13625, 12500, 0x6b, },
  1368. { 21, 13500, 12375, 0x6a, },
  1369. { 22, 13375, 12250, 0x69, },
  1370. { 23, 13250, 12125, 0x68, },
  1371. { 24, 13125, 12000, 0x67, },
  1372. { 25, 13000, 11875, 0x66, },
  1373. { 26, 12875, 11750, 0x65, },
  1374. { 27, 12750, 11625, 0x64, },
  1375. { 28, 12625, 11500, 0x63, },
  1376. { 29, 12500, 11375, 0x62, },
  1377. { 30, 12375, 11250, 0x61, },
  1378. { 31, 12250, 11125, 0x60, },
  1379. { 32, 12125, 11000, 0x5f, },
  1380. { 33, 12000, 10875, 0x5e, },
  1381. { 34, 11875, 10750, 0x5d, },
  1382. { 35, 11750, 10625, 0x5c, },
  1383. { 36, 11625, 10500, 0x5b, },
  1384. { 37, 11500, 10375, 0x5a, },
  1385. { 38, 11375, 10250, 0x59, },
  1386. { 39, 11250, 10125, 0x58, },
  1387. { 40, 11125, 10000, 0x57, },
  1388. { 41, 11000, 9875, 0x56, },
  1389. { 42, 10875, 9750, 0x55, },
  1390. { 43, 10750, 9625, 0x54, },
  1391. { 44, 10625, 9500, 0x53, },
  1392. { 45, 10500, 9375, 0x52, },
  1393. { 46, 10375, 9250, 0x51, },
  1394. { 47, 10250, 9125, 0x50, },
  1395. { 48, 10125, 9000, 0x4f, },
  1396. { 49, 10000, 8875, 0x4e, },
  1397. { 50, 9875, 8750, 0x4d, },
  1398. { 51, 9750, 8625, 0x4c, },
  1399. { 52, 9625, 8500, 0x4b, },
  1400. { 53, 9500, 8375, 0x4a, },
  1401. { 54, 9375, 8250, 0x49, },
  1402. { 55, 9250, 8125, 0x48, },
  1403. { 56, 9125, 8000, 0x47, },
  1404. { 57, 9000, 7875, 0x46, },
  1405. { 58, 8875, 7750, 0x45, },
  1406. { 59, 8750, 7625, 0x44, },
  1407. { 60, 8625, 7500, 0x43, },
  1408. { 61, 8500, 7375, 0x42, },
  1409. { 62, 8375, 7250, 0x41, },
  1410. { 63, 8250, 7125, 0x40, },
  1411. { 64, 8125, 7000, 0x3f, },
  1412. { 65, 8000, 6875, 0x3e, },
  1413. { 66, 7875, 6750, 0x3d, },
  1414. { 67, 7750, 6625, 0x3c, },
  1415. { 68, 7625, 6500, 0x3b, },
  1416. { 69, 7500, 6375, 0x3a, },
  1417. { 70, 7375, 6250, 0x39, },
  1418. { 71, 7250, 6125, 0x38, },
  1419. { 72, 7125, 6000, 0x37, },
  1420. { 73, 7000, 5875, 0x36, },
  1421. { 74, 6875, 5750, 0x35, },
  1422. { 75, 6750, 5625, 0x34, },
  1423. { 76, 6625, 5500, 0x33, },
  1424. { 77, 6500, 5375, 0x32, },
  1425. { 78, 6375, 5250, 0x31, },
  1426. { 79, 6250, 5125, 0x30, },
  1427. { 80, 6125, 5000, 0x2f, },
  1428. { 81, 6000, 4875, 0x2e, },
  1429. { 82, 5875, 4750, 0x2d, },
  1430. { 83, 5750, 4625, 0x2c, },
  1431. { 84, 5625, 4500, 0x2b, },
  1432. { 85, 5500, 4375, 0x2a, },
  1433. { 86, 5375, 4250, 0x29, },
  1434. { 87, 5250, 4125, 0x28, },
  1435. { 88, 5125, 4000, 0x27, },
  1436. { 89, 5000, 3875, 0x26, },
  1437. { 90, 4875, 3750, 0x25, },
  1438. { 91, 4750, 3625, 0x24, },
  1439. { 92, 4625, 3500, 0x23, },
  1440. { 93, 4500, 3375, 0x22, },
  1441. { 94, 4375, 3250, 0x21, },
  1442. { 95, 4250, 3125, 0x20, },
  1443. { 96, 4125, 3000, 0x1f, },
  1444. { 97, 4125, 3000, 0x1e, },
  1445. { 98, 4125, 3000, 0x1d, },
  1446. { 99, 4125, 3000, 0x1c, },
  1447. { 100, 4125, 3000, 0x1b, },
  1448. { 101, 4125, 3000, 0x1a, },
  1449. { 102, 4125, 3000, 0x19, },
  1450. { 103, 4125, 3000, 0x18, },
  1451. { 104, 4125, 3000, 0x17, },
  1452. { 105, 4125, 3000, 0x16, },
  1453. { 106, 4125, 3000, 0x15, },
  1454. { 107, 4125, 3000, 0x14, },
  1455. { 108, 4125, 3000, 0x13, },
  1456. { 109, 4125, 3000, 0x12, },
  1457. { 110, 4125, 3000, 0x11, },
  1458. { 111, 4125, 3000, 0x10, },
  1459. { 112, 4125, 3000, 0x0f, },
  1460. { 113, 4125, 3000, 0x0e, },
  1461. { 114, 4125, 3000, 0x0d, },
  1462. { 115, 4125, 3000, 0x0c, },
  1463. { 116, 4125, 3000, 0x0b, },
  1464. { 117, 4125, 3000, 0x0a, },
  1465. { 118, 4125, 3000, 0x09, },
  1466. { 119, 4125, 3000, 0x08, },
  1467. { 120, 1125, 0, 0x07, },
  1468. { 121, 1000, 0, 0x06, },
  1469. { 122, 875, 0, 0x05, },
  1470. { 123, 750, 0, 0x04, },
  1471. { 124, 625, 0, 0x03, },
  1472. { 125, 500, 0, 0x02, },
  1473. { 126, 375, 0, 0x01, },
  1474. { 127, 0, 0, 0x00, },
  1475. };
  1476. struct cparams {
  1477. int i;
  1478. int t;
  1479. int m;
  1480. int c;
  1481. };
  1482. static struct cparams cparams[] = {
  1483. { 1, 1333, 301, 28664 },
  1484. { 1, 1066, 294, 24460 },
  1485. { 1, 800, 294, 25192 },
  1486. { 0, 1333, 276, 27605 },
  1487. { 0, 1066, 276, 27605 },
  1488. { 0, 800, 231, 23784 },
  1489. };
  1490. unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
  1491. {
  1492. u64 total_count, diff, ret;
  1493. u32 count1, count2, count3, m = 0, c = 0;
  1494. unsigned long now = jiffies_to_msecs(jiffies), diff1;
  1495. int i;
  1496. diff1 = now - dev_priv->last_time1;
  1497. count1 = I915_READ(DMIEC);
  1498. count2 = I915_READ(DDREC);
  1499. count3 = I915_READ(CSIEC);
  1500. total_count = count1 + count2 + count3;
  1501. /* FIXME: handle per-counter overflow */
  1502. if (total_count < dev_priv->last_count1) {
  1503. diff = ~0UL - dev_priv->last_count1;
  1504. diff += total_count;
  1505. } else {
  1506. diff = total_count - dev_priv->last_count1;
  1507. }
  1508. for (i = 0; i < ARRAY_SIZE(cparams); i++) {
  1509. if (cparams[i].i == dev_priv->c_m &&
  1510. cparams[i].t == dev_priv->r_t) {
  1511. m = cparams[i].m;
  1512. c = cparams[i].c;
  1513. break;
  1514. }
  1515. }
  1516. div_u64(diff, diff1);
  1517. ret = ((m * diff) + c);
  1518. div_u64(ret, 10);
  1519. dev_priv->last_count1 = total_count;
  1520. dev_priv->last_time1 = now;
  1521. return ret;
  1522. }
  1523. unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
  1524. {
  1525. unsigned long m, x, b;
  1526. u32 tsfs;
  1527. tsfs = I915_READ(TSFS);
  1528. m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
  1529. x = I915_READ8(TR1);
  1530. b = tsfs & TSFS_INTR_MASK;
  1531. return ((m * x) / 127) - b;
  1532. }
  1533. static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
  1534. {
  1535. unsigned long val = 0;
  1536. int i;
  1537. for (i = 0; i < ARRAY_SIZE(v_table); i++) {
  1538. if (v_table[i].pvid == pxvid) {
  1539. if (IS_MOBILE(dev_priv->dev))
  1540. val = v_table[i].vm;
  1541. else
  1542. val = v_table[i].vd;
  1543. }
  1544. }
  1545. return val;
  1546. }
  1547. void i915_update_gfx_val(struct drm_i915_private *dev_priv)
  1548. {
  1549. struct timespec now, diff1;
  1550. u64 diff;
  1551. unsigned long diffms;
  1552. u32 count;
  1553. getrawmonotonic(&now);
  1554. diff1 = timespec_sub(now, dev_priv->last_time2);
  1555. /* Don't divide by 0 */
  1556. diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
  1557. if (!diffms)
  1558. return;
  1559. count = I915_READ(GFXEC);
  1560. if (count < dev_priv->last_count2) {
  1561. diff = ~0UL - dev_priv->last_count2;
  1562. diff += count;
  1563. } else {
  1564. diff = count - dev_priv->last_count2;
  1565. }
  1566. dev_priv->last_count2 = count;
  1567. dev_priv->last_time2 = now;
  1568. /* More magic constants... */
  1569. diff = diff * 1181;
  1570. div_u64(diff, diffms * 10);
  1571. dev_priv->gfx_power = diff;
  1572. }
  1573. unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
  1574. {
  1575. unsigned long t, corr, state1, corr2, state2;
  1576. u32 pxvid, ext_v;
  1577. pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
  1578. pxvid = (pxvid >> 24) & 0x7f;
  1579. ext_v = pvid_to_extvid(dev_priv, pxvid);
  1580. state1 = ext_v;
  1581. t = i915_mch_val(dev_priv);
  1582. /* Revel in the empirically derived constants */
  1583. /* Correction factor in 1/100000 units */
  1584. if (t > 80)
  1585. corr = ((t * 2349) + 135940);
  1586. else if (t >= 50)
  1587. corr = ((t * 964) + 29317);
  1588. else /* < 50 */
  1589. corr = ((t * 301) + 1004);
  1590. corr = corr * ((150142 * state1) / 10000 - 78642);
  1591. corr /= 100000;
  1592. corr2 = (corr * dev_priv->corr);
  1593. state2 = (corr2 * state1) / 10000;
  1594. state2 /= 100; /* convert to mW */
  1595. i915_update_gfx_val(dev_priv);
  1596. return dev_priv->gfx_power + state2;
  1597. }
  1598. /* Global for IPS driver to get at the current i915 device */
  1599. static struct drm_i915_private *i915_mch_dev;
  1600. /*
  1601. * Lock protecting IPS related data structures
  1602. * - i915_mch_dev
  1603. * - dev_priv->max_delay
  1604. * - dev_priv->min_delay
  1605. * - dev_priv->fmax
  1606. * - dev_priv->gpu_busy
  1607. */
  1608. DEFINE_SPINLOCK(mchdev_lock);
  1609. /**
  1610. * i915_read_mch_val - return value for IPS use
  1611. *
  1612. * Calculate and return a value for the IPS driver to use when deciding whether
  1613. * we have thermal and power headroom to increase CPU or GPU power budget.
  1614. */
  1615. unsigned long i915_read_mch_val(void)
  1616. {
  1617. struct drm_i915_private *dev_priv;
  1618. unsigned long chipset_val, graphics_val, ret = 0;
  1619. spin_lock(&mchdev_lock);
  1620. if (!i915_mch_dev)
  1621. goto out_unlock;
  1622. dev_priv = i915_mch_dev;
  1623. chipset_val = i915_chipset_val(dev_priv);
  1624. graphics_val = i915_gfx_val(dev_priv);
  1625. ret = chipset_val + graphics_val;
  1626. out_unlock:
  1627. spin_unlock(&mchdev_lock);
  1628. return ret;
  1629. }
  1630. EXPORT_SYMBOL_GPL(i915_read_mch_val);
  1631. /**
  1632. * i915_gpu_raise - raise GPU frequency limit
  1633. *
  1634. * Raise the limit; IPS indicates we have thermal headroom.
  1635. */
  1636. bool i915_gpu_raise(void)
  1637. {
  1638. struct drm_i915_private *dev_priv;
  1639. bool ret = true;
  1640. spin_lock(&mchdev_lock);
  1641. if (!i915_mch_dev) {
  1642. ret = false;
  1643. goto out_unlock;
  1644. }
  1645. dev_priv = i915_mch_dev;
  1646. if (dev_priv->max_delay > dev_priv->fmax)
  1647. dev_priv->max_delay--;
  1648. out_unlock:
  1649. spin_unlock(&mchdev_lock);
  1650. return ret;
  1651. }
  1652. EXPORT_SYMBOL_GPL(i915_gpu_raise);
  1653. /**
  1654. * i915_gpu_lower - lower GPU frequency limit
  1655. *
  1656. * IPS indicates we're close to a thermal limit, so throttle back the GPU
  1657. * frequency maximum.
  1658. */
  1659. bool i915_gpu_lower(void)
  1660. {
  1661. struct drm_i915_private *dev_priv;
  1662. bool ret = true;
  1663. spin_lock(&mchdev_lock);
  1664. if (!i915_mch_dev) {
  1665. ret = false;
  1666. goto out_unlock;
  1667. }
  1668. dev_priv = i915_mch_dev;
  1669. if (dev_priv->max_delay < dev_priv->min_delay)
  1670. dev_priv->max_delay++;
  1671. out_unlock:
  1672. spin_unlock(&mchdev_lock);
  1673. return ret;
  1674. }
  1675. EXPORT_SYMBOL_GPL(i915_gpu_lower);
  1676. /**
  1677. * i915_gpu_busy - indicate GPU business to IPS
  1678. *
  1679. * Tell the IPS driver whether or not the GPU is busy.
  1680. */
  1681. bool i915_gpu_busy(void)
  1682. {
  1683. struct drm_i915_private *dev_priv;
  1684. bool ret = false;
  1685. spin_lock(&mchdev_lock);
  1686. if (!i915_mch_dev)
  1687. goto out_unlock;
  1688. dev_priv = i915_mch_dev;
  1689. ret = dev_priv->busy;
  1690. out_unlock:
  1691. spin_unlock(&mchdev_lock);
  1692. return ret;
  1693. }
  1694. EXPORT_SYMBOL_GPL(i915_gpu_busy);
  1695. /**
  1696. * i915_gpu_turbo_disable - disable graphics turbo
  1697. *
  1698. * Disable graphics turbo by resetting the max frequency and setting the
  1699. * current frequency to the default.
  1700. */
  1701. bool i915_gpu_turbo_disable(void)
  1702. {
  1703. struct drm_i915_private *dev_priv;
  1704. bool ret = true;
  1705. spin_lock(&mchdev_lock);
  1706. if (!i915_mch_dev) {
  1707. ret = false;
  1708. goto out_unlock;
  1709. }
  1710. dev_priv = i915_mch_dev;
  1711. dev_priv->max_delay = dev_priv->fstart;
  1712. if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
  1713. ret = false;
  1714. out_unlock:
  1715. spin_unlock(&mchdev_lock);
  1716. return ret;
  1717. }
  1718. EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
  1719. /**
  1720. * i915_driver_load - setup chip and create an initial config
  1721. * @dev: DRM device
  1722. * @flags: startup flags
  1723. *
  1724. * The driver load routine has to do several things:
  1725. * - drive output discovery via intel_modeset_init()
  1726. * - initialize the memory manager
  1727. * - allocate initial config memory
  1728. * - setup the DRM framebuffer with the allocated memory
  1729. */
  1730. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  1731. {
  1732. struct drm_i915_private *dev_priv;
  1733. resource_size_t base, size;
  1734. int ret = 0, mmio_bar;
  1735. uint32_t agp_size, prealloc_size, prealloc_start;
  1736. /* i915 has 4 more counters */
  1737. dev->counters += 4;
  1738. dev->types[6] = _DRM_STAT_IRQ;
  1739. dev->types[7] = _DRM_STAT_PRIMARY;
  1740. dev->types[8] = _DRM_STAT_SECONDARY;
  1741. dev->types[9] = _DRM_STAT_DMA;
  1742. dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
  1743. if (dev_priv == NULL)
  1744. return -ENOMEM;
  1745. dev->dev_private = (void *)dev_priv;
  1746. dev_priv->dev = dev;
  1747. dev_priv->info = (struct intel_device_info *) flags;
  1748. /* Add register map (needed for suspend/resume) */
  1749. mmio_bar = IS_I9XX(dev) ? 0 : 1;
  1750. base = drm_get_resource_start(dev, mmio_bar);
  1751. size = drm_get_resource_len(dev, mmio_bar);
  1752. if (i915_get_bridge_dev(dev)) {
  1753. ret = -EIO;
  1754. goto free_priv;
  1755. }
  1756. dev_priv->regs = ioremap(base, size);
  1757. if (!dev_priv->regs) {
  1758. DRM_ERROR("failed to map registers\n");
  1759. ret = -EIO;
  1760. goto put_bridge;
  1761. }
  1762. dev_priv->mm.gtt_mapping =
  1763. io_mapping_create_wc(dev->agp->base,
  1764. dev->agp->agp_info.aper_size * 1024*1024);
  1765. if (dev_priv->mm.gtt_mapping == NULL) {
  1766. ret = -EIO;
  1767. goto out_rmmap;
  1768. }
  1769. /* Set up a WC MTRR for non-PAT systems. This is more common than
  1770. * one would think, because the kernel disables PAT on first
  1771. * generation Core chips because WC PAT gets overridden by a UC
  1772. * MTRR if present. Even if a UC MTRR isn't present.
  1773. */
  1774. dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
  1775. dev->agp->agp_info.aper_size *
  1776. 1024 * 1024,
  1777. MTRR_TYPE_WRCOMB, 1);
  1778. if (dev_priv->mm.gtt_mtrr < 0) {
  1779. DRM_INFO("MTRR allocation failed. Graphics "
  1780. "performance may suffer.\n");
  1781. }
  1782. ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
  1783. if (ret)
  1784. goto out_iomapfree;
  1785. dev_priv->wq = create_singlethread_workqueue("i915");
  1786. if (dev_priv->wq == NULL) {
  1787. DRM_ERROR("Failed to create our workqueue.\n");
  1788. ret = -ENOMEM;
  1789. goto out_iomapfree;
  1790. }
  1791. /* enable GEM by default */
  1792. dev_priv->has_gem = 1;
  1793. if (prealloc_size > agp_size * 3 / 4) {
  1794. DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
  1795. "memory stolen.\n",
  1796. prealloc_size / 1024, agp_size / 1024);
  1797. DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
  1798. "updating the BIOS to fix).\n");
  1799. dev_priv->has_gem = 0;
  1800. }
  1801. if (dev_priv->has_gem == 0 &&
  1802. drm_core_check_feature(dev, DRIVER_MODESET)) {
  1803. DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
  1804. ret = -ENODEV;
  1805. goto out_iomapfree;
  1806. }
  1807. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  1808. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  1809. if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
  1810. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  1811. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  1812. }
  1813. /* Try to make sure MCHBAR is enabled before poking at it */
  1814. intel_setup_mchbar(dev);
  1815. i915_gem_load(dev);
  1816. /* Init HWS */
  1817. if (!I915_NEED_GFX_HWS(dev)) {
  1818. ret = i915_init_phys_hws(dev);
  1819. if (ret != 0)
  1820. goto out_workqueue_free;
  1821. }
  1822. if (IS_PINEVIEW(dev))
  1823. i915_pineview_get_mem_freq(dev);
  1824. else if (IS_IRONLAKE(dev))
  1825. i915_ironlake_get_mem_freq(dev);
  1826. /* On the 945G/GM, the chipset reports the MSI capability on the
  1827. * integrated graphics even though the support isn't actually there
  1828. * according to the published specs. It doesn't appear to function
  1829. * correctly in testing on 945G.
  1830. * This may be a side effect of MSI having been made available for PEG
  1831. * and the registers being closely associated.
  1832. *
  1833. * According to chipset errata, on the 965GM, MSI interrupts may
  1834. * be lost or delayed, but we use them anyways to avoid
  1835. * stuck interrupts on some machines.
  1836. */
  1837. if (!IS_I945G(dev) && !IS_I945GM(dev))
  1838. pci_enable_msi(dev->pdev);
  1839. spin_lock_init(&dev_priv->user_irq_lock);
  1840. spin_lock_init(&dev_priv->error_lock);
  1841. dev_priv->trace_irq_seqno = 0;
  1842. ret = drm_vblank_init(dev, I915_NUM_PIPE);
  1843. if (ret) {
  1844. (void) i915_driver_unload(dev);
  1845. return ret;
  1846. }
  1847. /* Start out suspended */
  1848. dev_priv->mm.suspended = 1;
  1849. intel_detect_pch(dev);
  1850. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1851. ret = i915_load_modeset_init(dev, prealloc_start,
  1852. prealloc_size, agp_size);
  1853. if (ret < 0) {
  1854. DRM_ERROR("failed to init modeset\n");
  1855. goto out_workqueue_free;
  1856. }
  1857. }
  1858. /* Must be done after probing outputs */
  1859. intel_opregion_init(dev, 0);
  1860. setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
  1861. (unsigned long) dev);
  1862. spin_lock(&mchdev_lock);
  1863. i915_mch_dev = dev_priv;
  1864. dev_priv->mchdev_lock = &mchdev_lock;
  1865. spin_unlock(&mchdev_lock);
  1866. return 0;
  1867. out_workqueue_free:
  1868. destroy_workqueue(dev_priv->wq);
  1869. out_iomapfree:
  1870. io_mapping_free(dev_priv->mm.gtt_mapping);
  1871. out_rmmap:
  1872. iounmap(dev_priv->regs);
  1873. put_bridge:
  1874. pci_dev_put(dev_priv->bridge_dev);
  1875. free_priv:
  1876. kfree(dev_priv);
  1877. return ret;
  1878. }
  1879. int i915_driver_unload(struct drm_device *dev)
  1880. {
  1881. struct drm_i915_private *dev_priv = dev->dev_private;
  1882. i915_destroy_error_state(dev);
  1883. spin_lock(&mchdev_lock);
  1884. i915_mch_dev = NULL;
  1885. spin_unlock(&mchdev_lock);
  1886. destroy_workqueue(dev_priv->wq);
  1887. del_timer_sync(&dev_priv->hangcheck_timer);
  1888. io_mapping_free(dev_priv->mm.gtt_mapping);
  1889. if (dev_priv->mm.gtt_mtrr >= 0) {
  1890. mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
  1891. dev->agp->agp_info.aper_size * 1024 * 1024);
  1892. dev_priv->mm.gtt_mtrr = -1;
  1893. }
  1894. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1895. intel_modeset_cleanup(dev);
  1896. /*
  1897. * free the memory space allocated for the child device
  1898. * config parsed from VBT
  1899. */
  1900. if (dev_priv->child_dev && dev_priv->child_dev_num) {
  1901. kfree(dev_priv->child_dev);
  1902. dev_priv->child_dev = NULL;
  1903. dev_priv->child_dev_num = 0;
  1904. }
  1905. drm_irq_uninstall(dev);
  1906. vga_switcheroo_unregister_client(dev->pdev);
  1907. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1908. }
  1909. if (dev->pdev->msi_enabled)
  1910. pci_disable_msi(dev->pdev);
  1911. if (dev_priv->regs != NULL)
  1912. iounmap(dev_priv->regs);
  1913. intel_opregion_free(dev, 0);
  1914. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1915. i915_gem_free_all_phys_object(dev);
  1916. mutex_lock(&dev->struct_mutex);
  1917. i915_gem_cleanup_ringbuffer(dev);
  1918. mutex_unlock(&dev->struct_mutex);
  1919. if (I915_HAS_FBC(dev) && i915_powersave)
  1920. i915_cleanup_compression(dev);
  1921. drm_mm_takedown(&dev_priv->vram);
  1922. i915_gem_lastclose(dev);
  1923. intel_cleanup_overlay(dev);
  1924. }
  1925. intel_teardown_mchbar(dev);
  1926. pci_dev_put(dev_priv->bridge_dev);
  1927. kfree(dev->dev_private);
  1928. return 0;
  1929. }
  1930. int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
  1931. {
  1932. struct drm_i915_file_private *i915_file_priv;
  1933. DRM_DEBUG_DRIVER("\n");
  1934. i915_file_priv = (struct drm_i915_file_private *)
  1935. kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
  1936. if (!i915_file_priv)
  1937. return -ENOMEM;
  1938. file_priv->driver_priv = i915_file_priv;
  1939. INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
  1940. return 0;
  1941. }
  1942. /**
  1943. * i915_driver_lastclose - clean up after all DRM clients have exited
  1944. * @dev: DRM device
  1945. *
  1946. * Take care of cleaning up after all DRM clients have exited. In the
  1947. * mode setting case, we want to restore the kernel's initial mode (just
  1948. * in case the last client left us in a bad state).
  1949. *
  1950. * Additionally, in the non-mode setting case, we'll tear down the AGP
  1951. * and DMA structures, since the kernel won't be using them, and clea
  1952. * up any GEM state.
  1953. */
  1954. void i915_driver_lastclose(struct drm_device * dev)
  1955. {
  1956. drm_i915_private_t *dev_priv = dev->dev_private;
  1957. if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
  1958. drm_fb_helper_restore();
  1959. vga_switcheroo_process_delayed_switch();
  1960. return;
  1961. }
  1962. i915_gem_lastclose(dev);
  1963. if (dev_priv->agp_heap)
  1964. i915_mem_takedown(&(dev_priv->agp_heap));
  1965. i915_dma_cleanup(dev);
  1966. }
  1967. void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1968. {
  1969. drm_i915_private_t *dev_priv = dev->dev_private;
  1970. i915_gem_release(dev, file_priv);
  1971. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  1972. i915_mem_release(dev, file_priv, dev_priv->agp_heap);
  1973. }
  1974. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
  1975. {
  1976. struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
  1977. kfree(i915_file_priv);
  1978. }
  1979. struct drm_ioctl_desc i915_ioctls[] = {
  1980. DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1981. DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
  1982. DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
  1983. DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
  1984. DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
  1985. DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
  1986. DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
  1987. DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1988. DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
  1989. DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
  1990. DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1991. DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
  1992. DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1993. DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
  1994. DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
  1995. DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
  1996. DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1997. DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1998. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
  1999. DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
  2000. DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2001. DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2002. DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
  2003. DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
  2004. DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2005. DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  2006. DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
  2007. DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
  2008. DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
  2009. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
  2010. DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
  2011. DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
  2012. DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
  2013. DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
  2014. DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
  2015. DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
  2016. DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
  2017. DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
  2018. DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  2019. DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  2020. };
  2021. int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
  2022. /**
  2023. * Determine if the device really is AGP or not.
  2024. *
  2025. * All Intel graphics chipsets are treated as AGP, even if they are really
  2026. * PCI-e.
  2027. *
  2028. * \param dev The device to be tested.
  2029. *
  2030. * \returns
  2031. * A value of 1 is always retured to indictate every i9x5 is AGP.
  2032. */
  2033. int i915_driver_device_is_agp(struct drm_device * dev)
  2034. {
  2035. return 1;
  2036. }