sun4m_smp.c 6.2 KB

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  1. /*
  2. * sun4m SMP support.
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #include <linux/clockchips.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/profile.h>
  9. #include <linux/delay.h>
  10. #include <linux/sched.h>
  11. #include <linux/cpu.h>
  12. #include <asm/cacheflush.h>
  13. #include <asm/switch_to.h>
  14. #include <asm/tlbflush.h>
  15. #include <asm/timer.h>
  16. #include <asm/oplib.h>
  17. #include "irq.h"
  18. #include "kernel.h"
  19. #define IRQ_IPI_SINGLE 12
  20. #define IRQ_IPI_MASK 13
  21. #define IRQ_IPI_RESCHED 14
  22. #define IRQ_CROSS_CALL 15
  23. static inline unsigned long
  24. swap_ulong(volatile unsigned long *ptr, unsigned long val)
  25. {
  26. __asm__ __volatile__("swap [%1], %0\n\t" :
  27. "=&r" (val), "=&r" (ptr) :
  28. "0" (val), "1" (ptr));
  29. return val;
  30. }
  31. void __cpuinit smp4m_callin(void)
  32. {
  33. int cpuid = hard_smp_processor_id();
  34. local_ops->cache_all();
  35. local_ops->tlb_all();
  36. notify_cpu_starting(cpuid);
  37. register_percpu_ce(cpuid);
  38. calibrate_delay();
  39. smp_store_cpu_info(cpuid);
  40. local_ops->cache_all();
  41. local_ops->tlb_all();
  42. /*
  43. * Unblock the master CPU _only_ when the scheduler state
  44. * of all secondary CPUs will be up-to-date, so after
  45. * the SMP initialization the master will be just allowed
  46. * to call the scheduler code.
  47. */
  48. /* Allow master to continue. */
  49. swap_ulong(&cpu_callin_map[cpuid], 1);
  50. /* XXX: What's up with all the flushes? */
  51. local_ops->cache_all();
  52. local_ops->tlb_all();
  53. /* Fix idle thread fields. */
  54. __asm__ __volatile__("ld [%0], %%g6\n\t"
  55. : : "r" (&current_set[cpuid])
  56. : "memory" /* paranoid */);
  57. /* Attach to the address space of init_task. */
  58. atomic_inc(&init_mm.mm_count);
  59. current->active_mm = &init_mm;
  60. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  61. mb();
  62. local_irq_enable();
  63. set_cpu_online(cpuid, true);
  64. }
  65. /*
  66. * Cycle through the processors asking the PROM to start each one.
  67. */
  68. void __init smp4m_boot_cpus(void)
  69. {
  70. sun4m_unmask_profile_irq();
  71. local_ops->cache_all();
  72. }
  73. int __cpuinit smp4m_boot_one_cpu(int i, struct task_struct *idle)
  74. {
  75. unsigned long *entry = &sun4m_cpu_startup;
  76. int timeout;
  77. int cpu_node;
  78. cpu_find_by_mid(i, &cpu_node);
  79. current_set[i] = task_thread_info(idle);
  80. /* See trampoline.S for details... */
  81. entry += ((i - 1) * 3);
  82. /*
  83. * Initialize the contexts table
  84. * Since the call to prom_startcpu() trashes the structure,
  85. * we need to re-initialize it for each cpu
  86. */
  87. smp_penguin_ctable.which_io = 0;
  88. smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
  89. smp_penguin_ctable.reg_size = 0;
  90. /* whirrr, whirrr, whirrrrrrrrr... */
  91. printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
  92. local_ops->cache_all();
  93. prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
  94. /* wheee... it's going... */
  95. for (timeout = 0; timeout < 10000; timeout++) {
  96. if (cpu_callin_map[i])
  97. break;
  98. udelay(200);
  99. }
  100. if (!(cpu_callin_map[i])) {
  101. printk(KERN_ERR "Processor %d is stuck.\n", i);
  102. return -ENODEV;
  103. }
  104. local_ops->cache_all();
  105. return 0;
  106. }
  107. void __init smp4m_smp_done(void)
  108. {
  109. int i, first;
  110. int *prev;
  111. /* setup cpu list for irq rotation */
  112. first = 0;
  113. prev = &first;
  114. for_each_online_cpu(i) {
  115. *prev = i;
  116. prev = &cpu_data(i).next;
  117. }
  118. *prev = first;
  119. local_ops->cache_all();
  120. /* Ok, they are spinning and ready to go. */
  121. }
  122. static void sun4m_send_ipi(int cpu, int level)
  123. {
  124. sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
  125. }
  126. static void sun4m_ipi_resched(int cpu)
  127. {
  128. sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
  129. }
  130. static void sun4m_ipi_single(int cpu)
  131. {
  132. sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
  133. }
  134. static void sun4m_ipi_mask_one(int cpu)
  135. {
  136. sun4m_send_ipi(cpu, IRQ_IPI_MASK);
  137. }
  138. static struct smp_funcall {
  139. smpfunc_t func;
  140. unsigned long arg1;
  141. unsigned long arg2;
  142. unsigned long arg3;
  143. unsigned long arg4;
  144. unsigned long arg5;
  145. unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */
  146. unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
  147. } ccall_info;
  148. static DEFINE_SPINLOCK(cross_call_lock);
  149. /* Cross calls must be serialized, at least currently. */
  150. static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
  151. unsigned long arg2, unsigned long arg3,
  152. unsigned long arg4)
  153. {
  154. register int ncpus = SUN4M_NCPUS;
  155. unsigned long flags;
  156. spin_lock_irqsave(&cross_call_lock, flags);
  157. /* Init function glue. */
  158. ccall_info.func = func;
  159. ccall_info.arg1 = arg1;
  160. ccall_info.arg2 = arg2;
  161. ccall_info.arg3 = arg3;
  162. ccall_info.arg4 = arg4;
  163. ccall_info.arg5 = 0;
  164. /* Init receive/complete mapping, plus fire the IPI's off. */
  165. {
  166. register int i;
  167. cpumask_clear_cpu(smp_processor_id(), &mask);
  168. cpumask_and(&mask, cpu_online_mask, &mask);
  169. for (i = 0; i < ncpus; i++) {
  170. if (cpumask_test_cpu(i, &mask)) {
  171. ccall_info.processors_in[i] = 0;
  172. ccall_info.processors_out[i] = 0;
  173. sun4m_send_ipi(i, IRQ_CROSS_CALL);
  174. } else {
  175. ccall_info.processors_in[i] = 1;
  176. ccall_info.processors_out[i] = 1;
  177. }
  178. }
  179. }
  180. {
  181. register int i;
  182. i = 0;
  183. do {
  184. if (!cpumask_test_cpu(i, &mask))
  185. continue;
  186. while (!ccall_info.processors_in[i])
  187. barrier();
  188. } while (++i < ncpus);
  189. i = 0;
  190. do {
  191. if (!cpumask_test_cpu(i, &mask))
  192. continue;
  193. while (!ccall_info.processors_out[i])
  194. barrier();
  195. } while (++i < ncpus);
  196. }
  197. spin_unlock_irqrestore(&cross_call_lock, flags);
  198. }
  199. /* Running cross calls. */
  200. void smp4m_cross_call_irq(void)
  201. {
  202. int i = smp_processor_id();
  203. ccall_info.processors_in[i] = 1;
  204. ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
  205. ccall_info.arg4, ccall_info.arg5);
  206. ccall_info.processors_out[i] = 1;
  207. }
  208. void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
  209. {
  210. struct pt_regs *old_regs;
  211. struct clock_event_device *ce;
  212. int cpu = smp_processor_id();
  213. old_regs = set_irq_regs(regs);
  214. ce = &per_cpu(sparc32_clockevent, cpu);
  215. if (ce->mode & CLOCK_EVT_MODE_PERIODIC)
  216. sun4m_clear_profile_irq(cpu);
  217. else
  218. sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
  219. irq_enter();
  220. ce->event_handler(ce);
  221. irq_exit();
  222. set_irq_regs(old_regs);
  223. }
  224. static const struct sparc32_ipi_ops sun4m_ipi_ops = {
  225. .cross_call = sun4m_cross_call,
  226. .resched = sun4m_ipi_resched,
  227. .single = sun4m_ipi_single,
  228. .mask_one = sun4m_ipi_mask_one,
  229. };
  230. void __init sun4m_init_smp(void)
  231. {
  232. sparc32_ipi_ops = &sun4m_ipi_ops;
  233. }