nv04_software.c 3.6 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. #include <core/ramht.h>
  27. #include "nouveau_fence.h"
  28. #include "nouveau_software.h"
  29. #include "nouveau_hw.h"
  30. struct nv04_software_priv {
  31. struct nouveau_software_priv base;
  32. };
  33. struct nv04_software_chan {
  34. struct nouveau_software_chan base;
  35. };
  36. static int
  37. mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  38. {
  39. struct nv04_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
  40. return pch->base.flip(pch->base.flip_data);
  41. }
  42. static int
  43. nv04_software_context_new(struct nouveau_channel *chan, int engine)
  44. {
  45. struct nv04_software_chan *pch;
  46. pch = kzalloc(sizeof(*pch), GFP_KERNEL);
  47. if (!pch)
  48. return -ENOMEM;
  49. nouveau_software_context_new(chan, &pch->base);
  50. chan->engctx[engine] = pch;
  51. return 0;
  52. }
  53. static void
  54. nv04_software_context_del(struct nouveau_channel *chan, int engine)
  55. {
  56. struct nv04_software_chan *pch = chan->engctx[engine];
  57. chan->engctx[engine] = NULL;
  58. kfree(pch);
  59. }
  60. static int
  61. nv04_software_object_new(struct nouveau_channel *chan, int engine,
  62. u32 handle, u16 class)
  63. {
  64. struct drm_device *dev = chan->dev;
  65. struct nouveau_gpuobj *obj = NULL;
  66. int ret;
  67. ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
  68. if (ret)
  69. return ret;
  70. obj->engine = 0;
  71. obj->class = class;
  72. ret = nouveau_ramht_insert(chan, handle, obj);
  73. nouveau_gpuobj_ref(NULL, &obj);
  74. return ret;
  75. }
  76. static int
  77. nv04_software_init(struct drm_device *dev, int engine)
  78. {
  79. return 0;
  80. }
  81. static int
  82. nv04_software_fini(struct drm_device *dev, int engine, bool suspend)
  83. {
  84. return 0;
  85. }
  86. static void
  87. nv04_software_destroy(struct drm_device *dev, int engine)
  88. {
  89. struct nv04_software_priv *psw = nv_engine(dev, engine);
  90. NVOBJ_ENGINE_DEL(dev, SW);
  91. kfree(psw);
  92. }
  93. int
  94. nv04_software_create(struct drm_device *dev)
  95. {
  96. struct drm_nouveau_private *dev_priv = dev->dev_private;
  97. struct nv04_software_priv *psw;
  98. psw = kzalloc(sizeof(*psw), GFP_KERNEL);
  99. if (!psw)
  100. return -ENOMEM;
  101. psw->base.base.destroy = nv04_software_destroy;
  102. psw->base.base.init = nv04_software_init;
  103. psw->base.base.fini = nv04_software_fini;
  104. psw->base.base.context_new = nv04_software_context_new;
  105. psw->base.base.context_del = nv04_software_context_del;
  106. psw->base.base.object_new = nv04_software_object_new;
  107. nouveau_software_create(&psw->base);
  108. NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
  109. if (dev_priv->card_type <= NV_04) {
  110. NVOBJ_CLASS(dev, 0x006e, SW);
  111. NVOBJ_MTHD (dev, 0x006e, 0x0150, nv04_fence_mthd);
  112. NVOBJ_MTHD (dev, 0x006e, 0x0500, mthd_flip);
  113. } else {
  114. NVOBJ_CLASS(dev, 0x016e, SW);
  115. NVOBJ_MTHD (dev, 0x016e, 0x0500, mthd_flip);
  116. }
  117. return 0;
  118. }