vmwgfx_kms.c 54 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. struct vmw_clip_rect {
  31. int x1, x2, y1, y2;
  32. };
  33. /**
  34. * Clip @num_rects number of @rects against @clip storing the
  35. * results in @out_rects and the number of passed rects in @out_num.
  36. */
  37. void vmw_clip_cliprects(struct drm_clip_rect *rects,
  38. int num_rects,
  39. struct vmw_clip_rect clip,
  40. SVGASignedRect *out_rects,
  41. int *out_num)
  42. {
  43. int i, k;
  44. for (i = 0, k = 0; i < num_rects; i++) {
  45. int x1 = max_t(int, clip.x1, rects[i].x1);
  46. int y1 = max_t(int, clip.y1, rects[i].y1);
  47. int x2 = min_t(int, clip.x2, rects[i].x2);
  48. int y2 = min_t(int, clip.y2, rects[i].y2);
  49. if (x1 >= x2)
  50. continue;
  51. if (y1 >= y2)
  52. continue;
  53. out_rects[k].left = x1;
  54. out_rects[k].top = y1;
  55. out_rects[k].right = x2;
  56. out_rects[k].bottom = y2;
  57. k++;
  58. }
  59. *out_num = k;
  60. }
  61. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  62. {
  63. if (du->cursor_surface)
  64. vmw_surface_unreference(&du->cursor_surface);
  65. if (du->cursor_dmabuf)
  66. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  67. drm_crtc_cleanup(&du->crtc);
  68. drm_encoder_cleanup(&du->encoder);
  69. drm_connector_cleanup(&du->connector);
  70. }
  71. /*
  72. * Display Unit Cursor functions
  73. */
  74. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  75. u32 *image, u32 width, u32 height,
  76. u32 hotspotX, u32 hotspotY)
  77. {
  78. struct {
  79. u32 cmd;
  80. SVGAFifoCmdDefineAlphaCursor cursor;
  81. } *cmd;
  82. u32 image_size = width * height * 4;
  83. u32 cmd_size = sizeof(*cmd) + image_size;
  84. if (!image)
  85. return -EINVAL;
  86. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  87. if (unlikely(cmd == NULL)) {
  88. DRM_ERROR("Fifo reserve failed.\n");
  89. return -ENOMEM;
  90. }
  91. memset(cmd, 0, sizeof(*cmd));
  92. memcpy(&cmd[1], image, image_size);
  93. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  94. cmd->cursor.id = cpu_to_le32(0);
  95. cmd->cursor.width = cpu_to_le32(width);
  96. cmd->cursor.height = cpu_to_le32(height);
  97. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  98. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  99. vmw_fifo_commit(dev_priv, cmd_size);
  100. return 0;
  101. }
  102. int vmw_cursor_update_dmabuf(struct vmw_private *dev_priv,
  103. struct vmw_dma_buffer *dmabuf,
  104. u32 width, u32 height,
  105. u32 hotspotX, u32 hotspotY)
  106. {
  107. struct ttm_bo_kmap_obj map;
  108. unsigned long kmap_offset;
  109. unsigned long kmap_num;
  110. void *virtual;
  111. bool dummy;
  112. int ret;
  113. kmap_offset = 0;
  114. kmap_num = (width*height*4 + PAGE_SIZE - 1) >> PAGE_SHIFT;
  115. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  116. if (unlikely(ret != 0)) {
  117. DRM_ERROR("reserve failed\n");
  118. return -EINVAL;
  119. }
  120. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  121. if (unlikely(ret != 0))
  122. goto err_unreserve;
  123. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  124. ret = vmw_cursor_update_image(dev_priv, virtual, width, height,
  125. hotspotX, hotspotY);
  126. ttm_bo_kunmap(&map);
  127. err_unreserve:
  128. ttm_bo_unreserve(&dmabuf->base);
  129. return ret;
  130. }
  131. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  132. bool show, int x, int y)
  133. {
  134. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  135. uint32_t count;
  136. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  137. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  138. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  139. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  140. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  141. }
  142. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  143. uint32_t handle, uint32_t width, uint32_t height)
  144. {
  145. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  146. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  147. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  148. struct vmw_surface *surface = NULL;
  149. struct vmw_dma_buffer *dmabuf = NULL;
  150. int ret;
  151. /* A lot of the code assumes this */
  152. if (handle && (width != 64 || height != 64))
  153. return -EINVAL;
  154. if (handle) {
  155. ret = vmw_user_lookup_handle(dev_priv, tfile,
  156. handle, &surface, &dmabuf);
  157. if (ret) {
  158. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  159. return -EINVAL;
  160. }
  161. }
  162. /* need to do this before taking down old image */
  163. if (surface && !surface->snooper.image) {
  164. DRM_ERROR("surface not suitable for cursor\n");
  165. vmw_surface_unreference(&surface);
  166. return -EINVAL;
  167. }
  168. /* takedown old cursor */
  169. if (du->cursor_surface) {
  170. du->cursor_surface->snooper.crtc = NULL;
  171. vmw_surface_unreference(&du->cursor_surface);
  172. }
  173. if (du->cursor_dmabuf)
  174. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  175. /* setup new image */
  176. if (surface) {
  177. /* vmw_user_surface_lookup takes one reference */
  178. du->cursor_surface = surface;
  179. du->cursor_surface->snooper.crtc = crtc;
  180. du->cursor_age = du->cursor_surface->snooper.age;
  181. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  182. 64, 64, du->hotspot_x, du->hotspot_y);
  183. } else if (dmabuf) {
  184. /* vmw_user_surface_lookup takes one reference */
  185. du->cursor_dmabuf = dmabuf;
  186. ret = vmw_cursor_update_dmabuf(dev_priv, dmabuf, width, height,
  187. du->hotspot_x, du->hotspot_y);
  188. } else {
  189. vmw_cursor_update_position(dev_priv, false, 0, 0);
  190. return 0;
  191. }
  192. vmw_cursor_update_position(dev_priv, true,
  193. du->cursor_x + du->hotspot_x,
  194. du->cursor_y + du->hotspot_y);
  195. return 0;
  196. }
  197. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  198. {
  199. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  200. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  201. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  202. du->cursor_x = x + crtc->x;
  203. du->cursor_y = y + crtc->y;
  204. vmw_cursor_update_position(dev_priv, shown,
  205. du->cursor_x + du->hotspot_x,
  206. du->cursor_y + du->hotspot_y);
  207. return 0;
  208. }
  209. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  210. struct ttm_object_file *tfile,
  211. struct ttm_buffer_object *bo,
  212. SVGA3dCmdHeader *header)
  213. {
  214. struct ttm_bo_kmap_obj map;
  215. unsigned long kmap_offset;
  216. unsigned long kmap_num;
  217. SVGA3dCopyBox *box;
  218. unsigned box_count;
  219. void *virtual;
  220. bool dummy;
  221. struct vmw_dma_cmd {
  222. SVGA3dCmdHeader header;
  223. SVGA3dCmdSurfaceDMA dma;
  224. } *cmd;
  225. int i, ret;
  226. cmd = container_of(header, struct vmw_dma_cmd, header);
  227. /* No snooper installed */
  228. if (!srf->snooper.image)
  229. return;
  230. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  231. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  232. return;
  233. }
  234. if (cmd->header.size < 64) {
  235. DRM_ERROR("at least one full copy box must be given\n");
  236. return;
  237. }
  238. box = (SVGA3dCopyBox *)&cmd[1];
  239. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  240. sizeof(SVGA3dCopyBox);
  241. if (cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  242. box->x != 0 || box->y != 0 || box->z != 0 ||
  243. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  244. box->d != 1 || box_count != 1) {
  245. /* TODO handle none page aligned offsets */
  246. /* TODO handle more dst & src != 0 */
  247. /* TODO handle more then one copy */
  248. DRM_ERROR("Cant snoop dma request for cursor!\n");
  249. DRM_ERROR("(%u, %u, %u) (%u, %u, %u) (%ux%ux%u) %u %u\n",
  250. box->srcx, box->srcy, box->srcz,
  251. box->x, box->y, box->z,
  252. box->w, box->h, box->d, box_count,
  253. cmd->dma.guest.ptr.offset);
  254. return;
  255. }
  256. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  257. kmap_num = (64*64*4) >> PAGE_SHIFT;
  258. ret = ttm_bo_reserve(bo, true, false, false, 0);
  259. if (unlikely(ret != 0)) {
  260. DRM_ERROR("reserve failed\n");
  261. return;
  262. }
  263. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  264. if (unlikely(ret != 0))
  265. goto err_unreserve;
  266. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  267. if (box->w == 64 && cmd->dma.guest.pitch == 64*4) {
  268. memcpy(srf->snooper.image, virtual, 64*64*4);
  269. } else {
  270. /* Image is unsigned pointer. */
  271. for (i = 0; i < box->h; i++)
  272. memcpy(srf->snooper.image + i * 64,
  273. virtual + i * cmd->dma.guest.pitch,
  274. box->w * 4);
  275. }
  276. srf->snooper.age++;
  277. /* we can't call this function from this function since execbuf has
  278. * reserved fifo space.
  279. *
  280. * if (srf->snooper.crtc)
  281. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  282. * srf->snooper.image, 64, 64,
  283. * du->hotspot_x, du->hotspot_y);
  284. */
  285. ttm_bo_kunmap(&map);
  286. err_unreserve:
  287. ttm_bo_unreserve(bo);
  288. }
  289. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  290. {
  291. struct drm_device *dev = dev_priv->dev;
  292. struct vmw_display_unit *du;
  293. struct drm_crtc *crtc;
  294. mutex_lock(&dev->mode_config.mutex);
  295. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  296. du = vmw_crtc_to_du(crtc);
  297. if (!du->cursor_surface ||
  298. du->cursor_age == du->cursor_surface->snooper.age)
  299. continue;
  300. du->cursor_age = du->cursor_surface->snooper.age;
  301. vmw_cursor_update_image(dev_priv,
  302. du->cursor_surface->snooper.image,
  303. 64, 64, du->hotspot_x, du->hotspot_y);
  304. }
  305. mutex_unlock(&dev->mode_config.mutex);
  306. }
  307. /*
  308. * Generic framebuffer code
  309. */
  310. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  311. struct drm_file *file_priv,
  312. unsigned int *handle)
  313. {
  314. if (handle)
  315. *handle = 0;
  316. return 0;
  317. }
  318. /*
  319. * Surface framebuffer code
  320. */
  321. #define vmw_framebuffer_to_vfbs(x) \
  322. container_of(x, struct vmw_framebuffer_surface, base.base)
  323. struct vmw_framebuffer_surface {
  324. struct vmw_framebuffer base;
  325. struct vmw_surface *surface;
  326. struct vmw_dma_buffer *buffer;
  327. struct list_head head;
  328. struct drm_master *master;
  329. };
  330. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  331. {
  332. struct vmw_framebuffer_surface *vfbs =
  333. vmw_framebuffer_to_vfbs(framebuffer);
  334. struct vmw_master *vmaster = vmw_master(vfbs->master);
  335. mutex_lock(&vmaster->fb_surf_mutex);
  336. list_del(&vfbs->head);
  337. mutex_unlock(&vmaster->fb_surf_mutex);
  338. drm_master_put(&vfbs->master);
  339. drm_framebuffer_cleanup(framebuffer);
  340. vmw_surface_unreference(&vfbs->surface);
  341. ttm_base_object_unref(&vfbs->base.user_obj);
  342. kfree(vfbs);
  343. }
  344. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  345. struct drm_file *file_priv,
  346. struct vmw_framebuffer *framebuffer,
  347. unsigned flags, unsigned color,
  348. struct drm_clip_rect *clips,
  349. unsigned num_clips, int inc,
  350. struct vmw_fence_obj **out_fence)
  351. {
  352. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  353. struct drm_clip_rect *clips_ptr;
  354. struct drm_clip_rect *tmp;
  355. struct drm_crtc *crtc;
  356. size_t fifo_size;
  357. int i, num_units;
  358. int ret = 0; /* silence warning */
  359. int left, right, top, bottom;
  360. struct {
  361. SVGA3dCmdHeader header;
  362. SVGA3dCmdBlitSurfaceToScreen body;
  363. } *cmd;
  364. SVGASignedRect *blits;
  365. num_units = 0;
  366. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  367. head) {
  368. if (crtc->fb != &framebuffer->base)
  369. continue;
  370. units[num_units++] = vmw_crtc_to_du(crtc);
  371. }
  372. BUG_ON(!clips || !num_clips);
  373. tmp = kzalloc(sizeof(*tmp) * num_clips, GFP_KERNEL);
  374. if (unlikely(tmp == NULL)) {
  375. DRM_ERROR("Temporary cliprect memory alloc failed.\n");
  376. return -ENOMEM;
  377. }
  378. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  379. cmd = kzalloc(fifo_size, GFP_KERNEL);
  380. if (unlikely(cmd == NULL)) {
  381. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  382. ret = -ENOMEM;
  383. goto out_free_tmp;
  384. }
  385. /* setup blits pointer */
  386. blits = (SVGASignedRect *)&cmd[1];
  387. /* initial clip region */
  388. left = clips->x1;
  389. right = clips->x2;
  390. top = clips->y1;
  391. bottom = clips->y2;
  392. /* skip the first clip rect */
  393. for (i = 1, clips_ptr = clips + inc;
  394. i < num_clips; i++, clips_ptr += inc) {
  395. left = min_t(int, left, (int)clips_ptr->x1);
  396. right = max_t(int, right, (int)clips_ptr->x2);
  397. top = min_t(int, top, (int)clips_ptr->y1);
  398. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  399. }
  400. /* only need to do this once */
  401. memset(cmd, 0, fifo_size);
  402. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  403. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  404. cmd->body.srcRect.left = left;
  405. cmd->body.srcRect.right = right;
  406. cmd->body.srcRect.top = top;
  407. cmd->body.srcRect.bottom = bottom;
  408. clips_ptr = clips;
  409. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  410. tmp[i].x1 = clips_ptr->x1 - left;
  411. tmp[i].x2 = clips_ptr->x2 - left;
  412. tmp[i].y1 = clips_ptr->y1 - top;
  413. tmp[i].y2 = clips_ptr->y2 - top;
  414. }
  415. /* do per unit writing, reuse fifo for each */
  416. for (i = 0; i < num_units; i++) {
  417. struct vmw_display_unit *unit = units[i];
  418. struct vmw_clip_rect clip;
  419. int num;
  420. clip.x1 = left - unit->crtc.x;
  421. clip.y1 = top - unit->crtc.y;
  422. clip.x2 = right - unit->crtc.x;
  423. clip.y2 = bottom - unit->crtc.y;
  424. /* skip any crtcs that misses the clip region */
  425. if (clip.x1 >= unit->crtc.mode.hdisplay ||
  426. clip.y1 >= unit->crtc.mode.vdisplay ||
  427. clip.x2 <= 0 || clip.y2 <= 0)
  428. continue;
  429. /*
  430. * In order for the clip rects to be correctly scaled
  431. * the src and dest rects needs to be the same size.
  432. */
  433. cmd->body.destRect.left = clip.x1;
  434. cmd->body.destRect.right = clip.x2;
  435. cmd->body.destRect.top = clip.y1;
  436. cmd->body.destRect.bottom = clip.y2;
  437. /* create a clip rect of the crtc in dest coords */
  438. clip.x2 = unit->crtc.mode.hdisplay - clip.x1;
  439. clip.y2 = unit->crtc.mode.vdisplay - clip.y1;
  440. clip.x1 = 0 - clip.x1;
  441. clip.y1 = 0 - clip.y1;
  442. /* need to reset sid as it is changed by execbuf */
  443. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  444. cmd->body.destScreenId = unit->unit;
  445. /* clip and write blits to cmd stream */
  446. vmw_clip_cliprects(tmp, num_clips, clip, blits, &num);
  447. /* if no cliprects hit skip this */
  448. if (num == 0)
  449. continue;
  450. /* only return the last fence */
  451. if (out_fence && *out_fence)
  452. vmw_fence_obj_unreference(out_fence);
  453. /* recalculate package length */
  454. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num;
  455. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  456. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  457. fifo_size, 0, NULL, out_fence);
  458. if (unlikely(ret != 0))
  459. break;
  460. }
  461. kfree(cmd);
  462. out_free_tmp:
  463. kfree(tmp);
  464. return ret;
  465. }
  466. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  467. struct drm_file *file_priv,
  468. unsigned flags, unsigned color,
  469. struct drm_clip_rect *clips,
  470. unsigned num_clips)
  471. {
  472. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  473. struct vmw_master *vmaster = vmw_master(file_priv->master);
  474. struct vmw_framebuffer_surface *vfbs =
  475. vmw_framebuffer_to_vfbs(framebuffer);
  476. struct drm_clip_rect norect;
  477. int ret, inc = 1;
  478. if (unlikely(vfbs->master != file_priv->master))
  479. return -EINVAL;
  480. /* Require ScreenObject support for 3D */
  481. if (!dev_priv->sou_priv)
  482. return -EINVAL;
  483. ret = ttm_read_lock(&vmaster->lock, true);
  484. if (unlikely(ret != 0))
  485. return ret;
  486. if (!num_clips) {
  487. num_clips = 1;
  488. clips = &norect;
  489. norect.x1 = norect.y1 = 0;
  490. norect.x2 = framebuffer->width;
  491. norect.y2 = framebuffer->height;
  492. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  493. num_clips /= 2;
  494. inc = 2; /* skip source rects */
  495. }
  496. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base,
  497. flags, color,
  498. clips, num_clips, inc, NULL);
  499. ttm_read_unlock(&vmaster->lock);
  500. return 0;
  501. }
  502. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  503. .destroy = vmw_framebuffer_surface_destroy,
  504. .dirty = vmw_framebuffer_surface_dirty,
  505. .create_handle = vmw_framebuffer_create_handle,
  506. };
  507. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  508. struct drm_file *file_priv,
  509. struct vmw_surface *surface,
  510. struct vmw_framebuffer **out,
  511. const struct drm_mode_fb_cmd
  512. *mode_cmd)
  513. {
  514. struct drm_device *dev = dev_priv->dev;
  515. struct vmw_framebuffer_surface *vfbs;
  516. enum SVGA3dSurfaceFormat format;
  517. struct vmw_master *vmaster = vmw_master(file_priv->master);
  518. int ret;
  519. /* 3D is only supported on HWv8 hosts which supports screen objects */
  520. if (!dev_priv->sou_priv)
  521. return -ENOSYS;
  522. /*
  523. * Sanity checks.
  524. */
  525. /* Surface must be marked as a scanout. */
  526. if (unlikely(!surface->scanout))
  527. return -EINVAL;
  528. if (unlikely(surface->mip_levels[0] != 1 ||
  529. surface->num_sizes != 1 ||
  530. surface->sizes[0].width < mode_cmd->width ||
  531. surface->sizes[0].height < mode_cmd->height ||
  532. surface->sizes[0].depth != 1)) {
  533. DRM_ERROR("Incompatible surface dimensions "
  534. "for requested mode.\n");
  535. return -EINVAL;
  536. }
  537. switch (mode_cmd->depth) {
  538. case 32:
  539. format = SVGA3D_A8R8G8B8;
  540. break;
  541. case 24:
  542. format = SVGA3D_X8R8G8B8;
  543. break;
  544. case 16:
  545. format = SVGA3D_R5G6B5;
  546. break;
  547. case 15:
  548. format = SVGA3D_A1R5G5B5;
  549. break;
  550. case 8:
  551. format = SVGA3D_LUMINANCE8;
  552. break;
  553. default:
  554. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  555. return -EINVAL;
  556. }
  557. if (unlikely(format != surface->format)) {
  558. DRM_ERROR("Invalid surface format for requested mode.\n");
  559. return -EINVAL;
  560. }
  561. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  562. if (!vfbs) {
  563. ret = -ENOMEM;
  564. goto out_err1;
  565. }
  566. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  567. &vmw_framebuffer_surface_funcs);
  568. if (ret)
  569. goto out_err2;
  570. if (!vmw_surface_reference(surface)) {
  571. DRM_ERROR("failed to reference surface %p\n", surface);
  572. goto out_err3;
  573. }
  574. /* XXX get the first 3 from the surface info */
  575. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  576. vfbs->base.base.pitches[0] = mode_cmd->pitch;
  577. vfbs->base.base.depth = mode_cmd->depth;
  578. vfbs->base.base.width = mode_cmd->width;
  579. vfbs->base.base.height = mode_cmd->height;
  580. vfbs->surface = surface;
  581. vfbs->base.user_handle = mode_cmd->handle;
  582. vfbs->master = drm_master_get(file_priv->master);
  583. mutex_lock(&vmaster->fb_surf_mutex);
  584. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  585. mutex_unlock(&vmaster->fb_surf_mutex);
  586. *out = &vfbs->base;
  587. return 0;
  588. out_err3:
  589. drm_framebuffer_cleanup(&vfbs->base.base);
  590. out_err2:
  591. kfree(vfbs);
  592. out_err1:
  593. return ret;
  594. }
  595. /*
  596. * Dmabuf framebuffer code
  597. */
  598. #define vmw_framebuffer_to_vfbd(x) \
  599. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  600. struct vmw_framebuffer_dmabuf {
  601. struct vmw_framebuffer base;
  602. struct vmw_dma_buffer *buffer;
  603. };
  604. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  605. {
  606. struct vmw_framebuffer_dmabuf *vfbd =
  607. vmw_framebuffer_to_vfbd(framebuffer);
  608. drm_framebuffer_cleanup(framebuffer);
  609. vmw_dmabuf_unreference(&vfbd->buffer);
  610. ttm_base_object_unref(&vfbd->base.user_obj);
  611. kfree(vfbd);
  612. }
  613. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  614. struct vmw_framebuffer *framebuffer,
  615. unsigned flags, unsigned color,
  616. struct drm_clip_rect *clips,
  617. unsigned num_clips, int increment)
  618. {
  619. size_t fifo_size;
  620. int i;
  621. struct {
  622. uint32_t header;
  623. SVGAFifoCmdUpdate body;
  624. } *cmd;
  625. fifo_size = sizeof(*cmd) * num_clips;
  626. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  627. if (unlikely(cmd == NULL)) {
  628. DRM_ERROR("Fifo reserve failed.\n");
  629. return -ENOMEM;
  630. }
  631. memset(cmd, 0, fifo_size);
  632. for (i = 0; i < num_clips; i++, clips += increment) {
  633. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  634. cmd[i].body.x = cpu_to_le32(clips->x1);
  635. cmd[i].body.y = cpu_to_le32(clips->y1);
  636. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  637. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  638. }
  639. vmw_fifo_commit(dev_priv, fifo_size);
  640. return 0;
  641. }
  642. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  643. struct vmw_private *dev_priv,
  644. struct vmw_framebuffer *framebuffer)
  645. {
  646. int depth = framebuffer->base.depth;
  647. size_t fifo_size;
  648. int ret;
  649. struct {
  650. uint32_t header;
  651. SVGAFifoCmdDefineGMRFB body;
  652. } *cmd;
  653. /* Emulate RGBA support, contrary to svga_reg.h this is not
  654. * supported by hosts. This is only a problem if we are reading
  655. * this value later and expecting what we uploaded back.
  656. */
  657. if (depth == 32)
  658. depth = 24;
  659. fifo_size = sizeof(*cmd);
  660. cmd = kmalloc(fifo_size, GFP_KERNEL);
  661. if (unlikely(cmd == NULL)) {
  662. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  663. return -ENOMEM;
  664. }
  665. memset(cmd, 0, fifo_size);
  666. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  667. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  668. cmd->body.format.colorDepth = depth;
  669. cmd->body.format.reserved = 0;
  670. cmd->body.bytesPerLine = framebuffer->base.pitches[0];
  671. cmd->body.ptr.gmrId = framebuffer->user_handle;
  672. cmd->body.ptr.offset = 0;
  673. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  674. fifo_size, 0, NULL, NULL);
  675. kfree(cmd);
  676. return ret;
  677. }
  678. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  679. struct vmw_private *dev_priv,
  680. struct vmw_framebuffer *framebuffer,
  681. unsigned flags, unsigned color,
  682. struct drm_clip_rect *clips,
  683. unsigned num_clips, int increment,
  684. struct vmw_fence_obj **out_fence)
  685. {
  686. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  687. struct drm_clip_rect *clips_ptr;
  688. int i, k, num_units, ret;
  689. struct drm_crtc *crtc;
  690. size_t fifo_size;
  691. struct {
  692. uint32_t header;
  693. SVGAFifoCmdBlitGMRFBToScreen body;
  694. } *blits;
  695. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  696. if (unlikely(ret != 0))
  697. return ret; /* define_gmrfb prints warnings */
  698. fifo_size = sizeof(*blits) * num_clips;
  699. blits = kmalloc(fifo_size, GFP_KERNEL);
  700. if (unlikely(blits == NULL)) {
  701. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  702. return -ENOMEM;
  703. }
  704. num_units = 0;
  705. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  706. if (crtc->fb != &framebuffer->base)
  707. continue;
  708. units[num_units++] = vmw_crtc_to_du(crtc);
  709. }
  710. for (k = 0; k < num_units; k++) {
  711. struct vmw_display_unit *unit = units[k];
  712. int hit_num = 0;
  713. clips_ptr = clips;
  714. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  715. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  716. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  717. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  718. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  719. int move_x, move_y;
  720. /* skip any crtcs that misses the clip region */
  721. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  722. clip_y1 >= unit->crtc.mode.vdisplay ||
  723. clip_x2 <= 0 || clip_y2 <= 0)
  724. continue;
  725. /* clip size to crtc size */
  726. clip_x2 = min_t(int, clip_x2, unit->crtc.mode.hdisplay);
  727. clip_y2 = min_t(int, clip_y2, unit->crtc.mode.vdisplay);
  728. /* translate both src and dest to bring clip into screen */
  729. move_x = min_t(int, clip_x1, 0);
  730. move_y = min_t(int, clip_y1, 0);
  731. /* actual translate done here */
  732. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  733. blits[hit_num].body.destScreenId = unit->unit;
  734. blits[hit_num].body.srcOrigin.x = clips_ptr->x1 - move_x;
  735. blits[hit_num].body.srcOrigin.y = clips_ptr->y1 - move_y;
  736. blits[hit_num].body.destRect.left = clip_x1 - move_x;
  737. blits[hit_num].body.destRect.top = clip_y1 - move_y;
  738. blits[hit_num].body.destRect.right = clip_x2;
  739. blits[hit_num].body.destRect.bottom = clip_y2;
  740. hit_num++;
  741. }
  742. /* no clips hit the crtc */
  743. if (hit_num == 0)
  744. continue;
  745. /* only return the last fence */
  746. if (out_fence && *out_fence)
  747. vmw_fence_obj_unreference(out_fence);
  748. fifo_size = sizeof(*blits) * hit_num;
  749. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  750. fifo_size, 0, NULL, out_fence);
  751. if (unlikely(ret != 0))
  752. break;
  753. }
  754. kfree(blits);
  755. return ret;
  756. }
  757. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  758. struct drm_file *file_priv,
  759. unsigned flags, unsigned color,
  760. struct drm_clip_rect *clips,
  761. unsigned num_clips)
  762. {
  763. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  764. struct vmw_master *vmaster = vmw_master(file_priv->master);
  765. struct vmw_framebuffer_dmabuf *vfbd =
  766. vmw_framebuffer_to_vfbd(framebuffer);
  767. struct drm_clip_rect norect;
  768. int ret, increment = 1;
  769. ret = ttm_read_lock(&vmaster->lock, true);
  770. if (unlikely(ret != 0))
  771. return ret;
  772. if (!num_clips) {
  773. num_clips = 1;
  774. clips = &norect;
  775. norect.x1 = norect.y1 = 0;
  776. norect.x2 = framebuffer->width;
  777. norect.y2 = framebuffer->height;
  778. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  779. num_clips /= 2;
  780. increment = 2;
  781. }
  782. if (dev_priv->ldu_priv) {
  783. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base,
  784. flags, color,
  785. clips, num_clips, increment);
  786. } else {
  787. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  788. flags, color,
  789. clips, num_clips, increment, NULL);
  790. }
  791. ttm_read_unlock(&vmaster->lock);
  792. return ret;
  793. }
  794. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  795. .destroy = vmw_framebuffer_dmabuf_destroy,
  796. .dirty = vmw_framebuffer_dmabuf_dirty,
  797. .create_handle = vmw_framebuffer_create_handle,
  798. };
  799. /**
  800. * Pin the dmabuffer to the start of vram.
  801. */
  802. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  803. {
  804. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  805. struct vmw_framebuffer_dmabuf *vfbd =
  806. vmw_framebuffer_to_vfbd(&vfb->base);
  807. int ret;
  808. /* This code should not be used with screen objects */
  809. BUG_ON(dev_priv->sou_priv);
  810. vmw_overlay_pause_all(dev_priv);
  811. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  812. vmw_overlay_resume_all(dev_priv);
  813. WARN_ON(ret != 0);
  814. return 0;
  815. }
  816. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  817. {
  818. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  819. struct vmw_framebuffer_dmabuf *vfbd =
  820. vmw_framebuffer_to_vfbd(&vfb->base);
  821. if (!vfbd->buffer) {
  822. WARN_ON(!vfbd->buffer);
  823. return 0;
  824. }
  825. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  826. }
  827. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  828. struct vmw_dma_buffer *dmabuf,
  829. struct vmw_framebuffer **out,
  830. const struct drm_mode_fb_cmd
  831. *mode_cmd)
  832. {
  833. struct drm_device *dev = dev_priv->dev;
  834. struct vmw_framebuffer_dmabuf *vfbd;
  835. unsigned int requested_size;
  836. int ret;
  837. requested_size = mode_cmd->height * mode_cmd->pitch;
  838. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  839. DRM_ERROR("Screen buffer object size is too small "
  840. "for requested mode.\n");
  841. return -EINVAL;
  842. }
  843. /* Limited framebuffer color depth support for screen objects */
  844. if (dev_priv->sou_priv) {
  845. switch (mode_cmd->depth) {
  846. case 32:
  847. case 24:
  848. /* Only support 32 bpp for 32 and 24 depth fbs */
  849. if (mode_cmd->bpp == 32)
  850. break;
  851. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  852. mode_cmd->depth, mode_cmd->bpp);
  853. return -EINVAL;
  854. case 16:
  855. case 15:
  856. /* Only support 16 bpp for 16 and 15 depth fbs */
  857. if (mode_cmd->bpp == 16)
  858. break;
  859. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  860. mode_cmd->depth, mode_cmd->bpp);
  861. return -EINVAL;
  862. default:
  863. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  864. return -EINVAL;
  865. }
  866. }
  867. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  868. if (!vfbd) {
  869. ret = -ENOMEM;
  870. goto out_err1;
  871. }
  872. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  873. &vmw_framebuffer_dmabuf_funcs);
  874. if (ret)
  875. goto out_err2;
  876. if (!vmw_dmabuf_reference(dmabuf)) {
  877. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  878. goto out_err3;
  879. }
  880. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  881. vfbd->base.base.pitches[0] = mode_cmd->pitch;
  882. vfbd->base.base.depth = mode_cmd->depth;
  883. vfbd->base.base.width = mode_cmd->width;
  884. vfbd->base.base.height = mode_cmd->height;
  885. if (!dev_priv->sou_priv) {
  886. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  887. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  888. }
  889. vfbd->base.dmabuf = true;
  890. vfbd->buffer = dmabuf;
  891. vfbd->base.user_handle = mode_cmd->handle;
  892. *out = &vfbd->base;
  893. return 0;
  894. out_err3:
  895. drm_framebuffer_cleanup(&vfbd->base.base);
  896. out_err2:
  897. kfree(vfbd);
  898. out_err1:
  899. return ret;
  900. }
  901. /*
  902. * Generic Kernel modesetting functions
  903. */
  904. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  905. struct drm_file *file_priv,
  906. struct drm_mode_fb_cmd2 *mode_cmd2)
  907. {
  908. struct vmw_private *dev_priv = vmw_priv(dev);
  909. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  910. struct vmw_framebuffer *vfb = NULL;
  911. struct vmw_surface *surface = NULL;
  912. struct vmw_dma_buffer *bo = NULL;
  913. struct ttm_base_object *user_obj;
  914. struct drm_mode_fb_cmd mode_cmd;
  915. int ret;
  916. mode_cmd.width = mode_cmd2->width;
  917. mode_cmd.height = mode_cmd2->height;
  918. mode_cmd.pitch = mode_cmd2->pitches[0];
  919. mode_cmd.handle = mode_cmd2->handles[0];
  920. drm_fb_get_bpp_depth(mode_cmd2->pixel_format, &mode_cmd.depth,
  921. &mode_cmd.bpp);
  922. /**
  923. * This code should be conditioned on Screen Objects not being used.
  924. * If screen objects are used, we can allocate a GMR to hold the
  925. * requested framebuffer.
  926. */
  927. if (!vmw_kms_validate_mode_vram(dev_priv,
  928. mode_cmd.pitch,
  929. mode_cmd.height)) {
  930. DRM_ERROR("VRAM size is too small for requested mode.\n");
  931. return ERR_PTR(-ENOMEM);
  932. }
  933. /*
  934. * Take a reference on the user object of the resource
  935. * backing the kms fb. This ensures that user-space handle
  936. * lookups on that resource will always work as long as
  937. * it's registered with a kms framebuffer. This is important,
  938. * since vmw_execbuf_process identifies resources in the
  939. * command stream using user-space handles.
  940. */
  941. user_obj = ttm_base_object_lookup(tfile, mode_cmd.handle);
  942. if (unlikely(user_obj == NULL)) {
  943. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  944. return ERR_PTR(-ENOENT);
  945. }
  946. /**
  947. * End conditioned code.
  948. */
  949. /* returns either a dmabuf or surface */
  950. ret = vmw_user_lookup_handle(dev_priv, tfile,
  951. mode_cmd.handle,
  952. &surface, &bo);
  953. if (ret)
  954. goto err_out;
  955. /* Create the new framebuffer depending one what we got back */
  956. if (bo)
  957. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  958. &mode_cmd);
  959. else if (surface)
  960. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv,
  961. surface, &vfb, &mode_cmd);
  962. else
  963. BUG();
  964. err_out:
  965. /* vmw_user_lookup_handle takes one ref so does new_fb */
  966. if (bo)
  967. vmw_dmabuf_unreference(&bo);
  968. if (surface)
  969. vmw_surface_unreference(&surface);
  970. if (ret) {
  971. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  972. ttm_base_object_unref(&user_obj);
  973. return ERR_PTR(ret);
  974. } else
  975. vfb->user_obj = user_obj;
  976. return &vfb->base;
  977. }
  978. static const struct drm_mode_config_funcs vmw_kms_funcs = {
  979. .fb_create = vmw_kms_fb_create,
  980. };
  981. int vmw_kms_present(struct vmw_private *dev_priv,
  982. struct drm_file *file_priv,
  983. struct vmw_framebuffer *vfb,
  984. struct vmw_surface *surface,
  985. uint32_t sid,
  986. int32_t destX, int32_t destY,
  987. struct drm_vmw_rect *clips,
  988. uint32_t num_clips)
  989. {
  990. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  991. struct drm_clip_rect *tmp;
  992. struct drm_crtc *crtc;
  993. size_t fifo_size;
  994. int i, k, num_units;
  995. int ret = 0; /* silence warning */
  996. int left, right, top, bottom;
  997. struct {
  998. SVGA3dCmdHeader header;
  999. SVGA3dCmdBlitSurfaceToScreen body;
  1000. } *cmd;
  1001. SVGASignedRect *blits;
  1002. num_units = 0;
  1003. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1004. if (crtc->fb != &vfb->base)
  1005. continue;
  1006. units[num_units++] = vmw_crtc_to_du(crtc);
  1007. }
  1008. BUG_ON(surface == NULL);
  1009. BUG_ON(!clips || !num_clips);
  1010. tmp = kzalloc(sizeof(*tmp) * num_clips, GFP_KERNEL);
  1011. if (unlikely(tmp == NULL)) {
  1012. DRM_ERROR("Temporary cliprect memory alloc failed.\n");
  1013. return -ENOMEM;
  1014. }
  1015. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  1016. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1017. if (unlikely(cmd == NULL)) {
  1018. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1019. ret = -ENOMEM;
  1020. goto out_free_tmp;
  1021. }
  1022. left = clips->x;
  1023. right = clips->x + clips->w;
  1024. top = clips->y;
  1025. bottom = clips->y + clips->h;
  1026. for (i = 1; i < num_clips; i++) {
  1027. left = min_t(int, left, (int)clips[i].x);
  1028. right = max_t(int, right, (int)clips[i].x + clips[i].w);
  1029. top = min_t(int, top, (int)clips[i].y);
  1030. bottom = max_t(int, bottom, (int)clips[i].y + clips[i].h);
  1031. }
  1032. /* only need to do this once */
  1033. memset(cmd, 0, fifo_size);
  1034. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  1035. blits = (SVGASignedRect *)&cmd[1];
  1036. cmd->body.srcRect.left = left;
  1037. cmd->body.srcRect.right = right;
  1038. cmd->body.srcRect.top = top;
  1039. cmd->body.srcRect.bottom = bottom;
  1040. for (i = 0; i < num_clips; i++) {
  1041. tmp[i].x1 = clips[i].x - left;
  1042. tmp[i].x2 = clips[i].x + clips[i].w - left;
  1043. tmp[i].y1 = clips[i].y - top;
  1044. tmp[i].y2 = clips[i].y + clips[i].h - top;
  1045. }
  1046. for (k = 0; k < num_units; k++) {
  1047. struct vmw_display_unit *unit = units[k];
  1048. struct vmw_clip_rect clip;
  1049. int num;
  1050. clip.x1 = left + destX - unit->crtc.x;
  1051. clip.y1 = top + destY - unit->crtc.y;
  1052. clip.x2 = right + destX - unit->crtc.x;
  1053. clip.y2 = bottom + destY - unit->crtc.y;
  1054. /* skip any crtcs that misses the clip region */
  1055. if (clip.x1 >= unit->crtc.mode.hdisplay ||
  1056. clip.y1 >= unit->crtc.mode.vdisplay ||
  1057. clip.x2 <= 0 || clip.y2 <= 0)
  1058. continue;
  1059. /*
  1060. * In order for the clip rects to be correctly scaled
  1061. * the src and dest rects needs to be the same size.
  1062. */
  1063. cmd->body.destRect.left = clip.x1;
  1064. cmd->body.destRect.right = clip.x2;
  1065. cmd->body.destRect.top = clip.y1;
  1066. cmd->body.destRect.bottom = clip.y2;
  1067. /* create a clip rect of the crtc in dest coords */
  1068. clip.x2 = unit->crtc.mode.hdisplay - clip.x1;
  1069. clip.y2 = unit->crtc.mode.vdisplay - clip.y1;
  1070. clip.x1 = 0 - clip.x1;
  1071. clip.y1 = 0 - clip.y1;
  1072. /* need to reset sid as it is changed by execbuf */
  1073. cmd->body.srcImage.sid = sid;
  1074. cmd->body.destScreenId = unit->unit;
  1075. /* clip and write blits to cmd stream */
  1076. vmw_clip_cliprects(tmp, num_clips, clip, blits, &num);
  1077. /* if no cliprects hit skip this */
  1078. if (num == 0)
  1079. continue;
  1080. /* recalculate package length */
  1081. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num;
  1082. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  1083. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  1084. fifo_size, 0, NULL, NULL);
  1085. if (unlikely(ret != 0))
  1086. break;
  1087. }
  1088. kfree(cmd);
  1089. out_free_tmp:
  1090. kfree(tmp);
  1091. return ret;
  1092. }
  1093. int vmw_kms_readback(struct vmw_private *dev_priv,
  1094. struct drm_file *file_priv,
  1095. struct vmw_framebuffer *vfb,
  1096. struct drm_vmw_fence_rep __user *user_fence_rep,
  1097. struct drm_vmw_rect *clips,
  1098. uint32_t num_clips)
  1099. {
  1100. struct vmw_framebuffer_dmabuf *vfbd =
  1101. vmw_framebuffer_to_vfbd(&vfb->base);
  1102. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  1103. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  1104. struct drm_crtc *crtc;
  1105. size_t fifo_size;
  1106. int i, k, ret, num_units, blits_pos;
  1107. struct {
  1108. uint32_t header;
  1109. SVGAFifoCmdDefineGMRFB body;
  1110. } *cmd;
  1111. struct {
  1112. uint32_t header;
  1113. SVGAFifoCmdBlitScreenToGMRFB body;
  1114. } *blits;
  1115. num_units = 0;
  1116. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  1117. if (crtc->fb != &vfb->base)
  1118. continue;
  1119. units[num_units++] = vmw_crtc_to_du(crtc);
  1120. }
  1121. BUG_ON(dmabuf == NULL);
  1122. BUG_ON(!clips || !num_clips);
  1123. /* take a safe guess at fifo size */
  1124. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  1125. cmd = kmalloc(fifo_size, GFP_KERNEL);
  1126. if (unlikely(cmd == NULL)) {
  1127. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1128. return -ENOMEM;
  1129. }
  1130. memset(cmd, 0, fifo_size);
  1131. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1132. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1133. cmd->body.format.colorDepth = vfb->base.depth;
  1134. cmd->body.format.reserved = 0;
  1135. cmd->body.bytesPerLine = vfb->base.pitches[0];
  1136. cmd->body.ptr.gmrId = vfb->user_handle;
  1137. cmd->body.ptr.offset = 0;
  1138. blits = (void *)&cmd[1];
  1139. blits_pos = 0;
  1140. for (i = 0; i < num_units; i++) {
  1141. struct drm_vmw_rect *c = clips;
  1142. for (k = 0; k < num_clips; k++, c++) {
  1143. /* transform clip coords to crtc origin based coords */
  1144. int clip_x1 = c->x - units[i]->crtc.x;
  1145. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1146. int clip_y1 = c->y - units[i]->crtc.y;
  1147. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1148. int dest_x = c->x;
  1149. int dest_y = c->y;
  1150. /* compensate for clipping, we negate
  1151. * a negative number and add that.
  1152. */
  1153. if (clip_x1 < 0)
  1154. dest_x += -clip_x1;
  1155. if (clip_y1 < 0)
  1156. dest_y += -clip_y1;
  1157. /* clip */
  1158. clip_x1 = max(clip_x1, 0);
  1159. clip_y1 = max(clip_y1, 0);
  1160. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1161. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1162. /* and cull any rects that misses the crtc */
  1163. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1164. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1165. clip_x2 <= 0 || clip_y2 <= 0)
  1166. continue;
  1167. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1168. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1169. blits[blits_pos].body.destOrigin.x = dest_x;
  1170. blits[blits_pos].body.destOrigin.y = dest_y;
  1171. blits[blits_pos].body.srcRect.left = clip_x1;
  1172. blits[blits_pos].body.srcRect.top = clip_y1;
  1173. blits[blits_pos].body.srcRect.right = clip_x2;
  1174. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1175. blits_pos++;
  1176. }
  1177. }
  1178. /* reset size here and use calculated exact size from loops */
  1179. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1180. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1181. 0, user_fence_rep, NULL);
  1182. kfree(cmd);
  1183. return ret;
  1184. }
  1185. int vmw_kms_init(struct vmw_private *dev_priv)
  1186. {
  1187. struct drm_device *dev = dev_priv->dev;
  1188. int ret;
  1189. drm_mode_config_init(dev);
  1190. dev->mode_config.funcs = &vmw_kms_funcs;
  1191. dev->mode_config.min_width = 1;
  1192. dev->mode_config.min_height = 1;
  1193. /* assumed largest fb size */
  1194. dev->mode_config.max_width = 8192;
  1195. dev->mode_config.max_height = 8192;
  1196. ret = vmw_kms_init_screen_object_display(dev_priv);
  1197. if (ret) /* Fallback */
  1198. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1199. return 0;
  1200. }
  1201. int vmw_kms_close(struct vmw_private *dev_priv)
  1202. {
  1203. /*
  1204. * Docs says we should take the lock before calling this function
  1205. * but since it destroys encoders and our destructor calls
  1206. * drm_encoder_cleanup which takes the lock we deadlock.
  1207. */
  1208. drm_mode_config_cleanup(dev_priv->dev);
  1209. if (dev_priv->sou_priv)
  1210. vmw_kms_close_screen_object_display(dev_priv);
  1211. else
  1212. vmw_kms_close_legacy_display_system(dev_priv);
  1213. return 0;
  1214. }
  1215. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1216. struct drm_file *file_priv)
  1217. {
  1218. struct drm_vmw_cursor_bypass_arg *arg = data;
  1219. struct vmw_display_unit *du;
  1220. struct drm_mode_object *obj;
  1221. struct drm_crtc *crtc;
  1222. int ret = 0;
  1223. mutex_lock(&dev->mode_config.mutex);
  1224. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1225. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1226. du = vmw_crtc_to_du(crtc);
  1227. du->hotspot_x = arg->xhot;
  1228. du->hotspot_y = arg->yhot;
  1229. }
  1230. mutex_unlock(&dev->mode_config.mutex);
  1231. return 0;
  1232. }
  1233. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1234. if (!obj) {
  1235. ret = -EINVAL;
  1236. goto out;
  1237. }
  1238. crtc = obj_to_crtc(obj);
  1239. du = vmw_crtc_to_du(crtc);
  1240. du->hotspot_x = arg->xhot;
  1241. du->hotspot_y = arg->yhot;
  1242. out:
  1243. mutex_unlock(&dev->mode_config.mutex);
  1244. return ret;
  1245. }
  1246. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1247. unsigned width, unsigned height, unsigned pitch,
  1248. unsigned bpp, unsigned depth)
  1249. {
  1250. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1251. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1252. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1253. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1254. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1255. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1256. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1257. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1258. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1259. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1260. return -EINVAL;
  1261. }
  1262. return 0;
  1263. }
  1264. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1265. {
  1266. struct vmw_vga_topology_state *save;
  1267. uint32_t i;
  1268. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1269. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1270. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1271. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1272. vmw_priv->vga_pitchlock =
  1273. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1274. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1275. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1276. SVGA_FIFO_PITCHLOCK);
  1277. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1278. return 0;
  1279. vmw_priv->num_displays = vmw_read(vmw_priv,
  1280. SVGA_REG_NUM_GUEST_DISPLAYS);
  1281. if (vmw_priv->num_displays == 0)
  1282. vmw_priv->num_displays = 1;
  1283. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1284. save = &vmw_priv->vga_save[i];
  1285. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1286. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1287. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1288. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1289. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1290. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1291. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1292. if (i == 0 && vmw_priv->num_displays == 1 &&
  1293. save->width == 0 && save->height == 0) {
  1294. /*
  1295. * It should be fairly safe to assume that these
  1296. * values are uninitialized.
  1297. */
  1298. save->width = vmw_priv->vga_width - save->pos_x;
  1299. save->height = vmw_priv->vga_height - save->pos_y;
  1300. }
  1301. }
  1302. return 0;
  1303. }
  1304. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1305. {
  1306. struct vmw_vga_topology_state *save;
  1307. uint32_t i;
  1308. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1309. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1310. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1311. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1312. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1313. vmw_priv->vga_pitchlock);
  1314. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1315. iowrite32(vmw_priv->vga_pitchlock,
  1316. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1317. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1318. return 0;
  1319. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1320. save = &vmw_priv->vga_save[i];
  1321. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1322. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1323. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1324. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1325. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1326. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1327. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1328. }
  1329. return 0;
  1330. }
  1331. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1332. uint32_t pitch,
  1333. uint32_t height)
  1334. {
  1335. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1336. }
  1337. /**
  1338. * Function called by DRM code called with vbl_lock held.
  1339. */
  1340. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1341. {
  1342. return 0;
  1343. }
  1344. /**
  1345. * Function called by DRM code called with vbl_lock held.
  1346. */
  1347. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1348. {
  1349. return -ENOSYS;
  1350. }
  1351. /**
  1352. * Function called by DRM code called with vbl_lock held.
  1353. */
  1354. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1355. {
  1356. }
  1357. /*
  1358. * Small shared kms functions.
  1359. */
  1360. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1361. struct drm_vmw_rect *rects)
  1362. {
  1363. struct drm_device *dev = dev_priv->dev;
  1364. struct vmw_display_unit *du;
  1365. struct drm_connector *con;
  1366. mutex_lock(&dev->mode_config.mutex);
  1367. #if 0
  1368. {
  1369. unsigned int i;
  1370. DRM_INFO("%s: new layout ", __func__);
  1371. for (i = 0; i < num; i++)
  1372. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1373. rects[i].w, rects[i].h);
  1374. DRM_INFO("\n");
  1375. }
  1376. #endif
  1377. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1378. du = vmw_connector_to_du(con);
  1379. if (num > du->unit) {
  1380. du->pref_width = rects[du->unit].w;
  1381. du->pref_height = rects[du->unit].h;
  1382. du->pref_active = true;
  1383. du->gui_x = rects[du->unit].x;
  1384. du->gui_y = rects[du->unit].y;
  1385. } else {
  1386. du->pref_width = 800;
  1387. du->pref_height = 600;
  1388. du->pref_active = false;
  1389. }
  1390. con->status = vmw_du_connector_detect(con, true);
  1391. }
  1392. mutex_unlock(&dev->mode_config.mutex);
  1393. return 0;
  1394. }
  1395. int vmw_du_page_flip(struct drm_crtc *crtc,
  1396. struct drm_framebuffer *fb,
  1397. struct drm_pending_vblank_event *event)
  1398. {
  1399. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1400. struct drm_framebuffer *old_fb = crtc->fb;
  1401. struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(fb);
  1402. struct drm_file *file_priv ;
  1403. struct vmw_fence_obj *fence = NULL;
  1404. struct drm_clip_rect clips;
  1405. int ret;
  1406. if (event == NULL)
  1407. return -EINVAL;
  1408. /* require ScreenObject support for page flipping */
  1409. if (!dev_priv->sou_priv)
  1410. return -ENOSYS;
  1411. file_priv = event->base.file_priv;
  1412. if (!vmw_kms_screen_object_flippable(dev_priv, crtc))
  1413. return -EINVAL;
  1414. crtc->fb = fb;
  1415. /* do a full screen dirty update */
  1416. clips.x1 = clips.y1 = 0;
  1417. clips.x2 = fb->width;
  1418. clips.y2 = fb->height;
  1419. if (vfb->dmabuf)
  1420. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, vfb,
  1421. 0, 0, &clips, 1, 1, &fence);
  1422. else
  1423. ret = do_surface_dirty_sou(dev_priv, file_priv, vfb,
  1424. 0, 0, &clips, 1, 1, &fence);
  1425. if (ret != 0)
  1426. goto out_no_fence;
  1427. if (!fence) {
  1428. ret = -EINVAL;
  1429. goto out_no_fence;
  1430. }
  1431. ret = vmw_event_fence_action_queue(file_priv, fence,
  1432. &event->base,
  1433. &event->event.tv_sec,
  1434. &event->event.tv_usec,
  1435. true);
  1436. /*
  1437. * No need to hold on to this now. The only cleanup
  1438. * we need to do if we fail is unref the fence.
  1439. */
  1440. vmw_fence_obj_unreference(&fence);
  1441. if (vmw_crtc_to_du(crtc)->is_implicit)
  1442. vmw_kms_screen_object_update_implicit_fb(dev_priv, crtc);
  1443. return ret;
  1444. out_no_fence:
  1445. crtc->fb = old_fb;
  1446. return ret;
  1447. }
  1448. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1449. {
  1450. }
  1451. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1452. {
  1453. }
  1454. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1455. u16 *r, u16 *g, u16 *b,
  1456. uint32_t start, uint32_t size)
  1457. {
  1458. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1459. int i;
  1460. for (i = 0; i < size; i++) {
  1461. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1462. r[i], g[i], b[i]);
  1463. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1464. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1465. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1466. }
  1467. }
  1468. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1469. {
  1470. }
  1471. void vmw_du_connector_save(struct drm_connector *connector)
  1472. {
  1473. }
  1474. void vmw_du_connector_restore(struct drm_connector *connector)
  1475. {
  1476. }
  1477. enum drm_connector_status
  1478. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1479. {
  1480. uint32_t num_displays;
  1481. struct drm_device *dev = connector->dev;
  1482. struct vmw_private *dev_priv = vmw_priv(dev);
  1483. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1484. mutex_lock(&dev_priv->hw_mutex);
  1485. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1486. mutex_unlock(&dev_priv->hw_mutex);
  1487. return ((vmw_connector_to_du(connector)->unit < num_displays &&
  1488. du->pref_active) ?
  1489. connector_status_connected : connector_status_disconnected);
  1490. }
  1491. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1492. /* 640x480@60Hz */
  1493. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1494. 752, 800, 0, 480, 489, 492, 525, 0,
  1495. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1496. /* 800x600@60Hz */
  1497. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1498. 968, 1056, 0, 600, 601, 605, 628, 0,
  1499. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1500. /* 1024x768@60Hz */
  1501. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1502. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1503. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1504. /* 1152x864@75Hz */
  1505. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1506. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1507. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1508. /* 1280x768@60Hz */
  1509. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1510. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1511. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1512. /* 1280x800@60Hz */
  1513. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1514. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1515. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1516. /* 1280x960@60Hz */
  1517. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1518. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1519. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1520. /* 1280x1024@60Hz */
  1521. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1522. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1523. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1524. /* 1360x768@60Hz */
  1525. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1526. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1527. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1528. /* 1440x1050@60Hz */
  1529. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1530. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1531. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1532. /* 1440x900@60Hz */
  1533. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1534. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1535. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1536. /* 1600x1200@60Hz */
  1537. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1538. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1539. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1540. /* 1680x1050@60Hz */
  1541. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1542. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1543. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1544. /* 1792x1344@60Hz */
  1545. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1546. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1547. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1548. /* 1853x1392@60Hz */
  1549. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1550. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1551. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1552. /* 1920x1200@60Hz */
  1553. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1554. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1555. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1556. /* 1920x1440@60Hz */
  1557. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1558. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1559. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1560. /* 2560x1600@60Hz */
  1561. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1562. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1563. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1564. /* Terminate */
  1565. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1566. };
  1567. /**
  1568. * vmw_guess_mode_timing - Provide fake timings for a
  1569. * 60Hz vrefresh mode.
  1570. *
  1571. * @mode - Pointer to a struct drm_display_mode with hdisplay and vdisplay
  1572. * members filled in.
  1573. */
  1574. static void vmw_guess_mode_timing(struct drm_display_mode *mode)
  1575. {
  1576. mode->hsync_start = mode->hdisplay + 50;
  1577. mode->hsync_end = mode->hsync_start + 50;
  1578. mode->htotal = mode->hsync_end + 50;
  1579. mode->vsync_start = mode->vdisplay + 50;
  1580. mode->vsync_end = mode->vsync_start + 50;
  1581. mode->vtotal = mode->vsync_end + 50;
  1582. mode->clock = (u32)mode->htotal * (u32)mode->vtotal / 100 * 6;
  1583. mode->vrefresh = drm_mode_vrefresh(mode);
  1584. }
  1585. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1586. uint32_t max_width, uint32_t max_height)
  1587. {
  1588. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1589. struct drm_device *dev = connector->dev;
  1590. struct vmw_private *dev_priv = vmw_priv(dev);
  1591. struct drm_display_mode *mode = NULL;
  1592. struct drm_display_mode *bmode;
  1593. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1594. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1595. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1596. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1597. };
  1598. int i;
  1599. /* Add preferred mode */
  1600. {
  1601. mode = drm_mode_duplicate(dev, &prefmode);
  1602. if (!mode)
  1603. return 0;
  1604. mode->hdisplay = du->pref_width;
  1605. mode->vdisplay = du->pref_height;
  1606. vmw_guess_mode_timing(mode);
  1607. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1608. mode->vdisplay)) {
  1609. drm_mode_probed_add(connector, mode);
  1610. } else {
  1611. drm_mode_destroy(dev, mode);
  1612. mode = NULL;
  1613. }
  1614. if (du->pref_mode) {
  1615. list_del_init(&du->pref_mode->head);
  1616. drm_mode_destroy(dev, du->pref_mode);
  1617. }
  1618. /* mode might be null here, this is intended */
  1619. du->pref_mode = mode;
  1620. }
  1621. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1622. bmode = &vmw_kms_connector_builtin[i];
  1623. if (bmode->hdisplay > max_width ||
  1624. bmode->vdisplay > max_height)
  1625. continue;
  1626. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1627. bmode->vdisplay))
  1628. continue;
  1629. mode = drm_mode_duplicate(dev, bmode);
  1630. if (!mode)
  1631. return 0;
  1632. mode->vrefresh = drm_mode_vrefresh(mode);
  1633. drm_mode_probed_add(connector, mode);
  1634. }
  1635. /* Move the prefered mode first, help apps pick the right mode. */
  1636. if (du->pref_mode)
  1637. list_move(&du->pref_mode->head, &connector->probed_modes);
  1638. drm_mode_connector_list_update(connector);
  1639. return 1;
  1640. }
  1641. int vmw_du_connector_set_property(struct drm_connector *connector,
  1642. struct drm_property *property,
  1643. uint64_t val)
  1644. {
  1645. return 0;
  1646. }
  1647. int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
  1648. struct drm_file *file_priv)
  1649. {
  1650. struct vmw_private *dev_priv = vmw_priv(dev);
  1651. struct drm_vmw_update_layout_arg *arg =
  1652. (struct drm_vmw_update_layout_arg *)data;
  1653. struct vmw_master *vmaster = vmw_master(file_priv->master);
  1654. void __user *user_rects;
  1655. struct drm_vmw_rect *rects;
  1656. unsigned rects_size;
  1657. int ret;
  1658. int i;
  1659. struct drm_mode_config *mode_config = &dev->mode_config;
  1660. ret = ttm_read_lock(&vmaster->lock, true);
  1661. if (unlikely(ret != 0))
  1662. return ret;
  1663. if (!arg->num_outputs) {
  1664. struct drm_vmw_rect def_rect = {0, 0, 800, 600};
  1665. vmw_du_update_layout(dev_priv, 1, &def_rect);
  1666. goto out_unlock;
  1667. }
  1668. rects_size = arg->num_outputs * sizeof(struct drm_vmw_rect);
  1669. rects = kcalloc(arg->num_outputs, sizeof(struct drm_vmw_rect),
  1670. GFP_KERNEL);
  1671. if (unlikely(!rects)) {
  1672. ret = -ENOMEM;
  1673. goto out_unlock;
  1674. }
  1675. user_rects = (void __user *)(unsigned long)arg->rects;
  1676. ret = copy_from_user(rects, user_rects, rects_size);
  1677. if (unlikely(ret != 0)) {
  1678. DRM_ERROR("Failed to get rects.\n");
  1679. ret = -EFAULT;
  1680. goto out_free;
  1681. }
  1682. for (i = 0; i < arg->num_outputs; ++i) {
  1683. if (rects[i].x < 0 ||
  1684. rects[i].y < 0 ||
  1685. rects[i].x + rects[i].w > mode_config->max_width ||
  1686. rects[i].y + rects[i].h > mode_config->max_height) {
  1687. DRM_ERROR("Invalid GUI layout.\n");
  1688. ret = -EINVAL;
  1689. goto out_free;
  1690. }
  1691. }
  1692. vmw_du_update_layout(dev_priv, arg->num_outputs, rects);
  1693. out_free:
  1694. kfree(rects);
  1695. out_unlock:
  1696. ttm_read_unlock(&vmaster->lock);
  1697. return ret;
  1698. }