iwl3945-base.c 244 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. /*
  30. * NOTE: This file (iwl-base.c) is used to build to multiple hardware targets
  31. * by defining IWL to either 3945 or 4965. The Makefile used when building
  32. * the base targets will create base-3945.o and base-4965.o
  33. *
  34. * The eventual goal is to move as many of the #if IWL / #endif blocks out of
  35. * this file and into the hardware specific implementation files (iwl-XXXX.c)
  36. * and leave only the common (non #ifdef sprinkled) code in this file
  37. */
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/version.h>
  41. #include <linux/init.h>
  42. #include <linux/pci.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/delay.h>
  45. #include <linux/skbuff.h>
  46. #include <linux/netdevice.h>
  47. #include <linux/wireless.h>
  48. #include <linux/firmware.h>
  49. #include <linux/etherdevice.h>
  50. #include <linux/if_arp.h>
  51. #include <net/ieee80211_radiotap.h>
  52. #include <net/mac80211.h>
  53. #include <asm/div64.h>
  54. #include "iwl-3945.h"
  55. #include "iwl-helpers.h"
  56. #ifdef CONFIG_IWL3945_DEBUG
  57. u32 iwl3945_debug_level;
  58. #endif
  59. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  60. struct iwl3945_tx_queue *txq);
  61. /******************************************************************************
  62. *
  63. * module boiler plate
  64. *
  65. ******************************************************************************/
  66. /* module parameters */
  67. static int iwl3945_param_disable_hw_scan;
  68. static int iwl3945_param_debug;
  69. static int iwl3945_param_disable; /* def: enable radio */
  70. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  71. int iwl3945_param_hwcrypto; /* def: using software encryption */
  72. static int iwl3945_param_qos_enable = 1;
  73. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES;
  74. /*
  75. * module name, copyright, version, etc.
  76. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  77. */
  78. #define DRV_DESCRIPTION \
  79. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  80. #ifdef CONFIG_IWL3945_DEBUG
  81. #define VD "d"
  82. #else
  83. #define VD
  84. #endif
  85. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  86. #define VS "s"
  87. #else
  88. #define VS
  89. #endif
  90. #define IWLWIFI_VERSION "1.1.19k" VD VS
  91. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  92. #define DRV_VERSION IWLWIFI_VERSION
  93. /* Change firmware file name, using "-" and incrementing number,
  94. * *only* when uCode interface or architecture changes so that it
  95. * is not compatible with earlier drivers.
  96. * This number will also appear in << 8 position of 1st dword of uCode file */
  97. #define IWL3945_UCODE_API "-1"
  98. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  99. MODULE_VERSION(DRV_VERSION);
  100. MODULE_AUTHOR(DRV_COPYRIGHT);
  101. MODULE_LICENSE("GPL");
  102. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  103. {
  104. u16 fc = le16_to_cpu(hdr->frame_control);
  105. int hdr_len = ieee80211_get_hdrlen(fc);
  106. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  107. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  108. return NULL;
  109. }
  110. static const struct ieee80211_hw_mode *iwl3945_get_hw_mode(
  111. struct iwl3945_priv *priv, int mode)
  112. {
  113. int i;
  114. for (i = 0; i < 3; i++)
  115. if (priv->modes[i].mode == mode)
  116. return &priv->modes[i];
  117. return NULL;
  118. }
  119. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  120. {
  121. /* Single white space is for Linksys APs */
  122. if (essid_len == 1 && essid[0] == ' ')
  123. return 1;
  124. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  125. while (essid_len) {
  126. essid_len--;
  127. if (essid[essid_len] != '\0')
  128. return 0;
  129. }
  130. return 1;
  131. }
  132. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  133. {
  134. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  135. const char *s = essid;
  136. char *d = escaped;
  137. if (iwl3945_is_empty_essid(essid, essid_len)) {
  138. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  139. return escaped;
  140. }
  141. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  142. while (essid_len--) {
  143. if (*s == '\0') {
  144. *d++ = '\\';
  145. *d++ = '0';
  146. s++;
  147. } else
  148. *d++ = *s++;
  149. }
  150. *d = '\0';
  151. return escaped;
  152. }
  153. static void iwl3945_print_hex_dump(int level, void *p, u32 len)
  154. {
  155. #ifdef CONFIG_IWL3945_DEBUG
  156. if (!(iwl3945_debug_level & level))
  157. return;
  158. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  159. p, len, 1);
  160. #endif
  161. }
  162. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  163. * DMA services
  164. *
  165. * Theory of operation
  166. *
  167. * A queue is a circular buffers with 'Read' and 'Write' pointers.
  168. * 2 empty entries always kept in the buffer to protect from overflow.
  169. *
  170. * For Tx queue, there are low mark and high mark limits. If, after queuing
  171. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  172. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  173. * Tx queue resumed.
  174. *
  175. * The IWL operates with six queues, one receive queue in the device's
  176. * sram, one transmit queue for sending commands to the device firmware,
  177. * and four transmit queues for data.
  178. ***************************************************/
  179. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  180. {
  181. int s = q->read_ptr - q->write_ptr;
  182. if (q->read_ptr > q->write_ptr)
  183. s -= q->n_bd;
  184. if (s <= 0)
  185. s += q->n_window;
  186. /* keep some reserve to not confuse empty and full situations */
  187. s -= 2;
  188. if (s < 0)
  189. s = 0;
  190. return s;
  191. }
  192. /* XXX: n_bd must be power-of-two size */
  193. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  194. {
  195. return ++index & (n_bd - 1);
  196. }
  197. /* XXX: n_bd must be power-of-two size */
  198. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  199. {
  200. return --index & (n_bd - 1);
  201. }
  202. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  203. {
  204. return q->write_ptr > q->read_ptr ?
  205. (i >= q->read_ptr && i < q->write_ptr) :
  206. !(i < q->read_ptr && i >= q->write_ptr);
  207. }
  208. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  209. {
  210. if (is_huge)
  211. return q->n_window;
  212. return index & (q->n_window - 1);
  213. }
  214. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  215. int count, int slots_num, u32 id)
  216. {
  217. q->n_bd = count;
  218. q->n_window = slots_num;
  219. q->id = id;
  220. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  221. * and iwl3945_queue_dec_wrap are broken. */
  222. BUG_ON(!is_power_of_2(count));
  223. /* slots_num must be power-of-two size, otherwise
  224. * get_cmd_index is broken. */
  225. BUG_ON(!is_power_of_2(slots_num));
  226. q->low_mark = q->n_window / 4;
  227. if (q->low_mark < 4)
  228. q->low_mark = 4;
  229. q->high_mark = q->n_window / 8;
  230. if (q->high_mark < 2)
  231. q->high_mark = 2;
  232. q->write_ptr = q->read_ptr = 0;
  233. return 0;
  234. }
  235. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  236. struct iwl3945_tx_queue *txq, u32 id)
  237. {
  238. struct pci_dev *dev = priv->pci_dev;
  239. if (id != IWL_CMD_QUEUE_NUM) {
  240. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  241. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  242. if (!txq->txb) {
  243. IWL_ERROR("kmalloc for auxiliary BD "
  244. "structures failed\n");
  245. goto error;
  246. }
  247. } else
  248. txq->txb = NULL;
  249. txq->bd = pci_alloc_consistent(dev,
  250. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  251. &txq->q.dma_addr);
  252. if (!txq->bd) {
  253. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  254. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  255. goto error;
  256. }
  257. txq->q.id = id;
  258. return 0;
  259. error:
  260. if (txq->txb) {
  261. kfree(txq->txb);
  262. txq->txb = NULL;
  263. }
  264. return -ENOMEM;
  265. }
  266. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  267. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  268. {
  269. struct pci_dev *dev = priv->pci_dev;
  270. int len;
  271. int rc = 0;
  272. /* allocate command space + one big command for scan since scan
  273. * command is very huge the system will not have two scan at the
  274. * same time */
  275. len = sizeof(struct iwl3945_cmd) * slots_num;
  276. if (txq_id == IWL_CMD_QUEUE_NUM)
  277. len += IWL_MAX_SCAN_SIZE;
  278. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  279. if (!txq->cmd)
  280. return -ENOMEM;
  281. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  282. if (rc) {
  283. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  284. return -ENOMEM;
  285. }
  286. txq->need_update = 0;
  287. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  288. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  289. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  290. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  291. iwl3945_hw_tx_queue_init(priv, txq);
  292. return 0;
  293. }
  294. /**
  295. * iwl3945_tx_queue_free - Deallocate DMA queue.
  296. * @txq: Transmit queue to deallocate.
  297. *
  298. * Empty queue by removing and destroying all BD's.
  299. * Free all buffers. txq itself is not freed.
  300. *
  301. */
  302. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  303. {
  304. struct iwl3945_queue *q = &txq->q;
  305. struct pci_dev *dev = priv->pci_dev;
  306. int len;
  307. if (q->n_bd == 0)
  308. return;
  309. /* first, empty all BD's */
  310. for (; q->write_ptr != q->read_ptr;
  311. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  312. iwl3945_hw_txq_free_tfd(priv, txq);
  313. len = sizeof(struct iwl3945_cmd) * q->n_window;
  314. if (q->id == IWL_CMD_QUEUE_NUM)
  315. len += IWL_MAX_SCAN_SIZE;
  316. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  317. /* free buffers belonging to queue itself */
  318. if (txq->q.n_bd)
  319. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  320. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  321. if (txq->txb) {
  322. kfree(txq->txb);
  323. txq->txb = NULL;
  324. }
  325. /* 0 fill whole structure */
  326. memset(txq, 0, sizeof(*txq));
  327. }
  328. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  329. /*************** STATION TABLE MANAGEMENT ****
  330. *
  331. * NOTE: This needs to be overhauled to better synchronize between
  332. * how the iwl-4965.c is using iwl3945_hw_find_station vs. iwl-3945.c
  333. *
  334. * mac80211 should also be examined to determine if sta_info is duplicating
  335. * the functionality provided here
  336. */
  337. /**************************************************************/
  338. #if 0 /* temporary disable till we add real remove station */
  339. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  340. {
  341. int index = IWL_INVALID_STATION;
  342. int i;
  343. unsigned long flags;
  344. spin_lock_irqsave(&priv->sta_lock, flags);
  345. if (is_ap)
  346. index = IWL_AP_ID;
  347. else if (is_broadcast_ether_addr(addr))
  348. index = priv->hw_setting.bcast_sta_id;
  349. else
  350. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  351. if (priv->stations[i].used &&
  352. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  353. addr)) {
  354. index = i;
  355. break;
  356. }
  357. if (unlikely(index == IWL_INVALID_STATION))
  358. goto out;
  359. if (priv->stations[index].used) {
  360. priv->stations[index].used = 0;
  361. priv->num_stations--;
  362. }
  363. BUG_ON(priv->num_stations < 0);
  364. out:
  365. spin_unlock_irqrestore(&priv->sta_lock, flags);
  366. return 0;
  367. }
  368. #endif
  369. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  370. {
  371. unsigned long flags;
  372. spin_lock_irqsave(&priv->sta_lock, flags);
  373. priv->num_stations = 0;
  374. memset(priv->stations, 0, sizeof(priv->stations));
  375. spin_unlock_irqrestore(&priv->sta_lock, flags);
  376. }
  377. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  378. {
  379. int i;
  380. int index = IWL_INVALID_STATION;
  381. struct iwl3945_station_entry *station;
  382. unsigned long flags_spin;
  383. DECLARE_MAC_BUF(mac);
  384. u8 rate;
  385. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  386. if (is_ap)
  387. index = IWL_AP_ID;
  388. else if (is_broadcast_ether_addr(addr))
  389. index = priv->hw_setting.bcast_sta_id;
  390. else
  391. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  392. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  393. addr)) {
  394. index = i;
  395. break;
  396. }
  397. if (!priv->stations[i].used &&
  398. index == IWL_INVALID_STATION)
  399. index = i;
  400. }
  401. /* These two conditions has the same outcome but keep them separate
  402. since they have different meaning */
  403. if (unlikely(index == IWL_INVALID_STATION)) {
  404. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  405. return index;
  406. }
  407. if (priv->stations[index].used &&
  408. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  409. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  410. return index;
  411. }
  412. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  413. station = &priv->stations[index];
  414. station->used = 1;
  415. priv->num_stations++;
  416. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  417. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  418. station->sta.mode = 0;
  419. station->sta.sta.sta_id = index;
  420. station->sta.station_flags = 0;
  421. if (priv->phymode == MODE_IEEE80211A)
  422. rate = IWL_RATE_6M_PLCP;
  423. else
  424. rate = IWL_RATE_1M_PLCP;
  425. /* Turn on both antennas for the station... */
  426. station->sta.rate_n_flags =
  427. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  428. station->current_rate.rate_n_flags =
  429. le16_to_cpu(station->sta.rate_n_flags);
  430. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  431. iwl3945_send_add_station(priv, &station->sta, flags);
  432. return index;
  433. }
  434. /*************** DRIVER STATUS FUNCTIONS *****/
  435. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  436. {
  437. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  438. * set but EXIT_PENDING is not */
  439. return test_bit(STATUS_READY, &priv->status) &&
  440. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  441. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  442. }
  443. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  444. {
  445. return test_bit(STATUS_ALIVE, &priv->status);
  446. }
  447. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  448. {
  449. return test_bit(STATUS_INIT, &priv->status);
  450. }
  451. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  452. {
  453. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  454. test_bit(STATUS_RF_KILL_SW, &priv->status);
  455. }
  456. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  457. {
  458. if (iwl3945_is_rfkill(priv))
  459. return 0;
  460. return iwl3945_is_ready(priv);
  461. }
  462. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  463. #define IWL_CMD(x) case x : return #x
  464. static const char *get_cmd_string(u8 cmd)
  465. {
  466. switch (cmd) {
  467. IWL_CMD(REPLY_ALIVE);
  468. IWL_CMD(REPLY_ERROR);
  469. IWL_CMD(REPLY_RXON);
  470. IWL_CMD(REPLY_RXON_ASSOC);
  471. IWL_CMD(REPLY_QOS_PARAM);
  472. IWL_CMD(REPLY_RXON_TIMING);
  473. IWL_CMD(REPLY_ADD_STA);
  474. IWL_CMD(REPLY_REMOVE_STA);
  475. IWL_CMD(REPLY_REMOVE_ALL_STA);
  476. IWL_CMD(REPLY_3945_RX);
  477. IWL_CMD(REPLY_TX);
  478. IWL_CMD(REPLY_RATE_SCALE);
  479. IWL_CMD(REPLY_LEDS_CMD);
  480. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  481. IWL_CMD(RADAR_NOTIFICATION);
  482. IWL_CMD(REPLY_QUIET_CMD);
  483. IWL_CMD(REPLY_CHANNEL_SWITCH);
  484. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  485. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  486. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  487. IWL_CMD(POWER_TABLE_CMD);
  488. IWL_CMD(PM_SLEEP_NOTIFICATION);
  489. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  490. IWL_CMD(REPLY_SCAN_CMD);
  491. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  492. IWL_CMD(SCAN_START_NOTIFICATION);
  493. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  494. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  495. IWL_CMD(BEACON_NOTIFICATION);
  496. IWL_CMD(REPLY_TX_BEACON);
  497. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  498. IWL_CMD(QUIET_NOTIFICATION);
  499. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  500. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  501. IWL_CMD(REPLY_BT_CONFIG);
  502. IWL_CMD(REPLY_STATISTICS_CMD);
  503. IWL_CMD(STATISTICS_NOTIFICATION);
  504. IWL_CMD(REPLY_CARD_STATE_CMD);
  505. IWL_CMD(CARD_STATE_NOTIFICATION);
  506. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  507. default:
  508. return "UNKNOWN";
  509. }
  510. }
  511. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  512. /**
  513. * iwl3945_enqueue_hcmd - enqueue a uCode command
  514. * @priv: device private data point
  515. * @cmd: a point to the ucode command structure
  516. *
  517. * The function returns < 0 values to indicate the operation is
  518. * failed. On success, it turns the index (> 0) of command in the
  519. * command queue.
  520. */
  521. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  522. {
  523. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  524. struct iwl3945_queue *q = &txq->q;
  525. struct iwl3945_tfd_frame *tfd;
  526. u32 *control_flags;
  527. struct iwl3945_cmd *out_cmd;
  528. u32 idx;
  529. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  530. dma_addr_t phys_addr;
  531. int pad;
  532. u16 count;
  533. int ret;
  534. unsigned long flags;
  535. /* If any of the command structures end up being larger than
  536. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  537. * we will need to increase the size of the TFD entries */
  538. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  539. !(cmd->meta.flags & CMD_SIZE_HUGE));
  540. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  541. IWL_ERROR("No space for Tx\n");
  542. return -ENOSPC;
  543. }
  544. spin_lock_irqsave(&priv->hcmd_lock, flags);
  545. tfd = &txq->bd[q->write_ptr];
  546. memset(tfd, 0, sizeof(*tfd));
  547. control_flags = (u32 *) tfd;
  548. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  549. out_cmd = &txq->cmd[idx];
  550. out_cmd->hdr.cmd = cmd->id;
  551. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  552. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  553. /* At this point, the out_cmd now has all of the incoming cmd
  554. * information */
  555. out_cmd->hdr.flags = 0;
  556. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  557. INDEX_TO_SEQ(q->write_ptr));
  558. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  559. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  560. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  561. offsetof(struct iwl3945_cmd, hdr);
  562. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  563. pad = U32_PAD(cmd->len);
  564. count = TFD_CTL_COUNT_GET(*control_flags);
  565. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  566. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  567. "%d bytes at %d[%d]:%d\n",
  568. get_cmd_string(out_cmd->hdr.cmd),
  569. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  570. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  571. txq->need_update = 1;
  572. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  573. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  574. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  575. return ret ? ret : idx;
  576. }
  577. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  578. {
  579. int ret;
  580. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  581. /* An asynchronous command can not expect an SKB to be set. */
  582. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  583. /* An asynchronous command MUST have a callback. */
  584. BUG_ON(!cmd->meta.u.callback);
  585. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  586. return -EBUSY;
  587. ret = iwl3945_enqueue_hcmd(priv, cmd);
  588. if (ret < 0) {
  589. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  590. get_cmd_string(cmd->id), ret);
  591. return ret;
  592. }
  593. return 0;
  594. }
  595. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  596. {
  597. int cmd_idx;
  598. int ret;
  599. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  600. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  601. /* A synchronous command can not have a callback set. */
  602. BUG_ON(cmd->meta.u.callback != NULL);
  603. if (atomic_xchg(&entry, 1)) {
  604. IWL_ERROR("Error sending %s: Already sending a host command\n",
  605. get_cmd_string(cmd->id));
  606. return -EBUSY;
  607. }
  608. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  609. if (cmd->meta.flags & CMD_WANT_SKB)
  610. cmd->meta.source = &cmd->meta;
  611. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  612. if (cmd_idx < 0) {
  613. ret = cmd_idx;
  614. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  615. get_cmd_string(cmd->id), ret);
  616. goto out;
  617. }
  618. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  619. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  620. HOST_COMPLETE_TIMEOUT);
  621. if (!ret) {
  622. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  623. IWL_ERROR("Error sending %s: time out after %dms.\n",
  624. get_cmd_string(cmd->id),
  625. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  626. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  627. ret = -ETIMEDOUT;
  628. goto cancel;
  629. }
  630. }
  631. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  632. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  633. get_cmd_string(cmd->id));
  634. ret = -ECANCELED;
  635. goto fail;
  636. }
  637. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  638. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  639. get_cmd_string(cmd->id));
  640. ret = -EIO;
  641. goto fail;
  642. }
  643. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  644. IWL_ERROR("Error: Response NULL in '%s'\n",
  645. get_cmd_string(cmd->id));
  646. ret = -EIO;
  647. goto out;
  648. }
  649. ret = 0;
  650. goto out;
  651. cancel:
  652. if (cmd->meta.flags & CMD_WANT_SKB) {
  653. struct iwl3945_cmd *qcmd;
  654. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  655. * TX cmd queue. Otherwise in case the cmd comes
  656. * in later, it will possibly set an invalid
  657. * address (cmd->meta.source). */
  658. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  659. qcmd->meta.flags &= ~CMD_WANT_SKB;
  660. }
  661. fail:
  662. if (cmd->meta.u.skb) {
  663. dev_kfree_skb_any(cmd->meta.u.skb);
  664. cmd->meta.u.skb = NULL;
  665. }
  666. out:
  667. atomic_set(&entry, 0);
  668. return ret;
  669. }
  670. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  671. {
  672. if (cmd->meta.flags & CMD_ASYNC)
  673. return iwl3945_send_cmd_async(priv, cmd);
  674. return iwl3945_send_cmd_sync(priv, cmd);
  675. }
  676. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  677. {
  678. struct iwl3945_host_cmd cmd = {
  679. .id = id,
  680. .len = len,
  681. .data = data,
  682. };
  683. return iwl3945_send_cmd_sync(priv, &cmd);
  684. }
  685. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  686. {
  687. struct iwl3945_host_cmd cmd = {
  688. .id = id,
  689. .len = sizeof(val),
  690. .data = &val,
  691. };
  692. return iwl3945_send_cmd_sync(priv, &cmd);
  693. }
  694. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  695. {
  696. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  697. }
  698. /**
  699. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  700. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  701. * @channel: Any channel valid for the requested phymode
  702. * In addition to setting the staging RXON, priv->phymode is also set.
  703. *
  704. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  705. * in the staging RXON flag structure based on the phymode
  706. */
  707. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, u8 phymode, u16 channel)
  708. {
  709. if (!iwl3945_get_channel_info(priv, phymode, channel)) {
  710. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  711. channel, phymode);
  712. return -EINVAL;
  713. }
  714. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  715. (priv->phymode == phymode))
  716. return 0;
  717. priv->staging_rxon.channel = cpu_to_le16(channel);
  718. if (phymode == MODE_IEEE80211A)
  719. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  720. else
  721. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  722. priv->phymode = phymode;
  723. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
  724. return 0;
  725. }
  726. /**
  727. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  728. *
  729. * NOTE: This is really only useful during development and can eventually
  730. * be #ifdef'd out once the driver is stable and folks aren't actively
  731. * making changes
  732. */
  733. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  734. {
  735. int error = 0;
  736. int counter = 1;
  737. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  738. error |= le32_to_cpu(rxon->flags &
  739. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  740. RXON_FLG_RADAR_DETECT_MSK));
  741. if (error)
  742. IWL_WARNING("check 24G fields %d | %d\n",
  743. counter++, error);
  744. } else {
  745. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  746. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  747. if (error)
  748. IWL_WARNING("check 52 fields %d | %d\n",
  749. counter++, error);
  750. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  751. if (error)
  752. IWL_WARNING("check 52 CCK %d | %d\n",
  753. counter++, error);
  754. }
  755. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  756. if (error)
  757. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  758. /* make sure basic rates 6Mbps and 1Mbps are supported */
  759. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  760. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  761. if (error)
  762. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  763. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  764. if (error)
  765. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  766. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  767. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  768. if (error)
  769. IWL_WARNING("check CCK and short slot %d | %d\n",
  770. counter++, error);
  771. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  772. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  773. if (error)
  774. IWL_WARNING("check CCK & auto detect %d | %d\n",
  775. counter++, error);
  776. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  777. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  778. if (error)
  779. IWL_WARNING("check TGG and auto detect %d | %d\n",
  780. counter++, error);
  781. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  782. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  783. RXON_FLG_ANT_A_MSK)) == 0);
  784. if (error)
  785. IWL_WARNING("check antenna %d %d\n", counter++, error);
  786. if (error)
  787. IWL_WARNING("Tuning to channel %d\n",
  788. le16_to_cpu(rxon->channel));
  789. if (error) {
  790. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  791. return -1;
  792. }
  793. return 0;
  794. }
  795. /**
  796. * iwl3945_full_rxon_required - determine if RXON_ASSOC can be used in RXON commit
  797. * @priv: staging_rxon is compared to active_rxon
  798. *
  799. * If the RXON structure is changing sufficient to require a new
  800. * tune or to clear and reset the RXON_FILTER_ASSOC_MSK then return 1
  801. * to indicate a new tune is required.
  802. */
  803. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  804. {
  805. /* These items are only settable from the full RXON command */
  806. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  807. compare_ether_addr(priv->staging_rxon.bssid_addr,
  808. priv->active_rxon.bssid_addr) ||
  809. compare_ether_addr(priv->staging_rxon.node_addr,
  810. priv->active_rxon.node_addr) ||
  811. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  812. priv->active_rxon.wlap_bssid_addr) ||
  813. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  814. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  815. (priv->staging_rxon.air_propagation !=
  816. priv->active_rxon.air_propagation) ||
  817. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  818. return 1;
  819. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  820. * be updated with the RXON_ASSOC command -- however only some
  821. * flag transitions are allowed using RXON_ASSOC */
  822. /* Check if we are not switching bands */
  823. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  824. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  825. return 1;
  826. /* Check if we are switching association toggle */
  827. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  828. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  829. return 1;
  830. return 0;
  831. }
  832. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  833. {
  834. int rc = 0;
  835. struct iwl3945_rx_packet *res = NULL;
  836. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  837. struct iwl3945_host_cmd cmd = {
  838. .id = REPLY_RXON_ASSOC,
  839. .len = sizeof(rxon_assoc),
  840. .meta.flags = CMD_WANT_SKB,
  841. .data = &rxon_assoc,
  842. };
  843. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  844. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  845. if ((rxon1->flags == rxon2->flags) &&
  846. (rxon1->filter_flags == rxon2->filter_flags) &&
  847. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  848. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  849. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  850. return 0;
  851. }
  852. rxon_assoc.flags = priv->staging_rxon.flags;
  853. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  854. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  855. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  856. rxon_assoc.reserved = 0;
  857. rc = iwl3945_send_cmd_sync(priv, &cmd);
  858. if (rc)
  859. return rc;
  860. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  861. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  862. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  863. rc = -EIO;
  864. }
  865. priv->alloc_rxb_skb--;
  866. dev_kfree_skb_any(cmd.meta.u.skb);
  867. return rc;
  868. }
  869. /**
  870. * iwl3945_commit_rxon - commit staging_rxon to hardware
  871. *
  872. * The RXON command in staging_rxon is committed to the hardware and
  873. * the active_rxon structure is updated with the new data. This
  874. * function correctly transitions out of the RXON_ASSOC_MSK state if
  875. * a HW tune is required based on the RXON structure changes.
  876. */
  877. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  878. {
  879. /* cast away the const for active_rxon in this function */
  880. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  881. int rc = 0;
  882. DECLARE_MAC_BUF(mac);
  883. if (!iwl3945_is_alive(priv))
  884. return -1;
  885. /* always get timestamp with Rx frame */
  886. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  887. /* select antenna */
  888. priv->staging_rxon.flags &=
  889. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  890. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  891. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  892. if (rc) {
  893. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  894. return -EINVAL;
  895. }
  896. /* If we don't need to send a full RXON, we can use
  897. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  898. * and other flags for the current radio configuration. */
  899. if (!iwl3945_full_rxon_required(priv)) {
  900. rc = iwl3945_send_rxon_assoc(priv);
  901. if (rc) {
  902. IWL_ERROR("Error setting RXON_ASSOC "
  903. "configuration (%d).\n", rc);
  904. return rc;
  905. }
  906. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  907. return 0;
  908. }
  909. /* If we are currently associated and the new config requires
  910. * an RXON_ASSOC and the new config wants the associated mask enabled,
  911. * we must clear the associated from the active configuration
  912. * before we apply the new config */
  913. if (iwl3945_is_associated(priv) &&
  914. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  915. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  916. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  917. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  918. sizeof(struct iwl3945_rxon_cmd),
  919. &priv->active_rxon);
  920. /* If the mask clearing failed then we set
  921. * active_rxon back to what it was previously */
  922. if (rc) {
  923. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  924. IWL_ERROR("Error clearing ASSOC_MSK on current "
  925. "configuration (%d).\n", rc);
  926. return rc;
  927. }
  928. }
  929. IWL_DEBUG_INFO("Sending RXON\n"
  930. "* with%s RXON_FILTER_ASSOC_MSK\n"
  931. "* channel = %d\n"
  932. "* bssid = %s\n",
  933. ((priv->staging_rxon.filter_flags &
  934. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  935. le16_to_cpu(priv->staging_rxon.channel),
  936. print_mac(mac, priv->staging_rxon.bssid_addr));
  937. /* Apply the new configuration */
  938. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  939. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  940. if (rc) {
  941. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  942. return rc;
  943. }
  944. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  945. iwl3945_clear_stations_table(priv);
  946. /* If we issue a new RXON command which required a tune then we must
  947. * send a new TXPOWER command or we won't be able to Tx any frames */
  948. rc = iwl3945_hw_reg_send_txpower(priv);
  949. if (rc) {
  950. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  951. return rc;
  952. }
  953. /* Add the broadcast address so we can send broadcast frames */
  954. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  955. IWL_INVALID_STATION) {
  956. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  957. return -EIO;
  958. }
  959. /* If we have set the ASSOC_MSK and we are in BSS mode then
  960. * add the IWL_AP_ID to the station rate table */
  961. if (iwl3945_is_associated(priv) &&
  962. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  963. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  964. == IWL_INVALID_STATION) {
  965. IWL_ERROR("Error adding AP address for transmit.\n");
  966. return -EIO;
  967. }
  968. /* Init the hardware's rate fallback order based on the
  969. * phymode */
  970. rc = iwl3945_init_hw_rate_table(priv);
  971. if (rc) {
  972. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  973. return -EIO;
  974. }
  975. return 0;
  976. }
  977. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  978. {
  979. struct iwl3945_bt_cmd bt_cmd = {
  980. .flags = 3,
  981. .lead_time = 0xAA,
  982. .max_kill = 1,
  983. .kill_ack_mask = 0,
  984. .kill_cts_mask = 0,
  985. };
  986. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  987. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  988. }
  989. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  990. {
  991. int rc = 0;
  992. struct iwl3945_rx_packet *res;
  993. struct iwl3945_host_cmd cmd = {
  994. .id = REPLY_SCAN_ABORT_CMD,
  995. .meta.flags = CMD_WANT_SKB,
  996. };
  997. /* If there isn't a scan actively going on in the hardware
  998. * then we are in between scan bands and not actually
  999. * actively scanning, so don't send the abort command */
  1000. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1001. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1002. return 0;
  1003. }
  1004. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1005. if (rc) {
  1006. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1007. return rc;
  1008. }
  1009. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1010. if (res->u.status != CAN_ABORT_STATUS) {
  1011. /* The scan abort will return 1 for success or
  1012. * 2 for "failure". A failure condition can be
  1013. * due to simply not being in an active scan which
  1014. * can occur if we send the scan abort before we
  1015. * the microcode has notified us that a scan is
  1016. * completed. */
  1017. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1018. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1019. clear_bit(STATUS_SCAN_HW, &priv->status);
  1020. }
  1021. dev_kfree_skb_any(cmd.meta.u.skb);
  1022. return rc;
  1023. }
  1024. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1025. struct iwl3945_cmd *cmd,
  1026. struct sk_buff *skb)
  1027. {
  1028. return 1;
  1029. }
  1030. /*
  1031. * CARD_STATE_CMD
  1032. *
  1033. * Use: Sets the internal card state to enable, disable, or halt
  1034. *
  1035. * When in the 'enable' state the card operates as normal.
  1036. * When in the 'disable' state, the card enters into a low power mode.
  1037. * When in the 'halt' state, the card is shut down and must be fully
  1038. * restarted to come back on.
  1039. */
  1040. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1041. {
  1042. struct iwl3945_host_cmd cmd = {
  1043. .id = REPLY_CARD_STATE_CMD,
  1044. .len = sizeof(u32),
  1045. .data = &flags,
  1046. .meta.flags = meta_flag,
  1047. };
  1048. if (meta_flag & CMD_ASYNC)
  1049. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1050. return iwl3945_send_cmd(priv, &cmd);
  1051. }
  1052. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1053. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1054. {
  1055. struct iwl3945_rx_packet *res = NULL;
  1056. if (!skb) {
  1057. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1058. return 1;
  1059. }
  1060. res = (struct iwl3945_rx_packet *)skb->data;
  1061. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1062. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1063. res->hdr.flags);
  1064. return 1;
  1065. }
  1066. switch (res->u.add_sta.status) {
  1067. case ADD_STA_SUCCESS_MSK:
  1068. break;
  1069. default:
  1070. break;
  1071. }
  1072. /* We didn't cache the SKB; let the caller free it */
  1073. return 1;
  1074. }
  1075. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1076. struct iwl3945_addsta_cmd *sta, u8 flags)
  1077. {
  1078. struct iwl3945_rx_packet *res = NULL;
  1079. int rc = 0;
  1080. struct iwl3945_host_cmd cmd = {
  1081. .id = REPLY_ADD_STA,
  1082. .len = sizeof(struct iwl3945_addsta_cmd),
  1083. .meta.flags = flags,
  1084. .data = sta,
  1085. };
  1086. if (flags & CMD_ASYNC)
  1087. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1088. else
  1089. cmd.meta.flags |= CMD_WANT_SKB;
  1090. rc = iwl3945_send_cmd(priv, &cmd);
  1091. if (rc || (flags & CMD_ASYNC))
  1092. return rc;
  1093. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1094. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1095. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1096. res->hdr.flags);
  1097. rc = -EIO;
  1098. }
  1099. if (rc == 0) {
  1100. switch (res->u.add_sta.status) {
  1101. case ADD_STA_SUCCESS_MSK:
  1102. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1103. break;
  1104. default:
  1105. rc = -EIO;
  1106. IWL_WARNING("REPLY_ADD_STA failed\n");
  1107. break;
  1108. }
  1109. }
  1110. priv->alloc_rxb_skb--;
  1111. dev_kfree_skb_any(cmd.meta.u.skb);
  1112. return rc;
  1113. }
  1114. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1115. struct ieee80211_key_conf *keyconf,
  1116. u8 sta_id)
  1117. {
  1118. unsigned long flags;
  1119. __le16 key_flags = 0;
  1120. switch (keyconf->alg) {
  1121. case ALG_CCMP:
  1122. key_flags |= STA_KEY_FLG_CCMP;
  1123. key_flags |= cpu_to_le16(
  1124. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1125. key_flags &= ~STA_KEY_FLG_INVALID;
  1126. break;
  1127. case ALG_TKIP:
  1128. case ALG_WEP:
  1129. default:
  1130. return -EINVAL;
  1131. }
  1132. spin_lock_irqsave(&priv->sta_lock, flags);
  1133. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1134. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1135. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1136. keyconf->keylen);
  1137. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1138. keyconf->keylen);
  1139. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1140. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1141. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1142. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1143. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1144. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1145. return 0;
  1146. }
  1147. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1148. {
  1149. unsigned long flags;
  1150. spin_lock_irqsave(&priv->sta_lock, flags);
  1151. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1152. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1153. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1154. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1155. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1156. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1157. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1158. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1159. return 0;
  1160. }
  1161. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1162. {
  1163. struct list_head *element;
  1164. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1165. priv->frames_count);
  1166. while (!list_empty(&priv->free_frames)) {
  1167. element = priv->free_frames.next;
  1168. list_del(element);
  1169. kfree(list_entry(element, struct iwl3945_frame, list));
  1170. priv->frames_count--;
  1171. }
  1172. if (priv->frames_count) {
  1173. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1174. priv->frames_count);
  1175. priv->frames_count = 0;
  1176. }
  1177. }
  1178. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1179. {
  1180. struct iwl3945_frame *frame;
  1181. struct list_head *element;
  1182. if (list_empty(&priv->free_frames)) {
  1183. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1184. if (!frame) {
  1185. IWL_ERROR("Could not allocate frame!\n");
  1186. return NULL;
  1187. }
  1188. priv->frames_count++;
  1189. return frame;
  1190. }
  1191. element = priv->free_frames.next;
  1192. list_del(element);
  1193. return list_entry(element, struct iwl3945_frame, list);
  1194. }
  1195. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1196. {
  1197. memset(frame, 0, sizeof(*frame));
  1198. list_add(&frame->list, &priv->free_frames);
  1199. }
  1200. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1201. struct ieee80211_hdr *hdr,
  1202. const u8 *dest, int left)
  1203. {
  1204. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1205. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1206. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1207. return 0;
  1208. if (priv->ibss_beacon->len > left)
  1209. return 0;
  1210. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1211. return priv->ibss_beacon->len;
  1212. }
  1213. static int iwl3945_rate_index_from_plcp(int plcp)
  1214. {
  1215. int i = 0;
  1216. for (i = 0; i < IWL_RATE_COUNT; i++)
  1217. if (iwl3945_rates[i].plcp == plcp)
  1218. return i;
  1219. return -1;
  1220. }
  1221. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1222. {
  1223. u8 i;
  1224. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1225. i = iwl3945_rates[i].next_ieee) {
  1226. if (rate_mask & (1 << i))
  1227. return iwl3945_rates[i].plcp;
  1228. }
  1229. return IWL_RATE_INVALID;
  1230. }
  1231. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1232. {
  1233. struct iwl3945_frame *frame;
  1234. unsigned int frame_size;
  1235. int rc;
  1236. u8 rate;
  1237. frame = iwl3945_get_free_frame(priv);
  1238. if (!frame) {
  1239. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1240. "command.\n");
  1241. return -ENOMEM;
  1242. }
  1243. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1244. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1245. 0xFF0);
  1246. if (rate == IWL_INVALID_RATE)
  1247. rate = IWL_RATE_6M_PLCP;
  1248. } else {
  1249. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1250. if (rate == IWL_INVALID_RATE)
  1251. rate = IWL_RATE_1M_PLCP;
  1252. }
  1253. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1254. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1255. &frame->u.cmd[0]);
  1256. iwl3945_free_frame(priv, frame);
  1257. return rc;
  1258. }
  1259. /******************************************************************************
  1260. *
  1261. * EEPROM related functions
  1262. *
  1263. ******************************************************************************/
  1264. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1265. {
  1266. memcpy(mac, priv->eeprom.mac_address, 6);
  1267. }
  1268. /**
  1269. * iwl3945_eeprom_init - read EEPROM contents
  1270. *
  1271. * Load the EEPROM from adapter into priv->eeprom
  1272. *
  1273. * NOTE: This routine uses the non-debug IO access functions.
  1274. */
  1275. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1276. {
  1277. u16 *e = (u16 *)&priv->eeprom;
  1278. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1279. u32 r;
  1280. int sz = sizeof(priv->eeprom);
  1281. int rc;
  1282. int i;
  1283. u16 addr;
  1284. /* The EEPROM structure has several padding buffers within it
  1285. * and when adding new EEPROM maps is subject to programmer errors
  1286. * which may be very difficult to identify without explicitly
  1287. * checking the resulting size of the eeprom map. */
  1288. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1289. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1290. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1291. return -ENOENT;
  1292. }
  1293. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1294. if (rc < 0) {
  1295. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1296. return -ENOENT;
  1297. }
  1298. /* eeprom is an array of 16bit values */
  1299. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1300. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1301. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1302. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1303. i += IWL_EEPROM_ACCESS_DELAY) {
  1304. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1305. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1306. break;
  1307. udelay(IWL_EEPROM_ACCESS_DELAY);
  1308. }
  1309. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1310. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1311. return -ETIMEDOUT;
  1312. }
  1313. e[addr / 2] = le16_to_cpu(r >> 16);
  1314. }
  1315. return 0;
  1316. }
  1317. /******************************************************************************
  1318. *
  1319. * Misc. internal state and helper functions
  1320. *
  1321. ******************************************************************************/
  1322. #ifdef CONFIG_IWL3945_DEBUG
  1323. /**
  1324. * iwl3945_report_frame - dump frame to syslog during debug sessions
  1325. *
  1326. * hack this function to show different aspects of received frames,
  1327. * including selective frame dumps.
  1328. * group100 parameter selects whether to show 1 out of 100 good frames.
  1329. *
  1330. * TODO: ieee80211_hdr stuff is common to 3945 and 4965, so frame type
  1331. * info output is okay, but some of this stuff (e.g. iwl3945_rx_frame_stats)
  1332. * is 3945-specific and gives bad output for 4965. Need to split the
  1333. * functionality, keep common stuff here.
  1334. */
  1335. void iwl3945_report_frame(struct iwl3945_priv *priv,
  1336. struct iwl3945_rx_packet *pkt,
  1337. struct ieee80211_hdr *header, int group100)
  1338. {
  1339. u32 to_us;
  1340. u32 print_summary = 0;
  1341. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1342. u32 hundred = 0;
  1343. u32 dataframe = 0;
  1344. u16 fc;
  1345. u16 seq_ctl;
  1346. u16 channel;
  1347. u16 phy_flags;
  1348. int rate_sym;
  1349. u16 length;
  1350. u16 status;
  1351. u16 bcn_tmr;
  1352. u32 tsf_low;
  1353. u64 tsf;
  1354. u8 rssi;
  1355. u8 agc;
  1356. u16 sig_avg;
  1357. u16 noise_diff;
  1358. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1359. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1360. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1361. u8 *data = IWL_RX_DATA(pkt);
  1362. /* MAC header */
  1363. fc = le16_to_cpu(header->frame_control);
  1364. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1365. /* metadata */
  1366. channel = le16_to_cpu(rx_hdr->channel);
  1367. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1368. rate_sym = rx_hdr->rate;
  1369. length = le16_to_cpu(rx_hdr->len);
  1370. /* end-of-frame status and timestamp */
  1371. status = le32_to_cpu(rx_end->status);
  1372. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1373. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1374. tsf = le64_to_cpu(rx_end->timestamp);
  1375. /* signal statistics */
  1376. rssi = rx_stats->rssi;
  1377. agc = rx_stats->agc;
  1378. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1379. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1380. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1381. /* if data frame is to us and all is good,
  1382. * (optionally) print summary for only 1 out of every 100 */
  1383. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1384. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1385. dataframe = 1;
  1386. if (!group100)
  1387. print_summary = 1; /* print each frame */
  1388. else if (priv->framecnt_to_us < 100) {
  1389. priv->framecnt_to_us++;
  1390. print_summary = 0;
  1391. } else {
  1392. priv->framecnt_to_us = 0;
  1393. print_summary = 1;
  1394. hundred = 1;
  1395. }
  1396. } else {
  1397. /* print summary for all other frames */
  1398. print_summary = 1;
  1399. }
  1400. if (print_summary) {
  1401. char *title;
  1402. u32 rate;
  1403. if (hundred)
  1404. title = "100Frames";
  1405. else if (fc & IEEE80211_FCTL_RETRY)
  1406. title = "Retry";
  1407. else if (ieee80211_is_assoc_response(fc))
  1408. title = "AscRsp";
  1409. else if (ieee80211_is_reassoc_response(fc))
  1410. title = "RasRsp";
  1411. else if (ieee80211_is_probe_response(fc)) {
  1412. title = "PrbRsp";
  1413. print_dump = 1; /* dump frame contents */
  1414. } else if (ieee80211_is_beacon(fc)) {
  1415. title = "Beacon";
  1416. print_dump = 1; /* dump frame contents */
  1417. } else if (ieee80211_is_atim(fc))
  1418. title = "ATIM";
  1419. else if (ieee80211_is_auth(fc))
  1420. title = "Auth";
  1421. else if (ieee80211_is_deauth(fc))
  1422. title = "DeAuth";
  1423. else if (ieee80211_is_disassoc(fc))
  1424. title = "DisAssoc";
  1425. else
  1426. title = "Frame";
  1427. rate = iwl3945_rate_index_from_plcp(rate_sym);
  1428. if (rate == -1)
  1429. rate = 0;
  1430. else
  1431. rate = iwl3945_rates[rate].ieee / 2;
  1432. /* print frame summary.
  1433. * MAC addresses show just the last byte (for brevity),
  1434. * but you can hack it to show more, if you'd like to. */
  1435. if (dataframe)
  1436. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1437. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1438. title, fc, header->addr1[5],
  1439. length, rssi, channel, rate);
  1440. else {
  1441. /* src/dst addresses assume managed mode */
  1442. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1443. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1444. "phy=0x%02x, chnl=%d\n",
  1445. title, fc, header->addr1[5],
  1446. header->addr3[5], rssi,
  1447. tsf_low - priv->scan_start_tsf,
  1448. phy_flags, channel);
  1449. }
  1450. }
  1451. if (print_dump)
  1452. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  1453. }
  1454. #endif
  1455. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1456. {
  1457. if (priv->hw_setting.shared_virt)
  1458. pci_free_consistent(priv->pci_dev,
  1459. sizeof(struct iwl3945_shared),
  1460. priv->hw_setting.shared_virt,
  1461. priv->hw_setting.shared_phys);
  1462. }
  1463. /**
  1464. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1465. *
  1466. * return : set the bit for each supported rate insert in ie
  1467. */
  1468. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1469. u16 basic_rate, int *left)
  1470. {
  1471. u16 ret_rates = 0, bit;
  1472. int i;
  1473. u8 *cnt = ie;
  1474. u8 *rates = ie + 1;
  1475. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1476. if (bit & supported_rate) {
  1477. ret_rates |= bit;
  1478. rates[*cnt] = iwl3945_rates[i].ieee |
  1479. ((bit & basic_rate) ? 0x80 : 0x00);
  1480. (*cnt)++;
  1481. (*left)--;
  1482. if ((*left <= 0) ||
  1483. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1484. break;
  1485. }
  1486. }
  1487. return ret_rates;
  1488. }
  1489. /**
  1490. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1491. */
  1492. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1493. struct ieee80211_mgmt *frame,
  1494. int left, int is_direct)
  1495. {
  1496. int len = 0;
  1497. u8 *pos = NULL;
  1498. u16 active_rates, ret_rates, cck_rates;
  1499. /* Make sure there is enough space for the probe request,
  1500. * two mandatory IEs and the data */
  1501. left -= 24;
  1502. if (left < 0)
  1503. return 0;
  1504. len += 24;
  1505. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1506. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1507. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1508. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1509. frame->seq_ctrl = 0;
  1510. /* fill in our indirect SSID IE */
  1511. /* ...next IE... */
  1512. left -= 2;
  1513. if (left < 0)
  1514. return 0;
  1515. len += 2;
  1516. pos = &(frame->u.probe_req.variable[0]);
  1517. *pos++ = WLAN_EID_SSID;
  1518. *pos++ = 0;
  1519. /* fill in our direct SSID IE... */
  1520. if (is_direct) {
  1521. /* ...next IE... */
  1522. left -= 2 + priv->essid_len;
  1523. if (left < 0)
  1524. return 0;
  1525. /* ... fill it in... */
  1526. *pos++ = WLAN_EID_SSID;
  1527. *pos++ = priv->essid_len;
  1528. memcpy(pos, priv->essid, priv->essid_len);
  1529. pos += priv->essid_len;
  1530. len += 2 + priv->essid_len;
  1531. }
  1532. /* fill in supported rate */
  1533. /* ...next IE... */
  1534. left -= 2;
  1535. if (left < 0)
  1536. return 0;
  1537. /* ... fill it in... */
  1538. *pos++ = WLAN_EID_SUPP_RATES;
  1539. *pos = 0;
  1540. priv->active_rate = priv->rates_mask;
  1541. active_rates = priv->active_rate;
  1542. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1543. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1544. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1545. priv->active_rate_basic, &left);
  1546. active_rates &= ~ret_rates;
  1547. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1548. priv->active_rate_basic, &left);
  1549. active_rates &= ~ret_rates;
  1550. len += 2 + *pos;
  1551. pos += (*pos) + 1;
  1552. if (active_rates == 0)
  1553. goto fill_end;
  1554. /* fill in supported extended rate */
  1555. /* ...next IE... */
  1556. left -= 2;
  1557. if (left < 0)
  1558. return 0;
  1559. /* ... fill it in... */
  1560. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1561. *pos = 0;
  1562. iwl3945_supported_rate_to_ie(pos, active_rates,
  1563. priv->active_rate_basic, &left);
  1564. if (*pos > 0)
  1565. len += 2 + *pos;
  1566. fill_end:
  1567. return (u16)len;
  1568. }
  1569. /*
  1570. * QoS support
  1571. */
  1572. #ifdef CONFIG_IWL3945_QOS
  1573. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1574. struct iwl3945_qosparam_cmd *qos)
  1575. {
  1576. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1577. sizeof(struct iwl3945_qosparam_cmd), qos);
  1578. }
  1579. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1580. {
  1581. u16 cw_min = 15;
  1582. u16 cw_max = 1023;
  1583. u8 aifs = 2;
  1584. u8 is_legacy = 0;
  1585. unsigned long flags;
  1586. int i;
  1587. spin_lock_irqsave(&priv->lock, flags);
  1588. priv->qos_data.qos_active = 0;
  1589. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1590. if (priv->qos_data.qos_enable)
  1591. priv->qos_data.qos_active = 1;
  1592. if (!(priv->active_rate & 0xfff0)) {
  1593. cw_min = 31;
  1594. is_legacy = 1;
  1595. }
  1596. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1597. if (priv->qos_data.qos_enable)
  1598. priv->qos_data.qos_active = 1;
  1599. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1600. cw_min = 31;
  1601. is_legacy = 1;
  1602. }
  1603. if (priv->qos_data.qos_active)
  1604. aifs = 3;
  1605. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1606. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1607. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1608. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1609. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1610. if (priv->qos_data.qos_active) {
  1611. i = 1;
  1612. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1613. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1614. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1615. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1616. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1617. i = 2;
  1618. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1619. cpu_to_le16((cw_min + 1) / 2 - 1);
  1620. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1621. cpu_to_le16(cw_max);
  1622. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1623. if (is_legacy)
  1624. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1625. cpu_to_le16(6016);
  1626. else
  1627. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1628. cpu_to_le16(3008);
  1629. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1630. i = 3;
  1631. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1632. cpu_to_le16((cw_min + 1) / 4 - 1);
  1633. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1634. cpu_to_le16((cw_max + 1) / 2 - 1);
  1635. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1636. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1637. if (is_legacy)
  1638. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1639. cpu_to_le16(3264);
  1640. else
  1641. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1642. cpu_to_le16(1504);
  1643. } else {
  1644. for (i = 1; i < 4; i++) {
  1645. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1646. cpu_to_le16(cw_min);
  1647. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1648. cpu_to_le16(cw_max);
  1649. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1650. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1651. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1652. }
  1653. }
  1654. IWL_DEBUG_QOS("set QoS to default \n");
  1655. spin_unlock_irqrestore(&priv->lock, flags);
  1656. }
  1657. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1658. {
  1659. unsigned long flags;
  1660. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1661. return;
  1662. if (!priv->qos_data.qos_enable)
  1663. return;
  1664. spin_lock_irqsave(&priv->lock, flags);
  1665. priv->qos_data.def_qos_parm.qos_flags = 0;
  1666. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1667. !priv->qos_data.qos_cap.q_AP.txop_request)
  1668. priv->qos_data.def_qos_parm.qos_flags |=
  1669. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1670. if (priv->qos_data.qos_active)
  1671. priv->qos_data.def_qos_parm.qos_flags |=
  1672. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1673. spin_unlock_irqrestore(&priv->lock, flags);
  1674. if (force || iwl3945_is_associated(priv)) {
  1675. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1676. priv->qos_data.qos_active);
  1677. iwl3945_send_qos_params_command(priv,
  1678. &(priv->qos_data.def_qos_parm));
  1679. }
  1680. }
  1681. #endif /* CONFIG_IWL3945_QOS */
  1682. /*
  1683. * Power management (not Tx power!) functions
  1684. */
  1685. #define MSEC_TO_USEC 1024
  1686. #define NOSLP __constant_cpu_to_le32(0)
  1687. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1688. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1689. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1690. __constant_cpu_to_le32(X1), \
  1691. __constant_cpu_to_le32(X2), \
  1692. __constant_cpu_to_le32(X3), \
  1693. __constant_cpu_to_le32(X4)}
  1694. /* default power management (not Tx power) table values */
  1695. /* for tim 0-10 */
  1696. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1697. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1698. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1699. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1700. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1701. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1702. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1703. };
  1704. /* for tim > 10 */
  1705. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1706. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1707. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1708. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1709. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1710. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1711. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1712. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1713. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1714. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1715. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1716. };
  1717. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1718. {
  1719. int rc = 0, i;
  1720. struct iwl3945_power_mgr *pow_data;
  1721. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1722. u16 pci_pm;
  1723. IWL_DEBUG_POWER("Initialize power \n");
  1724. pow_data = &(priv->power_data);
  1725. memset(pow_data, 0, sizeof(*pow_data));
  1726. pow_data->active_index = IWL_POWER_RANGE_0;
  1727. pow_data->dtim_val = 0xffff;
  1728. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1729. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1730. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1731. if (rc != 0)
  1732. return 0;
  1733. else {
  1734. struct iwl3945_powertable_cmd *cmd;
  1735. IWL_DEBUG_POWER("adjust power command flags\n");
  1736. for (i = 0; i < IWL_POWER_AC; i++) {
  1737. cmd = &pow_data->pwr_range_0[i].cmd;
  1738. if (pci_pm & 0x1)
  1739. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1740. else
  1741. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1742. }
  1743. }
  1744. return rc;
  1745. }
  1746. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1747. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1748. {
  1749. int rc = 0, i;
  1750. u8 skip;
  1751. u32 max_sleep = 0;
  1752. struct iwl3945_power_vec_entry *range;
  1753. u8 period = 0;
  1754. struct iwl3945_power_mgr *pow_data;
  1755. if (mode > IWL_POWER_INDEX_5) {
  1756. IWL_DEBUG_POWER("Error invalid power mode \n");
  1757. return -1;
  1758. }
  1759. pow_data = &(priv->power_data);
  1760. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1761. range = &pow_data->pwr_range_0[0];
  1762. else
  1763. range = &pow_data->pwr_range_1[1];
  1764. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1765. #ifdef IWL_MAC80211_DISABLE
  1766. if (priv->assoc_network != NULL) {
  1767. unsigned long flags;
  1768. period = priv->assoc_network->tim.tim_period;
  1769. }
  1770. #endif /*IWL_MAC80211_DISABLE */
  1771. skip = range[mode].no_dtim;
  1772. if (period == 0) {
  1773. period = 1;
  1774. skip = 0;
  1775. }
  1776. if (skip == 0) {
  1777. max_sleep = period;
  1778. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1779. } else {
  1780. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1781. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1782. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1783. }
  1784. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1785. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1786. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1787. }
  1788. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1789. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1790. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1791. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1792. le32_to_cpu(cmd->sleep_interval[0]),
  1793. le32_to_cpu(cmd->sleep_interval[1]),
  1794. le32_to_cpu(cmd->sleep_interval[2]),
  1795. le32_to_cpu(cmd->sleep_interval[3]),
  1796. le32_to_cpu(cmd->sleep_interval[4]));
  1797. return rc;
  1798. }
  1799. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1800. {
  1801. u32 uninitialized_var(final_mode);
  1802. int rc;
  1803. struct iwl3945_powertable_cmd cmd;
  1804. /* If on battery, set to 3,
  1805. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1806. * else user level */
  1807. switch (mode) {
  1808. case IWL_POWER_BATTERY:
  1809. final_mode = IWL_POWER_INDEX_3;
  1810. break;
  1811. case IWL_POWER_AC:
  1812. final_mode = IWL_POWER_MODE_CAM;
  1813. break;
  1814. default:
  1815. final_mode = mode;
  1816. break;
  1817. }
  1818. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1819. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1820. if (final_mode == IWL_POWER_MODE_CAM)
  1821. clear_bit(STATUS_POWER_PMI, &priv->status);
  1822. else
  1823. set_bit(STATUS_POWER_PMI, &priv->status);
  1824. return rc;
  1825. }
  1826. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1827. {
  1828. /* Filter incoming packets to determine if they are targeted toward
  1829. * this network, discarding packets coming from ourselves */
  1830. switch (priv->iw_mode) {
  1831. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1832. /* packets from our adapter are dropped (echo) */
  1833. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1834. return 0;
  1835. /* {broad,multi}cast packets to our IBSS go through */
  1836. if (is_multicast_ether_addr(header->addr1))
  1837. return !compare_ether_addr(header->addr3, priv->bssid);
  1838. /* packets to our adapter go through */
  1839. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1840. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1841. /* packets from our adapter are dropped (echo) */
  1842. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1843. return 0;
  1844. /* {broad,multi}cast packets to our BSS go through */
  1845. if (is_multicast_ether_addr(header->addr1))
  1846. return !compare_ether_addr(header->addr2, priv->bssid);
  1847. /* packets to our adapter go through */
  1848. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1849. }
  1850. return 1;
  1851. }
  1852. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1853. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1854. {
  1855. switch (status & TX_STATUS_MSK) {
  1856. case TX_STATUS_SUCCESS:
  1857. return "SUCCESS";
  1858. TX_STATUS_ENTRY(SHORT_LIMIT);
  1859. TX_STATUS_ENTRY(LONG_LIMIT);
  1860. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1861. TX_STATUS_ENTRY(MGMNT_ABORT);
  1862. TX_STATUS_ENTRY(NEXT_FRAG);
  1863. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1864. TX_STATUS_ENTRY(DEST_PS);
  1865. TX_STATUS_ENTRY(ABORTED);
  1866. TX_STATUS_ENTRY(BT_RETRY);
  1867. TX_STATUS_ENTRY(STA_INVALID);
  1868. TX_STATUS_ENTRY(FRAG_DROPPED);
  1869. TX_STATUS_ENTRY(TID_DISABLE);
  1870. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1871. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1872. TX_STATUS_ENTRY(TX_LOCKED);
  1873. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1874. }
  1875. return "UNKNOWN";
  1876. }
  1877. /**
  1878. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1879. *
  1880. * NOTE: priv->mutex is not required before calling this function
  1881. */
  1882. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1883. {
  1884. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1885. clear_bit(STATUS_SCANNING, &priv->status);
  1886. return 0;
  1887. }
  1888. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1889. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1890. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1891. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1892. queue_work(priv->workqueue, &priv->abort_scan);
  1893. } else
  1894. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1895. return test_bit(STATUS_SCANNING, &priv->status);
  1896. }
  1897. return 0;
  1898. }
  1899. /**
  1900. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1901. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1902. *
  1903. * NOTE: priv->mutex must be held before calling this function
  1904. */
  1905. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1906. {
  1907. unsigned long now = jiffies;
  1908. int ret;
  1909. ret = iwl3945_scan_cancel(priv);
  1910. if (ret && ms) {
  1911. mutex_unlock(&priv->mutex);
  1912. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1913. test_bit(STATUS_SCANNING, &priv->status))
  1914. msleep(1);
  1915. mutex_lock(&priv->mutex);
  1916. return test_bit(STATUS_SCANNING, &priv->status);
  1917. }
  1918. return ret;
  1919. }
  1920. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1921. {
  1922. /* Reset ieee stats */
  1923. /* We don't reset the net_device_stats (ieee->stats) on
  1924. * re-association */
  1925. priv->last_seq_num = -1;
  1926. priv->last_frag_num = -1;
  1927. priv->last_packet_time = 0;
  1928. iwl3945_scan_cancel(priv);
  1929. }
  1930. #define MAX_UCODE_BEACON_INTERVAL 1024
  1931. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1932. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1933. {
  1934. u16 new_val = 0;
  1935. u16 beacon_factor = 0;
  1936. beacon_factor =
  1937. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1938. / MAX_UCODE_BEACON_INTERVAL;
  1939. new_val = beacon_val / beacon_factor;
  1940. return cpu_to_le16(new_val);
  1941. }
  1942. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1943. {
  1944. u64 interval_tm_unit;
  1945. u64 tsf, result;
  1946. unsigned long flags;
  1947. struct ieee80211_conf *conf = NULL;
  1948. u16 beacon_int = 0;
  1949. conf = ieee80211_get_hw_conf(priv->hw);
  1950. spin_lock_irqsave(&priv->lock, flags);
  1951. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1952. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1953. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1954. tsf = priv->timestamp1;
  1955. tsf = ((tsf << 32) | priv->timestamp0);
  1956. beacon_int = priv->beacon_int;
  1957. spin_unlock_irqrestore(&priv->lock, flags);
  1958. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1959. if (beacon_int == 0) {
  1960. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1961. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1962. } else {
  1963. priv->rxon_timing.beacon_interval =
  1964. cpu_to_le16(beacon_int);
  1965. priv->rxon_timing.beacon_interval =
  1966. iwl3945_adjust_beacon_interval(
  1967. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1968. }
  1969. priv->rxon_timing.atim_window = 0;
  1970. } else {
  1971. priv->rxon_timing.beacon_interval =
  1972. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1973. /* TODO: we need to get atim_window from upper stack
  1974. * for now we set to 0 */
  1975. priv->rxon_timing.atim_window = 0;
  1976. }
  1977. interval_tm_unit =
  1978. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1979. result = do_div(tsf, interval_tm_unit);
  1980. priv->rxon_timing.beacon_init_val =
  1981. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1982. IWL_DEBUG_ASSOC
  1983. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1984. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1985. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1986. le16_to_cpu(priv->rxon_timing.atim_window));
  1987. }
  1988. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1989. {
  1990. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1991. IWL_ERROR("APs don't scan.\n");
  1992. return 0;
  1993. }
  1994. if (!iwl3945_is_ready_rf(priv)) {
  1995. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1996. return -EIO;
  1997. }
  1998. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1999. IWL_DEBUG_SCAN("Scan already in progress.\n");
  2000. return -EAGAIN;
  2001. }
  2002. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2003. IWL_DEBUG_SCAN("Scan request while abort pending. "
  2004. "Queuing.\n");
  2005. return -EAGAIN;
  2006. }
  2007. IWL_DEBUG_INFO("Starting scan...\n");
  2008. priv->scan_bands = 2;
  2009. set_bit(STATUS_SCANNING, &priv->status);
  2010. priv->scan_start = jiffies;
  2011. priv->scan_pass_start = priv->scan_start;
  2012. queue_work(priv->workqueue, &priv->request_scan);
  2013. return 0;
  2014. }
  2015. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  2016. {
  2017. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  2018. if (hw_decrypt)
  2019. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2020. else
  2021. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2022. return 0;
  2023. }
  2024. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode)
  2025. {
  2026. if (phymode == MODE_IEEE80211A) {
  2027. priv->staging_rxon.flags &=
  2028. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2029. | RXON_FLG_CCK_MSK);
  2030. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2031. } else {
  2032. /* Copied from iwl3945_bg_post_associate() */
  2033. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2034. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2035. else
  2036. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2037. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2038. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2039. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2040. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2041. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2042. }
  2043. }
  2044. /*
  2045. * initialize rxon structure with default values from eeprom
  2046. */
  2047. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  2048. {
  2049. const struct iwl3945_channel_info *ch_info;
  2050. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2051. switch (priv->iw_mode) {
  2052. case IEEE80211_IF_TYPE_AP:
  2053. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2054. break;
  2055. case IEEE80211_IF_TYPE_STA:
  2056. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2057. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2058. break;
  2059. case IEEE80211_IF_TYPE_IBSS:
  2060. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2061. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2062. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2063. RXON_FILTER_ACCEPT_GRP_MSK;
  2064. break;
  2065. case IEEE80211_IF_TYPE_MNTR:
  2066. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2067. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2068. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2069. break;
  2070. }
  2071. #if 0
  2072. /* TODO: Figure out when short_preamble would be set and cache from
  2073. * that */
  2074. if (!hw_to_local(priv->hw)->short_preamble)
  2075. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2076. else
  2077. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2078. #endif
  2079. ch_info = iwl3945_get_channel_info(priv, priv->phymode,
  2080. le16_to_cpu(priv->staging_rxon.channel));
  2081. if (!ch_info)
  2082. ch_info = &priv->channel_info[0];
  2083. /*
  2084. * in some case A channels are all non IBSS
  2085. * in this case force B/G channel
  2086. */
  2087. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2088. !(is_channel_ibss(ch_info)))
  2089. ch_info = &priv->channel_info[0];
  2090. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2091. if (is_channel_a_band(ch_info))
  2092. priv->phymode = MODE_IEEE80211A;
  2093. else
  2094. priv->phymode = MODE_IEEE80211G;
  2095. iwl3945_set_flags_for_phymode(priv, priv->phymode);
  2096. priv->staging_rxon.ofdm_basic_rates =
  2097. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2098. priv->staging_rxon.cck_basic_rates =
  2099. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2100. }
  2101. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2102. {
  2103. if (!iwl3945_is_ready_rf(priv))
  2104. return -EAGAIN;
  2105. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2106. const struct iwl3945_channel_info *ch_info;
  2107. ch_info = iwl3945_get_channel_info(priv,
  2108. priv->phymode,
  2109. le16_to_cpu(priv->staging_rxon.channel));
  2110. if (!ch_info || !is_channel_ibss(ch_info)) {
  2111. IWL_ERROR("channel %d not IBSS channel\n",
  2112. le16_to_cpu(priv->staging_rxon.channel));
  2113. return -EINVAL;
  2114. }
  2115. }
  2116. cancel_delayed_work(&priv->scan_check);
  2117. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2118. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2119. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2120. return -EAGAIN;
  2121. }
  2122. priv->iw_mode = mode;
  2123. iwl3945_connection_init_rx_config(priv);
  2124. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2125. iwl3945_clear_stations_table(priv);
  2126. iwl3945_commit_rxon(priv);
  2127. return 0;
  2128. }
  2129. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2130. struct ieee80211_tx_control *ctl,
  2131. struct iwl3945_cmd *cmd,
  2132. struct sk_buff *skb_frag,
  2133. int last_frag)
  2134. {
  2135. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2136. switch (keyinfo->alg) {
  2137. case ALG_CCMP:
  2138. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2139. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2140. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2141. break;
  2142. case ALG_TKIP:
  2143. #if 0
  2144. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2145. if (last_frag)
  2146. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2147. 8);
  2148. else
  2149. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2150. #endif
  2151. break;
  2152. case ALG_WEP:
  2153. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2154. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2155. if (keyinfo->keylen == 13)
  2156. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2157. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2158. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2159. "with key %d\n", ctl->key_idx);
  2160. break;
  2161. default:
  2162. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2163. break;
  2164. }
  2165. }
  2166. /*
  2167. * handle build REPLY_TX command notification.
  2168. */
  2169. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2170. struct iwl3945_cmd *cmd,
  2171. struct ieee80211_tx_control *ctrl,
  2172. struct ieee80211_hdr *hdr,
  2173. int is_unicast, u8 std_id)
  2174. {
  2175. __le16 *qc;
  2176. u16 fc = le16_to_cpu(hdr->frame_control);
  2177. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2178. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2179. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2180. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2181. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2182. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2183. if (ieee80211_is_probe_response(fc) &&
  2184. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2185. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2186. } else {
  2187. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2188. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2189. }
  2190. cmd->cmd.tx.sta_id = std_id;
  2191. if (ieee80211_get_morefrag(hdr))
  2192. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2193. qc = ieee80211_get_qos_ctrl(hdr);
  2194. if (qc) {
  2195. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2196. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2197. } else
  2198. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2199. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2200. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2201. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2202. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2203. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2204. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2205. }
  2206. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2207. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2208. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2209. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2210. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2211. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2212. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2213. else
  2214. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2215. } else
  2216. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2217. cmd->cmd.tx.driver_txop = 0;
  2218. cmd->cmd.tx.tx_flags = tx_flags;
  2219. cmd->cmd.tx.next_frame_len = 0;
  2220. }
  2221. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2222. {
  2223. int sta_id;
  2224. u16 fc = le16_to_cpu(hdr->frame_control);
  2225. /* If this frame is broadcast or not data then use the broadcast
  2226. * station id */
  2227. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2228. is_multicast_ether_addr(hdr->addr1))
  2229. return priv->hw_setting.bcast_sta_id;
  2230. switch (priv->iw_mode) {
  2231. /* If this frame is part of a BSS network (we're a station), then
  2232. * we use the AP's station id */
  2233. case IEEE80211_IF_TYPE_STA:
  2234. return IWL_AP_ID;
  2235. /* If we are an AP, then find the station, or use BCAST */
  2236. case IEEE80211_IF_TYPE_AP:
  2237. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2238. if (sta_id != IWL_INVALID_STATION)
  2239. return sta_id;
  2240. return priv->hw_setting.bcast_sta_id;
  2241. /* If this frame is part of a IBSS network, then we use the
  2242. * target specific station id */
  2243. case IEEE80211_IF_TYPE_IBSS: {
  2244. DECLARE_MAC_BUF(mac);
  2245. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2246. if (sta_id != IWL_INVALID_STATION)
  2247. return sta_id;
  2248. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2249. if (sta_id != IWL_INVALID_STATION)
  2250. return sta_id;
  2251. IWL_DEBUG_DROP("Station %s not in station map. "
  2252. "Defaulting to broadcast...\n",
  2253. print_mac(mac, hdr->addr1));
  2254. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2255. return priv->hw_setting.bcast_sta_id;
  2256. }
  2257. default:
  2258. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2259. return priv->hw_setting.bcast_sta_id;
  2260. }
  2261. }
  2262. /*
  2263. * start REPLY_TX command process
  2264. */
  2265. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2266. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2267. {
  2268. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2269. struct iwl3945_tfd_frame *tfd;
  2270. u32 *control_flags;
  2271. int txq_id = ctl->queue;
  2272. struct iwl3945_tx_queue *txq = NULL;
  2273. struct iwl3945_queue *q = NULL;
  2274. dma_addr_t phys_addr;
  2275. dma_addr_t txcmd_phys;
  2276. struct iwl3945_cmd *out_cmd = NULL;
  2277. u16 len, idx, len_org;
  2278. u8 id, hdr_len, unicast;
  2279. u8 sta_id;
  2280. u16 seq_number = 0;
  2281. u16 fc;
  2282. __le16 *qc;
  2283. u8 wait_write_ptr = 0;
  2284. unsigned long flags;
  2285. int rc;
  2286. spin_lock_irqsave(&priv->lock, flags);
  2287. if (iwl3945_is_rfkill(priv)) {
  2288. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2289. goto drop_unlock;
  2290. }
  2291. if (!priv->interface_id) {
  2292. IWL_DEBUG_DROP("Dropping - !priv->interface_id\n");
  2293. goto drop_unlock;
  2294. }
  2295. if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
  2296. IWL_ERROR("ERROR: No TX rate available.\n");
  2297. goto drop_unlock;
  2298. }
  2299. unicast = !is_multicast_ether_addr(hdr->addr1);
  2300. id = 0;
  2301. fc = le16_to_cpu(hdr->frame_control);
  2302. #ifdef CONFIG_IWL3945_DEBUG
  2303. if (ieee80211_is_auth(fc))
  2304. IWL_DEBUG_TX("Sending AUTH frame\n");
  2305. else if (ieee80211_is_assoc_request(fc))
  2306. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2307. else if (ieee80211_is_reassoc_request(fc))
  2308. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2309. #endif
  2310. if (!iwl3945_is_associated(priv) &&
  2311. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2312. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2313. goto drop_unlock;
  2314. }
  2315. spin_unlock_irqrestore(&priv->lock, flags);
  2316. hdr_len = ieee80211_get_hdrlen(fc);
  2317. sta_id = iwl3945_get_sta_id(priv, hdr);
  2318. if (sta_id == IWL_INVALID_STATION) {
  2319. DECLARE_MAC_BUF(mac);
  2320. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2321. print_mac(mac, hdr->addr1));
  2322. goto drop;
  2323. }
  2324. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2325. qc = ieee80211_get_qos_ctrl(hdr);
  2326. if (qc) {
  2327. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2328. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2329. IEEE80211_SCTL_SEQ;
  2330. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2331. (hdr->seq_ctrl &
  2332. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2333. seq_number += 0x10;
  2334. }
  2335. txq = &priv->txq[txq_id];
  2336. q = &txq->q;
  2337. spin_lock_irqsave(&priv->lock, flags);
  2338. tfd = &txq->bd[q->write_ptr];
  2339. memset(tfd, 0, sizeof(*tfd));
  2340. control_flags = (u32 *) tfd;
  2341. idx = get_cmd_index(q, q->write_ptr, 0);
  2342. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2343. txq->txb[q->write_ptr].skb[0] = skb;
  2344. memcpy(&(txq->txb[q->write_ptr].status.control),
  2345. ctl, sizeof(struct ieee80211_tx_control));
  2346. out_cmd = &txq->cmd[idx];
  2347. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2348. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2349. out_cmd->hdr.cmd = REPLY_TX;
  2350. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2351. INDEX_TO_SEQ(q->write_ptr)));
  2352. /* copy frags header */
  2353. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2354. /* hdr = (struct ieee80211_hdr *)out_cmd->cmd.tx.hdr; */
  2355. len = priv->hw_setting.tx_cmd_len +
  2356. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2357. len_org = len;
  2358. len = (len + 3) & ~3;
  2359. if (len_org != len)
  2360. len_org = 1;
  2361. else
  2362. len_org = 0;
  2363. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2364. offsetof(struct iwl3945_cmd, hdr);
  2365. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2366. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2367. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2368. /* 802.11 null functions have no payload... */
  2369. len = skb->len - hdr_len;
  2370. if (len) {
  2371. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2372. len, PCI_DMA_TODEVICE);
  2373. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2374. }
  2375. /* If there is no payload, then only one TFD is used */
  2376. if (!len)
  2377. *control_flags = TFD_CTL_COUNT_SET(1);
  2378. else
  2379. *control_flags = TFD_CTL_COUNT_SET(2) |
  2380. TFD_CTL_PAD_SET(U32_PAD(len));
  2381. len = (u16)skb->len;
  2382. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2383. /* TODO need this for burst mode later on */
  2384. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2385. /* set is_hcca to 0; it probably will never be implemented */
  2386. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2387. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2388. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2389. if (!ieee80211_get_morefrag(hdr)) {
  2390. txq->need_update = 1;
  2391. if (qc) {
  2392. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2393. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2394. }
  2395. } else {
  2396. wait_write_ptr = 1;
  2397. txq->need_update = 0;
  2398. }
  2399. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2400. sizeof(out_cmd->cmd.tx));
  2401. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2402. ieee80211_get_hdrlen(fc));
  2403. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2404. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2405. spin_unlock_irqrestore(&priv->lock, flags);
  2406. if (rc)
  2407. return rc;
  2408. if ((iwl3945_queue_space(q) < q->high_mark)
  2409. && priv->mac80211_registered) {
  2410. if (wait_write_ptr) {
  2411. spin_lock_irqsave(&priv->lock, flags);
  2412. txq->need_update = 1;
  2413. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2414. spin_unlock_irqrestore(&priv->lock, flags);
  2415. }
  2416. ieee80211_stop_queue(priv->hw, ctl->queue);
  2417. }
  2418. return 0;
  2419. drop_unlock:
  2420. spin_unlock_irqrestore(&priv->lock, flags);
  2421. drop:
  2422. return -1;
  2423. }
  2424. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2425. {
  2426. const struct ieee80211_hw_mode *hw = NULL;
  2427. struct ieee80211_rate *rate;
  2428. int i;
  2429. hw = iwl3945_get_hw_mode(priv, priv->phymode);
  2430. if (!hw) {
  2431. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2432. return;
  2433. }
  2434. priv->active_rate = 0;
  2435. priv->active_rate_basic = 0;
  2436. IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
  2437. hw->mode == MODE_IEEE80211A ?
  2438. 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
  2439. for (i = 0; i < hw->num_rates; i++) {
  2440. rate = &(hw->rates[i]);
  2441. if ((rate->val < IWL_RATE_COUNT) &&
  2442. (rate->flags & IEEE80211_RATE_SUPPORTED)) {
  2443. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
  2444. rate->val, iwl3945_rates[rate->val].plcp,
  2445. (rate->flags & IEEE80211_RATE_BASIC) ?
  2446. "*" : "");
  2447. priv->active_rate |= (1 << rate->val);
  2448. if (rate->flags & IEEE80211_RATE_BASIC)
  2449. priv->active_rate_basic |= (1 << rate->val);
  2450. } else
  2451. IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
  2452. rate->val, iwl3945_rates[rate->val].plcp);
  2453. }
  2454. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2455. priv->active_rate, priv->active_rate_basic);
  2456. /*
  2457. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2458. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2459. * OFDM
  2460. */
  2461. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2462. priv->staging_rxon.cck_basic_rates =
  2463. ((priv->active_rate_basic &
  2464. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2465. else
  2466. priv->staging_rxon.cck_basic_rates =
  2467. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2468. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2469. priv->staging_rxon.ofdm_basic_rates =
  2470. ((priv->active_rate_basic &
  2471. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2472. IWL_FIRST_OFDM_RATE) & 0xFF;
  2473. else
  2474. priv->staging_rxon.ofdm_basic_rates =
  2475. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2476. }
  2477. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2478. {
  2479. unsigned long flags;
  2480. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2481. return;
  2482. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2483. disable_radio ? "OFF" : "ON");
  2484. if (disable_radio) {
  2485. iwl3945_scan_cancel(priv);
  2486. /* FIXME: This is a workaround for AP */
  2487. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2488. spin_lock_irqsave(&priv->lock, flags);
  2489. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2490. CSR_UCODE_SW_BIT_RFKILL);
  2491. spin_unlock_irqrestore(&priv->lock, flags);
  2492. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2493. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2494. }
  2495. return;
  2496. }
  2497. spin_lock_irqsave(&priv->lock, flags);
  2498. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2499. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2500. spin_unlock_irqrestore(&priv->lock, flags);
  2501. /* wake up ucode */
  2502. msleep(10);
  2503. spin_lock_irqsave(&priv->lock, flags);
  2504. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2505. if (!iwl3945_grab_nic_access(priv))
  2506. iwl3945_release_nic_access(priv);
  2507. spin_unlock_irqrestore(&priv->lock, flags);
  2508. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2509. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2510. "disabled by HW switch\n");
  2511. return;
  2512. }
  2513. queue_work(priv->workqueue, &priv->restart);
  2514. return;
  2515. }
  2516. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2517. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2518. {
  2519. u16 fc =
  2520. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2521. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2522. return;
  2523. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2524. return;
  2525. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2526. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2527. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2528. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2529. RX_RES_STATUS_BAD_ICV_MIC)
  2530. stats->flag |= RX_FLAG_MMIC_ERROR;
  2531. case RX_RES_STATUS_SEC_TYPE_WEP:
  2532. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2533. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2534. RX_RES_STATUS_DECRYPT_OK) {
  2535. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2536. stats->flag |= RX_FLAG_DECRYPTED;
  2537. }
  2538. break;
  2539. default:
  2540. break;
  2541. }
  2542. }
  2543. void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
  2544. struct iwl3945_rx_mem_buffer *rxb,
  2545. void *data, short len,
  2546. struct ieee80211_rx_status *stats,
  2547. u16 phy_flags)
  2548. {
  2549. struct iwl3945_rt_rx_hdr *iwl3945_rt;
  2550. /* First cache any information we need before we overwrite
  2551. * the information provided in the skb from the hardware */
  2552. s8 signal = stats->ssi;
  2553. s8 noise = 0;
  2554. int rate = stats->rate;
  2555. u64 tsf = stats->mactime;
  2556. __le16 phy_flags_hw = cpu_to_le16(phy_flags);
  2557. /* We received data from the HW, so stop the watchdog */
  2558. if (len > IWL_RX_BUF_SIZE - sizeof(*iwl3945_rt)) {
  2559. IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
  2560. return;
  2561. }
  2562. /* copy the frame data to write after where the radiotap header goes */
  2563. iwl3945_rt = (void *)rxb->skb->data;
  2564. memmove(iwl3945_rt->payload, data, len);
  2565. iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2566. iwl3945_rt->rt_hdr.it_pad = 0; /* always good to zero */
  2567. /* total header + data */
  2568. iwl3945_rt->rt_hdr.it_len = cpu_to_le16(sizeof(*iwl3945_rt));
  2569. /* Set the size of the skb to the size of the frame */
  2570. skb_put(rxb->skb, sizeof(*iwl3945_rt) + len);
  2571. /* Big bitfield of all the fields we provide in radiotap */
  2572. iwl3945_rt->rt_hdr.it_present =
  2573. cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2574. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2575. (1 << IEEE80211_RADIOTAP_RATE) |
  2576. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2577. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2578. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2579. (1 << IEEE80211_RADIOTAP_ANTENNA));
  2580. /* Zero the flags, we'll add to them as we go */
  2581. iwl3945_rt->rt_flags = 0;
  2582. iwl3945_rt->rt_tsf = cpu_to_le64(tsf);
  2583. /* Convert to dBm */
  2584. iwl3945_rt->rt_dbmsignal = signal;
  2585. iwl3945_rt->rt_dbmnoise = noise;
  2586. /* Convert the channel frequency and set the flags */
  2587. iwl3945_rt->rt_channelMHz = cpu_to_le16(stats->freq);
  2588. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2589. iwl3945_rt->rt_chbitmask =
  2590. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ));
  2591. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2592. iwl3945_rt->rt_chbitmask =
  2593. cpu_to_le16((IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ));
  2594. else /* 802.11g */
  2595. iwl3945_rt->rt_chbitmask =
  2596. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ));
  2597. rate = iwl3945_rate_index_from_plcp(rate);
  2598. if (rate == -1)
  2599. iwl3945_rt->rt_rate = 0;
  2600. else
  2601. iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
  2602. /* antenna number */
  2603. iwl3945_rt->rt_antenna =
  2604. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  2605. /* set the preamble flag if we have it */
  2606. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2607. iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2608. IWL_DEBUG_RX("Rx packet of %d bytes.\n", rxb->skb->len);
  2609. stats->flag |= RX_FLAG_RADIOTAP;
  2610. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2611. rxb->skb = NULL;
  2612. }
  2613. #define IWL_PACKET_RETRY_TIME HZ
  2614. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2615. {
  2616. u16 sc = le16_to_cpu(header->seq_ctrl);
  2617. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2618. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2619. u16 *last_seq, *last_frag;
  2620. unsigned long *last_time;
  2621. switch (priv->iw_mode) {
  2622. case IEEE80211_IF_TYPE_IBSS:{
  2623. struct list_head *p;
  2624. struct iwl3945_ibss_seq *entry = NULL;
  2625. u8 *mac = header->addr2;
  2626. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2627. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2628. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2629. if (!compare_ether_addr(entry->mac, mac))
  2630. break;
  2631. }
  2632. if (p == &priv->ibss_mac_hash[index]) {
  2633. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2634. if (!entry) {
  2635. IWL_ERROR("Cannot malloc new mac entry\n");
  2636. return 0;
  2637. }
  2638. memcpy(entry->mac, mac, ETH_ALEN);
  2639. entry->seq_num = seq;
  2640. entry->frag_num = frag;
  2641. entry->packet_time = jiffies;
  2642. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2643. return 0;
  2644. }
  2645. last_seq = &entry->seq_num;
  2646. last_frag = &entry->frag_num;
  2647. last_time = &entry->packet_time;
  2648. break;
  2649. }
  2650. case IEEE80211_IF_TYPE_STA:
  2651. last_seq = &priv->last_seq_num;
  2652. last_frag = &priv->last_frag_num;
  2653. last_time = &priv->last_packet_time;
  2654. break;
  2655. default:
  2656. return 0;
  2657. }
  2658. if ((*last_seq == seq) &&
  2659. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2660. if (*last_frag == frag)
  2661. goto drop;
  2662. if (*last_frag + 1 != frag)
  2663. /* out-of-order fragment */
  2664. goto drop;
  2665. } else
  2666. *last_seq = seq;
  2667. *last_frag = frag;
  2668. *last_time = jiffies;
  2669. return 0;
  2670. drop:
  2671. return 1;
  2672. }
  2673. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2674. #include "iwl-spectrum.h"
  2675. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2676. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2677. #define TIME_UNIT 1024
  2678. /*
  2679. * extended beacon time format
  2680. * time in usec will be changed into a 32-bit value in 8:24 format
  2681. * the high 1 byte is the beacon counts
  2682. * the lower 3 bytes is the time in usec within one beacon interval
  2683. */
  2684. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2685. {
  2686. u32 quot;
  2687. u32 rem;
  2688. u32 interval = beacon_interval * 1024;
  2689. if (!interval || !usec)
  2690. return 0;
  2691. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2692. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2693. return (quot << 24) + rem;
  2694. }
  2695. /* base is usually what we get from ucode with each received frame,
  2696. * the same as HW timer counter counting down
  2697. */
  2698. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2699. {
  2700. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2701. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2702. u32 interval = beacon_interval * TIME_UNIT;
  2703. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2704. (addon & BEACON_TIME_MASK_HIGH);
  2705. if (base_low > addon_low)
  2706. res += base_low - addon_low;
  2707. else if (base_low < addon_low) {
  2708. res += interval + base_low - addon_low;
  2709. res += (1 << 24);
  2710. } else
  2711. res += (1 << 24);
  2712. return cpu_to_le32(res);
  2713. }
  2714. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2715. struct ieee80211_measurement_params *params,
  2716. u8 type)
  2717. {
  2718. struct iwl3945_spectrum_cmd spectrum;
  2719. struct iwl3945_rx_packet *res;
  2720. struct iwl3945_host_cmd cmd = {
  2721. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2722. .data = (void *)&spectrum,
  2723. .meta.flags = CMD_WANT_SKB,
  2724. };
  2725. u32 add_time = le64_to_cpu(params->start_time);
  2726. int rc;
  2727. int spectrum_resp_status;
  2728. int duration = le16_to_cpu(params->duration);
  2729. if (iwl3945_is_associated(priv))
  2730. add_time =
  2731. iwl3945_usecs_to_beacons(
  2732. le64_to_cpu(params->start_time) - priv->last_tsf,
  2733. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2734. memset(&spectrum, 0, sizeof(spectrum));
  2735. spectrum.channel_count = cpu_to_le16(1);
  2736. spectrum.flags =
  2737. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2738. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2739. cmd.len = sizeof(spectrum);
  2740. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2741. if (iwl3945_is_associated(priv))
  2742. spectrum.start_time =
  2743. iwl3945_add_beacon_time(priv->last_beacon_time,
  2744. add_time,
  2745. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2746. else
  2747. spectrum.start_time = 0;
  2748. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2749. spectrum.channels[0].channel = params->channel;
  2750. spectrum.channels[0].type = type;
  2751. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2752. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2753. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2754. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2755. if (rc)
  2756. return rc;
  2757. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2758. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2759. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2760. rc = -EIO;
  2761. }
  2762. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2763. switch (spectrum_resp_status) {
  2764. case 0: /* Command will be handled */
  2765. if (res->u.spectrum.id != 0xff) {
  2766. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2767. res->u.spectrum.id);
  2768. priv->measurement_status &= ~MEASUREMENT_READY;
  2769. }
  2770. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2771. rc = 0;
  2772. break;
  2773. case 1: /* Command will not be handled */
  2774. rc = -EAGAIN;
  2775. break;
  2776. }
  2777. dev_kfree_skb_any(cmd.meta.u.skb);
  2778. return rc;
  2779. }
  2780. #endif
  2781. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2782. struct iwl3945_tx_info *tx_sta)
  2783. {
  2784. tx_sta->status.ack_signal = 0;
  2785. tx_sta->status.excessive_retries = 0;
  2786. tx_sta->status.queue_length = 0;
  2787. tx_sta->status.queue_number = 0;
  2788. if (in_interrupt())
  2789. ieee80211_tx_status_irqsafe(priv->hw,
  2790. tx_sta->skb[0], &(tx_sta->status));
  2791. else
  2792. ieee80211_tx_status(priv->hw,
  2793. tx_sta->skb[0], &(tx_sta->status));
  2794. tx_sta->skb[0] = NULL;
  2795. }
  2796. /**
  2797. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries no more used by NIC.
  2798. *
  2799. * When FW advances 'R' index, all entries between old and
  2800. * new 'R' index need to be reclaimed. As result, some free space
  2801. * forms. If there is enough free space (> low mark), wake Tx queue.
  2802. */
  2803. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2804. {
  2805. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2806. struct iwl3945_queue *q = &txq->q;
  2807. int nfreed = 0;
  2808. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2809. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2810. "is out of range [0-%d] %d %d.\n", txq_id,
  2811. index, q->n_bd, q->write_ptr, q->read_ptr);
  2812. return 0;
  2813. }
  2814. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2815. q->read_ptr != index;
  2816. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2817. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2818. iwl3945_txstatus_to_ieee(priv,
  2819. &(txq->txb[txq->q.read_ptr]));
  2820. iwl3945_hw_txq_free_tfd(priv, txq);
  2821. } else if (nfreed > 1) {
  2822. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2823. q->write_ptr, q->read_ptr);
  2824. queue_work(priv->workqueue, &priv->restart);
  2825. }
  2826. nfreed++;
  2827. }
  2828. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2829. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2830. priv->mac80211_registered)
  2831. ieee80211_wake_queue(priv->hw, txq_id);
  2832. return nfreed;
  2833. }
  2834. static int iwl3945_is_tx_success(u32 status)
  2835. {
  2836. return (status & 0xFF) == 0x1;
  2837. }
  2838. /******************************************************************************
  2839. *
  2840. * Generic RX handler implementations
  2841. *
  2842. ******************************************************************************/
  2843. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2844. struct iwl3945_rx_mem_buffer *rxb)
  2845. {
  2846. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2847. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2848. int txq_id = SEQ_TO_QUEUE(sequence);
  2849. int index = SEQ_TO_INDEX(sequence);
  2850. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2851. struct ieee80211_tx_status *tx_status;
  2852. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2853. u32 status = le32_to_cpu(tx_resp->status);
  2854. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2855. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2856. "is out of range [0-%d] %d %d\n", txq_id,
  2857. index, txq->q.n_bd, txq->q.write_ptr,
  2858. txq->q.read_ptr);
  2859. return;
  2860. }
  2861. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2862. tx_status->retry_count = tx_resp->failure_frame;
  2863. tx_status->queue_number = status;
  2864. tx_status->queue_length = tx_resp->bt_kill_count;
  2865. tx_status->queue_length |= tx_resp->failure_rts;
  2866. tx_status->flags =
  2867. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2868. tx_status->control.tx_rate = iwl3945_rate_index_from_plcp(tx_resp->rate);
  2869. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2870. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2871. tx_resp->rate, tx_resp->failure_frame);
  2872. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2873. if (index != -1)
  2874. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2875. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2876. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2877. }
  2878. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2879. struct iwl3945_rx_mem_buffer *rxb)
  2880. {
  2881. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2882. struct iwl3945_alive_resp *palive;
  2883. struct delayed_work *pwork;
  2884. palive = &pkt->u.alive_frame;
  2885. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2886. "0x%01X 0x%01X\n",
  2887. palive->is_valid, palive->ver_type,
  2888. palive->ver_subtype);
  2889. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2890. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2891. memcpy(&priv->card_alive_init,
  2892. &pkt->u.alive_frame,
  2893. sizeof(struct iwl3945_init_alive_resp));
  2894. pwork = &priv->init_alive_start;
  2895. } else {
  2896. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2897. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2898. sizeof(struct iwl3945_alive_resp));
  2899. pwork = &priv->alive_start;
  2900. iwl3945_disable_events(priv);
  2901. }
  2902. /* We delay the ALIVE response by 5ms to
  2903. * give the HW RF Kill time to activate... */
  2904. if (palive->is_valid == UCODE_VALID_OK)
  2905. queue_delayed_work(priv->workqueue, pwork,
  2906. msecs_to_jiffies(5));
  2907. else
  2908. IWL_WARNING("uCode did not respond OK.\n");
  2909. }
  2910. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2911. struct iwl3945_rx_mem_buffer *rxb)
  2912. {
  2913. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2914. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2915. return;
  2916. }
  2917. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2918. struct iwl3945_rx_mem_buffer *rxb)
  2919. {
  2920. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2921. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2922. "seq 0x%04X ser 0x%08X\n",
  2923. le32_to_cpu(pkt->u.err_resp.error_type),
  2924. get_cmd_string(pkt->u.err_resp.cmd_id),
  2925. pkt->u.err_resp.cmd_id,
  2926. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2927. le32_to_cpu(pkt->u.err_resp.error_info));
  2928. }
  2929. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2930. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2931. {
  2932. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2933. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2934. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2935. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2936. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2937. rxon->channel = csa->channel;
  2938. priv->staging_rxon.channel = csa->channel;
  2939. }
  2940. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2941. struct iwl3945_rx_mem_buffer *rxb)
  2942. {
  2943. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2944. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2945. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2946. if (!report->state) {
  2947. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2948. "Spectrum Measure Notification: Start\n");
  2949. return;
  2950. }
  2951. memcpy(&priv->measure_report, report, sizeof(*report));
  2952. priv->measurement_status |= MEASUREMENT_READY;
  2953. #endif
  2954. }
  2955. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2956. struct iwl3945_rx_mem_buffer *rxb)
  2957. {
  2958. #ifdef CONFIG_IWL3945_DEBUG
  2959. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2960. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2961. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2962. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2963. #endif
  2964. }
  2965. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2966. struct iwl3945_rx_mem_buffer *rxb)
  2967. {
  2968. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2969. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2970. "notification for %s:\n",
  2971. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2972. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2973. }
  2974. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2975. {
  2976. struct iwl3945_priv *priv =
  2977. container_of(work, struct iwl3945_priv, beacon_update);
  2978. struct sk_buff *beacon;
  2979. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2980. beacon = ieee80211_beacon_get(priv->hw, priv->interface_id, NULL);
  2981. if (!beacon) {
  2982. IWL_ERROR("update beacon failed\n");
  2983. return;
  2984. }
  2985. mutex_lock(&priv->mutex);
  2986. /* new beacon skb is allocated every time; dispose previous.*/
  2987. if (priv->ibss_beacon)
  2988. dev_kfree_skb(priv->ibss_beacon);
  2989. priv->ibss_beacon = beacon;
  2990. mutex_unlock(&priv->mutex);
  2991. iwl3945_send_beacon_cmd(priv);
  2992. }
  2993. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2994. struct iwl3945_rx_mem_buffer *rxb)
  2995. {
  2996. #ifdef CONFIG_IWL3945_DEBUG
  2997. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2998. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2999. u8 rate = beacon->beacon_notify_hdr.rate;
  3000. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  3001. "tsf %d %d rate %d\n",
  3002. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  3003. beacon->beacon_notify_hdr.failure_frame,
  3004. le32_to_cpu(beacon->ibss_mgr_status),
  3005. le32_to_cpu(beacon->high_tsf),
  3006. le32_to_cpu(beacon->low_tsf), rate);
  3007. #endif
  3008. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  3009. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  3010. queue_work(priv->workqueue, &priv->beacon_update);
  3011. }
  3012. /* Service response to REPLY_SCAN_CMD (0x80) */
  3013. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  3014. struct iwl3945_rx_mem_buffer *rxb)
  3015. {
  3016. #ifdef CONFIG_IWL3945_DEBUG
  3017. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3018. struct iwl3945_scanreq_notification *notif =
  3019. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  3020. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3021. #endif
  3022. }
  3023. /* Service SCAN_START_NOTIFICATION (0x82) */
  3024. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  3025. struct iwl3945_rx_mem_buffer *rxb)
  3026. {
  3027. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3028. struct iwl3945_scanstart_notification *notif =
  3029. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  3030. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3031. IWL_DEBUG_SCAN("Scan start: "
  3032. "%d [802.11%s] "
  3033. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3034. notif->channel,
  3035. notif->band ? "bg" : "a",
  3036. notif->tsf_high,
  3037. notif->tsf_low, notif->status, notif->beacon_timer);
  3038. }
  3039. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3040. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  3041. struct iwl3945_rx_mem_buffer *rxb)
  3042. {
  3043. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3044. struct iwl3945_scanresults_notification *notif =
  3045. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  3046. IWL_DEBUG_SCAN("Scan ch.res: "
  3047. "%d [802.11%s] "
  3048. "(TSF: 0x%08X:%08X) - %d "
  3049. "elapsed=%lu usec (%dms since last)\n",
  3050. notif->channel,
  3051. notif->band ? "bg" : "a",
  3052. le32_to_cpu(notif->tsf_high),
  3053. le32_to_cpu(notif->tsf_low),
  3054. le32_to_cpu(notif->statistics[0]),
  3055. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3056. jiffies_to_msecs(elapsed_jiffies
  3057. (priv->last_scan_jiffies, jiffies)));
  3058. priv->last_scan_jiffies = jiffies;
  3059. }
  3060. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3061. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  3062. struct iwl3945_rx_mem_buffer *rxb)
  3063. {
  3064. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3065. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3066. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3067. scan_notif->scanned_channels,
  3068. scan_notif->tsf_low,
  3069. scan_notif->tsf_high, scan_notif->status);
  3070. /* The HW is no longer scanning */
  3071. clear_bit(STATUS_SCAN_HW, &priv->status);
  3072. /* The scan completion notification came in, so kill that timer... */
  3073. cancel_delayed_work(&priv->scan_check);
  3074. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3075. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3076. jiffies_to_msecs(elapsed_jiffies
  3077. (priv->scan_pass_start, jiffies)));
  3078. /* Remove this scanned band from the list
  3079. * of pending bands to scan */
  3080. priv->scan_bands--;
  3081. /* If a request to abort was given, or the scan did not succeed
  3082. * then we reset the scan state machine and terminate,
  3083. * re-queuing another scan if one has been requested */
  3084. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3085. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3086. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3087. } else {
  3088. /* If there are more bands on this scan pass reschedule */
  3089. if (priv->scan_bands > 0)
  3090. goto reschedule;
  3091. }
  3092. priv->last_scan_jiffies = jiffies;
  3093. IWL_DEBUG_INFO("Setting scan to off\n");
  3094. clear_bit(STATUS_SCANNING, &priv->status);
  3095. IWL_DEBUG_INFO("Scan took %dms\n",
  3096. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3097. queue_work(priv->workqueue, &priv->scan_completed);
  3098. return;
  3099. reschedule:
  3100. priv->scan_pass_start = jiffies;
  3101. queue_work(priv->workqueue, &priv->request_scan);
  3102. }
  3103. /* Handle notification from uCode that card's power state is changing
  3104. * due to software, hardware, or critical temperature RFKILL */
  3105. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  3106. struct iwl3945_rx_mem_buffer *rxb)
  3107. {
  3108. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3109. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3110. unsigned long status = priv->status;
  3111. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3112. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3113. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3114. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3115. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3116. if (flags & HW_CARD_DISABLED)
  3117. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3118. else
  3119. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3120. if (flags & SW_CARD_DISABLED)
  3121. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3122. else
  3123. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3124. iwl3945_scan_cancel(priv);
  3125. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3126. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3127. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3128. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3129. queue_work(priv->workqueue, &priv->rf_kill);
  3130. else
  3131. wake_up_interruptible(&priv->wait_command_queue);
  3132. }
  3133. /**
  3134. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  3135. *
  3136. * Setup the RX handlers for each of the reply types sent from the uCode
  3137. * to the host.
  3138. *
  3139. * This function chains into the hardware specific files for them to setup
  3140. * any hardware specific handlers as well.
  3141. */
  3142. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3143. {
  3144. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3145. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3146. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3147. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3148. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3149. iwl3945_rx_spectrum_measure_notif;
  3150. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3151. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3152. iwl3945_rx_pm_debug_statistics_notif;
  3153. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3154. /* NOTE: iwl3945_rx_statistics is different based on whether
  3155. * the build is for the 3945 or the 4965. See the
  3156. * corresponding implementation in iwl-XXXX.c
  3157. *
  3158. * The same handler is used for both the REPLY to a
  3159. * discrete statistics request from the host as well as
  3160. * for the periodic statistics notification from the uCode
  3161. */
  3162. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3163. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3164. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3165. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3166. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3167. iwl3945_rx_scan_results_notif;
  3168. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3169. iwl3945_rx_scan_complete_notif;
  3170. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3171. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3172. /* Setup hardware specific Rx handlers */
  3173. iwl3945_hw_rx_handler_setup(priv);
  3174. }
  3175. /**
  3176. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3177. * @rxb: Rx buffer to reclaim
  3178. *
  3179. * If an Rx buffer has an async callback associated with it the callback
  3180. * will be executed. The attached skb (if present) will only be freed
  3181. * if the callback returns 1
  3182. */
  3183. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3184. struct iwl3945_rx_mem_buffer *rxb)
  3185. {
  3186. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3187. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3188. int txq_id = SEQ_TO_QUEUE(sequence);
  3189. int index = SEQ_TO_INDEX(sequence);
  3190. int huge = sequence & SEQ_HUGE_FRAME;
  3191. int cmd_index;
  3192. struct iwl3945_cmd *cmd;
  3193. /* If a Tx command is being handled and it isn't in the actual
  3194. * command queue then there a command routing bug has been introduced
  3195. * in the queue management code. */
  3196. if (txq_id != IWL_CMD_QUEUE_NUM)
  3197. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3198. txq_id, pkt->hdr.cmd);
  3199. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3200. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3201. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3202. /* Input error checking is done when commands are added to queue. */
  3203. if (cmd->meta.flags & CMD_WANT_SKB) {
  3204. cmd->meta.source->u.skb = rxb->skb;
  3205. rxb->skb = NULL;
  3206. } else if (cmd->meta.u.callback &&
  3207. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3208. rxb->skb = NULL;
  3209. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3210. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3211. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3212. wake_up_interruptible(&priv->wait_command_queue);
  3213. }
  3214. }
  3215. /************************** RX-FUNCTIONS ****************************/
  3216. /*
  3217. * Rx theory of operation
  3218. *
  3219. * The host allocates 32 DMA target addresses and passes the host address
  3220. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3221. * 0 to 31
  3222. *
  3223. * Rx Queue Indexes
  3224. * The host/firmware share two index registers for managing the Rx buffers.
  3225. *
  3226. * The READ index maps to the first position that the firmware may be writing
  3227. * to -- the driver can read up to (but not including) this position and get
  3228. * good data.
  3229. * The READ index is managed by the firmware once the card is enabled.
  3230. *
  3231. * The WRITE index maps to the last position the driver has read from -- the
  3232. * position preceding WRITE is the last slot the firmware can place a packet.
  3233. *
  3234. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3235. * WRITE = READ.
  3236. *
  3237. * During initialization the host sets up the READ queue position to the first
  3238. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3239. *
  3240. * When the firmware places a packet in a buffer it will advance the READ index
  3241. * and fire the RX interrupt. The driver can then query the READ index and
  3242. * process as many packets as possible, moving the WRITE index forward as it
  3243. * resets the Rx queue buffers with new memory.
  3244. *
  3245. * The management in the driver is as follows:
  3246. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3247. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3248. * to replenish the iwl->rxq->rx_free.
  3249. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3250. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3251. * 'processed' and 'read' driver indexes as well)
  3252. * + A received packet is processed and handed to the kernel network stack,
  3253. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3254. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3255. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3256. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3257. * were enough free buffers and RX_STALLED is set it is cleared.
  3258. *
  3259. *
  3260. * Driver sequence:
  3261. *
  3262. * iwl3945_rx_queue_alloc() Allocates rx_free
  3263. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3264. * iwl3945_rx_queue_restock
  3265. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3266. * queue, updates firmware pointers, and updates
  3267. * the WRITE index. If insufficient rx_free buffers
  3268. * are available, schedules iwl3945_rx_replenish
  3269. *
  3270. * -- enable interrupts --
  3271. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3272. * READ INDEX, detaching the SKB from the pool.
  3273. * Moves the packet buffer from queue to rx_used.
  3274. * Calls iwl3945_rx_queue_restock to refill any empty
  3275. * slots.
  3276. * ...
  3277. *
  3278. */
  3279. /**
  3280. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3281. */
  3282. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3283. {
  3284. int s = q->read - q->write;
  3285. if (s <= 0)
  3286. s += RX_QUEUE_SIZE;
  3287. /* keep some buffer to not confuse full and empty queue */
  3288. s -= 2;
  3289. if (s < 0)
  3290. s = 0;
  3291. return s;
  3292. }
  3293. /**
  3294. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3295. *
  3296. * NOTE: This function has 3945 and 4965 specific code sections
  3297. * but is declared in base due to the majority of the
  3298. * implementation being the same (only a numeric constant is
  3299. * different)
  3300. *
  3301. */
  3302. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3303. {
  3304. u32 reg = 0;
  3305. int rc = 0;
  3306. unsigned long flags;
  3307. spin_lock_irqsave(&q->lock, flags);
  3308. if (q->need_update == 0)
  3309. goto exit_unlock;
  3310. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3311. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3312. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3313. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3314. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3315. goto exit_unlock;
  3316. }
  3317. rc = iwl3945_grab_nic_access(priv);
  3318. if (rc)
  3319. goto exit_unlock;
  3320. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3321. q->write & ~0x7);
  3322. iwl3945_release_nic_access(priv);
  3323. } else
  3324. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3325. q->need_update = 0;
  3326. exit_unlock:
  3327. spin_unlock_irqrestore(&q->lock, flags);
  3328. return rc;
  3329. }
  3330. /**
  3331. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer pointer.
  3332. *
  3333. * NOTE: This function has 3945 and 4965 specific code paths in it.
  3334. */
  3335. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3336. dma_addr_t dma_addr)
  3337. {
  3338. return cpu_to_le32((u32)dma_addr);
  3339. }
  3340. /**
  3341. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3342. *
  3343. * If there are slots in the RX queue that need to be restocked,
  3344. * and we have free pre-allocated buffers, fill the ranks as much
  3345. * as we can pulling from rx_free.
  3346. *
  3347. * This moves the 'write' index forward to catch up with 'processed', and
  3348. * also updates the memory address in the firmware to reference the new
  3349. * target buffer.
  3350. */
  3351. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3352. {
  3353. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3354. struct list_head *element;
  3355. struct iwl3945_rx_mem_buffer *rxb;
  3356. unsigned long flags;
  3357. int write, rc;
  3358. spin_lock_irqsave(&rxq->lock, flags);
  3359. write = rxq->write & ~0x7;
  3360. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3361. element = rxq->rx_free.next;
  3362. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3363. list_del(element);
  3364. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3365. rxq->queue[rxq->write] = rxb;
  3366. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3367. rxq->free_count--;
  3368. }
  3369. spin_unlock_irqrestore(&rxq->lock, flags);
  3370. /* If the pre-allocated buffer pool is dropping low, schedule to
  3371. * refill it */
  3372. if (rxq->free_count <= RX_LOW_WATERMARK)
  3373. queue_work(priv->workqueue, &priv->rx_replenish);
  3374. /* If we've added more space for the firmware to place data, tell it */
  3375. if ((write != (rxq->write & ~0x7))
  3376. || (abs(rxq->write - rxq->read) > 7)) {
  3377. spin_lock_irqsave(&rxq->lock, flags);
  3378. rxq->need_update = 1;
  3379. spin_unlock_irqrestore(&rxq->lock, flags);
  3380. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3381. if (rc)
  3382. return rc;
  3383. }
  3384. return 0;
  3385. }
  3386. /**
  3387. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3388. *
  3389. * When moving to rx_free an SKB is allocated for the slot.
  3390. *
  3391. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3392. * This is called as a scheduled work item (except for during initialization)
  3393. */
  3394. void iwl3945_rx_replenish(void *data)
  3395. {
  3396. struct iwl3945_priv *priv = data;
  3397. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3398. struct list_head *element;
  3399. struct iwl3945_rx_mem_buffer *rxb;
  3400. unsigned long flags;
  3401. spin_lock_irqsave(&rxq->lock, flags);
  3402. while (!list_empty(&rxq->rx_used)) {
  3403. element = rxq->rx_used.next;
  3404. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3405. rxb->skb =
  3406. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3407. if (!rxb->skb) {
  3408. if (net_ratelimit())
  3409. printk(KERN_CRIT DRV_NAME
  3410. ": Can not allocate SKB buffers\n");
  3411. /* We don't reschedule replenish work here -- we will
  3412. * call the restock method and if it still needs
  3413. * more buffers it will schedule replenish */
  3414. break;
  3415. }
  3416. priv->alloc_rxb_skb++;
  3417. list_del(element);
  3418. rxb->dma_addr =
  3419. pci_map_single(priv->pci_dev, rxb->skb->data,
  3420. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3421. list_add_tail(&rxb->list, &rxq->rx_free);
  3422. rxq->free_count++;
  3423. }
  3424. spin_unlock_irqrestore(&rxq->lock, flags);
  3425. spin_lock_irqsave(&priv->lock, flags);
  3426. iwl3945_rx_queue_restock(priv);
  3427. spin_unlock_irqrestore(&priv->lock, flags);
  3428. }
  3429. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3430. * If an SKB has been detached, the POOL needs to have it's SKB set to NULL
  3431. * This free routine walks the list of POOL entries and if SKB is set to
  3432. * non NULL it is unmapped and freed
  3433. */
  3434. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3435. {
  3436. int i;
  3437. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3438. if (rxq->pool[i].skb != NULL) {
  3439. pci_unmap_single(priv->pci_dev,
  3440. rxq->pool[i].dma_addr,
  3441. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3442. dev_kfree_skb(rxq->pool[i].skb);
  3443. }
  3444. }
  3445. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3446. rxq->dma_addr);
  3447. rxq->bd = NULL;
  3448. }
  3449. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3450. {
  3451. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3452. struct pci_dev *dev = priv->pci_dev;
  3453. int i;
  3454. spin_lock_init(&rxq->lock);
  3455. INIT_LIST_HEAD(&rxq->rx_free);
  3456. INIT_LIST_HEAD(&rxq->rx_used);
  3457. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3458. if (!rxq->bd)
  3459. return -ENOMEM;
  3460. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3461. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3462. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3463. /* Set us so that we have processed and used all buffers, but have
  3464. * not restocked the Rx queue with fresh buffers */
  3465. rxq->read = rxq->write = 0;
  3466. rxq->free_count = 0;
  3467. rxq->need_update = 0;
  3468. return 0;
  3469. }
  3470. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3471. {
  3472. unsigned long flags;
  3473. int i;
  3474. spin_lock_irqsave(&rxq->lock, flags);
  3475. INIT_LIST_HEAD(&rxq->rx_free);
  3476. INIT_LIST_HEAD(&rxq->rx_used);
  3477. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3478. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3479. /* In the reset function, these buffers may have been allocated
  3480. * to an SKB, so we need to unmap and free potential storage */
  3481. if (rxq->pool[i].skb != NULL) {
  3482. pci_unmap_single(priv->pci_dev,
  3483. rxq->pool[i].dma_addr,
  3484. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3485. priv->alloc_rxb_skb--;
  3486. dev_kfree_skb(rxq->pool[i].skb);
  3487. rxq->pool[i].skb = NULL;
  3488. }
  3489. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3490. }
  3491. /* Set us so that we have processed and used all buffers, but have
  3492. * not restocked the Rx queue with fresh buffers */
  3493. rxq->read = rxq->write = 0;
  3494. rxq->free_count = 0;
  3495. spin_unlock_irqrestore(&rxq->lock, flags);
  3496. }
  3497. /* Convert linear signal-to-noise ratio into dB */
  3498. static u8 ratio2dB[100] = {
  3499. /* 0 1 2 3 4 5 6 7 8 9 */
  3500. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3501. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3502. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3503. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3504. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3505. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3506. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3507. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3508. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3509. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3510. };
  3511. /* Calculates a relative dB value from a ratio of linear
  3512. * (i.e. not dB) signal levels.
  3513. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3514. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3515. {
  3516. /* Anything above 1000:1 just report as 60 dB */
  3517. if (sig_ratio > 1000)
  3518. return 60;
  3519. /* Above 100:1, divide by 10 and use table,
  3520. * add 20 dB to make up for divide by 10 */
  3521. if (sig_ratio > 100)
  3522. return (20 + (int)ratio2dB[sig_ratio/10]);
  3523. /* We shouldn't see this */
  3524. if (sig_ratio < 1)
  3525. return 0;
  3526. /* Use table for ratios 1:1 - 99:1 */
  3527. return (int)ratio2dB[sig_ratio];
  3528. }
  3529. #define PERFECT_RSSI (-20) /* dBm */
  3530. #define WORST_RSSI (-95) /* dBm */
  3531. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3532. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3533. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3534. * about formulas used below. */
  3535. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3536. {
  3537. int sig_qual;
  3538. int degradation = PERFECT_RSSI - rssi_dbm;
  3539. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3540. * as indicator; formula is (signal dbm - noise dbm).
  3541. * SNR at or above 40 is a great signal (100%).
  3542. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3543. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3544. if (noise_dbm) {
  3545. if (rssi_dbm - noise_dbm >= 40)
  3546. return 100;
  3547. else if (rssi_dbm < noise_dbm)
  3548. return 0;
  3549. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3550. /* Else use just the signal level.
  3551. * This formula is a least squares fit of data points collected and
  3552. * compared with a reference system that had a percentage (%) display
  3553. * for signal quality. */
  3554. } else
  3555. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3556. (15 * RSSI_RANGE + 62 * degradation)) /
  3557. (RSSI_RANGE * RSSI_RANGE);
  3558. if (sig_qual > 100)
  3559. sig_qual = 100;
  3560. else if (sig_qual < 1)
  3561. sig_qual = 0;
  3562. return sig_qual;
  3563. }
  3564. /**
  3565. * iwl3945_rx_handle - Main entry function for receiving responses from the uCode
  3566. *
  3567. * Uses the priv->rx_handlers callback function array to invoke
  3568. * the appropriate handlers, including command responses,
  3569. * frame-received notifications, and other notifications.
  3570. */
  3571. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3572. {
  3573. struct iwl3945_rx_mem_buffer *rxb;
  3574. struct iwl3945_rx_packet *pkt;
  3575. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3576. u32 r, i;
  3577. int reclaim;
  3578. unsigned long flags;
  3579. r = iwl3945_hw_get_rx_read(priv);
  3580. i = rxq->read;
  3581. /* Rx interrupt, but nothing sent from uCode */
  3582. if (i == r)
  3583. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3584. while (i != r) {
  3585. rxb = rxq->queue[i];
  3586. /* If an RXB doesn't have a queue slot associated with it
  3587. * then a bug has been introduced in the queue refilling
  3588. * routines -- catch it here */
  3589. BUG_ON(rxb == NULL);
  3590. rxq->queue[i] = NULL;
  3591. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3592. IWL_RX_BUF_SIZE,
  3593. PCI_DMA_FROMDEVICE);
  3594. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3595. /* Reclaim a command buffer only if this packet is a response
  3596. * to a (driver-originated) command.
  3597. * If the packet (e.g. Rx frame) originated from uCode,
  3598. * there is no command buffer to reclaim.
  3599. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3600. * but apparently a few don't get set; catch them here. */
  3601. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3602. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3603. (pkt->hdr.cmd != REPLY_TX);
  3604. /* Based on type of command response or notification,
  3605. * handle those that need handling via function in
  3606. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3607. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3608. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3609. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3610. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3611. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3612. } else {
  3613. /* No handling needed */
  3614. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3615. "r %d i %d No handler needed for %s, 0x%02x\n",
  3616. r, i, get_cmd_string(pkt->hdr.cmd),
  3617. pkt->hdr.cmd);
  3618. }
  3619. if (reclaim) {
  3620. /* Invoke any callbacks, transfer the skb to caller,
  3621. * and fire off the (possibly) blocking iwl3945_send_cmd()
  3622. * as we reclaim the driver command queue */
  3623. if (rxb && rxb->skb)
  3624. iwl3945_tx_cmd_complete(priv, rxb);
  3625. else
  3626. IWL_WARNING("Claim null rxb?\n");
  3627. }
  3628. /* For now we just don't re-use anything. We can tweak this
  3629. * later to try and re-use notification packets and SKBs that
  3630. * fail to Rx correctly */
  3631. if (rxb->skb != NULL) {
  3632. priv->alloc_rxb_skb--;
  3633. dev_kfree_skb_any(rxb->skb);
  3634. rxb->skb = NULL;
  3635. }
  3636. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3637. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3638. spin_lock_irqsave(&rxq->lock, flags);
  3639. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3640. spin_unlock_irqrestore(&rxq->lock, flags);
  3641. i = (i + 1) & RX_QUEUE_MASK;
  3642. }
  3643. /* Backtrack one entry */
  3644. priv->rxq.read = i;
  3645. iwl3945_rx_queue_restock(priv);
  3646. }
  3647. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3648. struct iwl3945_tx_queue *txq)
  3649. {
  3650. u32 reg = 0;
  3651. int rc = 0;
  3652. int txq_id = txq->q.id;
  3653. if (txq->need_update == 0)
  3654. return rc;
  3655. /* if we're trying to save power */
  3656. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3657. /* wake up nic if it's powered down ...
  3658. * uCode will wake up, and interrupt us again, so next
  3659. * time we'll skip this part. */
  3660. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3661. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3662. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3663. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3664. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3665. return rc;
  3666. }
  3667. /* restore this queue's parameters in nic hardware. */
  3668. rc = iwl3945_grab_nic_access(priv);
  3669. if (rc)
  3670. return rc;
  3671. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3672. txq->q.write_ptr | (txq_id << 8));
  3673. iwl3945_release_nic_access(priv);
  3674. /* else not in power-save mode, uCode will never sleep when we're
  3675. * trying to tx (during RFKILL, we're not trying to tx). */
  3676. } else
  3677. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3678. txq->q.write_ptr | (txq_id << 8));
  3679. txq->need_update = 0;
  3680. return rc;
  3681. }
  3682. #ifdef CONFIG_IWL3945_DEBUG
  3683. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3684. {
  3685. DECLARE_MAC_BUF(mac);
  3686. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3687. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3688. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3689. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3690. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3691. le32_to_cpu(rxon->filter_flags));
  3692. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3693. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3694. rxon->ofdm_basic_rates);
  3695. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3696. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3697. print_mac(mac, rxon->node_addr));
  3698. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3699. print_mac(mac, rxon->bssid_addr));
  3700. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3701. }
  3702. #endif
  3703. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3704. {
  3705. IWL_DEBUG_ISR("Enabling interrupts\n");
  3706. set_bit(STATUS_INT_ENABLED, &priv->status);
  3707. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3708. }
  3709. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3710. {
  3711. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3712. /* disable interrupts from uCode/NIC to host */
  3713. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3714. /* acknowledge/clear/reset any interrupts still pending
  3715. * from uCode or flow handler (Rx/Tx DMA) */
  3716. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3717. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3718. IWL_DEBUG_ISR("Disabled interrupts\n");
  3719. }
  3720. static const char *desc_lookup(int i)
  3721. {
  3722. switch (i) {
  3723. case 1:
  3724. return "FAIL";
  3725. case 2:
  3726. return "BAD_PARAM";
  3727. case 3:
  3728. return "BAD_CHECKSUM";
  3729. case 4:
  3730. return "NMI_INTERRUPT";
  3731. case 5:
  3732. return "SYSASSERT";
  3733. case 6:
  3734. return "FATAL_ERROR";
  3735. }
  3736. return "UNKNOWN";
  3737. }
  3738. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3739. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3740. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3741. {
  3742. u32 i;
  3743. u32 desc, time, count, base, data1;
  3744. u32 blink1, blink2, ilink1, ilink2;
  3745. int rc;
  3746. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3747. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3748. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3749. return;
  3750. }
  3751. rc = iwl3945_grab_nic_access(priv);
  3752. if (rc) {
  3753. IWL_WARNING("Can not read from adapter at this time.\n");
  3754. return;
  3755. }
  3756. count = iwl3945_read_targ_mem(priv, base);
  3757. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3758. IWL_ERROR("Start IWL Error Log Dump:\n");
  3759. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  3760. priv->status, priv->config, count);
  3761. }
  3762. IWL_ERROR("Desc Time asrtPC blink2 "
  3763. "ilink1 nmiPC Line\n");
  3764. for (i = ERROR_START_OFFSET;
  3765. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3766. i += ERROR_ELEM_SIZE) {
  3767. desc = iwl3945_read_targ_mem(priv, base + i);
  3768. time =
  3769. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3770. blink1 =
  3771. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3772. blink2 =
  3773. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3774. ilink1 =
  3775. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3776. ilink2 =
  3777. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3778. data1 =
  3779. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3780. IWL_ERROR
  3781. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3782. desc_lookup(desc), desc, time, blink1, blink2,
  3783. ilink1, ilink2, data1);
  3784. }
  3785. iwl3945_release_nic_access(priv);
  3786. }
  3787. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3788. /**
  3789. * iwl3945_print_event_log - Dump error event log to syslog
  3790. *
  3791. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3792. */
  3793. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3794. u32 num_events, u32 mode)
  3795. {
  3796. u32 i;
  3797. u32 base; /* SRAM byte address of event log header */
  3798. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3799. u32 ptr; /* SRAM byte address of log data */
  3800. u32 ev, time, data; /* event log data */
  3801. if (num_events == 0)
  3802. return;
  3803. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3804. if (mode == 0)
  3805. event_size = 2 * sizeof(u32);
  3806. else
  3807. event_size = 3 * sizeof(u32);
  3808. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3809. /* "time" is actually "data" for mode 0 (no timestamp).
  3810. * place event id # at far right for easier visual parsing. */
  3811. for (i = 0; i < num_events; i++) {
  3812. ev = iwl3945_read_targ_mem(priv, ptr);
  3813. ptr += sizeof(u32);
  3814. time = iwl3945_read_targ_mem(priv, ptr);
  3815. ptr += sizeof(u32);
  3816. if (mode == 0)
  3817. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3818. else {
  3819. data = iwl3945_read_targ_mem(priv, ptr);
  3820. ptr += sizeof(u32);
  3821. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3822. }
  3823. }
  3824. }
  3825. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3826. {
  3827. int rc;
  3828. u32 base; /* SRAM byte address of event log header */
  3829. u32 capacity; /* event log capacity in # entries */
  3830. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3831. u32 num_wraps; /* # times uCode wrapped to top of log */
  3832. u32 next_entry; /* index of next entry to be written by uCode */
  3833. u32 size; /* # entries that we'll print */
  3834. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3835. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3836. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3837. return;
  3838. }
  3839. rc = iwl3945_grab_nic_access(priv);
  3840. if (rc) {
  3841. IWL_WARNING("Can not read from adapter at this time.\n");
  3842. return;
  3843. }
  3844. /* event log header */
  3845. capacity = iwl3945_read_targ_mem(priv, base);
  3846. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3847. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3848. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3849. size = num_wraps ? capacity : next_entry;
  3850. /* bail out if nothing in log */
  3851. if (size == 0) {
  3852. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3853. iwl3945_release_nic_access(priv);
  3854. return;
  3855. }
  3856. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3857. size, num_wraps);
  3858. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3859. * i.e the next one that uCode would fill. */
  3860. if (num_wraps)
  3861. iwl3945_print_event_log(priv, next_entry,
  3862. capacity - next_entry, mode);
  3863. /* (then/else) start at top of log */
  3864. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3865. iwl3945_release_nic_access(priv);
  3866. }
  3867. /**
  3868. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3869. */
  3870. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3871. {
  3872. /* Set the FW error flag -- cleared on iwl3945_down */
  3873. set_bit(STATUS_FW_ERROR, &priv->status);
  3874. /* Cancel currently queued command. */
  3875. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3876. #ifdef CONFIG_IWL3945_DEBUG
  3877. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3878. iwl3945_dump_nic_error_log(priv);
  3879. iwl3945_dump_nic_event_log(priv);
  3880. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3881. }
  3882. #endif
  3883. wake_up_interruptible(&priv->wait_command_queue);
  3884. /* Keep the restart process from trying to send host
  3885. * commands by clearing the INIT status bit */
  3886. clear_bit(STATUS_READY, &priv->status);
  3887. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3888. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3889. "Restarting adapter due to uCode error.\n");
  3890. if (iwl3945_is_associated(priv)) {
  3891. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3892. sizeof(priv->recovery_rxon));
  3893. priv->error_recovering = 1;
  3894. }
  3895. queue_work(priv->workqueue, &priv->restart);
  3896. }
  3897. }
  3898. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3899. {
  3900. unsigned long flags;
  3901. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3902. sizeof(priv->staging_rxon));
  3903. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3904. iwl3945_commit_rxon(priv);
  3905. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3906. spin_lock_irqsave(&priv->lock, flags);
  3907. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3908. priv->error_recovering = 0;
  3909. spin_unlock_irqrestore(&priv->lock, flags);
  3910. }
  3911. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3912. {
  3913. u32 inta, handled = 0;
  3914. u32 inta_fh;
  3915. unsigned long flags;
  3916. #ifdef CONFIG_IWL3945_DEBUG
  3917. u32 inta_mask;
  3918. #endif
  3919. spin_lock_irqsave(&priv->lock, flags);
  3920. /* Ack/clear/reset pending uCode interrupts.
  3921. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3922. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3923. inta = iwl3945_read32(priv, CSR_INT);
  3924. iwl3945_write32(priv, CSR_INT, inta);
  3925. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3926. * Any new interrupts that happen after this, either while we're
  3927. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3928. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3929. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3930. #ifdef CONFIG_IWL3945_DEBUG
  3931. if (iwl3945_debug_level & IWL_DL_ISR) {
  3932. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3933. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3934. inta, inta_mask, inta_fh);
  3935. }
  3936. #endif
  3937. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3938. * atomic, make sure that inta covers all the interrupts that
  3939. * we've discovered, even if FH interrupt came in just after
  3940. * reading CSR_INT. */
  3941. if (inta_fh & CSR_FH_INT_RX_MASK)
  3942. inta |= CSR_INT_BIT_FH_RX;
  3943. if (inta_fh & CSR_FH_INT_TX_MASK)
  3944. inta |= CSR_INT_BIT_FH_TX;
  3945. /* Now service all interrupt bits discovered above. */
  3946. if (inta & CSR_INT_BIT_HW_ERR) {
  3947. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3948. /* Tell the device to stop sending interrupts */
  3949. iwl3945_disable_interrupts(priv);
  3950. iwl3945_irq_handle_error(priv);
  3951. handled |= CSR_INT_BIT_HW_ERR;
  3952. spin_unlock_irqrestore(&priv->lock, flags);
  3953. return;
  3954. }
  3955. #ifdef CONFIG_IWL3945_DEBUG
  3956. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3957. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3958. if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
  3959. IWL_DEBUG_ISR("Microcode started or stopped.\n");
  3960. /* Alive notification via Rx interrupt will do the real work */
  3961. if (inta & CSR_INT_BIT_ALIVE)
  3962. IWL_DEBUG_ISR("Alive interrupt\n");
  3963. }
  3964. #endif
  3965. /* Safely ignore these bits for debug checks below */
  3966. inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
  3967. /* HW RF KILL switch toggled (4965 only) */
  3968. if (inta & CSR_INT_BIT_RF_KILL) {
  3969. int hw_rf_kill = 0;
  3970. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3971. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3972. hw_rf_kill = 1;
  3973. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3974. "RF_KILL bit toggled to %s.\n",
  3975. hw_rf_kill ? "disable radio":"enable radio");
  3976. /* Queue restart only if RF_KILL switch was set to "kill"
  3977. * when we loaded driver, and is now set to "enable".
  3978. * After we're Alive, RF_KILL gets handled by
  3979. * iwl_rx_card_state_notif() */
  3980. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3981. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3982. queue_work(priv->workqueue, &priv->restart);
  3983. }
  3984. handled |= CSR_INT_BIT_RF_KILL;
  3985. }
  3986. /* Chip got too hot and stopped itself (4965 only) */
  3987. if (inta & CSR_INT_BIT_CT_KILL) {
  3988. IWL_ERROR("Microcode CT kill error detected.\n");
  3989. handled |= CSR_INT_BIT_CT_KILL;
  3990. }
  3991. /* Error detected by uCode */
  3992. if (inta & CSR_INT_BIT_SW_ERR) {
  3993. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3994. inta);
  3995. iwl3945_irq_handle_error(priv);
  3996. handled |= CSR_INT_BIT_SW_ERR;
  3997. }
  3998. /* uCode wakes up after power-down sleep */
  3999. if (inta & CSR_INT_BIT_WAKEUP) {
  4000. IWL_DEBUG_ISR("Wakeup interrupt\n");
  4001. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  4002. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  4003. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  4004. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  4005. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  4006. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  4007. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  4008. handled |= CSR_INT_BIT_WAKEUP;
  4009. }
  4010. /* All uCode command responses, including Tx command responses,
  4011. * Rx "responses" (frame-received notification), and other
  4012. * notifications from uCode come through here*/
  4013. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  4014. iwl3945_rx_handle(priv);
  4015. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  4016. }
  4017. if (inta & CSR_INT_BIT_FH_TX) {
  4018. IWL_DEBUG_ISR("Tx interrupt\n");
  4019. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  4020. if (!iwl3945_grab_nic_access(priv)) {
  4021. iwl3945_write_direct32(priv,
  4022. FH_TCSR_CREDIT
  4023. (ALM_FH_SRVC_CHNL), 0x0);
  4024. iwl3945_release_nic_access(priv);
  4025. }
  4026. handled |= CSR_INT_BIT_FH_TX;
  4027. }
  4028. if (inta & ~handled)
  4029. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4030. if (inta & ~CSR_INI_SET_MASK) {
  4031. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4032. inta & ~CSR_INI_SET_MASK);
  4033. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4034. }
  4035. /* Re-enable all interrupts */
  4036. iwl3945_enable_interrupts(priv);
  4037. #ifdef CONFIG_IWL3945_DEBUG
  4038. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4039. inta = iwl3945_read32(priv, CSR_INT);
  4040. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4041. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4042. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4043. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4044. }
  4045. #endif
  4046. spin_unlock_irqrestore(&priv->lock, flags);
  4047. }
  4048. static irqreturn_t iwl3945_isr(int irq, void *data)
  4049. {
  4050. struct iwl3945_priv *priv = data;
  4051. u32 inta, inta_mask;
  4052. u32 inta_fh;
  4053. if (!priv)
  4054. return IRQ_NONE;
  4055. spin_lock(&priv->lock);
  4056. /* Disable (but don't clear!) interrupts here to avoid
  4057. * back-to-back ISRs and sporadic interrupts from our NIC.
  4058. * If we have something to service, the tasklet will re-enable ints.
  4059. * If we *don't* have something, we'll re-enable before leaving here. */
  4060. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  4061. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  4062. /* Discover which interrupts are active/pending */
  4063. inta = iwl3945_read32(priv, CSR_INT);
  4064. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4065. /* Ignore interrupt if there's nothing in NIC to service.
  4066. * This may be due to IRQ shared with another device,
  4067. * or due to sporadic interrupts thrown from our NIC. */
  4068. if (!inta && !inta_fh) {
  4069. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4070. goto none;
  4071. }
  4072. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4073. /* Hardware disappeared */
  4074. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4075. goto unplugged;
  4076. }
  4077. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4078. inta, inta_mask, inta_fh);
  4079. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  4080. tasklet_schedule(&priv->irq_tasklet);
  4081. unplugged:
  4082. spin_unlock(&priv->lock);
  4083. return IRQ_HANDLED;
  4084. none:
  4085. /* re-enable interrupts here since we don't have anything to service. */
  4086. iwl3945_enable_interrupts(priv);
  4087. spin_unlock(&priv->lock);
  4088. return IRQ_NONE;
  4089. }
  4090. /************************** EEPROM BANDS ****************************
  4091. *
  4092. * The iwl3945_eeprom_band definitions below provide the mapping from the
  4093. * EEPROM contents to the specific channel number supported for each
  4094. * band.
  4095. *
  4096. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4097. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4098. * The specific geography and calibration information for that channel
  4099. * is contained in the eeprom map itself.
  4100. *
  4101. * During init, we copy the eeprom information and channel map
  4102. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4103. *
  4104. * channel_map_24/52 provides the index in the channel_info array for a
  4105. * given channel. We have to have two separate maps as there is channel
  4106. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4107. * band_2
  4108. *
  4109. * A value of 0xff stored in the channel_map indicates that the channel
  4110. * is not supported by the hardware at all.
  4111. *
  4112. * A value of 0xfe in the channel_map indicates that the channel is not
  4113. * valid for Tx with the current hardware. This means that
  4114. * while the system can tune and receive on a given channel, it may not
  4115. * be able to associate or transmit any frames on that
  4116. * channel. There is no corresponding channel information for that
  4117. * entry.
  4118. *
  4119. *********************************************************************/
  4120. /* 2.4 GHz */
  4121. static const u8 iwl3945_eeprom_band_1[14] = {
  4122. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4123. };
  4124. /* 5.2 GHz bands */
  4125. static const u8 iwl3945_eeprom_band_2[] = {
  4126. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4127. };
  4128. static const u8 iwl3945_eeprom_band_3[] = { /* 5205-5320MHz */
  4129. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4130. };
  4131. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4132. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4133. };
  4134. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4135. 145, 149, 153, 157, 161, 165
  4136. };
  4137. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4138. int *eeprom_ch_count,
  4139. const struct iwl3945_eeprom_channel
  4140. **eeprom_ch_info,
  4141. const u8 **eeprom_ch_index)
  4142. {
  4143. switch (band) {
  4144. case 1: /* 2.4GHz band */
  4145. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4146. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4147. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4148. break;
  4149. case 2: /* 5.2GHz band */
  4150. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4151. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4152. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4153. break;
  4154. case 3: /* 5.2GHz band */
  4155. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4156. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4157. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4158. break;
  4159. case 4: /* 5.2GHz band */
  4160. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4161. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4162. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4163. break;
  4164. case 5: /* 5.2GHz band */
  4165. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4166. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4167. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4168. break;
  4169. default:
  4170. BUG();
  4171. return;
  4172. }
  4173. }
  4174. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4175. int phymode, u16 channel)
  4176. {
  4177. int i;
  4178. switch (phymode) {
  4179. case MODE_IEEE80211A:
  4180. for (i = 14; i < priv->channel_count; i++) {
  4181. if (priv->channel_info[i].channel == channel)
  4182. return &priv->channel_info[i];
  4183. }
  4184. break;
  4185. case MODE_IEEE80211B:
  4186. case MODE_IEEE80211G:
  4187. if (channel >= 1 && channel <= 14)
  4188. return &priv->channel_info[channel - 1];
  4189. break;
  4190. }
  4191. return NULL;
  4192. }
  4193. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4194. ? # x " " : "")
  4195. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4196. {
  4197. int eeprom_ch_count = 0;
  4198. const u8 *eeprom_ch_index = NULL;
  4199. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4200. int band, ch;
  4201. struct iwl3945_channel_info *ch_info;
  4202. if (priv->channel_count) {
  4203. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4204. return 0;
  4205. }
  4206. if (priv->eeprom.version < 0x2f) {
  4207. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4208. priv->eeprom.version);
  4209. return -EINVAL;
  4210. }
  4211. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4212. priv->channel_count =
  4213. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4214. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4215. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4216. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4217. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4218. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4219. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4220. priv->channel_count, GFP_KERNEL);
  4221. if (!priv->channel_info) {
  4222. IWL_ERROR("Could not allocate channel_info\n");
  4223. priv->channel_count = 0;
  4224. return -ENOMEM;
  4225. }
  4226. ch_info = priv->channel_info;
  4227. /* Loop through the 5 EEPROM bands adding them in order to the
  4228. * channel map we maintain (that contains additional information than
  4229. * what just in the EEPROM) */
  4230. for (band = 1; band <= 5; band++) {
  4231. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4232. &eeprom_ch_info, &eeprom_ch_index);
  4233. /* Loop through each band adding each of the channels */
  4234. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4235. ch_info->channel = eeprom_ch_index[ch];
  4236. ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
  4237. MODE_IEEE80211A;
  4238. /* permanently store EEPROM's channel regulatory flags
  4239. * and max power in channel info database. */
  4240. ch_info->eeprom = eeprom_ch_info[ch];
  4241. /* Copy the run-time flags so they are there even on
  4242. * invalid channels */
  4243. ch_info->flags = eeprom_ch_info[ch].flags;
  4244. if (!(is_channel_valid(ch_info))) {
  4245. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4246. "No traffic\n",
  4247. ch_info->channel,
  4248. ch_info->flags,
  4249. is_channel_a_band(ch_info) ?
  4250. "5.2" : "2.4");
  4251. ch_info++;
  4252. continue;
  4253. }
  4254. /* Initialize regulatory-based run-time data */
  4255. ch_info->max_power_avg = ch_info->curr_txpow =
  4256. eeprom_ch_info[ch].max_power_avg;
  4257. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4258. ch_info->min_power = 0;
  4259. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4260. " %ddBm): Ad-Hoc %ssupported\n",
  4261. ch_info->channel,
  4262. is_channel_a_band(ch_info) ?
  4263. "5.2" : "2.4",
  4264. CHECK_AND_PRINT(IBSS),
  4265. CHECK_AND_PRINT(ACTIVE),
  4266. CHECK_AND_PRINT(RADAR),
  4267. CHECK_AND_PRINT(WIDE),
  4268. CHECK_AND_PRINT(NARROW),
  4269. CHECK_AND_PRINT(DFS),
  4270. eeprom_ch_info[ch].flags,
  4271. eeprom_ch_info[ch].max_power_avg,
  4272. ((eeprom_ch_info[ch].
  4273. flags & EEPROM_CHANNEL_IBSS)
  4274. && !(eeprom_ch_info[ch].
  4275. flags & EEPROM_CHANNEL_RADAR))
  4276. ? "" : "not ");
  4277. /* Set the user_txpower_limit to the highest power
  4278. * supported by any channel */
  4279. if (eeprom_ch_info[ch].max_power_avg >
  4280. priv->user_txpower_limit)
  4281. priv->user_txpower_limit =
  4282. eeprom_ch_info[ch].max_power_avg;
  4283. ch_info++;
  4284. }
  4285. }
  4286. if (iwl3945_txpower_set_from_eeprom(priv))
  4287. return -EIO;
  4288. return 0;
  4289. }
  4290. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4291. * sending probe req. This should be set long enough to hear probe responses
  4292. * from more than one AP. */
  4293. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4294. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4295. /* For faster active scanning, scan will move to the next channel if fewer than
  4296. * PLCP_QUIET_THRESH packets are heard on this channel within
  4297. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4298. * time if it's a quiet channel (nothing responded to our probe, and there's
  4299. * no other traffic).
  4300. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4301. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4302. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4303. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4304. * Must be set longer than active dwell time.
  4305. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4306. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4307. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4308. #define IWL_PASSIVE_DWELL_BASE (100)
  4309. #define IWL_CHANNEL_TUNE_TIME 5
  4310. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, int phymode)
  4311. {
  4312. if (phymode == MODE_IEEE80211A)
  4313. return IWL_ACTIVE_DWELL_TIME_52;
  4314. else
  4315. return IWL_ACTIVE_DWELL_TIME_24;
  4316. }
  4317. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, int phymode)
  4318. {
  4319. u16 active = iwl3945_get_active_dwell_time(priv, phymode);
  4320. u16 passive = (phymode != MODE_IEEE80211A) ?
  4321. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4322. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4323. if (iwl3945_is_associated(priv)) {
  4324. /* If we're associated, we clamp the maximum passive
  4325. * dwell time to be 98% of the beacon interval (minus
  4326. * 2 * channel tune time) */
  4327. passive = priv->beacon_int;
  4328. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4329. passive = IWL_PASSIVE_DWELL_BASE;
  4330. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4331. }
  4332. if (passive <= active)
  4333. passive = active + 1;
  4334. return passive;
  4335. }
  4336. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, int phymode,
  4337. u8 is_active, u8 direct_mask,
  4338. struct iwl3945_scan_channel *scan_ch)
  4339. {
  4340. const struct ieee80211_channel *channels = NULL;
  4341. const struct ieee80211_hw_mode *hw_mode;
  4342. const struct iwl3945_channel_info *ch_info;
  4343. u16 passive_dwell = 0;
  4344. u16 active_dwell = 0;
  4345. int added, i;
  4346. hw_mode = iwl3945_get_hw_mode(priv, phymode);
  4347. if (!hw_mode)
  4348. return 0;
  4349. channels = hw_mode->channels;
  4350. active_dwell = iwl3945_get_active_dwell_time(priv, phymode);
  4351. passive_dwell = iwl3945_get_passive_dwell_time(priv, phymode);
  4352. for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
  4353. if (channels[i].chan ==
  4354. le16_to_cpu(priv->active_rxon.channel)) {
  4355. if (iwl3945_is_associated(priv)) {
  4356. IWL_DEBUG_SCAN
  4357. ("Skipping current channel %d\n",
  4358. le16_to_cpu(priv->active_rxon.channel));
  4359. continue;
  4360. }
  4361. } else if (priv->only_active_channel)
  4362. continue;
  4363. scan_ch->channel = channels[i].chan;
  4364. ch_info = iwl3945_get_channel_info(priv, phymode, scan_ch->channel);
  4365. if (!is_channel_valid(ch_info)) {
  4366. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4367. scan_ch->channel);
  4368. continue;
  4369. }
  4370. if (!is_active || is_channel_passive(ch_info) ||
  4371. !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
  4372. scan_ch->type = 0; /* passive */
  4373. else
  4374. scan_ch->type = 1; /* active */
  4375. if (scan_ch->type & 1)
  4376. scan_ch->type |= (direct_mask << 1);
  4377. if (is_channel_narrow(ch_info))
  4378. scan_ch->type |= (1 << 7);
  4379. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4380. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4381. /* Set power levels to defaults */
  4382. scan_ch->tpc.dsp_atten = 110;
  4383. /* scan_pwr_info->tpc.dsp_atten; */
  4384. /*scan_pwr_info->tpc.tx_gain; */
  4385. if (phymode == MODE_IEEE80211A)
  4386. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4387. else {
  4388. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4389. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4390. * power level
  4391. scan_ch->tpc.tx_gain = ((1<<5) | (2 << 3)) | 3;
  4392. */
  4393. }
  4394. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4395. scan_ch->channel,
  4396. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4397. (scan_ch->type & 1) ?
  4398. active_dwell : passive_dwell);
  4399. scan_ch++;
  4400. added++;
  4401. }
  4402. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4403. return added;
  4404. }
  4405. static void iwl3945_reset_channel_flag(struct iwl3945_priv *priv)
  4406. {
  4407. int i, j;
  4408. for (i = 0; i < 3; i++) {
  4409. struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
  4410. for (j = 0; j < hw_mode->num_channels; j++)
  4411. hw_mode->channels[j].flag = hw_mode->channels[j].val;
  4412. }
  4413. }
  4414. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4415. struct ieee80211_rate *rates)
  4416. {
  4417. int i;
  4418. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4419. rates[i].rate = iwl3945_rates[i].ieee * 5;
  4420. rates[i].val = i; /* Rate scaling will work on indexes */
  4421. rates[i].val2 = i;
  4422. rates[i].flags = IEEE80211_RATE_SUPPORTED;
  4423. /* Only OFDM have the bits-per-symbol set */
  4424. if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
  4425. rates[i].flags |= IEEE80211_RATE_OFDM;
  4426. else {
  4427. /*
  4428. * If CCK 1M then set rate flag to CCK else CCK_2
  4429. * which is CCK | PREAMBLE2
  4430. */
  4431. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4432. IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
  4433. }
  4434. /* Set up which ones are basic rates... */
  4435. if (IWL_BASIC_RATES_MASK & (1 << i))
  4436. rates[i].flags |= IEEE80211_RATE_BASIC;
  4437. }
  4438. }
  4439. /**
  4440. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4441. */
  4442. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4443. {
  4444. struct iwl3945_channel_info *ch;
  4445. struct ieee80211_hw_mode *modes;
  4446. struct ieee80211_channel *channels;
  4447. struct ieee80211_channel *geo_ch;
  4448. struct ieee80211_rate *rates;
  4449. int i = 0;
  4450. enum {
  4451. A = 0,
  4452. B = 1,
  4453. G = 2,
  4454. };
  4455. int mode_count = 3;
  4456. if (priv->modes) {
  4457. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4458. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4459. return 0;
  4460. }
  4461. modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
  4462. GFP_KERNEL);
  4463. if (!modes)
  4464. return -ENOMEM;
  4465. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4466. priv->channel_count, GFP_KERNEL);
  4467. if (!channels) {
  4468. kfree(modes);
  4469. return -ENOMEM;
  4470. }
  4471. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4472. GFP_KERNEL);
  4473. if (!rates) {
  4474. kfree(modes);
  4475. kfree(channels);
  4476. return -ENOMEM;
  4477. }
  4478. /* 0 = 802.11a
  4479. * 1 = 802.11b
  4480. * 2 = 802.11g
  4481. */
  4482. /* 5.2GHz channels start after the 2.4GHz channels */
  4483. modes[A].mode = MODE_IEEE80211A;
  4484. modes[A].channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4485. modes[A].rates = &rates[4];
  4486. modes[A].num_rates = 8; /* just OFDM */
  4487. modes[A].num_channels = 0;
  4488. modes[B].mode = MODE_IEEE80211B;
  4489. modes[B].channels = channels;
  4490. modes[B].rates = rates;
  4491. modes[B].num_rates = 4; /* just CCK */
  4492. modes[B].num_channels = 0;
  4493. modes[G].mode = MODE_IEEE80211G;
  4494. modes[G].channels = channels;
  4495. modes[G].rates = rates;
  4496. modes[G].num_rates = 12; /* OFDM & CCK */
  4497. modes[G].num_channels = 0;
  4498. priv->ieee_channels = channels;
  4499. priv->ieee_rates = rates;
  4500. iwl3945_init_hw_rates(priv, rates);
  4501. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4502. ch = &priv->channel_info[i];
  4503. if (!is_channel_valid(ch)) {
  4504. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4505. "skipping.\n",
  4506. ch->channel, is_channel_a_band(ch) ?
  4507. "5.2" : "2.4");
  4508. continue;
  4509. }
  4510. if (is_channel_a_band(ch))
  4511. geo_ch = &modes[A].channels[modes[A].num_channels++];
  4512. else {
  4513. geo_ch = &modes[B].channels[modes[B].num_channels++];
  4514. modes[G].num_channels++;
  4515. }
  4516. geo_ch->freq = ieee80211chan2mhz(ch->channel);
  4517. geo_ch->chan = ch->channel;
  4518. geo_ch->power_level = ch->max_power_avg;
  4519. geo_ch->antenna_max = 0xff;
  4520. if (is_channel_valid(ch)) {
  4521. geo_ch->flag = IEEE80211_CHAN_W_SCAN;
  4522. if (ch->flags & EEPROM_CHANNEL_IBSS)
  4523. geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
  4524. if (ch->flags & EEPROM_CHANNEL_ACTIVE)
  4525. geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
  4526. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4527. geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
  4528. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4529. priv->max_channel_txpower_limit =
  4530. ch->max_power_avg;
  4531. }
  4532. geo_ch->val = geo_ch->flag;
  4533. }
  4534. if ((modes[A].num_channels == 0) && priv->is_abg) {
  4535. printk(KERN_INFO DRV_NAME
  4536. ": Incorrectly detected BG card as ABG. Please send "
  4537. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4538. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4539. priv->is_abg = 0;
  4540. }
  4541. printk(KERN_INFO DRV_NAME
  4542. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4543. modes[G].num_channels, modes[A].num_channels);
  4544. /*
  4545. * NOTE: We register these in preference of order -- the
  4546. * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
  4547. * a phymode based on rates or AP capabilities but seems to
  4548. * configure it purely on if the channel being configured
  4549. * is supported by a mode -- and the first match is taken
  4550. */
  4551. if (modes[G].num_channels)
  4552. ieee80211_register_hwmode(priv->hw, &modes[G]);
  4553. if (modes[B].num_channels)
  4554. ieee80211_register_hwmode(priv->hw, &modes[B]);
  4555. if (modes[A].num_channels)
  4556. ieee80211_register_hwmode(priv->hw, &modes[A]);
  4557. priv->modes = modes;
  4558. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4559. return 0;
  4560. }
  4561. /******************************************************************************
  4562. *
  4563. * uCode download functions
  4564. *
  4565. ******************************************************************************/
  4566. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4567. {
  4568. if (priv->ucode_code.v_addr != NULL) {
  4569. pci_free_consistent(priv->pci_dev,
  4570. priv->ucode_code.len,
  4571. priv->ucode_code.v_addr,
  4572. priv->ucode_code.p_addr);
  4573. priv->ucode_code.v_addr = NULL;
  4574. }
  4575. if (priv->ucode_data.v_addr != NULL) {
  4576. pci_free_consistent(priv->pci_dev,
  4577. priv->ucode_data.len,
  4578. priv->ucode_data.v_addr,
  4579. priv->ucode_data.p_addr);
  4580. priv->ucode_data.v_addr = NULL;
  4581. }
  4582. if (priv->ucode_data_backup.v_addr != NULL) {
  4583. pci_free_consistent(priv->pci_dev,
  4584. priv->ucode_data_backup.len,
  4585. priv->ucode_data_backup.v_addr,
  4586. priv->ucode_data_backup.p_addr);
  4587. priv->ucode_data_backup.v_addr = NULL;
  4588. }
  4589. if (priv->ucode_init.v_addr != NULL) {
  4590. pci_free_consistent(priv->pci_dev,
  4591. priv->ucode_init.len,
  4592. priv->ucode_init.v_addr,
  4593. priv->ucode_init.p_addr);
  4594. priv->ucode_init.v_addr = NULL;
  4595. }
  4596. if (priv->ucode_init_data.v_addr != NULL) {
  4597. pci_free_consistent(priv->pci_dev,
  4598. priv->ucode_init_data.len,
  4599. priv->ucode_init_data.v_addr,
  4600. priv->ucode_init_data.p_addr);
  4601. priv->ucode_init_data.v_addr = NULL;
  4602. }
  4603. if (priv->ucode_boot.v_addr != NULL) {
  4604. pci_free_consistent(priv->pci_dev,
  4605. priv->ucode_boot.len,
  4606. priv->ucode_boot.v_addr,
  4607. priv->ucode_boot.p_addr);
  4608. priv->ucode_boot.v_addr = NULL;
  4609. }
  4610. }
  4611. /**
  4612. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4613. * looking at all data.
  4614. */
  4615. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4616. {
  4617. u32 val;
  4618. u32 save_len = len;
  4619. int rc = 0;
  4620. u32 errcnt;
  4621. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4622. rc = iwl3945_grab_nic_access(priv);
  4623. if (rc)
  4624. return rc;
  4625. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4626. errcnt = 0;
  4627. for (; len > 0; len -= sizeof(u32), image++) {
  4628. /* read data comes through single port, auto-incr addr */
  4629. /* NOTE: Use the debugless read so we don't flood kernel log
  4630. * if IWL_DL_IO is set */
  4631. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4632. if (val != le32_to_cpu(*image)) {
  4633. IWL_ERROR("uCode INST section is invalid at "
  4634. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4635. save_len - len, val, le32_to_cpu(*image));
  4636. rc = -EIO;
  4637. errcnt++;
  4638. if (errcnt >= 20)
  4639. break;
  4640. }
  4641. }
  4642. iwl3945_release_nic_access(priv);
  4643. if (!errcnt)
  4644. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4645. return rc;
  4646. }
  4647. /**
  4648. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4649. * using sample data 100 bytes apart. If these sample points are good,
  4650. * it's a pretty good bet that everything between them is good, too.
  4651. */
  4652. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4653. {
  4654. u32 val;
  4655. int rc = 0;
  4656. u32 errcnt = 0;
  4657. u32 i;
  4658. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4659. rc = iwl3945_grab_nic_access(priv);
  4660. if (rc)
  4661. return rc;
  4662. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4663. /* read data comes through single port, auto-incr addr */
  4664. /* NOTE: Use the debugless read so we don't flood kernel log
  4665. * if IWL_DL_IO is set */
  4666. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4667. i + RTC_INST_LOWER_BOUND);
  4668. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4669. if (val != le32_to_cpu(*image)) {
  4670. #if 0 /* Enable this if you want to see details */
  4671. IWL_ERROR("uCode INST section is invalid at "
  4672. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4673. i, val, *image);
  4674. #endif
  4675. rc = -EIO;
  4676. errcnt++;
  4677. if (errcnt >= 3)
  4678. break;
  4679. }
  4680. }
  4681. iwl3945_release_nic_access(priv);
  4682. return rc;
  4683. }
  4684. /**
  4685. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4686. * and verify its contents
  4687. */
  4688. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4689. {
  4690. __le32 *image;
  4691. u32 len;
  4692. int rc = 0;
  4693. /* Try bootstrap */
  4694. image = (__le32 *)priv->ucode_boot.v_addr;
  4695. len = priv->ucode_boot.len;
  4696. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4697. if (rc == 0) {
  4698. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4699. return 0;
  4700. }
  4701. /* Try initialize */
  4702. image = (__le32 *)priv->ucode_init.v_addr;
  4703. len = priv->ucode_init.len;
  4704. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4705. if (rc == 0) {
  4706. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4707. return 0;
  4708. }
  4709. /* Try runtime/protocol */
  4710. image = (__le32 *)priv->ucode_code.v_addr;
  4711. len = priv->ucode_code.len;
  4712. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4713. if (rc == 0) {
  4714. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4715. return 0;
  4716. }
  4717. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4718. /* Show first several data entries in instruction SRAM.
  4719. * Selection of bootstrap image is arbitrary. */
  4720. image = (__le32 *)priv->ucode_boot.v_addr;
  4721. len = priv->ucode_boot.len;
  4722. rc = iwl3945_verify_inst_full(priv, image, len);
  4723. return rc;
  4724. }
  4725. /* check contents of special bootstrap uCode SRAM */
  4726. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4727. {
  4728. __le32 *image = priv->ucode_boot.v_addr;
  4729. u32 len = priv->ucode_boot.len;
  4730. u32 reg;
  4731. u32 val;
  4732. IWL_DEBUG_INFO("Begin verify bsm\n");
  4733. /* verify BSM SRAM contents */
  4734. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4735. for (reg = BSM_SRAM_LOWER_BOUND;
  4736. reg < BSM_SRAM_LOWER_BOUND + len;
  4737. reg += sizeof(u32), image ++) {
  4738. val = iwl3945_read_prph(priv, reg);
  4739. if (val != le32_to_cpu(*image)) {
  4740. IWL_ERROR("BSM uCode verification failed at "
  4741. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4742. BSM_SRAM_LOWER_BOUND,
  4743. reg - BSM_SRAM_LOWER_BOUND, len,
  4744. val, le32_to_cpu(*image));
  4745. return -EIO;
  4746. }
  4747. }
  4748. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4749. return 0;
  4750. }
  4751. /**
  4752. * iwl3945_load_bsm - Load bootstrap instructions
  4753. *
  4754. * BSM operation:
  4755. *
  4756. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4757. * in special SRAM that does not power down during RFKILL. When powering back
  4758. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4759. * the bootstrap program into the on-board processor, and starts it.
  4760. *
  4761. * The bootstrap program loads (via DMA) instructions and data for a new
  4762. * program from host DRAM locations indicated by the host driver in the
  4763. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4764. * automatically.
  4765. *
  4766. * When initializing the NIC, the host driver points the BSM to the
  4767. * "initialize" uCode image. This uCode sets up some internal data, then
  4768. * notifies host via "initialize alive" that it is complete.
  4769. *
  4770. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4771. * normal runtime uCode instructions and a backup uCode data cache buffer
  4772. * (filled initially with starting data values for the on-board processor),
  4773. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4774. * which begins normal operation.
  4775. *
  4776. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4777. * the backup data cache in DRAM before SRAM is powered down.
  4778. *
  4779. * When powering back up, the BSM loads the bootstrap program. This reloads
  4780. * the runtime uCode instructions and the backup data cache into SRAM,
  4781. * and re-launches the runtime uCode from where it left off.
  4782. */
  4783. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4784. {
  4785. __le32 *image = priv->ucode_boot.v_addr;
  4786. u32 len = priv->ucode_boot.len;
  4787. dma_addr_t pinst;
  4788. dma_addr_t pdata;
  4789. u32 inst_len;
  4790. u32 data_len;
  4791. int rc;
  4792. int i;
  4793. u32 done;
  4794. u32 reg_offset;
  4795. IWL_DEBUG_INFO("Begin load bsm\n");
  4796. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4797. if (len > IWL_MAX_BSM_SIZE)
  4798. return -EINVAL;
  4799. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4800. * in host DRAM ... bits 31:0 for 3945, bits 35:4 for 4965.
  4801. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4802. * after the "initialize" uCode has run, to point to
  4803. * runtime/protocol instructions and backup data cache. */
  4804. pinst = priv->ucode_init.p_addr;
  4805. pdata = priv->ucode_init_data.p_addr;
  4806. inst_len = priv->ucode_init.len;
  4807. data_len = priv->ucode_init_data.len;
  4808. rc = iwl3945_grab_nic_access(priv);
  4809. if (rc)
  4810. return rc;
  4811. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4812. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4813. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4814. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4815. /* Fill BSM memory with bootstrap instructions */
  4816. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4817. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4818. reg_offset += sizeof(u32), image++)
  4819. _iwl3945_write_prph(priv, reg_offset,
  4820. le32_to_cpu(*image));
  4821. rc = iwl3945_verify_bsm(priv);
  4822. if (rc) {
  4823. iwl3945_release_nic_access(priv);
  4824. return rc;
  4825. }
  4826. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4827. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4828. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4829. RTC_INST_LOWER_BOUND);
  4830. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4831. /* Load bootstrap code into instruction SRAM now,
  4832. * to prepare to load "initialize" uCode */
  4833. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4834. BSM_WR_CTRL_REG_BIT_START);
  4835. /* Wait for load of bootstrap uCode to finish */
  4836. for (i = 0; i < 100; i++) {
  4837. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4838. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4839. break;
  4840. udelay(10);
  4841. }
  4842. if (i < 100)
  4843. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4844. else {
  4845. IWL_ERROR("BSM write did not complete!\n");
  4846. return -EIO;
  4847. }
  4848. /* Enable future boot loads whenever power management unit triggers it
  4849. * (e.g. when powering back up after power-save shutdown) */
  4850. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4851. BSM_WR_CTRL_REG_BIT_START_EN);
  4852. iwl3945_release_nic_access(priv);
  4853. return 0;
  4854. }
  4855. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4856. {
  4857. /* Remove all resets to allow NIC to operate */
  4858. iwl3945_write32(priv, CSR_RESET, 0);
  4859. }
  4860. static int iwl3945_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  4861. {
  4862. desc->v_addr = pci_alloc_consistent(pci_dev, desc->len, &desc->p_addr);
  4863. return (desc->v_addr != NULL) ? 0 : -ENOMEM;
  4864. }
  4865. /**
  4866. * iwl3945_read_ucode - Read uCode images from disk file.
  4867. *
  4868. * Copy into buffers for card to fetch via bus-mastering
  4869. */
  4870. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4871. {
  4872. struct iwl3945_ucode *ucode;
  4873. int ret = 0;
  4874. const struct firmware *ucode_raw;
  4875. /* firmware file name contains uCode/driver compatibility version */
  4876. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4877. u8 *src;
  4878. size_t len;
  4879. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4880. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4881. * request_firmware() is synchronous, file is in memory on return. */
  4882. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4883. if (ret < 0) {
  4884. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4885. name, ret);
  4886. goto error;
  4887. }
  4888. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4889. name, ucode_raw->size);
  4890. /* Make sure that we got at least our header! */
  4891. if (ucode_raw->size < sizeof(*ucode)) {
  4892. IWL_ERROR("File size way too small!\n");
  4893. ret = -EINVAL;
  4894. goto err_release;
  4895. }
  4896. /* Data from ucode file: header followed by uCode images */
  4897. ucode = (void *)ucode_raw->data;
  4898. ver = le32_to_cpu(ucode->ver);
  4899. inst_size = le32_to_cpu(ucode->inst_size);
  4900. data_size = le32_to_cpu(ucode->data_size);
  4901. init_size = le32_to_cpu(ucode->init_size);
  4902. init_data_size = le32_to_cpu(ucode->init_data_size);
  4903. boot_size = le32_to_cpu(ucode->boot_size);
  4904. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4905. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4906. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4907. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4908. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4909. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4910. /* Verify size of file vs. image size info in file's header */
  4911. if (ucode_raw->size < sizeof(*ucode) +
  4912. inst_size + data_size + init_size +
  4913. init_data_size + boot_size) {
  4914. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4915. (int)ucode_raw->size);
  4916. ret = -EINVAL;
  4917. goto err_release;
  4918. }
  4919. /* Verify that uCode images will fit in card's SRAM */
  4920. if (inst_size > IWL_MAX_INST_SIZE) {
  4921. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4922. inst_size);
  4923. ret = -EINVAL;
  4924. goto err_release;
  4925. }
  4926. if (data_size > IWL_MAX_DATA_SIZE) {
  4927. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4928. data_size);
  4929. ret = -EINVAL;
  4930. goto err_release;
  4931. }
  4932. if (init_size > IWL_MAX_INST_SIZE) {
  4933. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4934. init_size);
  4935. ret = -EINVAL;
  4936. goto err_release;
  4937. }
  4938. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4939. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4940. init_data_size);
  4941. ret = -EINVAL;
  4942. goto err_release;
  4943. }
  4944. if (boot_size > IWL_MAX_BSM_SIZE) {
  4945. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4946. boot_size);
  4947. ret = -EINVAL;
  4948. goto err_release;
  4949. }
  4950. /* Allocate ucode buffers for card's bus-master loading ... */
  4951. /* Runtime instructions and 2 copies of data:
  4952. * 1) unmodified from disk
  4953. * 2) backup cache for save/restore during power-downs */
  4954. priv->ucode_code.len = inst_size;
  4955. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4956. priv->ucode_data.len = data_size;
  4957. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4958. priv->ucode_data_backup.len = data_size;
  4959. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4960. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4961. !priv->ucode_data_backup.v_addr)
  4962. goto err_pci_alloc;
  4963. /* Initialization instructions and data */
  4964. if (init_size && init_data_size) {
  4965. priv->ucode_init.len = init_size;
  4966. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4967. priv->ucode_init_data.len = init_data_size;
  4968. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4969. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4970. goto err_pci_alloc;
  4971. }
  4972. /* Bootstrap (instructions only, no data) */
  4973. if (boot_size) {
  4974. priv->ucode_boot.len = boot_size;
  4975. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4976. if (!priv->ucode_boot.v_addr)
  4977. goto err_pci_alloc;
  4978. }
  4979. /* Copy images into buffers for card's bus-master reads ... */
  4980. /* Runtime instructions (first block of data in file) */
  4981. src = &ucode->data[0];
  4982. len = priv->ucode_code.len;
  4983. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4984. memcpy(priv->ucode_code.v_addr, src, len);
  4985. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4986. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4987. /* Runtime data (2nd block)
  4988. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4989. src = &ucode->data[inst_size];
  4990. len = priv->ucode_data.len;
  4991. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4992. memcpy(priv->ucode_data.v_addr, src, len);
  4993. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4994. /* Initialization instructions (3rd block) */
  4995. if (init_size) {
  4996. src = &ucode->data[inst_size + data_size];
  4997. len = priv->ucode_init.len;
  4998. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4999. len);
  5000. memcpy(priv->ucode_init.v_addr, src, len);
  5001. }
  5002. /* Initialization data (4th block) */
  5003. if (init_data_size) {
  5004. src = &ucode->data[inst_size + data_size + init_size];
  5005. len = priv->ucode_init_data.len;
  5006. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  5007. (int)len);
  5008. memcpy(priv->ucode_init_data.v_addr, src, len);
  5009. }
  5010. /* Bootstrap instructions (5th block) */
  5011. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  5012. len = priv->ucode_boot.len;
  5013. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  5014. (int)len);
  5015. memcpy(priv->ucode_boot.v_addr, src, len);
  5016. /* We have our copies now, allow OS release its copies */
  5017. release_firmware(ucode_raw);
  5018. return 0;
  5019. err_pci_alloc:
  5020. IWL_ERROR("failed to allocate pci memory\n");
  5021. ret = -ENOMEM;
  5022. iwl3945_dealloc_ucode_pci(priv);
  5023. err_release:
  5024. release_firmware(ucode_raw);
  5025. error:
  5026. return ret;
  5027. }
  5028. /**
  5029. * iwl3945_set_ucode_ptrs - Set uCode address location
  5030. *
  5031. * Tell initialization uCode where to find runtime uCode.
  5032. *
  5033. * BSM registers initially contain pointers to initialization uCode.
  5034. * We need to replace them to load runtime uCode inst and data,
  5035. * and to save runtime data when powering down.
  5036. */
  5037. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  5038. {
  5039. dma_addr_t pinst;
  5040. dma_addr_t pdata;
  5041. int rc = 0;
  5042. unsigned long flags;
  5043. /* bits 31:0 for 3945 */
  5044. pinst = priv->ucode_code.p_addr;
  5045. pdata = priv->ucode_data_backup.p_addr;
  5046. spin_lock_irqsave(&priv->lock, flags);
  5047. rc = iwl3945_grab_nic_access(priv);
  5048. if (rc) {
  5049. spin_unlock_irqrestore(&priv->lock, flags);
  5050. return rc;
  5051. }
  5052. /* Tell bootstrap uCode where to find image to load */
  5053. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5054. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5055. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5056. priv->ucode_data.len);
  5057. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5058. * that all new ptr/size info is in place */
  5059. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5060. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5061. iwl3945_release_nic_access(priv);
  5062. spin_unlock_irqrestore(&priv->lock, flags);
  5063. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5064. return rc;
  5065. }
  5066. /**
  5067. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  5068. *
  5069. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5070. *
  5071. * The 4965 "initialize" ALIVE reply contains calibration data for:
  5072. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  5073. * (3945 does not contain this data).
  5074. *
  5075. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5076. */
  5077. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  5078. {
  5079. /* Check alive response for "valid" sign from uCode */
  5080. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5081. /* We had an error bringing up the hardware, so take it
  5082. * all the way back down so we can try again */
  5083. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5084. goto restart;
  5085. }
  5086. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5087. * This is a paranoid check, because we would not have gotten the
  5088. * "initialize" alive if code weren't properly loaded. */
  5089. if (iwl3945_verify_ucode(priv)) {
  5090. /* Runtime instruction load was bad;
  5091. * take it all the way back down so we can try again */
  5092. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5093. goto restart;
  5094. }
  5095. /* Send pointers to protocol/runtime uCode image ... init code will
  5096. * load and launch runtime uCode, which will send us another "Alive"
  5097. * notification. */
  5098. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5099. if (iwl3945_set_ucode_ptrs(priv)) {
  5100. /* Runtime instruction load won't happen;
  5101. * take it all the way back down so we can try again */
  5102. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5103. goto restart;
  5104. }
  5105. return;
  5106. restart:
  5107. queue_work(priv->workqueue, &priv->restart);
  5108. }
  5109. /**
  5110. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  5111. * from protocol/runtime uCode (initialization uCode's
  5112. * Alive gets handled by iwl3945_init_alive_start()).
  5113. */
  5114. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  5115. {
  5116. int rc = 0;
  5117. int thermal_spin = 0;
  5118. u32 rfkill;
  5119. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5120. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5121. /* We had an error bringing up the hardware, so take it
  5122. * all the way back down so we can try again */
  5123. IWL_DEBUG_INFO("Alive failed.\n");
  5124. goto restart;
  5125. }
  5126. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5127. * This is a paranoid check, because we would not have gotten the
  5128. * "runtime" alive if code weren't properly loaded. */
  5129. if (iwl3945_verify_ucode(priv)) {
  5130. /* Runtime instruction load was bad;
  5131. * take it all the way back down so we can try again */
  5132. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5133. goto restart;
  5134. }
  5135. iwl3945_clear_stations_table(priv);
  5136. rc = iwl3945_grab_nic_access(priv);
  5137. if (rc) {
  5138. IWL_WARNING("Can not read rfkill status from adapter\n");
  5139. return;
  5140. }
  5141. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  5142. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  5143. iwl3945_release_nic_access(priv);
  5144. if (rfkill & 0x1) {
  5145. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5146. /* if rfkill is not on, then wait for thermal
  5147. * sensor in adapter to kick in */
  5148. while (iwl3945_hw_get_temperature(priv) == 0) {
  5149. thermal_spin++;
  5150. udelay(10);
  5151. }
  5152. if (thermal_spin)
  5153. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5154. thermal_spin * 10);
  5155. } else
  5156. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5157. /* After the ALIVE response, we can process host commands */
  5158. set_bit(STATUS_ALIVE, &priv->status);
  5159. /* Clear out the uCode error bit if it is set */
  5160. clear_bit(STATUS_FW_ERROR, &priv->status);
  5161. rc = iwl3945_init_channel_map(priv);
  5162. if (rc) {
  5163. IWL_ERROR("initializing regulatory failed: %d\n", rc);
  5164. return;
  5165. }
  5166. iwl3945_init_geos(priv);
  5167. if (iwl3945_is_rfkill(priv))
  5168. return;
  5169. if (!priv->mac80211_registered) {
  5170. /* Unlock so any user space entry points can call back into
  5171. * the driver without a deadlock... */
  5172. mutex_unlock(&priv->mutex);
  5173. iwl3945_rate_control_register(priv->hw);
  5174. rc = ieee80211_register_hw(priv->hw);
  5175. priv->hw->conf.beacon_int = 100;
  5176. mutex_lock(&priv->mutex);
  5177. if (rc) {
  5178. iwl3945_rate_control_unregister(priv->hw);
  5179. IWL_ERROR("Failed to register network "
  5180. "device (error %d)\n", rc);
  5181. return;
  5182. }
  5183. priv->mac80211_registered = 1;
  5184. iwl3945_reset_channel_flag(priv);
  5185. } else
  5186. ieee80211_start_queues(priv->hw);
  5187. priv->active_rate = priv->rates_mask;
  5188. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5189. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5190. if (iwl3945_is_associated(priv)) {
  5191. struct iwl3945_rxon_cmd *active_rxon =
  5192. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5193. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5194. sizeof(priv->staging_rxon));
  5195. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5196. } else {
  5197. /* Initialize our rx_config data */
  5198. iwl3945_connection_init_rx_config(priv);
  5199. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5200. }
  5201. /* Configure BT coexistence */
  5202. iwl3945_send_bt_config(priv);
  5203. /* Configure the adapter for unassociated operation */
  5204. iwl3945_commit_rxon(priv);
  5205. /* At this point, the NIC is initialized and operational */
  5206. priv->notif_missed_beacons = 0;
  5207. set_bit(STATUS_READY, &priv->status);
  5208. iwl3945_reg_txpower_periodic(priv);
  5209. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5210. if (priv->error_recovering)
  5211. iwl3945_error_recovery(priv);
  5212. return;
  5213. restart:
  5214. queue_work(priv->workqueue, &priv->restart);
  5215. }
  5216. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5217. static void __iwl3945_down(struct iwl3945_priv *priv)
  5218. {
  5219. unsigned long flags;
  5220. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5221. struct ieee80211_conf *conf = NULL;
  5222. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5223. conf = ieee80211_get_hw_conf(priv->hw);
  5224. if (!exit_pending)
  5225. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5226. iwl3945_clear_stations_table(priv);
  5227. /* Unblock any waiting calls */
  5228. wake_up_interruptible_all(&priv->wait_command_queue);
  5229. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5230. * exiting the module */
  5231. if (!exit_pending)
  5232. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5233. /* stop and reset the on-board processor */
  5234. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5235. /* tell the device to stop sending interrupts */
  5236. iwl3945_disable_interrupts(priv);
  5237. if (priv->mac80211_registered)
  5238. ieee80211_stop_queues(priv->hw);
  5239. /* If we have not previously called iwl3945_init() then
  5240. * clear all bits but the RF Kill and SUSPEND bits and return */
  5241. if (!iwl3945_is_init(priv)) {
  5242. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5243. STATUS_RF_KILL_HW |
  5244. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5245. STATUS_RF_KILL_SW |
  5246. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5247. STATUS_IN_SUSPEND;
  5248. goto exit;
  5249. }
  5250. /* ...otherwise clear out all the status bits but the RF Kill and
  5251. * SUSPEND bits and continue taking the NIC down. */
  5252. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5253. STATUS_RF_KILL_HW |
  5254. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5255. STATUS_RF_KILL_SW |
  5256. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5257. STATUS_IN_SUSPEND |
  5258. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5259. STATUS_FW_ERROR;
  5260. spin_lock_irqsave(&priv->lock, flags);
  5261. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5262. spin_unlock_irqrestore(&priv->lock, flags);
  5263. iwl3945_hw_txq_ctx_stop(priv);
  5264. iwl3945_hw_rxq_stop(priv);
  5265. spin_lock_irqsave(&priv->lock, flags);
  5266. if (!iwl3945_grab_nic_access(priv)) {
  5267. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5268. APMG_CLK_VAL_DMA_CLK_RQT);
  5269. iwl3945_release_nic_access(priv);
  5270. }
  5271. spin_unlock_irqrestore(&priv->lock, flags);
  5272. udelay(5);
  5273. iwl3945_hw_nic_stop_master(priv);
  5274. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5275. iwl3945_hw_nic_reset(priv);
  5276. exit:
  5277. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5278. if (priv->ibss_beacon)
  5279. dev_kfree_skb(priv->ibss_beacon);
  5280. priv->ibss_beacon = NULL;
  5281. /* clear out any free frames */
  5282. iwl3945_clear_free_frames(priv);
  5283. }
  5284. static void iwl3945_down(struct iwl3945_priv *priv)
  5285. {
  5286. mutex_lock(&priv->mutex);
  5287. __iwl3945_down(priv);
  5288. mutex_unlock(&priv->mutex);
  5289. iwl3945_cancel_deferred_work(priv);
  5290. }
  5291. #define MAX_HW_RESTARTS 5
  5292. static int __iwl3945_up(struct iwl3945_priv *priv)
  5293. {
  5294. DECLARE_MAC_BUF(mac);
  5295. int rc, i;
  5296. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5297. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5298. return -EIO;
  5299. }
  5300. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5301. IWL_WARNING("Radio disabled by SW RF kill (module "
  5302. "parameter)\n");
  5303. return 0;
  5304. }
  5305. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5306. IWL_ERROR("ucode not available for device bringup\n");
  5307. return -EIO;
  5308. }
  5309. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5310. rc = iwl3945_hw_nic_init(priv);
  5311. if (rc) {
  5312. IWL_ERROR("Unable to int nic\n");
  5313. return rc;
  5314. }
  5315. /* make sure rfkill handshake bits are cleared */
  5316. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5317. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5318. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5319. /* clear (again), then enable host interrupts */
  5320. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5321. iwl3945_enable_interrupts(priv);
  5322. /* really make sure rfkill handshake bits are cleared */
  5323. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5324. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5325. /* Copy original ucode data image from disk into backup cache.
  5326. * This will be used to initialize the on-board processor's
  5327. * data SRAM for a clean start when the runtime program first loads. */
  5328. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5329. priv->ucode_data.len);
  5330. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5331. iwl3945_clear_stations_table(priv);
  5332. /* load bootstrap state machine,
  5333. * load bootstrap program into processor's memory,
  5334. * prepare to load the "initialize" uCode */
  5335. rc = iwl3945_load_bsm(priv);
  5336. if (rc) {
  5337. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5338. continue;
  5339. }
  5340. /* start card; "initialize" will load runtime ucode */
  5341. iwl3945_nic_start(priv);
  5342. /* MAC Address location in EEPROM same for 3945/4965 */
  5343. get_eeprom_mac(priv, priv->mac_addr);
  5344. IWL_DEBUG_INFO("MAC address: %s\n",
  5345. print_mac(mac, priv->mac_addr));
  5346. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  5347. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5348. return 0;
  5349. }
  5350. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5351. __iwl3945_down(priv);
  5352. /* tried to restart and config the device for as long as our
  5353. * patience could withstand */
  5354. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5355. return -EIO;
  5356. }
  5357. /*****************************************************************************
  5358. *
  5359. * Workqueue callbacks
  5360. *
  5361. *****************************************************************************/
  5362. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5363. {
  5364. struct iwl3945_priv *priv =
  5365. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5366. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5367. return;
  5368. mutex_lock(&priv->mutex);
  5369. iwl3945_init_alive_start(priv);
  5370. mutex_unlock(&priv->mutex);
  5371. }
  5372. static void iwl3945_bg_alive_start(struct work_struct *data)
  5373. {
  5374. struct iwl3945_priv *priv =
  5375. container_of(data, struct iwl3945_priv, alive_start.work);
  5376. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5377. return;
  5378. mutex_lock(&priv->mutex);
  5379. iwl3945_alive_start(priv);
  5380. mutex_unlock(&priv->mutex);
  5381. }
  5382. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5383. {
  5384. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5385. wake_up_interruptible(&priv->wait_command_queue);
  5386. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5387. return;
  5388. mutex_lock(&priv->mutex);
  5389. if (!iwl3945_is_rfkill(priv)) {
  5390. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5391. "HW and/or SW RF Kill no longer active, restarting "
  5392. "device\n");
  5393. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5394. queue_work(priv->workqueue, &priv->restart);
  5395. } else {
  5396. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5397. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5398. "disabled by SW switch\n");
  5399. else
  5400. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5401. "Kill switch must be turned off for "
  5402. "wireless networking to work.\n");
  5403. }
  5404. mutex_unlock(&priv->mutex);
  5405. }
  5406. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5407. static void iwl3945_bg_scan_check(struct work_struct *data)
  5408. {
  5409. struct iwl3945_priv *priv =
  5410. container_of(data, struct iwl3945_priv, scan_check.work);
  5411. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5412. return;
  5413. mutex_lock(&priv->mutex);
  5414. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5415. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5416. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5417. "Scan completion watchdog resetting adapter (%dms)\n",
  5418. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5419. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5420. iwl3945_send_scan_abort(priv);
  5421. }
  5422. mutex_unlock(&priv->mutex);
  5423. }
  5424. static void iwl3945_bg_request_scan(struct work_struct *data)
  5425. {
  5426. struct iwl3945_priv *priv =
  5427. container_of(data, struct iwl3945_priv, request_scan);
  5428. struct iwl3945_host_cmd cmd = {
  5429. .id = REPLY_SCAN_CMD,
  5430. .len = sizeof(struct iwl3945_scan_cmd),
  5431. .meta.flags = CMD_SIZE_HUGE,
  5432. };
  5433. int rc = 0;
  5434. struct iwl3945_scan_cmd *scan;
  5435. struct ieee80211_conf *conf = NULL;
  5436. u8 direct_mask;
  5437. int phymode;
  5438. conf = ieee80211_get_hw_conf(priv->hw);
  5439. mutex_lock(&priv->mutex);
  5440. if (!iwl3945_is_ready(priv)) {
  5441. IWL_WARNING("request scan called when driver not ready.\n");
  5442. goto done;
  5443. }
  5444. /* Make sure the scan wasn't cancelled before this queued work
  5445. * was given the chance to run... */
  5446. if (!test_bit(STATUS_SCANNING, &priv->status))
  5447. goto done;
  5448. /* This should never be called or scheduled if there is currently
  5449. * a scan active in the hardware. */
  5450. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5451. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5452. "Ignoring second request.\n");
  5453. rc = -EIO;
  5454. goto done;
  5455. }
  5456. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5457. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5458. goto done;
  5459. }
  5460. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5461. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5462. goto done;
  5463. }
  5464. if (iwl3945_is_rfkill(priv)) {
  5465. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5466. goto done;
  5467. }
  5468. if (!test_bit(STATUS_READY, &priv->status)) {
  5469. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5470. goto done;
  5471. }
  5472. if (!priv->scan_bands) {
  5473. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5474. goto done;
  5475. }
  5476. if (!priv->scan) {
  5477. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5478. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5479. if (!priv->scan) {
  5480. rc = -ENOMEM;
  5481. goto done;
  5482. }
  5483. }
  5484. scan = priv->scan;
  5485. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5486. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5487. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5488. if (iwl3945_is_associated(priv)) {
  5489. u16 interval = 0;
  5490. u32 extra;
  5491. u32 suspend_time = 100;
  5492. u32 scan_suspend_time = 100;
  5493. unsigned long flags;
  5494. IWL_DEBUG_INFO("Scanning while associated...\n");
  5495. spin_lock_irqsave(&priv->lock, flags);
  5496. interval = priv->beacon_int;
  5497. spin_unlock_irqrestore(&priv->lock, flags);
  5498. scan->suspend_time = 0;
  5499. scan->max_out_time = cpu_to_le32(200 * 1024);
  5500. if (!interval)
  5501. interval = suspend_time;
  5502. /*
  5503. * suspend time format:
  5504. * 0-19: beacon interval in usec (time before exec.)
  5505. * 20-23: 0
  5506. * 24-31: number of beacons (suspend between channels)
  5507. */
  5508. extra = (suspend_time / interval) << 24;
  5509. scan_suspend_time = 0xFF0FFFFF &
  5510. (extra | ((suspend_time % interval) * 1024));
  5511. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5512. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5513. scan_suspend_time, interval);
  5514. }
  5515. /* We should add the ability for user to lock to PASSIVE ONLY */
  5516. if (priv->one_direct_scan) {
  5517. IWL_DEBUG_SCAN
  5518. ("Kicking off one direct scan for '%s'\n",
  5519. iwl3945_escape_essid(priv->direct_ssid,
  5520. priv->direct_ssid_len));
  5521. scan->direct_scan[0].id = WLAN_EID_SSID;
  5522. scan->direct_scan[0].len = priv->direct_ssid_len;
  5523. memcpy(scan->direct_scan[0].ssid,
  5524. priv->direct_ssid, priv->direct_ssid_len);
  5525. direct_mask = 1;
  5526. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5527. scan->direct_scan[0].id = WLAN_EID_SSID;
  5528. scan->direct_scan[0].len = priv->essid_len;
  5529. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5530. direct_mask = 1;
  5531. } else
  5532. direct_mask = 0;
  5533. /* We don't build a direct scan probe request; the uCode will do
  5534. * that based on the direct_mask added to each channel entry */
  5535. scan->tx_cmd.len = cpu_to_le16(
  5536. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5537. IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
  5538. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5539. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5540. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5541. /* flags + rate selection */
  5542. switch (priv->scan_bands) {
  5543. case 2:
  5544. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5545. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5546. scan->good_CRC_th = 0;
  5547. phymode = MODE_IEEE80211G;
  5548. break;
  5549. case 1:
  5550. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5551. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5552. phymode = MODE_IEEE80211A;
  5553. break;
  5554. default:
  5555. IWL_WARNING("Invalid scan band count\n");
  5556. goto done;
  5557. }
  5558. /* select Rx antennas */
  5559. scan->flags |= iwl3945_get_antenna_flags(priv);
  5560. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5561. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5562. if (direct_mask)
  5563. IWL_DEBUG_SCAN
  5564. ("Initiating direct scan for %s.\n",
  5565. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5566. else
  5567. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5568. scan->channel_count =
  5569. iwl3945_get_channels_for_scan(
  5570. priv, phymode, 1, /* active */
  5571. direct_mask,
  5572. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5573. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5574. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5575. cmd.data = scan;
  5576. scan->len = cpu_to_le16(cmd.len);
  5577. set_bit(STATUS_SCAN_HW, &priv->status);
  5578. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5579. if (rc)
  5580. goto done;
  5581. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5582. IWL_SCAN_CHECK_WATCHDOG);
  5583. mutex_unlock(&priv->mutex);
  5584. return;
  5585. done:
  5586. /* inform mac80211 scan aborted */
  5587. queue_work(priv->workqueue, &priv->scan_completed);
  5588. mutex_unlock(&priv->mutex);
  5589. }
  5590. static void iwl3945_bg_up(struct work_struct *data)
  5591. {
  5592. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5593. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5594. return;
  5595. mutex_lock(&priv->mutex);
  5596. __iwl3945_up(priv);
  5597. mutex_unlock(&priv->mutex);
  5598. }
  5599. static void iwl3945_bg_restart(struct work_struct *data)
  5600. {
  5601. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5602. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5603. return;
  5604. iwl3945_down(priv);
  5605. queue_work(priv->workqueue, &priv->up);
  5606. }
  5607. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5608. {
  5609. struct iwl3945_priv *priv =
  5610. container_of(data, struct iwl3945_priv, rx_replenish);
  5611. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5612. return;
  5613. mutex_lock(&priv->mutex);
  5614. iwl3945_rx_replenish(priv);
  5615. mutex_unlock(&priv->mutex);
  5616. }
  5617. static void iwl3945_bg_post_associate(struct work_struct *data)
  5618. {
  5619. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5620. post_associate.work);
  5621. int rc = 0;
  5622. struct ieee80211_conf *conf = NULL;
  5623. DECLARE_MAC_BUF(mac);
  5624. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5625. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5626. return;
  5627. }
  5628. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5629. priv->assoc_id,
  5630. print_mac(mac, priv->active_rxon.bssid_addr));
  5631. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5632. return;
  5633. mutex_lock(&priv->mutex);
  5634. if (!priv->interface_id || !priv->is_open) {
  5635. mutex_unlock(&priv->mutex);
  5636. return;
  5637. }
  5638. iwl3945_scan_cancel_timeout(priv, 200);
  5639. conf = ieee80211_get_hw_conf(priv->hw);
  5640. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5641. iwl3945_commit_rxon(priv);
  5642. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5643. iwl3945_setup_rxon_timing(priv);
  5644. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5645. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5646. if (rc)
  5647. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5648. "Attempting to continue.\n");
  5649. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5650. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5651. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5652. priv->assoc_id, priv->beacon_int);
  5653. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5654. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5655. else
  5656. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5657. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5658. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5659. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5660. else
  5661. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5662. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5663. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5664. }
  5665. iwl3945_commit_rxon(priv);
  5666. switch (priv->iw_mode) {
  5667. case IEEE80211_IF_TYPE_STA:
  5668. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5669. break;
  5670. case IEEE80211_IF_TYPE_IBSS:
  5671. /* clear out the station table */
  5672. iwl3945_clear_stations_table(priv);
  5673. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5674. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5675. iwl3945_sync_sta(priv, IWL_STA_ID,
  5676. (priv->phymode == MODE_IEEE80211A)?
  5677. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5678. CMD_ASYNC);
  5679. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5680. iwl3945_send_beacon_cmd(priv);
  5681. break;
  5682. default:
  5683. IWL_ERROR("%s Should not be called in %d mode\n",
  5684. __FUNCTION__, priv->iw_mode);
  5685. break;
  5686. }
  5687. iwl3945_sequence_reset(priv);
  5688. #ifdef CONFIG_IWL3945_QOS
  5689. iwl3945_activate_qos(priv, 0);
  5690. #endif /* CONFIG_IWL3945_QOS */
  5691. mutex_unlock(&priv->mutex);
  5692. }
  5693. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5694. {
  5695. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5696. if (!iwl3945_is_ready(priv))
  5697. return;
  5698. mutex_lock(&priv->mutex);
  5699. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5700. iwl3945_send_scan_abort(priv);
  5701. mutex_unlock(&priv->mutex);
  5702. }
  5703. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5704. {
  5705. struct iwl3945_priv *priv =
  5706. container_of(work, struct iwl3945_priv, scan_completed);
  5707. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5708. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5709. return;
  5710. ieee80211_scan_completed(priv->hw);
  5711. /* Since setting the TXPOWER may have been deferred while
  5712. * performing the scan, fire one off */
  5713. mutex_lock(&priv->mutex);
  5714. iwl3945_hw_reg_send_txpower(priv);
  5715. mutex_unlock(&priv->mutex);
  5716. }
  5717. /*****************************************************************************
  5718. *
  5719. * mac80211 entry point functions
  5720. *
  5721. *****************************************************************************/
  5722. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5723. {
  5724. struct iwl3945_priv *priv = hw->priv;
  5725. IWL_DEBUG_MAC80211("enter\n");
  5726. /* we should be verifying the device is ready to be opened */
  5727. mutex_lock(&priv->mutex);
  5728. priv->is_open = 1;
  5729. if (!iwl3945_is_rfkill(priv))
  5730. ieee80211_start_queues(priv->hw);
  5731. mutex_unlock(&priv->mutex);
  5732. IWL_DEBUG_MAC80211("leave\n");
  5733. return 0;
  5734. }
  5735. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5736. {
  5737. struct iwl3945_priv *priv = hw->priv;
  5738. IWL_DEBUG_MAC80211("enter\n");
  5739. mutex_lock(&priv->mutex);
  5740. /* stop mac, cancel any scan request and clear
  5741. * RXON_FILTER_ASSOC_MSK BIT
  5742. */
  5743. priv->is_open = 0;
  5744. iwl3945_scan_cancel_timeout(priv, 100);
  5745. cancel_delayed_work(&priv->post_associate);
  5746. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5747. iwl3945_commit_rxon(priv);
  5748. mutex_unlock(&priv->mutex);
  5749. IWL_DEBUG_MAC80211("leave\n");
  5750. }
  5751. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5752. struct ieee80211_tx_control *ctl)
  5753. {
  5754. struct iwl3945_priv *priv = hw->priv;
  5755. IWL_DEBUG_MAC80211("enter\n");
  5756. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5757. IWL_DEBUG_MAC80211("leave - monitor\n");
  5758. return -1;
  5759. }
  5760. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5761. ctl->tx_rate);
  5762. if (iwl3945_tx_skb(priv, skb, ctl))
  5763. dev_kfree_skb_any(skb);
  5764. IWL_DEBUG_MAC80211("leave\n");
  5765. return 0;
  5766. }
  5767. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5768. struct ieee80211_if_init_conf *conf)
  5769. {
  5770. struct iwl3945_priv *priv = hw->priv;
  5771. unsigned long flags;
  5772. DECLARE_MAC_BUF(mac);
  5773. IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
  5774. if (priv->interface_id) {
  5775. IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
  5776. return -EOPNOTSUPP;
  5777. }
  5778. spin_lock_irqsave(&priv->lock, flags);
  5779. priv->interface_id = conf->if_id;
  5780. spin_unlock_irqrestore(&priv->lock, flags);
  5781. mutex_lock(&priv->mutex);
  5782. if (conf->mac_addr) {
  5783. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5784. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5785. }
  5786. iwl3945_set_mode(priv, conf->type);
  5787. IWL_DEBUG_MAC80211("leave\n");
  5788. mutex_unlock(&priv->mutex);
  5789. return 0;
  5790. }
  5791. /**
  5792. * iwl3945_mac_config - mac80211 config callback
  5793. *
  5794. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5795. * be set inappropriately and the driver currently sets the hardware up to
  5796. * use it whenever needed.
  5797. */
  5798. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5799. {
  5800. struct iwl3945_priv *priv = hw->priv;
  5801. const struct iwl3945_channel_info *ch_info;
  5802. unsigned long flags;
  5803. mutex_lock(&priv->mutex);
  5804. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
  5805. if (!iwl3945_is_ready(priv)) {
  5806. IWL_DEBUG_MAC80211("leave - not ready\n");
  5807. mutex_unlock(&priv->mutex);
  5808. return -EIO;
  5809. }
  5810. /* TODO: Figure out how to get ieee80211_local->sta_scanning w/ only
  5811. * what is exposed through include/ declarations */
  5812. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5813. test_bit(STATUS_SCANNING, &priv->status))) {
  5814. IWL_DEBUG_MAC80211("leave - scanning\n");
  5815. mutex_unlock(&priv->mutex);
  5816. return 0;
  5817. }
  5818. spin_lock_irqsave(&priv->lock, flags);
  5819. ch_info = iwl3945_get_channel_info(priv, conf->phymode, conf->channel);
  5820. if (!is_channel_valid(ch_info)) {
  5821. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5822. conf->channel, conf->phymode);
  5823. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5824. spin_unlock_irqrestore(&priv->lock, flags);
  5825. mutex_unlock(&priv->mutex);
  5826. return -EINVAL;
  5827. }
  5828. iwl3945_set_rxon_channel(priv, conf->phymode, conf->channel);
  5829. iwl3945_set_flags_for_phymode(priv, conf->phymode);
  5830. /* The list of supported rates and rate mask can be different
  5831. * for each phymode; since the phymode may have changed, reset
  5832. * the rate mask to what mac80211 lists */
  5833. iwl3945_set_rate(priv);
  5834. spin_unlock_irqrestore(&priv->lock, flags);
  5835. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5836. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5837. iwl3945_hw_channel_switch(priv, conf->channel);
  5838. mutex_unlock(&priv->mutex);
  5839. return 0;
  5840. }
  5841. #endif
  5842. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5843. if (!conf->radio_enabled) {
  5844. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5845. mutex_unlock(&priv->mutex);
  5846. return 0;
  5847. }
  5848. if (iwl3945_is_rfkill(priv)) {
  5849. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5850. mutex_unlock(&priv->mutex);
  5851. return -EIO;
  5852. }
  5853. iwl3945_set_rate(priv);
  5854. if (memcmp(&priv->active_rxon,
  5855. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5856. iwl3945_commit_rxon(priv);
  5857. else
  5858. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5859. IWL_DEBUG_MAC80211("leave\n");
  5860. mutex_unlock(&priv->mutex);
  5861. return 0;
  5862. }
  5863. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5864. {
  5865. int rc = 0;
  5866. if (priv->status & STATUS_EXIT_PENDING)
  5867. return;
  5868. /* The following should be done only at AP bring up */
  5869. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5870. /* RXON - unassoc (to set timing command) */
  5871. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5872. iwl3945_commit_rxon(priv);
  5873. /* RXON Timing */
  5874. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5875. iwl3945_setup_rxon_timing(priv);
  5876. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5877. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5878. if (rc)
  5879. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5880. "Attempting to continue.\n");
  5881. /* FIXME: what should be the assoc_id for AP? */
  5882. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5883. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5884. priv->staging_rxon.flags |=
  5885. RXON_FLG_SHORT_PREAMBLE_MSK;
  5886. else
  5887. priv->staging_rxon.flags &=
  5888. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5889. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5890. if (priv->assoc_capability &
  5891. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5892. priv->staging_rxon.flags |=
  5893. RXON_FLG_SHORT_SLOT_MSK;
  5894. else
  5895. priv->staging_rxon.flags &=
  5896. ~RXON_FLG_SHORT_SLOT_MSK;
  5897. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5898. priv->staging_rxon.flags &=
  5899. ~RXON_FLG_SHORT_SLOT_MSK;
  5900. }
  5901. /* restore RXON assoc */
  5902. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5903. iwl3945_commit_rxon(priv);
  5904. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5905. }
  5906. iwl3945_send_beacon_cmd(priv);
  5907. /* FIXME - we need to add code here to detect a totally new
  5908. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5909. * clear sta table, add BCAST sta... */
  5910. }
  5911. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, int if_id,
  5912. struct ieee80211_if_conf *conf)
  5913. {
  5914. struct iwl3945_priv *priv = hw->priv;
  5915. DECLARE_MAC_BUF(mac);
  5916. unsigned long flags;
  5917. int rc;
  5918. if (conf == NULL)
  5919. return -EIO;
  5920. /* XXX: this MUST use conf->mac_addr */
  5921. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5922. (!conf->beacon || !conf->ssid_len)) {
  5923. IWL_DEBUG_MAC80211
  5924. ("Leaving in AP mode because HostAPD is not ready.\n");
  5925. return 0;
  5926. }
  5927. mutex_lock(&priv->mutex);
  5928. IWL_DEBUG_MAC80211("enter: interface id %d\n", if_id);
  5929. if (conf->bssid)
  5930. IWL_DEBUG_MAC80211("bssid: %s\n",
  5931. print_mac(mac, conf->bssid));
  5932. /*
  5933. * very dubious code was here; the probe filtering flag is never set:
  5934. *
  5935. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5936. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5937. */
  5938. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  5939. IWL_DEBUG_MAC80211("leave - scanning\n");
  5940. mutex_unlock(&priv->mutex);
  5941. return 0;
  5942. }
  5943. if (priv->interface_id != if_id) {
  5944. IWL_DEBUG_MAC80211("leave - interface_id != if_id\n");
  5945. mutex_unlock(&priv->mutex);
  5946. return 0;
  5947. }
  5948. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5949. if (!conf->bssid) {
  5950. conf->bssid = priv->mac_addr;
  5951. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5952. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5953. print_mac(mac, conf->bssid));
  5954. }
  5955. if (priv->ibss_beacon)
  5956. dev_kfree_skb(priv->ibss_beacon);
  5957. priv->ibss_beacon = conf->beacon;
  5958. }
  5959. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5960. !is_multicast_ether_addr(conf->bssid)) {
  5961. /* If there is currently a HW scan going on in the background
  5962. * then we need to cancel it else the RXON below will fail. */
  5963. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5964. IWL_WARNING("Aborted scan still in progress "
  5965. "after 100ms\n");
  5966. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5967. mutex_unlock(&priv->mutex);
  5968. return -EAGAIN;
  5969. }
  5970. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5971. /* TODO: Audit driver for usage of these members and see
  5972. * if mac80211 deprecates them (priv->bssid looks like it
  5973. * shouldn't be there, but I haven't scanned the IBSS code
  5974. * to verify) - jpk */
  5975. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5976. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5977. iwl3945_config_ap(priv);
  5978. else {
  5979. rc = iwl3945_commit_rxon(priv);
  5980. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5981. iwl3945_add_station(priv,
  5982. priv->active_rxon.bssid_addr, 1, 0);
  5983. }
  5984. } else {
  5985. iwl3945_scan_cancel_timeout(priv, 100);
  5986. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5987. iwl3945_commit_rxon(priv);
  5988. }
  5989. spin_lock_irqsave(&priv->lock, flags);
  5990. if (!conf->ssid_len)
  5991. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5992. else
  5993. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5994. priv->essid_len = conf->ssid_len;
  5995. spin_unlock_irqrestore(&priv->lock, flags);
  5996. IWL_DEBUG_MAC80211("leave\n");
  5997. mutex_unlock(&priv->mutex);
  5998. return 0;
  5999. }
  6000. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  6001. unsigned int changed_flags,
  6002. unsigned int *total_flags,
  6003. int mc_count, struct dev_addr_list *mc_list)
  6004. {
  6005. /*
  6006. * XXX: dummy
  6007. * see also iwl3945_connection_init_rx_config
  6008. */
  6009. *total_flags = 0;
  6010. }
  6011. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  6012. struct ieee80211_if_init_conf *conf)
  6013. {
  6014. struct iwl3945_priv *priv = hw->priv;
  6015. IWL_DEBUG_MAC80211("enter\n");
  6016. mutex_lock(&priv->mutex);
  6017. iwl3945_scan_cancel_timeout(priv, 100);
  6018. cancel_delayed_work(&priv->post_associate);
  6019. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6020. iwl3945_commit_rxon(priv);
  6021. if (priv->interface_id == conf->if_id) {
  6022. priv->interface_id = 0;
  6023. memset(priv->bssid, 0, ETH_ALEN);
  6024. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6025. priv->essid_len = 0;
  6026. }
  6027. mutex_unlock(&priv->mutex);
  6028. IWL_DEBUG_MAC80211("leave\n");
  6029. }
  6030. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  6031. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6032. {
  6033. int rc = 0;
  6034. unsigned long flags;
  6035. struct iwl3945_priv *priv = hw->priv;
  6036. IWL_DEBUG_MAC80211("enter\n");
  6037. mutex_lock(&priv->mutex);
  6038. spin_lock_irqsave(&priv->lock, flags);
  6039. if (!iwl3945_is_ready_rf(priv)) {
  6040. rc = -EIO;
  6041. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6042. goto out_unlock;
  6043. }
  6044. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6045. rc = -EIO;
  6046. IWL_ERROR("ERROR: APs don't scan\n");
  6047. goto out_unlock;
  6048. }
  6049. /* if we just finished scan ask for delay */
  6050. if (priv->last_scan_jiffies &&
  6051. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  6052. jiffies)) {
  6053. rc = -EAGAIN;
  6054. goto out_unlock;
  6055. }
  6056. if (len) {
  6057. IWL_DEBUG_SCAN("direct scan for "
  6058. "%s [%d]\n ",
  6059. iwl3945_escape_essid(ssid, len), (int)len);
  6060. priv->one_direct_scan = 1;
  6061. priv->direct_ssid_len = (u8)
  6062. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6063. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6064. } else
  6065. priv->one_direct_scan = 0;
  6066. rc = iwl3945_scan_initiate(priv);
  6067. IWL_DEBUG_MAC80211("leave\n");
  6068. out_unlock:
  6069. spin_unlock_irqrestore(&priv->lock, flags);
  6070. mutex_unlock(&priv->mutex);
  6071. return rc;
  6072. }
  6073. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6074. const u8 *local_addr, const u8 *addr,
  6075. struct ieee80211_key_conf *key)
  6076. {
  6077. struct iwl3945_priv *priv = hw->priv;
  6078. int rc = 0;
  6079. u8 sta_id;
  6080. IWL_DEBUG_MAC80211("enter\n");
  6081. if (!iwl3945_param_hwcrypto) {
  6082. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6083. return -EOPNOTSUPP;
  6084. }
  6085. if (is_zero_ether_addr(addr))
  6086. /* only support pairwise keys */
  6087. return -EOPNOTSUPP;
  6088. sta_id = iwl3945_hw_find_station(priv, addr);
  6089. if (sta_id == IWL_INVALID_STATION) {
  6090. DECLARE_MAC_BUF(mac);
  6091. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6092. print_mac(mac, addr));
  6093. return -EINVAL;
  6094. }
  6095. mutex_lock(&priv->mutex);
  6096. iwl3945_scan_cancel_timeout(priv, 100);
  6097. switch (cmd) {
  6098. case SET_KEY:
  6099. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6100. if (!rc) {
  6101. iwl3945_set_rxon_hwcrypto(priv, 1);
  6102. iwl3945_commit_rxon(priv);
  6103. key->hw_key_idx = sta_id;
  6104. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6105. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6106. }
  6107. break;
  6108. case DISABLE_KEY:
  6109. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6110. if (!rc) {
  6111. iwl3945_set_rxon_hwcrypto(priv, 0);
  6112. iwl3945_commit_rxon(priv);
  6113. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6114. }
  6115. break;
  6116. default:
  6117. rc = -EINVAL;
  6118. }
  6119. IWL_DEBUG_MAC80211("leave\n");
  6120. mutex_unlock(&priv->mutex);
  6121. return rc;
  6122. }
  6123. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6124. const struct ieee80211_tx_queue_params *params)
  6125. {
  6126. struct iwl3945_priv *priv = hw->priv;
  6127. #ifdef CONFIG_IWL3945_QOS
  6128. unsigned long flags;
  6129. int q;
  6130. #endif /* CONFIG_IWL3945_QOS */
  6131. IWL_DEBUG_MAC80211("enter\n");
  6132. if (!iwl3945_is_ready_rf(priv)) {
  6133. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6134. return -EIO;
  6135. }
  6136. if (queue >= AC_NUM) {
  6137. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6138. return 0;
  6139. }
  6140. #ifdef CONFIG_IWL3945_QOS
  6141. if (!priv->qos_data.qos_enable) {
  6142. priv->qos_data.qos_active = 0;
  6143. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6144. return 0;
  6145. }
  6146. q = AC_NUM - 1 - queue;
  6147. spin_lock_irqsave(&priv->lock, flags);
  6148. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6149. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6150. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6151. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6152. cpu_to_le16((params->burst_time * 100));
  6153. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6154. priv->qos_data.qos_active = 1;
  6155. spin_unlock_irqrestore(&priv->lock, flags);
  6156. mutex_lock(&priv->mutex);
  6157. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6158. iwl3945_activate_qos(priv, 1);
  6159. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6160. iwl3945_activate_qos(priv, 0);
  6161. mutex_unlock(&priv->mutex);
  6162. #endif /*CONFIG_IWL3945_QOS */
  6163. IWL_DEBUG_MAC80211("leave\n");
  6164. return 0;
  6165. }
  6166. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6167. struct ieee80211_tx_queue_stats *stats)
  6168. {
  6169. struct iwl3945_priv *priv = hw->priv;
  6170. int i, avail;
  6171. struct iwl3945_tx_queue *txq;
  6172. struct iwl3945_queue *q;
  6173. unsigned long flags;
  6174. IWL_DEBUG_MAC80211("enter\n");
  6175. if (!iwl3945_is_ready_rf(priv)) {
  6176. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6177. return -EIO;
  6178. }
  6179. spin_lock_irqsave(&priv->lock, flags);
  6180. for (i = 0; i < AC_NUM; i++) {
  6181. txq = &priv->txq[i];
  6182. q = &txq->q;
  6183. avail = iwl3945_queue_space(q);
  6184. stats->data[i].len = q->n_window - avail;
  6185. stats->data[i].limit = q->n_window - q->high_mark;
  6186. stats->data[i].count = q->n_window;
  6187. }
  6188. spin_unlock_irqrestore(&priv->lock, flags);
  6189. IWL_DEBUG_MAC80211("leave\n");
  6190. return 0;
  6191. }
  6192. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6193. struct ieee80211_low_level_stats *stats)
  6194. {
  6195. IWL_DEBUG_MAC80211("enter\n");
  6196. IWL_DEBUG_MAC80211("leave\n");
  6197. return 0;
  6198. }
  6199. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6200. {
  6201. IWL_DEBUG_MAC80211("enter\n");
  6202. IWL_DEBUG_MAC80211("leave\n");
  6203. return 0;
  6204. }
  6205. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6206. {
  6207. struct iwl3945_priv *priv = hw->priv;
  6208. unsigned long flags;
  6209. mutex_lock(&priv->mutex);
  6210. IWL_DEBUG_MAC80211("enter\n");
  6211. #ifdef CONFIG_IWL3945_QOS
  6212. iwl3945_reset_qos(priv);
  6213. #endif
  6214. cancel_delayed_work(&priv->post_associate);
  6215. spin_lock_irqsave(&priv->lock, flags);
  6216. priv->assoc_id = 0;
  6217. priv->assoc_capability = 0;
  6218. priv->call_post_assoc_from_beacon = 0;
  6219. /* new association get rid of ibss beacon skb */
  6220. if (priv->ibss_beacon)
  6221. dev_kfree_skb(priv->ibss_beacon);
  6222. priv->ibss_beacon = NULL;
  6223. priv->beacon_int = priv->hw->conf.beacon_int;
  6224. priv->timestamp1 = 0;
  6225. priv->timestamp0 = 0;
  6226. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6227. priv->beacon_int = 0;
  6228. spin_unlock_irqrestore(&priv->lock, flags);
  6229. /* we are restarting association process
  6230. * clear RXON_FILTER_ASSOC_MSK bit
  6231. */
  6232. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6233. iwl3945_scan_cancel_timeout(priv, 100);
  6234. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6235. iwl3945_commit_rxon(priv);
  6236. }
  6237. /* Per mac80211.h: This is only used in IBSS mode... */
  6238. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6239. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6240. mutex_unlock(&priv->mutex);
  6241. return;
  6242. }
  6243. if (!iwl3945_is_ready_rf(priv)) {
  6244. IWL_DEBUG_MAC80211("leave - not ready\n");
  6245. mutex_unlock(&priv->mutex);
  6246. return;
  6247. }
  6248. priv->only_active_channel = 0;
  6249. iwl3945_set_rate(priv);
  6250. mutex_unlock(&priv->mutex);
  6251. IWL_DEBUG_MAC80211("leave\n");
  6252. }
  6253. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6254. struct ieee80211_tx_control *control)
  6255. {
  6256. struct iwl3945_priv *priv = hw->priv;
  6257. unsigned long flags;
  6258. mutex_lock(&priv->mutex);
  6259. IWL_DEBUG_MAC80211("enter\n");
  6260. if (!iwl3945_is_ready_rf(priv)) {
  6261. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6262. mutex_unlock(&priv->mutex);
  6263. return -EIO;
  6264. }
  6265. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6266. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6267. mutex_unlock(&priv->mutex);
  6268. return -EIO;
  6269. }
  6270. spin_lock_irqsave(&priv->lock, flags);
  6271. if (priv->ibss_beacon)
  6272. dev_kfree_skb(priv->ibss_beacon);
  6273. priv->ibss_beacon = skb;
  6274. priv->assoc_id = 0;
  6275. IWL_DEBUG_MAC80211("leave\n");
  6276. spin_unlock_irqrestore(&priv->lock, flags);
  6277. #ifdef CONFIG_IWL3945_QOS
  6278. iwl3945_reset_qos(priv);
  6279. #endif
  6280. queue_work(priv->workqueue, &priv->post_associate.work);
  6281. mutex_unlock(&priv->mutex);
  6282. return 0;
  6283. }
  6284. /*****************************************************************************
  6285. *
  6286. * sysfs attributes
  6287. *
  6288. *****************************************************************************/
  6289. #ifdef CONFIG_IWL3945_DEBUG
  6290. /*
  6291. * The following adds a new attribute to the sysfs representation
  6292. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6293. * used for controlling the debug level.
  6294. *
  6295. * See the level definitions in iwl for details.
  6296. */
  6297. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6298. {
  6299. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6300. }
  6301. static ssize_t store_debug_level(struct device_driver *d,
  6302. const char *buf, size_t count)
  6303. {
  6304. char *p = (char *)buf;
  6305. u32 val;
  6306. val = simple_strtoul(p, &p, 0);
  6307. if (p == buf)
  6308. printk(KERN_INFO DRV_NAME
  6309. ": %s is not in hex or decimal form.\n", buf);
  6310. else
  6311. iwl3945_debug_level = val;
  6312. return strnlen(buf, count);
  6313. }
  6314. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6315. show_debug_level, store_debug_level);
  6316. #endif /* CONFIG_IWL3945_DEBUG */
  6317. static ssize_t show_rf_kill(struct device *d,
  6318. struct device_attribute *attr, char *buf)
  6319. {
  6320. /*
  6321. * 0 - RF kill not enabled
  6322. * 1 - SW based RF kill active (sysfs)
  6323. * 2 - HW based RF kill active
  6324. * 3 - Both HW and SW based RF kill active
  6325. */
  6326. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6327. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6328. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6329. return sprintf(buf, "%i\n", val);
  6330. }
  6331. static ssize_t store_rf_kill(struct device *d,
  6332. struct device_attribute *attr,
  6333. const char *buf, size_t count)
  6334. {
  6335. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6336. mutex_lock(&priv->mutex);
  6337. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6338. mutex_unlock(&priv->mutex);
  6339. return count;
  6340. }
  6341. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6342. static ssize_t show_temperature(struct device *d,
  6343. struct device_attribute *attr, char *buf)
  6344. {
  6345. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6346. if (!iwl3945_is_alive(priv))
  6347. return -EAGAIN;
  6348. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6349. }
  6350. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6351. static ssize_t show_rs_window(struct device *d,
  6352. struct device_attribute *attr,
  6353. char *buf)
  6354. {
  6355. struct iwl3945_priv *priv = d->driver_data;
  6356. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6357. }
  6358. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6359. static ssize_t show_tx_power(struct device *d,
  6360. struct device_attribute *attr, char *buf)
  6361. {
  6362. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6363. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6364. }
  6365. static ssize_t store_tx_power(struct device *d,
  6366. struct device_attribute *attr,
  6367. const char *buf, size_t count)
  6368. {
  6369. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6370. char *p = (char *)buf;
  6371. u32 val;
  6372. val = simple_strtoul(p, &p, 10);
  6373. if (p == buf)
  6374. printk(KERN_INFO DRV_NAME
  6375. ": %s is not in decimal form.\n", buf);
  6376. else
  6377. iwl3945_hw_reg_set_txpower(priv, val);
  6378. return count;
  6379. }
  6380. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6381. static ssize_t show_flags(struct device *d,
  6382. struct device_attribute *attr, char *buf)
  6383. {
  6384. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6385. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6386. }
  6387. static ssize_t store_flags(struct device *d,
  6388. struct device_attribute *attr,
  6389. const char *buf, size_t count)
  6390. {
  6391. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6392. u32 flags = simple_strtoul(buf, NULL, 0);
  6393. mutex_lock(&priv->mutex);
  6394. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6395. /* Cancel any currently running scans... */
  6396. if (iwl3945_scan_cancel_timeout(priv, 100))
  6397. IWL_WARNING("Could not cancel scan.\n");
  6398. else {
  6399. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6400. flags);
  6401. priv->staging_rxon.flags = cpu_to_le32(flags);
  6402. iwl3945_commit_rxon(priv);
  6403. }
  6404. }
  6405. mutex_unlock(&priv->mutex);
  6406. return count;
  6407. }
  6408. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6409. static ssize_t show_filter_flags(struct device *d,
  6410. struct device_attribute *attr, char *buf)
  6411. {
  6412. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6413. return sprintf(buf, "0x%04X\n",
  6414. le32_to_cpu(priv->active_rxon.filter_flags));
  6415. }
  6416. static ssize_t store_filter_flags(struct device *d,
  6417. struct device_attribute *attr,
  6418. const char *buf, size_t count)
  6419. {
  6420. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6421. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6422. mutex_lock(&priv->mutex);
  6423. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6424. /* Cancel any currently running scans... */
  6425. if (iwl3945_scan_cancel_timeout(priv, 100))
  6426. IWL_WARNING("Could not cancel scan.\n");
  6427. else {
  6428. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6429. "0x%04X\n", filter_flags);
  6430. priv->staging_rxon.filter_flags =
  6431. cpu_to_le32(filter_flags);
  6432. iwl3945_commit_rxon(priv);
  6433. }
  6434. }
  6435. mutex_unlock(&priv->mutex);
  6436. return count;
  6437. }
  6438. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6439. store_filter_flags);
  6440. static ssize_t show_tune(struct device *d,
  6441. struct device_attribute *attr, char *buf)
  6442. {
  6443. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6444. return sprintf(buf, "0x%04X\n",
  6445. (priv->phymode << 8) |
  6446. le16_to_cpu(priv->active_rxon.channel));
  6447. }
  6448. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode);
  6449. static ssize_t store_tune(struct device *d,
  6450. struct device_attribute *attr,
  6451. const char *buf, size_t count)
  6452. {
  6453. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6454. char *p = (char *)buf;
  6455. u16 tune = simple_strtoul(p, &p, 0);
  6456. u8 phymode = (tune >> 8) & 0xff;
  6457. u16 channel = tune & 0xff;
  6458. IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
  6459. mutex_lock(&priv->mutex);
  6460. if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
  6461. (priv->phymode != phymode)) {
  6462. const struct iwl3945_channel_info *ch_info;
  6463. ch_info = iwl3945_get_channel_info(priv, phymode, channel);
  6464. if (!ch_info) {
  6465. IWL_WARNING("Requested invalid phymode/channel "
  6466. "combination: %d %d\n", phymode, channel);
  6467. mutex_unlock(&priv->mutex);
  6468. return -EINVAL;
  6469. }
  6470. /* Cancel any currently running scans... */
  6471. if (iwl3945_scan_cancel_timeout(priv, 100))
  6472. IWL_WARNING("Could not cancel scan.\n");
  6473. else {
  6474. IWL_DEBUG_INFO("Committing phymode and "
  6475. "rxon.channel = %d %d\n",
  6476. phymode, channel);
  6477. iwl3945_set_rxon_channel(priv, phymode, channel);
  6478. iwl3945_set_flags_for_phymode(priv, phymode);
  6479. iwl3945_set_rate(priv);
  6480. iwl3945_commit_rxon(priv);
  6481. }
  6482. }
  6483. mutex_unlock(&priv->mutex);
  6484. return count;
  6485. }
  6486. static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
  6487. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6488. static ssize_t show_measurement(struct device *d,
  6489. struct device_attribute *attr, char *buf)
  6490. {
  6491. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6492. struct iwl3945_spectrum_notification measure_report;
  6493. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6494. u8 *data = (u8 *) & measure_report;
  6495. unsigned long flags;
  6496. spin_lock_irqsave(&priv->lock, flags);
  6497. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6498. spin_unlock_irqrestore(&priv->lock, flags);
  6499. return 0;
  6500. }
  6501. memcpy(&measure_report, &priv->measure_report, size);
  6502. priv->measurement_status = 0;
  6503. spin_unlock_irqrestore(&priv->lock, flags);
  6504. while (size && (PAGE_SIZE - len)) {
  6505. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6506. PAGE_SIZE - len, 1);
  6507. len = strlen(buf);
  6508. if (PAGE_SIZE - len)
  6509. buf[len++] = '\n';
  6510. ofs += 16;
  6511. size -= min(size, 16U);
  6512. }
  6513. return len;
  6514. }
  6515. static ssize_t store_measurement(struct device *d,
  6516. struct device_attribute *attr,
  6517. const char *buf, size_t count)
  6518. {
  6519. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6520. struct ieee80211_measurement_params params = {
  6521. .channel = le16_to_cpu(priv->active_rxon.channel),
  6522. .start_time = cpu_to_le64(priv->last_tsf),
  6523. .duration = cpu_to_le16(1),
  6524. };
  6525. u8 type = IWL_MEASURE_BASIC;
  6526. u8 buffer[32];
  6527. u8 channel;
  6528. if (count) {
  6529. char *p = buffer;
  6530. strncpy(buffer, buf, min(sizeof(buffer), count));
  6531. channel = simple_strtoul(p, NULL, 0);
  6532. if (channel)
  6533. params.channel = channel;
  6534. p = buffer;
  6535. while (*p && *p != ' ')
  6536. p++;
  6537. if (*p)
  6538. type = simple_strtoul(p + 1, NULL, 0);
  6539. }
  6540. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6541. "channel %d (for '%s')\n", type, params.channel, buf);
  6542. iwl3945_get_measurement(priv, &params, type);
  6543. return count;
  6544. }
  6545. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6546. show_measurement, store_measurement);
  6547. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6548. static ssize_t show_rate(struct device *d,
  6549. struct device_attribute *attr, char *buf)
  6550. {
  6551. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6552. unsigned long flags;
  6553. int i;
  6554. spin_lock_irqsave(&priv->sta_lock, flags);
  6555. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  6556. i = priv->stations[IWL_AP_ID].current_rate.s.rate;
  6557. else
  6558. i = priv->stations[IWL_STA_ID].current_rate.s.rate;
  6559. spin_unlock_irqrestore(&priv->sta_lock, flags);
  6560. i = iwl3945_rate_index_from_plcp(i);
  6561. if (i == -1)
  6562. return sprintf(buf, "0\n");
  6563. return sprintf(buf, "%d%s\n",
  6564. (iwl3945_rates[i].ieee >> 1),
  6565. (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
  6566. }
  6567. static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
  6568. static ssize_t store_retry_rate(struct device *d,
  6569. struct device_attribute *attr,
  6570. const char *buf, size_t count)
  6571. {
  6572. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6573. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6574. if (priv->retry_rate <= 0)
  6575. priv->retry_rate = 1;
  6576. return count;
  6577. }
  6578. static ssize_t show_retry_rate(struct device *d,
  6579. struct device_attribute *attr, char *buf)
  6580. {
  6581. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6582. return sprintf(buf, "%d", priv->retry_rate);
  6583. }
  6584. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6585. store_retry_rate);
  6586. static ssize_t store_power_level(struct device *d,
  6587. struct device_attribute *attr,
  6588. const char *buf, size_t count)
  6589. {
  6590. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6591. int rc;
  6592. int mode;
  6593. mode = simple_strtoul(buf, NULL, 0);
  6594. mutex_lock(&priv->mutex);
  6595. if (!iwl3945_is_ready(priv)) {
  6596. rc = -EAGAIN;
  6597. goto out;
  6598. }
  6599. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6600. mode = IWL_POWER_AC;
  6601. else
  6602. mode |= IWL_POWER_ENABLED;
  6603. if (mode != priv->power_mode) {
  6604. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6605. if (rc) {
  6606. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6607. goto out;
  6608. }
  6609. priv->power_mode = mode;
  6610. }
  6611. rc = count;
  6612. out:
  6613. mutex_unlock(&priv->mutex);
  6614. return rc;
  6615. }
  6616. #define MAX_WX_STRING 80
  6617. /* Values are in microsecond */
  6618. static const s32 timeout_duration[] = {
  6619. 350000,
  6620. 250000,
  6621. 75000,
  6622. 37000,
  6623. 25000,
  6624. };
  6625. static const s32 period_duration[] = {
  6626. 400000,
  6627. 700000,
  6628. 1000000,
  6629. 1000000,
  6630. 1000000
  6631. };
  6632. static ssize_t show_power_level(struct device *d,
  6633. struct device_attribute *attr, char *buf)
  6634. {
  6635. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6636. int level = IWL_POWER_LEVEL(priv->power_mode);
  6637. char *p = buf;
  6638. p += sprintf(p, "%d ", level);
  6639. switch (level) {
  6640. case IWL_POWER_MODE_CAM:
  6641. case IWL_POWER_AC:
  6642. p += sprintf(p, "(AC)");
  6643. break;
  6644. case IWL_POWER_BATTERY:
  6645. p += sprintf(p, "(BATTERY)");
  6646. break;
  6647. default:
  6648. p += sprintf(p,
  6649. "(Timeout %dms, Period %dms)",
  6650. timeout_duration[level - 1] / 1000,
  6651. period_duration[level - 1] / 1000);
  6652. }
  6653. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6654. p += sprintf(p, " OFF\n");
  6655. else
  6656. p += sprintf(p, " \n");
  6657. return (p - buf + 1);
  6658. }
  6659. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6660. store_power_level);
  6661. static ssize_t show_channels(struct device *d,
  6662. struct device_attribute *attr, char *buf)
  6663. {
  6664. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6665. int len = 0, i;
  6666. struct ieee80211_channel *channels = NULL;
  6667. const struct ieee80211_hw_mode *hw_mode = NULL;
  6668. int count = 0;
  6669. if (!iwl3945_is_ready(priv))
  6670. return -EAGAIN;
  6671. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211G);
  6672. if (!hw_mode)
  6673. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211B);
  6674. if (hw_mode) {
  6675. channels = hw_mode->channels;
  6676. count = hw_mode->num_channels;
  6677. }
  6678. len +=
  6679. sprintf(&buf[len],
  6680. "Displaying %d channels in 2.4GHz band "
  6681. "(802.11bg):\n", count);
  6682. for (i = 0; i < count; i++)
  6683. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6684. channels[i].chan,
  6685. channels[i].power_level,
  6686. channels[i].
  6687. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6688. " (IEEE 802.11h required)" : "",
  6689. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6690. || (channels[i].
  6691. flag &
  6692. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6693. ", IBSS",
  6694. channels[i].
  6695. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6696. "active/passive" : "passive only");
  6697. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211A);
  6698. if (hw_mode) {
  6699. channels = hw_mode->channels;
  6700. count = hw_mode->num_channels;
  6701. } else {
  6702. channels = NULL;
  6703. count = 0;
  6704. }
  6705. len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
  6706. "(802.11a):\n", count);
  6707. for (i = 0; i < count; i++)
  6708. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6709. channels[i].chan,
  6710. channels[i].power_level,
  6711. channels[i].
  6712. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6713. " (IEEE 802.11h required)" : "",
  6714. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6715. || (channels[i].
  6716. flag &
  6717. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6718. ", IBSS",
  6719. channels[i].
  6720. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6721. "active/passive" : "passive only");
  6722. return len;
  6723. }
  6724. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6725. static ssize_t show_statistics(struct device *d,
  6726. struct device_attribute *attr, char *buf)
  6727. {
  6728. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6729. u32 size = sizeof(struct iwl3945_notif_statistics);
  6730. u32 len = 0, ofs = 0;
  6731. u8 *data = (u8 *) & priv->statistics;
  6732. int rc = 0;
  6733. if (!iwl3945_is_alive(priv))
  6734. return -EAGAIN;
  6735. mutex_lock(&priv->mutex);
  6736. rc = iwl3945_send_statistics_request(priv);
  6737. mutex_unlock(&priv->mutex);
  6738. if (rc) {
  6739. len = sprintf(buf,
  6740. "Error sending statistics request: 0x%08X\n", rc);
  6741. return len;
  6742. }
  6743. while (size && (PAGE_SIZE - len)) {
  6744. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6745. PAGE_SIZE - len, 1);
  6746. len = strlen(buf);
  6747. if (PAGE_SIZE - len)
  6748. buf[len++] = '\n';
  6749. ofs += 16;
  6750. size -= min(size, 16U);
  6751. }
  6752. return len;
  6753. }
  6754. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6755. static ssize_t show_antenna(struct device *d,
  6756. struct device_attribute *attr, char *buf)
  6757. {
  6758. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6759. if (!iwl3945_is_alive(priv))
  6760. return -EAGAIN;
  6761. return sprintf(buf, "%d\n", priv->antenna);
  6762. }
  6763. static ssize_t store_antenna(struct device *d,
  6764. struct device_attribute *attr,
  6765. const char *buf, size_t count)
  6766. {
  6767. int ant;
  6768. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6769. if (count == 0)
  6770. return 0;
  6771. if (sscanf(buf, "%1i", &ant) != 1) {
  6772. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6773. return count;
  6774. }
  6775. if ((ant >= 0) && (ant <= 2)) {
  6776. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6777. priv->antenna = (enum iwl3945_antenna)ant;
  6778. } else
  6779. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6780. return count;
  6781. }
  6782. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6783. static ssize_t show_status(struct device *d,
  6784. struct device_attribute *attr, char *buf)
  6785. {
  6786. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6787. if (!iwl3945_is_alive(priv))
  6788. return -EAGAIN;
  6789. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6790. }
  6791. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6792. static ssize_t dump_error_log(struct device *d,
  6793. struct device_attribute *attr,
  6794. const char *buf, size_t count)
  6795. {
  6796. char *p = (char *)buf;
  6797. if (p[0] == '1')
  6798. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6799. return strnlen(buf, count);
  6800. }
  6801. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6802. static ssize_t dump_event_log(struct device *d,
  6803. struct device_attribute *attr,
  6804. const char *buf, size_t count)
  6805. {
  6806. char *p = (char *)buf;
  6807. if (p[0] == '1')
  6808. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6809. return strnlen(buf, count);
  6810. }
  6811. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6812. /*****************************************************************************
  6813. *
  6814. * driver setup and teardown
  6815. *
  6816. *****************************************************************************/
  6817. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6818. {
  6819. priv->workqueue = create_workqueue(DRV_NAME);
  6820. init_waitqueue_head(&priv->wait_command_queue);
  6821. INIT_WORK(&priv->up, iwl3945_bg_up);
  6822. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6823. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6824. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6825. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6826. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6827. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6828. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6829. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6830. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6831. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6832. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6833. iwl3945_hw_setup_deferred_work(priv);
  6834. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6835. iwl3945_irq_tasklet, (unsigned long)priv);
  6836. }
  6837. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6838. {
  6839. iwl3945_hw_cancel_deferred_work(priv);
  6840. cancel_delayed_work_sync(&priv->init_alive_start);
  6841. cancel_delayed_work(&priv->scan_check);
  6842. cancel_delayed_work(&priv->alive_start);
  6843. cancel_delayed_work(&priv->post_associate);
  6844. cancel_work_sync(&priv->beacon_update);
  6845. }
  6846. static struct attribute *iwl3945_sysfs_entries[] = {
  6847. &dev_attr_antenna.attr,
  6848. &dev_attr_channels.attr,
  6849. &dev_attr_dump_errors.attr,
  6850. &dev_attr_dump_events.attr,
  6851. &dev_attr_flags.attr,
  6852. &dev_attr_filter_flags.attr,
  6853. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6854. &dev_attr_measurement.attr,
  6855. #endif
  6856. &dev_attr_power_level.attr,
  6857. &dev_attr_rate.attr,
  6858. &dev_attr_retry_rate.attr,
  6859. &dev_attr_rf_kill.attr,
  6860. &dev_attr_rs_window.attr,
  6861. &dev_attr_statistics.attr,
  6862. &dev_attr_status.attr,
  6863. &dev_attr_temperature.attr,
  6864. &dev_attr_tune.attr,
  6865. &dev_attr_tx_power.attr,
  6866. NULL
  6867. };
  6868. static struct attribute_group iwl3945_attribute_group = {
  6869. .name = NULL, /* put in device directory */
  6870. .attrs = iwl3945_sysfs_entries,
  6871. };
  6872. static struct ieee80211_ops iwl3945_hw_ops = {
  6873. .tx = iwl3945_mac_tx,
  6874. .start = iwl3945_mac_start,
  6875. .stop = iwl3945_mac_stop,
  6876. .add_interface = iwl3945_mac_add_interface,
  6877. .remove_interface = iwl3945_mac_remove_interface,
  6878. .config = iwl3945_mac_config,
  6879. .config_interface = iwl3945_mac_config_interface,
  6880. .configure_filter = iwl3945_configure_filter,
  6881. .set_key = iwl3945_mac_set_key,
  6882. .get_stats = iwl3945_mac_get_stats,
  6883. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6884. .conf_tx = iwl3945_mac_conf_tx,
  6885. .get_tsf = iwl3945_mac_get_tsf,
  6886. .reset_tsf = iwl3945_mac_reset_tsf,
  6887. .beacon_update = iwl3945_mac_beacon_update,
  6888. .hw_scan = iwl3945_mac_hw_scan
  6889. };
  6890. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6891. {
  6892. int err = 0;
  6893. u32 pci_id;
  6894. struct iwl3945_priv *priv;
  6895. struct ieee80211_hw *hw;
  6896. int i;
  6897. if (iwl3945_param_disable_hw_scan) {
  6898. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6899. iwl3945_hw_ops.hw_scan = NULL;
  6900. }
  6901. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6902. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6903. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6904. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6905. err = -EINVAL;
  6906. goto out;
  6907. }
  6908. /* mac80211 allocates memory for this device instance, including
  6909. * space for this driver's private structure */
  6910. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6911. if (hw == NULL) {
  6912. IWL_ERROR("Can not allocate network device\n");
  6913. err = -ENOMEM;
  6914. goto out;
  6915. }
  6916. SET_IEEE80211_DEV(hw, &pdev->dev);
  6917. hw->rate_control_algorithm = "iwl-3945-rs";
  6918. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6919. priv = hw->priv;
  6920. priv->hw = hw;
  6921. priv->pci_dev = pdev;
  6922. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6923. #ifdef CONFIG_IWL3945_DEBUG
  6924. iwl3945_debug_level = iwl3945_param_debug;
  6925. atomic_set(&priv->restrict_refcnt, 0);
  6926. #endif
  6927. priv->retry_rate = 1;
  6928. priv->ibss_beacon = NULL;
  6929. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6930. * the range of signal quality values that we'll provide.
  6931. * Negative values for level/noise indicate that we'll provide dBm.
  6932. * For WE, at least, non-0 values here *enable* display of values
  6933. * in app (iwconfig). */
  6934. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6935. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6936. hw->max_signal = 100; /* link quality indication (%) */
  6937. /* Tell mac80211 our Tx characteristics */
  6938. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6939. hw->queues = 4;
  6940. spin_lock_init(&priv->lock);
  6941. spin_lock_init(&priv->power_data.lock);
  6942. spin_lock_init(&priv->sta_lock);
  6943. spin_lock_init(&priv->hcmd_lock);
  6944. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6945. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6946. INIT_LIST_HEAD(&priv->free_frames);
  6947. mutex_init(&priv->mutex);
  6948. if (pci_enable_device(pdev)) {
  6949. err = -ENODEV;
  6950. goto out_ieee80211_free_hw;
  6951. }
  6952. pci_set_master(pdev);
  6953. iwl3945_clear_stations_table(priv);
  6954. priv->data_retry_limit = -1;
  6955. priv->ieee_channels = NULL;
  6956. priv->ieee_rates = NULL;
  6957. priv->phymode = -1;
  6958. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6959. if (!err)
  6960. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6961. if (err) {
  6962. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6963. goto out_pci_disable_device;
  6964. }
  6965. pci_set_drvdata(pdev, priv);
  6966. err = pci_request_regions(pdev, DRV_NAME);
  6967. if (err)
  6968. goto out_pci_disable_device;
  6969. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6970. * PCI Tx retries from interfering with C3 CPU state */
  6971. pci_write_config_byte(pdev, 0x41, 0x00);
  6972. priv->hw_base = pci_iomap(pdev, 0, 0);
  6973. if (!priv->hw_base) {
  6974. err = -ENODEV;
  6975. goto out_pci_release_regions;
  6976. }
  6977. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6978. (unsigned long long) pci_resource_len(pdev, 0));
  6979. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6980. /* Initialize module parameter values here */
  6981. if (iwl3945_param_disable) {
  6982. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6983. IWL_DEBUG_INFO("Radio disabled.\n");
  6984. }
  6985. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6986. pci_id =
  6987. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  6988. switch (pci_id) {
  6989. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  6990. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  6991. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  6992. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  6993. priv->is_abg = 0;
  6994. break;
  6995. /*
  6996. * Rest are assumed ABG SKU -- if this is not the
  6997. * case then the card will get the wrong 'Detected'
  6998. * line in the kernel log however the code that
  6999. * initializes the GEO table will detect no A-band
  7000. * channels and remove the is_abg mask.
  7001. */
  7002. default:
  7003. priv->is_abg = 1;
  7004. break;
  7005. }
  7006. printk(KERN_INFO DRV_NAME
  7007. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  7008. priv->is_abg ? "A" : "");
  7009. /* Device-specific setup */
  7010. if (iwl3945_hw_set_hw_setting(priv)) {
  7011. IWL_ERROR("failed to set hw settings\n");
  7012. mutex_unlock(&priv->mutex);
  7013. goto out_iounmap;
  7014. }
  7015. #ifdef CONFIG_IWL3945_QOS
  7016. if (iwl3945_param_qos_enable)
  7017. priv->qos_data.qos_enable = 1;
  7018. iwl3945_reset_qos(priv);
  7019. priv->qos_data.qos_active = 0;
  7020. priv->qos_data.qos_cap.val = 0;
  7021. #endif /* CONFIG_IWL3945_QOS */
  7022. iwl3945_set_rxon_channel(priv, MODE_IEEE80211G, 6);
  7023. iwl3945_setup_deferred_work(priv);
  7024. iwl3945_setup_rx_handlers(priv);
  7025. priv->rates_mask = IWL_RATES_MASK;
  7026. /* If power management is turned on, default to AC mode */
  7027. priv->power_mode = IWL_POWER_AC;
  7028. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  7029. iwl3945_disable_interrupts(priv);
  7030. pci_enable_msi(pdev);
  7031. err = request_irq(pdev->irq, iwl3945_isr, IRQF_SHARED, DRV_NAME, priv);
  7032. if (err) {
  7033. IWL_ERROR("Error allocating IRQ %d\n", pdev->irq);
  7034. goto out_disable_msi;
  7035. }
  7036. mutex_lock(&priv->mutex);
  7037. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7038. if (err) {
  7039. IWL_ERROR("failed to create sysfs device attributes\n");
  7040. mutex_unlock(&priv->mutex);
  7041. goto out_release_irq;
  7042. }
  7043. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  7044. * ucode filename and max sizes are card-specific. */
  7045. err = iwl3945_read_ucode(priv);
  7046. if (err) {
  7047. IWL_ERROR("Could not read microcode: %d\n", err);
  7048. mutex_unlock(&priv->mutex);
  7049. goto out_pci_alloc;
  7050. }
  7051. mutex_unlock(&priv->mutex);
  7052. IWL_DEBUG_INFO("Queueing UP work.\n");
  7053. queue_work(priv->workqueue, &priv->up);
  7054. return 0;
  7055. out_pci_alloc:
  7056. iwl3945_dealloc_ucode_pci(priv);
  7057. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7058. out_release_irq:
  7059. free_irq(pdev->irq, priv);
  7060. out_disable_msi:
  7061. pci_disable_msi(pdev);
  7062. destroy_workqueue(priv->workqueue);
  7063. priv->workqueue = NULL;
  7064. iwl3945_unset_hw_setting(priv);
  7065. out_iounmap:
  7066. pci_iounmap(pdev, priv->hw_base);
  7067. out_pci_release_regions:
  7068. pci_release_regions(pdev);
  7069. out_pci_disable_device:
  7070. pci_disable_device(pdev);
  7071. pci_set_drvdata(pdev, NULL);
  7072. out_ieee80211_free_hw:
  7073. ieee80211_free_hw(priv->hw);
  7074. out:
  7075. return err;
  7076. }
  7077. static void iwl3945_pci_remove(struct pci_dev *pdev)
  7078. {
  7079. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7080. struct list_head *p, *q;
  7081. int i;
  7082. if (!priv)
  7083. return;
  7084. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7085. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7086. iwl3945_down(priv);
  7087. /* Free MAC hash list for ADHOC */
  7088. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7089. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7090. list_del(p);
  7091. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  7092. }
  7093. }
  7094. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7095. iwl3945_dealloc_ucode_pci(priv);
  7096. if (priv->rxq.bd)
  7097. iwl3945_rx_queue_free(priv, &priv->rxq);
  7098. iwl3945_hw_txq_ctx_free(priv);
  7099. iwl3945_unset_hw_setting(priv);
  7100. iwl3945_clear_stations_table(priv);
  7101. if (priv->mac80211_registered) {
  7102. ieee80211_unregister_hw(priv->hw);
  7103. iwl3945_rate_control_unregister(priv->hw);
  7104. }
  7105. /*netif_stop_queue(dev); */
  7106. flush_workqueue(priv->workqueue);
  7107. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  7108. * priv->workqueue... so we can't take down the workqueue
  7109. * until now... */
  7110. destroy_workqueue(priv->workqueue);
  7111. priv->workqueue = NULL;
  7112. free_irq(pdev->irq, priv);
  7113. pci_disable_msi(pdev);
  7114. pci_iounmap(pdev, priv->hw_base);
  7115. pci_release_regions(pdev);
  7116. pci_disable_device(pdev);
  7117. pci_set_drvdata(pdev, NULL);
  7118. kfree(priv->channel_info);
  7119. kfree(priv->ieee_channels);
  7120. kfree(priv->ieee_rates);
  7121. if (priv->ibss_beacon)
  7122. dev_kfree_skb(priv->ibss_beacon);
  7123. ieee80211_free_hw(priv->hw);
  7124. }
  7125. #ifdef CONFIG_PM
  7126. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7127. {
  7128. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7129. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7130. /* Take down the device; powers it off, etc. */
  7131. iwl3945_down(priv);
  7132. if (priv->mac80211_registered)
  7133. ieee80211_stop_queues(priv->hw);
  7134. pci_save_state(pdev);
  7135. pci_disable_device(pdev);
  7136. pci_set_power_state(pdev, PCI_D3hot);
  7137. return 0;
  7138. }
  7139. static void iwl3945_resume(struct iwl3945_priv *priv)
  7140. {
  7141. unsigned long flags;
  7142. /* The following it a temporary work around due to the
  7143. * suspend / resume not fully initializing the NIC correctly.
  7144. * Without all of the following, resume will not attempt to take
  7145. * down the NIC (it shouldn't really need to) and will just try
  7146. * and bring the NIC back up. However that fails during the
  7147. * ucode verification process. This then causes iwl3945_down to be
  7148. * called *after* iwl3945_hw_nic_init() has succeeded -- which
  7149. * then lets the next init sequence succeed. So, we've
  7150. * replicated all of that NIC init code here... */
  7151. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7152. iwl3945_hw_nic_init(priv);
  7153. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7154. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  7155. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  7156. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7157. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7158. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7159. /* tell the device to stop sending interrupts */
  7160. iwl3945_disable_interrupts(priv);
  7161. spin_lock_irqsave(&priv->lock, flags);
  7162. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  7163. if (!iwl3945_grab_nic_access(priv)) {
  7164. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  7165. APMG_CLK_VAL_DMA_CLK_RQT);
  7166. iwl3945_release_nic_access(priv);
  7167. }
  7168. spin_unlock_irqrestore(&priv->lock, flags);
  7169. udelay(5);
  7170. iwl3945_hw_nic_reset(priv);
  7171. /* Bring the device back up */
  7172. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7173. queue_work(priv->workqueue, &priv->up);
  7174. }
  7175. static int iwl3945_pci_resume(struct pci_dev *pdev)
  7176. {
  7177. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7178. int err;
  7179. printk(KERN_INFO "Coming out of suspend...\n");
  7180. pci_set_power_state(pdev, PCI_D0);
  7181. err = pci_enable_device(pdev);
  7182. pci_restore_state(pdev);
  7183. /*
  7184. * Suspend/Resume resets the PCI configuration space, so we have to
  7185. * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
  7186. * from interfering with C3 CPU state. pci_restore_state won't help
  7187. * here since it only restores the first 64 bytes pci config header.
  7188. */
  7189. pci_write_config_byte(pdev, 0x41, 0x00);
  7190. iwl3945_resume(priv);
  7191. return 0;
  7192. }
  7193. #endif /* CONFIG_PM */
  7194. /*****************************************************************************
  7195. *
  7196. * driver and module entry point
  7197. *
  7198. *****************************************************************************/
  7199. static struct pci_driver iwl3945_driver = {
  7200. .name = DRV_NAME,
  7201. .id_table = iwl3945_hw_card_ids,
  7202. .probe = iwl3945_pci_probe,
  7203. .remove = __devexit_p(iwl3945_pci_remove),
  7204. #ifdef CONFIG_PM
  7205. .suspend = iwl3945_pci_suspend,
  7206. .resume = iwl3945_pci_resume,
  7207. #endif
  7208. };
  7209. static int __init iwl3945_init(void)
  7210. {
  7211. int ret;
  7212. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7213. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7214. ret = pci_register_driver(&iwl3945_driver);
  7215. if (ret) {
  7216. IWL_ERROR("Unable to initialize PCI module\n");
  7217. return ret;
  7218. }
  7219. #ifdef CONFIG_IWL3945_DEBUG
  7220. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7221. if (ret) {
  7222. IWL_ERROR("Unable to create driver sysfs file\n");
  7223. pci_unregister_driver(&iwl3945_driver);
  7224. return ret;
  7225. }
  7226. #endif
  7227. return ret;
  7228. }
  7229. static void __exit iwl3945_exit(void)
  7230. {
  7231. #ifdef CONFIG_IWL3945_DEBUG
  7232. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7233. #endif
  7234. pci_unregister_driver(&iwl3945_driver);
  7235. }
  7236. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  7237. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7238. module_param_named(disable, iwl3945_param_disable, int, 0444);
  7239. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7240. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  7241. MODULE_PARM_DESC(hwcrypto,
  7242. "using hardware crypto engine (default 0 [software])\n");
  7243. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7244. MODULE_PARM_DESC(debug, "debug output mask");
  7245. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7246. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7247. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7248. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7249. /* QoS */
  7250. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7251. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7252. module_exit(iwl3945_exit);
  7253. module_init(iwl3945_init);