i915_irq.c 99 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. static const u32 hpd_ibx[] = {
  37. [HPD_CRT] = SDE_CRT_HOTPLUG,
  38. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  39. [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  40. [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  41. [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  42. };
  43. static const u32 hpd_cpt[] = {
  44. [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  45. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  46. [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  47. [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  48. [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  49. };
  50. static const u32 hpd_mask_i915[] = {
  51. [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54. [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55. [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56. [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57. };
  58. static const u32 hpd_status_gen4[] = {
  59. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  60. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  61. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  62. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  63. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  64. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  65. };
  66. static const u32 hpd_status_i965[] = {
  67. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  68. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  69. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  70. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  71. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  72. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  73. };
  74. static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81. };
  82. static void ibx_hpd_irq_setup(struct drm_device *dev);
  83. static void i915_hpd_irq_setup(struct drm_device *dev);
  84. /* For display hotplug interrupt */
  85. static void
  86. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  87. {
  88. if ((dev_priv->irq_mask & mask) != 0) {
  89. dev_priv->irq_mask &= ~mask;
  90. I915_WRITE(DEIMR, dev_priv->irq_mask);
  91. POSTING_READ(DEIMR);
  92. }
  93. }
  94. static void
  95. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  96. {
  97. if ((dev_priv->irq_mask & mask) != mask) {
  98. dev_priv->irq_mask |= mask;
  99. I915_WRITE(DEIMR, dev_priv->irq_mask);
  100. POSTING_READ(DEIMR);
  101. }
  102. }
  103. static bool ivb_can_enable_err_int(struct drm_device *dev)
  104. {
  105. struct drm_i915_private *dev_priv = dev->dev_private;
  106. struct intel_crtc *crtc;
  107. enum pipe pipe;
  108. for_each_pipe(pipe) {
  109. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  110. if (crtc->cpu_fifo_underrun_disabled)
  111. return false;
  112. }
  113. return true;
  114. }
  115. static bool cpt_can_enable_serr_int(struct drm_device *dev)
  116. {
  117. struct drm_i915_private *dev_priv = dev->dev_private;
  118. enum pipe pipe;
  119. struct intel_crtc *crtc;
  120. for_each_pipe(pipe) {
  121. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  122. if (crtc->pch_fifo_underrun_disabled)
  123. return false;
  124. }
  125. return true;
  126. }
  127. static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
  128. enum pipe pipe, bool enable)
  129. {
  130. struct drm_i915_private *dev_priv = dev->dev_private;
  131. uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
  132. DE_PIPEB_FIFO_UNDERRUN;
  133. if (enable)
  134. ironlake_enable_display_irq(dev_priv, bit);
  135. else
  136. ironlake_disable_display_irq(dev_priv, bit);
  137. }
  138. static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
  139. bool enable)
  140. {
  141. struct drm_i915_private *dev_priv = dev->dev_private;
  142. if (enable) {
  143. if (!ivb_can_enable_err_int(dev))
  144. return;
  145. I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN_A |
  146. ERR_INT_FIFO_UNDERRUN_B |
  147. ERR_INT_FIFO_UNDERRUN_C);
  148. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  149. } else {
  150. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  151. }
  152. }
  153. static void ibx_set_fifo_underrun_reporting(struct intel_crtc *crtc,
  154. bool enable)
  155. {
  156. struct drm_device *dev = crtc->base.dev;
  157. struct drm_i915_private *dev_priv = dev->dev_private;
  158. uint32_t bit = (crtc->pipe == PIPE_A) ? SDE_TRANSA_FIFO_UNDER :
  159. SDE_TRANSB_FIFO_UNDER;
  160. if (enable)
  161. I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit);
  162. else
  163. I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit);
  164. POSTING_READ(SDEIMR);
  165. }
  166. static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
  167. enum transcoder pch_transcoder,
  168. bool enable)
  169. {
  170. struct drm_i915_private *dev_priv = dev->dev_private;
  171. if (enable) {
  172. if (!cpt_can_enable_serr_int(dev))
  173. return;
  174. I915_WRITE(SERR_INT, SERR_INT_TRANS_A_FIFO_UNDERRUN |
  175. SERR_INT_TRANS_B_FIFO_UNDERRUN |
  176. SERR_INT_TRANS_C_FIFO_UNDERRUN);
  177. I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT);
  178. } else {
  179. I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT);
  180. }
  181. POSTING_READ(SDEIMR);
  182. }
  183. /**
  184. * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
  185. * @dev: drm device
  186. * @pipe: pipe
  187. * @enable: true if we want to report FIFO underrun errors, false otherwise
  188. *
  189. * This function makes us disable or enable CPU fifo underruns for a specific
  190. * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
  191. * reporting for one pipe may also disable all the other CPU error interruts for
  192. * the other pipes, due to the fact that there's just one interrupt mask/enable
  193. * bit for all the pipes.
  194. *
  195. * Returns the previous state of underrun reporting.
  196. */
  197. bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  198. enum pipe pipe, bool enable)
  199. {
  200. struct drm_i915_private *dev_priv = dev->dev_private;
  201. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  202. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  203. unsigned long flags;
  204. bool ret;
  205. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  206. ret = !intel_crtc->cpu_fifo_underrun_disabled;
  207. if (enable == ret)
  208. goto done;
  209. intel_crtc->cpu_fifo_underrun_disabled = !enable;
  210. if (IS_GEN5(dev) || IS_GEN6(dev))
  211. ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
  212. else if (IS_GEN7(dev))
  213. ivybridge_set_fifo_underrun_reporting(dev, enable);
  214. done:
  215. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  216. return ret;
  217. }
  218. /**
  219. * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
  220. * @dev: drm device
  221. * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
  222. * @enable: true if we want to report FIFO underrun errors, false otherwise
  223. *
  224. * This function makes us disable or enable PCH fifo underruns for a specific
  225. * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
  226. * underrun reporting for one transcoder may also disable all the other PCH
  227. * error interruts for the other transcoders, due to the fact that there's just
  228. * one interrupt mask/enable bit for all the transcoders.
  229. *
  230. * Returns the previous state of underrun reporting.
  231. */
  232. bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
  233. enum transcoder pch_transcoder,
  234. bool enable)
  235. {
  236. struct drm_i915_private *dev_priv = dev->dev_private;
  237. enum pipe p;
  238. struct drm_crtc *crtc;
  239. struct intel_crtc *intel_crtc;
  240. unsigned long flags;
  241. bool ret;
  242. if (HAS_PCH_LPT(dev)) {
  243. crtc = NULL;
  244. for_each_pipe(p) {
  245. struct drm_crtc *c = dev_priv->pipe_to_crtc_mapping[p];
  246. if (intel_pipe_has_type(c, INTEL_OUTPUT_ANALOG)) {
  247. crtc = c;
  248. break;
  249. }
  250. }
  251. if (!crtc) {
  252. DRM_ERROR("PCH FIFO underrun, but no CRTC using the PCH found\n");
  253. return false;
  254. }
  255. } else {
  256. crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
  257. }
  258. intel_crtc = to_intel_crtc(crtc);
  259. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  260. ret = !intel_crtc->pch_fifo_underrun_disabled;
  261. if (enable == ret)
  262. goto done;
  263. intel_crtc->pch_fifo_underrun_disabled = !enable;
  264. if (HAS_PCH_IBX(dev))
  265. ibx_set_fifo_underrun_reporting(intel_crtc, enable);
  266. else
  267. cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
  268. done:
  269. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  270. return ret;
  271. }
  272. void
  273. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  274. {
  275. u32 reg = PIPESTAT(pipe);
  276. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  277. if ((pipestat & mask) == mask)
  278. return;
  279. /* Enable the interrupt, clear any pending status */
  280. pipestat |= mask | (mask >> 16);
  281. I915_WRITE(reg, pipestat);
  282. POSTING_READ(reg);
  283. }
  284. void
  285. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  286. {
  287. u32 reg = PIPESTAT(pipe);
  288. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  289. if ((pipestat & mask) == 0)
  290. return;
  291. pipestat &= ~mask;
  292. I915_WRITE(reg, pipestat);
  293. POSTING_READ(reg);
  294. }
  295. /**
  296. * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
  297. */
  298. static void i915_enable_asle_pipestat(struct drm_device *dev)
  299. {
  300. drm_i915_private_t *dev_priv = dev->dev_private;
  301. unsigned long irqflags;
  302. if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
  303. return;
  304. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  305. i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
  306. if (INTEL_INFO(dev)->gen >= 4)
  307. i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
  308. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  309. }
  310. /**
  311. * i915_pipe_enabled - check if a pipe is enabled
  312. * @dev: DRM device
  313. * @pipe: pipe to check
  314. *
  315. * Reading certain registers when the pipe is disabled can hang the chip.
  316. * Use this routine to make sure the PLL is running and the pipe is active
  317. * before reading such registers if unsure.
  318. */
  319. static int
  320. i915_pipe_enabled(struct drm_device *dev, int pipe)
  321. {
  322. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  323. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  324. pipe);
  325. return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
  326. }
  327. /* Called from drm generic code, passed a 'crtc', which
  328. * we use as a pipe index
  329. */
  330. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  331. {
  332. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  333. unsigned long high_frame;
  334. unsigned long low_frame;
  335. u32 high1, high2, low;
  336. if (!i915_pipe_enabled(dev, pipe)) {
  337. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  338. "pipe %c\n", pipe_name(pipe));
  339. return 0;
  340. }
  341. high_frame = PIPEFRAME(pipe);
  342. low_frame = PIPEFRAMEPIXEL(pipe);
  343. /*
  344. * High & low register fields aren't synchronized, so make sure
  345. * we get a low value that's stable across two reads of the high
  346. * register.
  347. */
  348. do {
  349. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  350. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  351. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  352. } while (high1 != high2);
  353. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  354. low >>= PIPE_FRAME_LOW_SHIFT;
  355. return (high1 << 8) | low;
  356. }
  357. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  358. {
  359. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  360. int reg = PIPE_FRMCOUNT_GM45(pipe);
  361. if (!i915_pipe_enabled(dev, pipe)) {
  362. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  363. "pipe %c\n", pipe_name(pipe));
  364. return 0;
  365. }
  366. return I915_READ(reg);
  367. }
  368. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  369. int *vpos, int *hpos)
  370. {
  371. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  372. u32 vbl = 0, position = 0;
  373. int vbl_start, vbl_end, htotal, vtotal;
  374. bool in_vbl = true;
  375. int ret = 0;
  376. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  377. pipe);
  378. if (!i915_pipe_enabled(dev, pipe)) {
  379. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  380. "pipe %c\n", pipe_name(pipe));
  381. return 0;
  382. }
  383. /* Get vtotal. */
  384. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  385. if (INTEL_INFO(dev)->gen >= 4) {
  386. /* No obvious pixelcount register. Only query vertical
  387. * scanout position from Display scan line register.
  388. */
  389. position = I915_READ(PIPEDSL(pipe));
  390. /* Decode into vertical scanout position. Don't have
  391. * horizontal scanout position.
  392. */
  393. *vpos = position & 0x1fff;
  394. *hpos = 0;
  395. } else {
  396. /* Have access to pixelcount since start of frame.
  397. * We can split this into vertical and horizontal
  398. * scanout position.
  399. */
  400. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  401. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  402. *vpos = position / htotal;
  403. *hpos = position - (*vpos * htotal);
  404. }
  405. /* Query vblank area. */
  406. vbl = I915_READ(VBLANK(cpu_transcoder));
  407. /* Test position against vblank region. */
  408. vbl_start = vbl & 0x1fff;
  409. vbl_end = (vbl >> 16) & 0x1fff;
  410. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  411. in_vbl = false;
  412. /* Inside "upper part" of vblank area? Apply corrective offset: */
  413. if (in_vbl && (*vpos >= vbl_start))
  414. *vpos = *vpos - vtotal;
  415. /* Readouts valid? */
  416. if (vbl > 0)
  417. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  418. /* In vblank? */
  419. if (in_vbl)
  420. ret |= DRM_SCANOUTPOS_INVBL;
  421. return ret;
  422. }
  423. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  424. int *max_error,
  425. struct timeval *vblank_time,
  426. unsigned flags)
  427. {
  428. struct drm_crtc *crtc;
  429. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  430. DRM_ERROR("Invalid crtc %d\n", pipe);
  431. return -EINVAL;
  432. }
  433. /* Get drm_crtc to timestamp: */
  434. crtc = intel_get_crtc_for_pipe(dev, pipe);
  435. if (crtc == NULL) {
  436. DRM_ERROR("Invalid crtc %d\n", pipe);
  437. return -EINVAL;
  438. }
  439. if (!crtc->enabled) {
  440. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  441. return -EBUSY;
  442. }
  443. /* Helper routine in DRM core does all the work: */
  444. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  445. vblank_time, flags,
  446. crtc);
  447. }
  448. static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
  449. {
  450. enum drm_connector_status old_status;
  451. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  452. old_status = connector->status;
  453. connector->status = connector->funcs->detect(connector, false);
  454. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
  455. connector->base.id,
  456. drm_get_connector_name(connector),
  457. old_status, connector->status);
  458. return (old_status != connector->status);
  459. }
  460. /*
  461. * Handle hotplug events outside the interrupt handler proper.
  462. */
  463. #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
  464. static void i915_hotplug_work_func(struct work_struct *work)
  465. {
  466. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  467. hotplug_work);
  468. struct drm_device *dev = dev_priv->dev;
  469. struct drm_mode_config *mode_config = &dev->mode_config;
  470. struct intel_connector *intel_connector;
  471. struct intel_encoder *intel_encoder;
  472. struct drm_connector *connector;
  473. unsigned long irqflags;
  474. bool hpd_disabled = false;
  475. bool changed = false;
  476. u32 hpd_event_bits;
  477. /* HPD irq before everything is fully set up. */
  478. if (!dev_priv->enable_hotplug_processing)
  479. return;
  480. mutex_lock(&mode_config->mutex);
  481. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  482. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  483. hpd_event_bits = dev_priv->hpd_event_bits;
  484. dev_priv->hpd_event_bits = 0;
  485. list_for_each_entry(connector, &mode_config->connector_list, head) {
  486. intel_connector = to_intel_connector(connector);
  487. intel_encoder = intel_connector->encoder;
  488. if (intel_encoder->hpd_pin > HPD_NONE &&
  489. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
  490. connector->polled == DRM_CONNECTOR_POLL_HPD) {
  491. DRM_INFO("HPD interrupt storm detected on connector %s: "
  492. "switching from hotplug detection to polling\n",
  493. drm_get_connector_name(connector));
  494. dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
  495. connector->polled = DRM_CONNECTOR_POLL_CONNECT
  496. | DRM_CONNECTOR_POLL_DISCONNECT;
  497. hpd_disabled = true;
  498. }
  499. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  500. DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
  501. drm_get_connector_name(connector), intel_encoder->hpd_pin);
  502. }
  503. }
  504. /* if there were no outputs to poll, poll was disabled,
  505. * therefore make sure it's enabled when disabling HPD on
  506. * some connectors */
  507. if (hpd_disabled) {
  508. drm_kms_helper_poll_enable(dev);
  509. mod_timer(&dev_priv->hotplug_reenable_timer,
  510. jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
  511. }
  512. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  513. list_for_each_entry(connector, &mode_config->connector_list, head) {
  514. intel_connector = to_intel_connector(connector);
  515. intel_encoder = intel_connector->encoder;
  516. if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
  517. if (intel_encoder->hot_plug)
  518. intel_encoder->hot_plug(intel_encoder);
  519. if (intel_hpd_irq_event(dev, connector))
  520. changed = true;
  521. }
  522. }
  523. mutex_unlock(&mode_config->mutex);
  524. if (changed)
  525. drm_kms_helper_hotplug_event(dev);
  526. }
  527. static void ironlake_handle_rps_change(struct drm_device *dev)
  528. {
  529. drm_i915_private_t *dev_priv = dev->dev_private;
  530. u32 busy_up, busy_down, max_avg, min_avg;
  531. u8 new_delay;
  532. unsigned long flags;
  533. spin_lock_irqsave(&mchdev_lock, flags);
  534. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  535. new_delay = dev_priv->ips.cur_delay;
  536. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  537. busy_up = I915_READ(RCPREVBSYTUPAVG);
  538. busy_down = I915_READ(RCPREVBSYTDNAVG);
  539. max_avg = I915_READ(RCBMAXAVG);
  540. min_avg = I915_READ(RCBMINAVG);
  541. /* Handle RCS change request from hw */
  542. if (busy_up > max_avg) {
  543. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  544. new_delay = dev_priv->ips.cur_delay - 1;
  545. if (new_delay < dev_priv->ips.max_delay)
  546. new_delay = dev_priv->ips.max_delay;
  547. } else if (busy_down < min_avg) {
  548. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  549. new_delay = dev_priv->ips.cur_delay + 1;
  550. if (new_delay > dev_priv->ips.min_delay)
  551. new_delay = dev_priv->ips.min_delay;
  552. }
  553. if (ironlake_set_drps(dev, new_delay))
  554. dev_priv->ips.cur_delay = new_delay;
  555. spin_unlock_irqrestore(&mchdev_lock, flags);
  556. return;
  557. }
  558. static void notify_ring(struct drm_device *dev,
  559. struct intel_ring_buffer *ring)
  560. {
  561. struct drm_i915_private *dev_priv = dev->dev_private;
  562. if (ring->obj == NULL)
  563. return;
  564. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  565. wake_up_all(&ring->irq_queue);
  566. if (i915_enable_hangcheck) {
  567. dev_priv->gpu_error.hangcheck_count = 0;
  568. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  569. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  570. }
  571. }
  572. static void gen6_pm_rps_work(struct work_struct *work)
  573. {
  574. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  575. rps.work);
  576. u32 pm_iir, pm_imr;
  577. u8 new_delay;
  578. spin_lock_irq(&dev_priv->rps.lock);
  579. pm_iir = dev_priv->rps.pm_iir;
  580. dev_priv->rps.pm_iir = 0;
  581. pm_imr = I915_READ(GEN6_PMIMR);
  582. I915_WRITE(GEN6_PMIMR, 0);
  583. spin_unlock_irq(&dev_priv->rps.lock);
  584. if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
  585. return;
  586. mutex_lock(&dev_priv->rps.hw_lock);
  587. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  588. new_delay = dev_priv->rps.cur_delay + 1;
  589. else
  590. new_delay = dev_priv->rps.cur_delay - 1;
  591. /* sysfs frequency interfaces may have snuck in while servicing the
  592. * interrupt
  593. */
  594. if (!(new_delay > dev_priv->rps.max_delay ||
  595. new_delay < dev_priv->rps.min_delay)) {
  596. if (IS_VALLEYVIEW(dev_priv->dev))
  597. valleyview_set_rps(dev_priv->dev, new_delay);
  598. else
  599. gen6_set_rps(dev_priv->dev, new_delay);
  600. }
  601. if (IS_VALLEYVIEW(dev_priv->dev)) {
  602. /*
  603. * On VLV, when we enter RC6 we may not be at the minimum
  604. * voltage level, so arm a timer to check. It should only
  605. * fire when there's activity or once after we've entered
  606. * RC6, and then won't be re-armed until the next RPS interrupt.
  607. */
  608. mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
  609. msecs_to_jiffies(100));
  610. }
  611. mutex_unlock(&dev_priv->rps.hw_lock);
  612. }
  613. /**
  614. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  615. * occurred.
  616. * @work: workqueue struct
  617. *
  618. * Doesn't actually do anything except notify userspace. As a consequence of
  619. * this event, userspace should try to remap the bad rows since statistically
  620. * it is likely the same row is more likely to go bad again.
  621. */
  622. static void ivybridge_parity_work(struct work_struct *work)
  623. {
  624. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  625. l3_parity.error_work);
  626. u32 error_status, row, bank, subbank;
  627. char *parity_event[5];
  628. uint32_t misccpctl;
  629. unsigned long flags;
  630. /* We must turn off DOP level clock gating to access the L3 registers.
  631. * In order to prevent a get/put style interface, acquire struct mutex
  632. * any time we access those registers.
  633. */
  634. mutex_lock(&dev_priv->dev->struct_mutex);
  635. misccpctl = I915_READ(GEN7_MISCCPCTL);
  636. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  637. POSTING_READ(GEN7_MISCCPCTL);
  638. error_status = I915_READ(GEN7_L3CDERRST1);
  639. row = GEN7_PARITY_ERROR_ROW(error_status);
  640. bank = GEN7_PARITY_ERROR_BANK(error_status);
  641. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  642. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  643. GEN7_L3CDERRST1_ENABLE);
  644. POSTING_READ(GEN7_L3CDERRST1);
  645. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  646. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  647. dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  648. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  649. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  650. mutex_unlock(&dev_priv->dev->struct_mutex);
  651. parity_event[0] = "L3_PARITY_ERROR=1";
  652. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  653. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  654. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  655. parity_event[4] = NULL;
  656. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  657. KOBJ_CHANGE, parity_event);
  658. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  659. row, bank, subbank);
  660. kfree(parity_event[3]);
  661. kfree(parity_event[2]);
  662. kfree(parity_event[1]);
  663. }
  664. static void ivybridge_handle_parity_error(struct drm_device *dev)
  665. {
  666. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  667. unsigned long flags;
  668. if (!HAS_L3_GPU_CACHE(dev))
  669. return;
  670. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  671. dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  672. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  673. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  674. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  675. }
  676. static void snb_gt_irq_handler(struct drm_device *dev,
  677. struct drm_i915_private *dev_priv,
  678. u32 gt_iir)
  679. {
  680. if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
  681. GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
  682. notify_ring(dev, &dev_priv->ring[RCS]);
  683. if (gt_iir & GEN6_BSD_USER_INTERRUPT)
  684. notify_ring(dev, &dev_priv->ring[VCS]);
  685. if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
  686. notify_ring(dev, &dev_priv->ring[BCS]);
  687. if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  688. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  689. GT_RENDER_CS_ERROR_INTERRUPT)) {
  690. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  691. i915_handle_error(dev, false);
  692. }
  693. if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
  694. ivybridge_handle_parity_error(dev);
  695. }
  696. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  697. u32 pm_iir)
  698. {
  699. unsigned long flags;
  700. /*
  701. * IIR bits should never already be set because IMR should
  702. * prevent an interrupt from being shown in IIR. The warning
  703. * displays a case where we've unsafely cleared
  704. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  705. * type is not a problem, it displays a problem in the logic.
  706. *
  707. * The mask bit in IMR is cleared by dev_priv->rps.work.
  708. */
  709. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  710. dev_priv->rps.pm_iir |= pm_iir;
  711. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  712. POSTING_READ(GEN6_PMIMR);
  713. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  714. queue_work(dev_priv->wq, &dev_priv->rps.work);
  715. }
  716. #define HPD_STORM_DETECT_PERIOD 1000
  717. #define HPD_STORM_THRESHOLD 5
  718. static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
  719. u32 hotplug_trigger,
  720. const u32 *hpd)
  721. {
  722. drm_i915_private_t *dev_priv = dev->dev_private;
  723. unsigned long irqflags;
  724. int i;
  725. bool ret = false;
  726. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  727. for (i = 1; i < HPD_NUM_PINS; i++) {
  728. if (!(hpd[i] & hotplug_trigger) ||
  729. dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
  730. dev_priv->hpd_event_bits |= (1 << i);
  731. continue;
  732. if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
  733. dev_priv->hpd_stats[i].hpd_last_jiffies
  734. + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
  735. dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
  736. dev_priv->hpd_stats[i].hpd_cnt = 0;
  737. } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
  738. dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
  739. dev_priv->hpd_event_bits &= ~(1 << i);
  740. DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
  741. ret = true;
  742. } else {
  743. dev_priv->hpd_stats[i].hpd_cnt++;
  744. }
  745. }
  746. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  747. return ret;
  748. }
  749. static void gmbus_irq_handler(struct drm_device *dev)
  750. {
  751. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  752. wake_up_all(&dev_priv->gmbus_wait_queue);
  753. }
  754. static void dp_aux_irq_handler(struct drm_device *dev)
  755. {
  756. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  757. wake_up_all(&dev_priv->gmbus_wait_queue);
  758. }
  759. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  760. {
  761. struct drm_device *dev = (struct drm_device *) arg;
  762. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  763. u32 iir, gt_iir, pm_iir;
  764. irqreturn_t ret = IRQ_NONE;
  765. unsigned long irqflags;
  766. int pipe;
  767. u32 pipe_stats[I915_MAX_PIPES];
  768. atomic_inc(&dev_priv->irq_received);
  769. while (true) {
  770. iir = I915_READ(VLV_IIR);
  771. gt_iir = I915_READ(GTIIR);
  772. pm_iir = I915_READ(GEN6_PMIIR);
  773. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  774. goto out;
  775. ret = IRQ_HANDLED;
  776. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  777. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  778. for_each_pipe(pipe) {
  779. int reg = PIPESTAT(pipe);
  780. pipe_stats[pipe] = I915_READ(reg);
  781. /*
  782. * Clear the PIPE*STAT regs before the IIR
  783. */
  784. if (pipe_stats[pipe] & 0x8000ffff) {
  785. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  786. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  787. pipe_name(pipe));
  788. I915_WRITE(reg, pipe_stats[pipe]);
  789. }
  790. }
  791. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  792. for_each_pipe(pipe) {
  793. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  794. drm_handle_vblank(dev, pipe);
  795. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  796. intel_prepare_page_flip(dev, pipe);
  797. intel_finish_page_flip(dev, pipe);
  798. }
  799. }
  800. /* Consume port. Then clear IIR or we'll miss events */
  801. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  802. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  803. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  804. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  805. hotplug_status);
  806. if (hotplug_trigger) {
  807. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
  808. i915_hpd_irq_setup(dev);
  809. queue_work(dev_priv->wq,
  810. &dev_priv->hotplug_work);
  811. }
  812. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  813. I915_READ(PORT_HOTPLUG_STAT);
  814. }
  815. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  816. gmbus_irq_handler(dev);
  817. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  818. gen6_queue_rps_work(dev_priv, pm_iir);
  819. I915_WRITE(GTIIR, gt_iir);
  820. I915_WRITE(GEN6_PMIIR, pm_iir);
  821. I915_WRITE(VLV_IIR, iir);
  822. }
  823. out:
  824. return ret;
  825. }
  826. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  827. {
  828. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  829. int pipe;
  830. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
  831. if (hotplug_trigger) {
  832. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
  833. ibx_hpd_irq_setup(dev);
  834. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  835. }
  836. if (pch_iir & SDE_AUDIO_POWER_MASK) {
  837. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
  838. SDE_AUDIO_POWER_SHIFT);
  839. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  840. port_name(port));
  841. }
  842. if (pch_iir & SDE_AUX_MASK)
  843. dp_aux_irq_handler(dev);
  844. if (pch_iir & SDE_GMBUS)
  845. gmbus_irq_handler(dev);
  846. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  847. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  848. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  849. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  850. if (pch_iir & SDE_POISON)
  851. DRM_ERROR("PCH poison interrupt\n");
  852. if (pch_iir & SDE_FDI_MASK)
  853. for_each_pipe(pipe)
  854. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  855. pipe_name(pipe),
  856. I915_READ(FDI_RX_IIR(pipe)));
  857. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  858. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  859. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  860. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  861. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  862. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  863. false))
  864. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  865. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  866. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  867. false))
  868. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  869. }
  870. static void ivb_err_int_handler(struct drm_device *dev)
  871. {
  872. struct drm_i915_private *dev_priv = dev->dev_private;
  873. u32 err_int = I915_READ(GEN7_ERR_INT);
  874. if (err_int & ERR_INT_POISON)
  875. DRM_ERROR("Poison interrupt\n");
  876. if (err_int & ERR_INT_FIFO_UNDERRUN_A)
  877. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  878. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  879. if (err_int & ERR_INT_FIFO_UNDERRUN_B)
  880. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  881. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  882. if (err_int & ERR_INT_FIFO_UNDERRUN_C)
  883. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
  884. DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
  885. I915_WRITE(GEN7_ERR_INT, err_int);
  886. }
  887. static void cpt_serr_int_handler(struct drm_device *dev)
  888. {
  889. struct drm_i915_private *dev_priv = dev->dev_private;
  890. u32 serr_int = I915_READ(SERR_INT);
  891. if (serr_int & SERR_INT_POISON)
  892. DRM_ERROR("PCH poison interrupt\n");
  893. if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
  894. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
  895. false))
  896. DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
  897. if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
  898. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
  899. false))
  900. DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
  901. if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
  902. if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
  903. false))
  904. DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
  905. I915_WRITE(SERR_INT, serr_int);
  906. }
  907. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  908. {
  909. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  910. int pipe;
  911. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
  912. if (hotplug_trigger) {
  913. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
  914. ibx_hpd_irq_setup(dev);
  915. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  916. }
  917. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
  918. int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  919. SDE_AUDIO_POWER_SHIFT_CPT);
  920. DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
  921. port_name(port));
  922. }
  923. if (pch_iir & SDE_AUX_MASK_CPT)
  924. dp_aux_irq_handler(dev);
  925. if (pch_iir & SDE_GMBUS_CPT)
  926. gmbus_irq_handler(dev);
  927. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  928. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  929. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  930. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  931. if (pch_iir & SDE_FDI_MASK_CPT)
  932. for_each_pipe(pipe)
  933. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  934. pipe_name(pipe),
  935. I915_READ(FDI_RX_IIR(pipe)));
  936. if (pch_iir & SDE_ERROR_CPT)
  937. cpt_serr_int_handler(dev);
  938. }
  939. static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
  940. {
  941. struct drm_device *dev = (struct drm_device *) arg;
  942. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  943. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
  944. irqreturn_t ret = IRQ_NONE;
  945. int i;
  946. atomic_inc(&dev_priv->irq_received);
  947. /* We get interrupts on unclaimed registers, so check for this before we
  948. * do any I915_{READ,WRITE}. */
  949. if (IS_HASWELL(dev) &&
  950. (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
  951. DRM_ERROR("Unclaimed register before interrupt\n");
  952. I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
  953. }
  954. /* disable master interrupt before clearing iir */
  955. de_ier = I915_READ(DEIER);
  956. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  957. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  958. * interrupts will will be stored on its back queue, and then we'll be
  959. * able to process them after we restore SDEIER (as soon as we restore
  960. * it, we'll get an interrupt if SDEIIR still has something to process
  961. * due to its back queue). */
  962. if (!HAS_PCH_NOP(dev)) {
  963. sde_ier = I915_READ(SDEIER);
  964. I915_WRITE(SDEIER, 0);
  965. POSTING_READ(SDEIER);
  966. }
  967. /* On Haswell, also mask ERR_INT because we don't want to risk
  968. * generating "unclaimed register" interrupts from inside the interrupt
  969. * handler. */
  970. if (IS_HASWELL(dev))
  971. ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
  972. gt_iir = I915_READ(GTIIR);
  973. if (gt_iir) {
  974. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  975. I915_WRITE(GTIIR, gt_iir);
  976. ret = IRQ_HANDLED;
  977. }
  978. de_iir = I915_READ(DEIIR);
  979. if (de_iir) {
  980. if (de_iir & DE_ERR_INT_IVB)
  981. ivb_err_int_handler(dev);
  982. if (de_iir & DE_AUX_CHANNEL_A_IVB)
  983. dp_aux_irq_handler(dev);
  984. if (de_iir & DE_GSE_IVB)
  985. intel_opregion_asle_intr(dev);
  986. for (i = 0; i < 3; i++) {
  987. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  988. drm_handle_vblank(dev, i);
  989. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  990. intel_prepare_page_flip(dev, i);
  991. intel_finish_page_flip_plane(dev, i);
  992. }
  993. }
  994. /* check event from PCH */
  995. if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  996. u32 pch_iir = I915_READ(SDEIIR);
  997. cpt_irq_handler(dev, pch_iir);
  998. /* clear PCH hotplug event before clear CPU irq */
  999. I915_WRITE(SDEIIR, pch_iir);
  1000. }
  1001. I915_WRITE(DEIIR, de_iir);
  1002. ret = IRQ_HANDLED;
  1003. }
  1004. pm_iir = I915_READ(GEN6_PMIIR);
  1005. if (pm_iir) {
  1006. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  1007. gen6_queue_rps_work(dev_priv, pm_iir);
  1008. I915_WRITE(GEN6_PMIIR, pm_iir);
  1009. ret = IRQ_HANDLED;
  1010. }
  1011. if (IS_HASWELL(dev) && ivb_can_enable_err_int(dev))
  1012. ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
  1013. I915_WRITE(DEIER, de_ier);
  1014. POSTING_READ(DEIER);
  1015. if (!HAS_PCH_NOP(dev)) {
  1016. I915_WRITE(SDEIER, sde_ier);
  1017. POSTING_READ(SDEIER);
  1018. }
  1019. return ret;
  1020. }
  1021. static void ilk_gt_irq_handler(struct drm_device *dev,
  1022. struct drm_i915_private *dev_priv,
  1023. u32 gt_iir)
  1024. {
  1025. if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
  1026. notify_ring(dev, &dev_priv->ring[RCS]);
  1027. if (gt_iir & GT_BSD_USER_INTERRUPT)
  1028. notify_ring(dev, &dev_priv->ring[VCS]);
  1029. }
  1030. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  1031. {
  1032. struct drm_device *dev = (struct drm_device *) arg;
  1033. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1034. int ret = IRQ_NONE;
  1035. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
  1036. atomic_inc(&dev_priv->irq_received);
  1037. /* disable master interrupt before clearing iir */
  1038. de_ier = I915_READ(DEIER);
  1039. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  1040. POSTING_READ(DEIER);
  1041. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  1042. * interrupts will will be stored on its back queue, and then we'll be
  1043. * able to process them after we restore SDEIER (as soon as we restore
  1044. * it, we'll get an interrupt if SDEIIR still has something to process
  1045. * due to its back queue). */
  1046. sde_ier = I915_READ(SDEIER);
  1047. I915_WRITE(SDEIER, 0);
  1048. POSTING_READ(SDEIER);
  1049. de_iir = I915_READ(DEIIR);
  1050. gt_iir = I915_READ(GTIIR);
  1051. pm_iir = I915_READ(GEN6_PMIIR);
  1052. if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
  1053. goto done;
  1054. ret = IRQ_HANDLED;
  1055. if (IS_GEN5(dev))
  1056. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  1057. else
  1058. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  1059. if (de_iir & DE_AUX_CHANNEL_A)
  1060. dp_aux_irq_handler(dev);
  1061. if (de_iir & DE_GSE)
  1062. intel_opregion_asle_intr(dev);
  1063. if (de_iir & DE_PIPEA_VBLANK)
  1064. drm_handle_vblank(dev, 0);
  1065. if (de_iir & DE_PIPEB_VBLANK)
  1066. drm_handle_vblank(dev, 1);
  1067. if (de_iir & DE_POISON)
  1068. DRM_ERROR("Poison interrupt\n");
  1069. if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
  1070. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
  1071. DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
  1072. if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
  1073. if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
  1074. DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
  1075. if (de_iir & DE_PLANEA_FLIP_DONE) {
  1076. intel_prepare_page_flip(dev, 0);
  1077. intel_finish_page_flip_plane(dev, 0);
  1078. }
  1079. if (de_iir & DE_PLANEB_FLIP_DONE) {
  1080. intel_prepare_page_flip(dev, 1);
  1081. intel_finish_page_flip_plane(dev, 1);
  1082. }
  1083. /* check event from PCH */
  1084. if (de_iir & DE_PCH_EVENT) {
  1085. u32 pch_iir = I915_READ(SDEIIR);
  1086. if (HAS_PCH_CPT(dev))
  1087. cpt_irq_handler(dev, pch_iir);
  1088. else
  1089. ibx_irq_handler(dev, pch_iir);
  1090. /* should clear PCH hotplug event before clear CPU irq */
  1091. I915_WRITE(SDEIIR, pch_iir);
  1092. }
  1093. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  1094. ironlake_handle_rps_change(dev);
  1095. if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
  1096. gen6_queue_rps_work(dev_priv, pm_iir);
  1097. I915_WRITE(GTIIR, gt_iir);
  1098. I915_WRITE(DEIIR, de_iir);
  1099. I915_WRITE(GEN6_PMIIR, pm_iir);
  1100. done:
  1101. I915_WRITE(DEIER, de_ier);
  1102. POSTING_READ(DEIER);
  1103. I915_WRITE(SDEIER, sde_ier);
  1104. POSTING_READ(SDEIER);
  1105. return ret;
  1106. }
  1107. /**
  1108. * i915_error_work_func - do process context error handling work
  1109. * @work: work struct
  1110. *
  1111. * Fire an error uevent so userspace can see that a hang or error
  1112. * was detected.
  1113. */
  1114. static void i915_error_work_func(struct work_struct *work)
  1115. {
  1116. struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
  1117. work);
  1118. drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
  1119. gpu_error);
  1120. struct drm_device *dev = dev_priv->dev;
  1121. struct intel_ring_buffer *ring;
  1122. char *error_event[] = { "ERROR=1", NULL };
  1123. char *reset_event[] = { "RESET=1", NULL };
  1124. char *reset_done_event[] = { "ERROR=0", NULL };
  1125. int i, ret;
  1126. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  1127. /*
  1128. * Note that there's only one work item which does gpu resets, so we
  1129. * need not worry about concurrent gpu resets potentially incrementing
  1130. * error->reset_counter twice. We only need to take care of another
  1131. * racing irq/hangcheck declaring the gpu dead for a second time. A
  1132. * quick check for that is good enough: schedule_work ensures the
  1133. * correct ordering between hang detection and this work item, and since
  1134. * the reset in-progress bit is only ever set by code outside of this
  1135. * work we don't need to worry about any other races.
  1136. */
  1137. if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  1138. DRM_DEBUG_DRIVER("resetting chip\n");
  1139. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
  1140. reset_event);
  1141. ret = i915_reset(dev);
  1142. if (ret == 0) {
  1143. /*
  1144. * After all the gem state is reset, increment the reset
  1145. * counter and wake up everyone waiting for the reset to
  1146. * complete.
  1147. *
  1148. * Since unlock operations are a one-sided barrier only,
  1149. * we need to insert a barrier here to order any seqno
  1150. * updates before
  1151. * the counter increment.
  1152. */
  1153. smp_mb__before_atomic_inc();
  1154. atomic_inc(&dev_priv->gpu_error.reset_counter);
  1155. kobject_uevent_env(&dev->primary->kdev.kobj,
  1156. KOBJ_CHANGE, reset_done_event);
  1157. } else {
  1158. atomic_set(&error->reset_counter, I915_WEDGED);
  1159. }
  1160. for_each_ring(ring, dev_priv, i)
  1161. wake_up_all(&ring->irq_queue);
  1162. intel_display_handle_reset(dev);
  1163. wake_up_all(&dev_priv->gpu_error.reset_queue);
  1164. }
  1165. }
  1166. /* NB: please notice the memset */
  1167. static void i915_get_extra_instdone(struct drm_device *dev,
  1168. uint32_t *instdone)
  1169. {
  1170. struct drm_i915_private *dev_priv = dev->dev_private;
  1171. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  1172. switch(INTEL_INFO(dev)->gen) {
  1173. case 2:
  1174. case 3:
  1175. instdone[0] = I915_READ(INSTDONE);
  1176. break;
  1177. case 4:
  1178. case 5:
  1179. case 6:
  1180. instdone[0] = I915_READ(INSTDONE_I965);
  1181. instdone[1] = I915_READ(INSTDONE1);
  1182. break;
  1183. default:
  1184. WARN_ONCE(1, "Unsupported platform\n");
  1185. case 7:
  1186. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  1187. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  1188. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  1189. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  1190. break;
  1191. }
  1192. }
  1193. #ifdef CONFIG_DEBUG_FS
  1194. static struct drm_i915_error_object *
  1195. i915_error_object_create_sized(struct drm_i915_private *dev_priv,
  1196. struct drm_i915_gem_object *src,
  1197. const int num_pages)
  1198. {
  1199. struct drm_i915_error_object *dst;
  1200. int i;
  1201. u32 reloc_offset;
  1202. if (src == NULL || src->pages == NULL)
  1203. return NULL;
  1204. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
  1205. if (dst == NULL)
  1206. return NULL;
  1207. reloc_offset = src->gtt_offset;
  1208. for (i = 0; i < num_pages; i++) {
  1209. unsigned long flags;
  1210. void *d;
  1211. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  1212. if (d == NULL)
  1213. goto unwind;
  1214. local_irq_save(flags);
  1215. if (reloc_offset < dev_priv->gtt.mappable_end &&
  1216. src->has_global_gtt_mapping) {
  1217. void __iomem *s;
  1218. /* Simply ignore tiling or any overlapping fence.
  1219. * It's part of the error state, and this hopefully
  1220. * captures what the GPU read.
  1221. */
  1222. s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  1223. reloc_offset);
  1224. memcpy_fromio(d, s, PAGE_SIZE);
  1225. io_mapping_unmap_atomic(s);
  1226. } else if (src->stolen) {
  1227. unsigned long offset;
  1228. offset = dev_priv->mm.stolen_base;
  1229. offset += src->stolen->start;
  1230. offset += i << PAGE_SHIFT;
  1231. memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
  1232. } else {
  1233. struct page *page;
  1234. void *s;
  1235. page = i915_gem_object_get_page(src, i);
  1236. drm_clflush_pages(&page, 1);
  1237. s = kmap_atomic(page);
  1238. memcpy(d, s, PAGE_SIZE);
  1239. kunmap_atomic(s);
  1240. drm_clflush_pages(&page, 1);
  1241. }
  1242. local_irq_restore(flags);
  1243. dst->pages[i] = d;
  1244. reloc_offset += PAGE_SIZE;
  1245. }
  1246. dst->page_count = num_pages;
  1247. dst->gtt_offset = src->gtt_offset;
  1248. return dst;
  1249. unwind:
  1250. while (i--)
  1251. kfree(dst->pages[i]);
  1252. kfree(dst);
  1253. return NULL;
  1254. }
  1255. #define i915_error_object_create(dev_priv, src) \
  1256. i915_error_object_create_sized((dev_priv), (src), \
  1257. (src)->base.size>>PAGE_SHIFT)
  1258. static void
  1259. i915_error_object_free(struct drm_i915_error_object *obj)
  1260. {
  1261. int page;
  1262. if (obj == NULL)
  1263. return;
  1264. for (page = 0; page < obj->page_count; page++)
  1265. kfree(obj->pages[page]);
  1266. kfree(obj);
  1267. }
  1268. void
  1269. i915_error_state_free(struct kref *error_ref)
  1270. {
  1271. struct drm_i915_error_state *error = container_of(error_ref,
  1272. typeof(*error), ref);
  1273. int i;
  1274. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  1275. i915_error_object_free(error->ring[i].batchbuffer);
  1276. i915_error_object_free(error->ring[i].ringbuffer);
  1277. kfree(error->ring[i].requests);
  1278. }
  1279. kfree(error->active_bo);
  1280. kfree(error->overlay);
  1281. kfree(error);
  1282. }
  1283. static void capture_bo(struct drm_i915_error_buffer *err,
  1284. struct drm_i915_gem_object *obj)
  1285. {
  1286. err->size = obj->base.size;
  1287. err->name = obj->base.name;
  1288. err->rseqno = obj->last_read_seqno;
  1289. err->wseqno = obj->last_write_seqno;
  1290. err->gtt_offset = obj->gtt_offset;
  1291. err->read_domains = obj->base.read_domains;
  1292. err->write_domain = obj->base.write_domain;
  1293. err->fence_reg = obj->fence_reg;
  1294. err->pinned = 0;
  1295. if (obj->pin_count > 0)
  1296. err->pinned = 1;
  1297. if (obj->user_pin_count > 0)
  1298. err->pinned = -1;
  1299. err->tiling = obj->tiling_mode;
  1300. err->dirty = obj->dirty;
  1301. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  1302. err->ring = obj->ring ? obj->ring->id : -1;
  1303. err->cache_level = obj->cache_level;
  1304. }
  1305. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  1306. int count, struct list_head *head)
  1307. {
  1308. struct drm_i915_gem_object *obj;
  1309. int i = 0;
  1310. list_for_each_entry(obj, head, mm_list) {
  1311. capture_bo(err++, obj);
  1312. if (++i == count)
  1313. break;
  1314. }
  1315. return i;
  1316. }
  1317. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  1318. int count, struct list_head *head)
  1319. {
  1320. struct drm_i915_gem_object *obj;
  1321. int i = 0;
  1322. list_for_each_entry(obj, head, gtt_list) {
  1323. if (obj->pin_count == 0)
  1324. continue;
  1325. capture_bo(err++, obj);
  1326. if (++i == count)
  1327. break;
  1328. }
  1329. return i;
  1330. }
  1331. static void i915_gem_record_fences(struct drm_device *dev,
  1332. struct drm_i915_error_state *error)
  1333. {
  1334. struct drm_i915_private *dev_priv = dev->dev_private;
  1335. int i;
  1336. /* Fences */
  1337. switch (INTEL_INFO(dev)->gen) {
  1338. case 7:
  1339. case 6:
  1340. for (i = 0; i < dev_priv->num_fence_regs; i++)
  1341. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  1342. break;
  1343. case 5:
  1344. case 4:
  1345. for (i = 0; i < 16; i++)
  1346. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  1347. break;
  1348. case 3:
  1349. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  1350. for (i = 0; i < 8; i++)
  1351. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  1352. case 2:
  1353. for (i = 0; i < 8; i++)
  1354. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  1355. break;
  1356. default:
  1357. BUG();
  1358. }
  1359. }
  1360. static struct drm_i915_error_object *
  1361. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  1362. struct intel_ring_buffer *ring)
  1363. {
  1364. struct drm_i915_gem_object *obj;
  1365. u32 seqno;
  1366. if (!ring->get_seqno)
  1367. return NULL;
  1368. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  1369. u32 acthd = I915_READ(ACTHD);
  1370. if (WARN_ON(ring->id != RCS))
  1371. return NULL;
  1372. obj = ring->private;
  1373. if (acthd >= obj->gtt_offset &&
  1374. acthd < obj->gtt_offset + obj->base.size)
  1375. return i915_error_object_create(dev_priv, obj);
  1376. }
  1377. seqno = ring->get_seqno(ring, false);
  1378. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  1379. if (obj->ring != ring)
  1380. continue;
  1381. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  1382. continue;
  1383. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  1384. continue;
  1385. /* We need to copy these to an anonymous buffer as the simplest
  1386. * method to avoid being overwritten by userspace.
  1387. */
  1388. return i915_error_object_create(dev_priv, obj);
  1389. }
  1390. return NULL;
  1391. }
  1392. static void i915_record_ring_state(struct drm_device *dev,
  1393. struct drm_i915_error_state *error,
  1394. struct intel_ring_buffer *ring)
  1395. {
  1396. struct drm_i915_private *dev_priv = dev->dev_private;
  1397. if (INTEL_INFO(dev)->gen >= 6) {
  1398. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  1399. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  1400. error->semaphore_mboxes[ring->id][0]
  1401. = I915_READ(RING_SYNC_0(ring->mmio_base));
  1402. error->semaphore_mboxes[ring->id][1]
  1403. = I915_READ(RING_SYNC_1(ring->mmio_base));
  1404. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  1405. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  1406. }
  1407. if (INTEL_INFO(dev)->gen >= 4) {
  1408. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  1409. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  1410. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  1411. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  1412. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  1413. if (ring->id == RCS)
  1414. error->bbaddr = I915_READ64(BB_ADDR);
  1415. } else {
  1416. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  1417. error->ipeir[ring->id] = I915_READ(IPEIR);
  1418. error->ipehr[ring->id] = I915_READ(IPEHR);
  1419. error->instdone[ring->id] = I915_READ(INSTDONE);
  1420. }
  1421. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  1422. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  1423. error->seqno[ring->id] = ring->get_seqno(ring, false);
  1424. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  1425. error->head[ring->id] = I915_READ_HEAD(ring);
  1426. error->tail[ring->id] = I915_READ_TAIL(ring);
  1427. error->ctl[ring->id] = I915_READ_CTL(ring);
  1428. error->cpu_ring_head[ring->id] = ring->head;
  1429. error->cpu_ring_tail[ring->id] = ring->tail;
  1430. }
  1431. static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
  1432. struct drm_i915_error_state *error,
  1433. struct drm_i915_error_ring *ering)
  1434. {
  1435. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1436. struct drm_i915_gem_object *obj;
  1437. /* Currently render ring is the only HW context user */
  1438. if (ring->id != RCS || !error->ccid)
  1439. return;
  1440. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  1441. if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
  1442. ering->ctx = i915_error_object_create_sized(dev_priv,
  1443. obj, 1);
  1444. }
  1445. }
  1446. }
  1447. static void i915_gem_record_rings(struct drm_device *dev,
  1448. struct drm_i915_error_state *error)
  1449. {
  1450. struct drm_i915_private *dev_priv = dev->dev_private;
  1451. struct intel_ring_buffer *ring;
  1452. struct drm_i915_gem_request *request;
  1453. int i, count;
  1454. for_each_ring(ring, dev_priv, i) {
  1455. i915_record_ring_state(dev, error, ring);
  1456. error->ring[i].batchbuffer =
  1457. i915_error_first_batchbuffer(dev_priv, ring);
  1458. error->ring[i].ringbuffer =
  1459. i915_error_object_create(dev_priv, ring->obj);
  1460. i915_gem_record_active_context(ring, error, &error->ring[i]);
  1461. count = 0;
  1462. list_for_each_entry(request, &ring->request_list, list)
  1463. count++;
  1464. error->ring[i].num_requests = count;
  1465. error->ring[i].requests =
  1466. kmalloc(count*sizeof(struct drm_i915_error_request),
  1467. GFP_ATOMIC);
  1468. if (error->ring[i].requests == NULL) {
  1469. error->ring[i].num_requests = 0;
  1470. continue;
  1471. }
  1472. count = 0;
  1473. list_for_each_entry(request, &ring->request_list, list) {
  1474. struct drm_i915_error_request *erq;
  1475. erq = &error->ring[i].requests[count++];
  1476. erq->seqno = request->seqno;
  1477. erq->jiffies = request->emitted_jiffies;
  1478. erq->tail = request->tail;
  1479. }
  1480. }
  1481. }
  1482. /**
  1483. * i915_capture_error_state - capture an error record for later analysis
  1484. * @dev: drm device
  1485. *
  1486. * Should be called when an error is detected (either a hang or an error
  1487. * interrupt) to capture error state from the time of the error. Fills
  1488. * out a structure which becomes available in debugfs for user level tools
  1489. * to pick up.
  1490. */
  1491. static void i915_capture_error_state(struct drm_device *dev)
  1492. {
  1493. struct drm_i915_private *dev_priv = dev->dev_private;
  1494. struct drm_i915_gem_object *obj;
  1495. struct drm_i915_error_state *error;
  1496. unsigned long flags;
  1497. int i, pipe;
  1498. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1499. error = dev_priv->gpu_error.first_error;
  1500. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1501. if (error)
  1502. return;
  1503. /* Account for pipe specific data like PIPE*STAT */
  1504. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1505. if (!error) {
  1506. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1507. return;
  1508. }
  1509. DRM_INFO("capturing error event; look for more information in "
  1510. "/sys/kernel/debug/dri/%d/i915_error_state\n",
  1511. dev->primary->index);
  1512. kref_init(&error->ref);
  1513. error->eir = I915_READ(EIR);
  1514. error->pgtbl_er = I915_READ(PGTBL_ER);
  1515. if (HAS_HW_CONTEXTS(dev))
  1516. error->ccid = I915_READ(CCID);
  1517. if (HAS_PCH_SPLIT(dev))
  1518. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1519. else if (IS_VALLEYVIEW(dev))
  1520. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1521. else if (IS_GEN2(dev))
  1522. error->ier = I915_READ16(IER);
  1523. else
  1524. error->ier = I915_READ(IER);
  1525. if (INTEL_INFO(dev)->gen >= 6)
  1526. error->derrmr = I915_READ(DERRMR);
  1527. if (IS_VALLEYVIEW(dev))
  1528. error->forcewake = I915_READ(FORCEWAKE_VLV);
  1529. else if (INTEL_INFO(dev)->gen >= 7)
  1530. error->forcewake = I915_READ(FORCEWAKE_MT);
  1531. else if (INTEL_INFO(dev)->gen == 6)
  1532. error->forcewake = I915_READ(FORCEWAKE);
  1533. if (!HAS_PCH_SPLIT(dev))
  1534. for_each_pipe(pipe)
  1535. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1536. if (INTEL_INFO(dev)->gen >= 6) {
  1537. error->error = I915_READ(ERROR_GEN6);
  1538. error->done_reg = I915_READ(DONE_REG);
  1539. }
  1540. if (INTEL_INFO(dev)->gen == 7)
  1541. error->err_int = I915_READ(GEN7_ERR_INT);
  1542. i915_get_extra_instdone(dev, error->extra_instdone);
  1543. i915_gem_record_fences(dev, error);
  1544. i915_gem_record_rings(dev, error);
  1545. /* Record buffers on the active and pinned lists. */
  1546. error->active_bo = NULL;
  1547. error->pinned_bo = NULL;
  1548. i = 0;
  1549. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1550. i++;
  1551. error->active_bo_count = i;
  1552. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
  1553. if (obj->pin_count)
  1554. i++;
  1555. error->pinned_bo_count = i - error->active_bo_count;
  1556. error->active_bo = NULL;
  1557. error->pinned_bo = NULL;
  1558. if (i) {
  1559. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1560. GFP_ATOMIC);
  1561. if (error->active_bo)
  1562. error->pinned_bo =
  1563. error->active_bo + error->active_bo_count;
  1564. }
  1565. if (error->active_bo)
  1566. error->active_bo_count =
  1567. capture_active_bo(error->active_bo,
  1568. error->active_bo_count,
  1569. &dev_priv->mm.active_list);
  1570. if (error->pinned_bo)
  1571. error->pinned_bo_count =
  1572. capture_pinned_bo(error->pinned_bo,
  1573. error->pinned_bo_count,
  1574. &dev_priv->mm.bound_list);
  1575. do_gettimeofday(&error->time);
  1576. error->overlay = intel_overlay_capture_error_state(dev);
  1577. error->display = intel_display_capture_error_state(dev);
  1578. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1579. if (dev_priv->gpu_error.first_error == NULL) {
  1580. dev_priv->gpu_error.first_error = error;
  1581. error = NULL;
  1582. }
  1583. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1584. if (error)
  1585. i915_error_state_free(&error->ref);
  1586. }
  1587. void i915_destroy_error_state(struct drm_device *dev)
  1588. {
  1589. struct drm_i915_private *dev_priv = dev->dev_private;
  1590. struct drm_i915_error_state *error;
  1591. unsigned long flags;
  1592. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1593. error = dev_priv->gpu_error.first_error;
  1594. dev_priv->gpu_error.first_error = NULL;
  1595. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1596. if (error)
  1597. kref_put(&error->ref, i915_error_state_free);
  1598. }
  1599. #else
  1600. #define i915_capture_error_state(x)
  1601. #endif
  1602. static void i915_report_and_clear_eir(struct drm_device *dev)
  1603. {
  1604. struct drm_i915_private *dev_priv = dev->dev_private;
  1605. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1606. u32 eir = I915_READ(EIR);
  1607. int pipe, i;
  1608. if (!eir)
  1609. return;
  1610. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1611. i915_get_extra_instdone(dev, instdone);
  1612. if (IS_G4X(dev)) {
  1613. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1614. u32 ipeir = I915_READ(IPEIR_I965);
  1615. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1616. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1617. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1618. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1619. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1620. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1621. I915_WRITE(IPEIR_I965, ipeir);
  1622. POSTING_READ(IPEIR_I965);
  1623. }
  1624. if (eir & GM45_ERROR_PAGE_TABLE) {
  1625. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1626. pr_err("page table error\n");
  1627. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1628. I915_WRITE(PGTBL_ER, pgtbl_err);
  1629. POSTING_READ(PGTBL_ER);
  1630. }
  1631. }
  1632. if (!IS_GEN2(dev)) {
  1633. if (eir & I915_ERROR_PAGE_TABLE) {
  1634. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1635. pr_err("page table error\n");
  1636. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1637. I915_WRITE(PGTBL_ER, pgtbl_err);
  1638. POSTING_READ(PGTBL_ER);
  1639. }
  1640. }
  1641. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1642. pr_err("memory refresh error:\n");
  1643. for_each_pipe(pipe)
  1644. pr_err("pipe %c stat: 0x%08x\n",
  1645. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1646. /* pipestat has already been acked */
  1647. }
  1648. if (eir & I915_ERROR_INSTRUCTION) {
  1649. pr_err("instruction error\n");
  1650. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1651. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1652. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1653. if (INTEL_INFO(dev)->gen < 4) {
  1654. u32 ipeir = I915_READ(IPEIR);
  1655. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1656. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1657. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1658. I915_WRITE(IPEIR, ipeir);
  1659. POSTING_READ(IPEIR);
  1660. } else {
  1661. u32 ipeir = I915_READ(IPEIR_I965);
  1662. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1663. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1664. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1665. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1666. I915_WRITE(IPEIR_I965, ipeir);
  1667. POSTING_READ(IPEIR_I965);
  1668. }
  1669. }
  1670. I915_WRITE(EIR, eir);
  1671. POSTING_READ(EIR);
  1672. eir = I915_READ(EIR);
  1673. if (eir) {
  1674. /*
  1675. * some errors might have become stuck,
  1676. * mask them.
  1677. */
  1678. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1679. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1680. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1681. }
  1682. }
  1683. /**
  1684. * i915_handle_error - handle an error interrupt
  1685. * @dev: drm device
  1686. *
  1687. * Do some basic checking of regsiter state at error interrupt time and
  1688. * dump it to the syslog. Also call i915_capture_error_state() to make
  1689. * sure we get a record and make it available in debugfs. Fire a uevent
  1690. * so userspace knows something bad happened (should trigger collection
  1691. * of a ring dump etc.).
  1692. */
  1693. void i915_handle_error(struct drm_device *dev, bool wedged)
  1694. {
  1695. struct drm_i915_private *dev_priv = dev->dev_private;
  1696. struct intel_ring_buffer *ring;
  1697. int i;
  1698. i915_capture_error_state(dev);
  1699. i915_report_and_clear_eir(dev);
  1700. if (wedged) {
  1701. atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
  1702. &dev_priv->gpu_error.reset_counter);
  1703. /*
  1704. * Wakeup waiting processes so that the reset work item
  1705. * doesn't deadlock trying to grab various locks.
  1706. */
  1707. for_each_ring(ring, dev_priv, i)
  1708. wake_up_all(&ring->irq_queue);
  1709. }
  1710. queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
  1711. }
  1712. static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1713. {
  1714. drm_i915_private_t *dev_priv = dev->dev_private;
  1715. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1716. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1717. struct drm_i915_gem_object *obj;
  1718. struct intel_unpin_work *work;
  1719. unsigned long flags;
  1720. bool stall_detected;
  1721. /* Ignore early vblank irqs */
  1722. if (intel_crtc == NULL)
  1723. return;
  1724. spin_lock_irqsave(&dev->event_lock, flags);
  1725. work = intel_crtc->unpin_work;
  1726. if (work == NULL ||
  1727. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1728. !work->enable_stall_check) {
  1729. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1730. spin_unlock_irqrestore(&dev->event_lock, flags);
  1731. return;
  1732. }
  1733. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1734. obj = work->pending_flip_obj;
  1735. if (INTEL_INFO(dev)->gen >= 4) {
  1736. int dspsurf = DSPSURF(intel_crtc->plane);
  1737. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1738. obj->gtt_offset;
  1739. } else {
  1740. int dspaddr = DSPADDR(intel_crtc->plane);
  1741. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1742. crtc->y * crtc->fb->pitches[0] +
  1743. crtc->x * crtc->fb->bits_per_pixel/8);
  1744. }
  1745. spin_unlock_irqrestore(&dev->event_lock, flags);
  1746. if (stall_detected) {
  1747. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1748. intel_prepare_page_flip(dev, intel_crtc->plane);
  1749. }
  1750. }
  1751. /* Called from drm generic code, passed 'crtc' which
  1752. * we use as a pipe index
  1753. */
  1754. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1755. {
  1756. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1757. unsigned long irqflags;
  1758. if (!i915_pipe_enabled(dev, pipe))
  1759. return -EINVAL;
  1760. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1761. if (INTEL_INFO(dev)->gen >= 4)
  1762. i915_enable_pipestat(dev_priv, pipe,
  1763. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1764. else
  1765. i915_enable_pipestat(dev_priv, pipe,
  1766. PIPE_VBLANK_INTERRUPT_ENABLE);
  1767. /* maintain vblank delivery even in deep C-states */
  1768. if (dev_priv->info->gen == 3)
  1769. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1770. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1771. return 0;
  1772. }
  1773. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1774. {
  1775. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1776. unsigned long irqflags;
  1777. if (!i915_pipe_enabled(dev, pipe))
  1778. return -EINVAL;
  1779. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1780. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1781. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1782. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1783. return 0;
  1784. }
  1785. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1786. {
  1787. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1788. unsigned long irqflags;
  1789. if (!i915_pipe_enabled(dev, pipe))
  1790. return -EINVAL;
  1791. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1792. ironlake_enable_display_irq(dev_priv,
  1793. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1794. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1795. return 0;
  1796. }
  1797. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1798. {
  1799. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1800. unsigned long irqflags;
  1801. u32 imr;
  1802. if (!i915_pipe_enabled(dev, pipe))
  1803. return -EINVAL;
  1804. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1805. imr = I915_READ(VLV_IMR);
  1806. if (pipe == 0)
  1807. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1808. else
  1809. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1810. I915_WRITE(VLV_IMR, imr);
  1811. i915_enable_pipestat(dev_priv, pipe,
  1812. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1813. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1814. return 0;
  1815. }
  1816. /* Called from drm generic code, passed 'crtc' which
  1817. * we use as a pipe index
  1818. */
  1819. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1820. {
  1821. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1822. unsigned long irqflags;
  1823. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1824. if (dev_priv->info->gen == 3)
  1825. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1826. i915_disable_pipestat(dev_priv, pipe,
  1827. PIPE_VBLANK_INTERRUPT_ENABLE |
  1828. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1829. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1830. }
  1831. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1832. {
  1833. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1834. unsigned long irqflags;
  1835. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1836. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1837. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1838. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1839. }
  1840. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1841. {
  1842. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1843. unsigned long irqflags;
  1844. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1845. ironlake_disable_display_irq(dev_priv,
  1846. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1847. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1848. }
  1849. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1850. {
  1851. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1852. unsigned long irqflags;
  1853. u32 imr;
  1854. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1855. i915_disable_pipestat(dev_priv, pipe,
  1856. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1857. imr = I915_READ(VLV_IMR);
  1858. if (pipe == 0)
  1859. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1860. else
  1861. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1862. I915_WRITE(VLV_IMR, imr);
  1863. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1864. }
  1865. static u32
  1866. ring_last_seqno(struct intel_ring_buffer *ring)
  1867. {
  1868. return list_entry(ring->request_list.prev,
  1869. struct drm_i915_gem_request, list)->seqno;
  1870. }
  1871. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1872. {
  1873. if (list_empty(&ring->request_list) ||
  1874. i915_seqno_passed(ring->get_seqno(ring, false),
  1875. ring_last_seqno(ring))) {
  1876. /* Issue a wake-up to catch stuck h/w. */
  1877. if (waitqueue_active(&ring->irq_queue)) {
  1878. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1879. ring->name);
  1880. wake_up_all(&ring->irq_queue);
  1881. *err = true;
  1882. }
  1883. return true;
  1884. }
  1885. return false;
  1886. }
  1887. static bool semaphore_passed(struct intel_ring_buffer *ring)
  1888. {
  1889. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1890. u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
  1891. struct intel_ring_buffer *signaller;
  1892. u32 cmd, ipehr, acthd_min;
  1893. ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  1894. if ((ipehr & ~(0x3 << 16)) !=
  1895. (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
  1896. return false;
  1897. /* ACTHD is likely pointing to the dword after the actual command,
  1898. * so scan backwards until we find the MBOX.
  1899. */
  1900. acthd_min = max((int)acthd - 3 * 4, 0);
  1901. do {
  1902. cmd = ioread32(ring->virtual_start + acthd);
  1903. if (cmd == ipehr)
  1904. break;
  1905. acthd -= 4;
  1906. if (acthd < acthd_min)
  1907. return false;
  1908. } while (1);
  1909. signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
  1910. return i915_seqno_passed(signaller->get_seqno(signaller, false),
  1911. ioread32(ring->virtual_start+acthd+4)+1);
  1912. }
  1913. static bool kick_ring(struct intel_ring_buffer *ring)
  1914. {
  1915. struct drm_device *dev = ring->dev;
  1916. struct drm_i915_private *dev_priv = dev->dev_private;
  1917. u32 tmp = I915_READ_CTL(ring);
  1918. if (tmp & RING_WAIT) {
  1919. DRM_ERROR("Kicking stuck wait on %s\n",
  1920. ring->name);
  1921. I915_WRITE_CTL(ring, tmp);
  1922. return true;
  1923. }
  1924. if (INTEL_INFO(dev)->gen >= 6 &&
  1925. tmp & RING_WAIT_SEMAPHORE &&
  1926. semaphore_passed(ring)) {
  1927. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1928. ring->name);
  1929. I915_WRITE_CTL(ring, tmp);
  1930. return true;
  1931. }
  1932. return false;
  1933. }
  1934. static bool i915_hangcheck_hung(struct drm_device *dev)
  1935. {
  1936. drm_i915_private_t *dev_priv = dev->dev_private;
  1937. if (dev_priv->gpu_error.hangcheck_count++ > 1) {
  1938. bool hung = true;
  1939. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1940. i915_handle_error(dev, true);
  1941. if (!IS_GEN2(dev)) {
  1942. struct intel_ring_buffer *ring;
  1943. int i;
  1944. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1945. * If so we can simply poke the RB_WAIT bit
  1946. * and break the hang. This should work on
  1947. * all but the second generation chipsets.
  1948. */
  1949. for_each_ring(ring, dev_priv, i)
  1950. hung &= !kick_ring(ring);
  1951. }
  1952. return hung;
  1953. }
  1954. return false;
  1955. }
  1956. /**
  1957. * This is called when the chip hasn't reported back with completed
  1958. * batchbuffers in a long time. The first time this is called we simply record
  1959. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1960. * again, we assume the chip is wedged and try to fix it.
  1961. */
  1962. void i915_hangcheck_elapsed(unsigned long data)
  1963. {
  1964. struct drm_device *dev = (struct drm_device *)data;
  1965. drm_i915_private_t *dev_priv = dev->dev_private;
  1966. uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
  1967. struct intel_ring_buffer *ring;
  1968. bool err = false, idle;
  1969. int i;
  1970. if (!i915_enable_hangcheck)
  1971. return;
  1972. memset(acthd, 0, sizeof(acthd));
  1973. idle = true;
  1974. for_each_ring(ring, dev_priv, i) {
  1975. idle &= i915_hangcheck_ring_idle(ring, &err);
  1976. acthd[i] = intel_ring_get_active_head(ring);
  1977. }
  1978. /* If all work is done then ACTHD clearly hasn't advanced. */
  1979. if (idle) {
  1980. if (err) {
  1981. if (i915_hangcheck_hung(dev))
  1982. return;
  1983. goto repeat;
  1984. }
  1985. dev_priv->gpu_error.hangcheck_count = 0;
  1986. return;
  1987. }
  1988. i915_get_extra_instdone(dev, instdone);
  1989. if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
  1990. sizeof(acthd)) == 0 &&
  1991. memcmp(dev_priv->gpu_error.prev_instdone, instdone,
  1992. sizeof(instdone)) == 0) {
  1993. if (i915_hangcheck_hung(dev))
  1994. return;
  1995. } else {
  1996. dev_priv->gpu_error.hangcheck_count = 0;
  1997. memcpy(dev_priv->gpu_error.last_acthd, acthd,
  1998. sizeof(acthd));
  1999. memcpy(dev_priv->gpu_error.prev_instdone, instdone,
  2000. sizeof(instdone));
  2001. }
  2002. repeat:
  2003. /* Reset timer case chip hangs without another request being added */
  2004. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  2005. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  2006. }
  2007. /* drm_dma.h hooks
  2008. */
  2009. static void ironlake_irq_preinstall(struct drm_device *dev)
  2010. {
  2011. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2012. atomic_set(&dev_priv->irq_received, 0);
  2013. I915_WRITE(HWSTAM, 0xeffe);
  2014. /* XXX hotplug from PCH */
  2015. I915_WRITE(DEIMR, 0xffffffff);
  2016. I915_WRITE(DEIER, 0x0);
  2017. POSTING_READ(DEIER);
  2018. /* and GT */
  2019. I915_WRITE(GTIMR, 0xffffffff);
  2020. I915_WRITE(GTIER, 0x0);
  2021. POSTING_READ(GTIER);
  2022. if (HAS_PCH_NOP(dev))
  2023. return;
  2024. /* south display irq */
  2025. I915_WRITE(SDEIMR, 0xffffffff);
  2026. /*
  2027. * SDEIER is also touched by the interrupt handler to work around missed
  2028. * PCH interrupts. Hence we can't update it after the interrupt handler
  2029. * is enabled - instead we unconditionally enable all PCH interrupt
  2030. * sources here, but then only unmask them as needed with SDEIMR.
  2031. */
  2032. I915_WRITE(SDEIER, 0xffffffff);
  2033. POSTING_READ(SDEIER);
  2034. }
  2035. static void valleyview_irq_preinstall(struct drm_device *dev)
  2036. {
  2037. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2038. int pipe;
  2039. atomic_set(&dev_priv->irq_received, 0);
  2040. /* VLV magic */
  2041. I915_WRITE(VLV_IMR, 0);
  2042. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  2043. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  2044. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  2045. /* and GT */
  2046. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2047. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2048. I915_WRITE(GTIMR, 0xffffffff);
  2049. I915_WRITE(GTIER, 0x0);
  2050. POSTING_READ(GTIER);
  2051. I915_WRITE(DPINVGTT, 0xff);
  2052. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2053. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2054. for_each_pipe(pipe)
  2055. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2056. I915_WRITE(VLV_IIR, 0xffffffff);
  2057. I915_WRITE(VLV_IMR, 0xffffffff);
  2058. I915_WRITE(VLV_IER, 0x0);
  2059. POSTING_READ(VLV_IER);
  2060. }
  2061. static void ibx_hpd_irq_setup(struct drm_device *dev)
  2062. {
  2063. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2064. struct drm_mode_config *mode_config = &dev->mode_config;
  2065. struct intel_encoder *intel_encoder;
  2066. u32 mask = ~I915_READ(SDEIMR);
  2067. u32 hotplug;
  2068. if (HAS_PCH_IBX(dev)) {
  2069. mask &= ~SDE_HOTPLUG_MASK;
  2070. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2071. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2072. mask |= hpd_ibx[intel_encoder->hpd_pin];
  2073. } else {
  2074. mask &= ~SDE_HOTPLUG_MASK_CPT;
  2075. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2076. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2077. mask |= hpd_cpt[intel_encoder->hpd_pin];
  2078. }
  2079. I915_WRITE(SDEIMR, ~mask);
  2080. /*
  2081. * Enable digital hotplug on the PCH, and configure the DP short pulse
  2082. * duration to 2ms (which is the minimum in the Display Port spec)
  2083. *
  2084. * This register is the same on all known PCH chips.
  2085. */
  2086. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  2087. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  2088. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  2089. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  2090. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  2091. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  2092. }
  2093. static void ibx_irq_postinstall(struct drm_device *dev)
  2094. {
  2095. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2096. u32 mask;
  2097. if (HAS_PCH_IBX(dev)) {
  2098. mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
  2099. SDE_TRANSA_FIFO_UNDER | SDE_POISON;
  2100. } else {
  2101. mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
  2102. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  2103. }
  2104. if (HAS_PCH_NOP(dev))
  2105. return;
  2106. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  2107. I915_WRITE(SDEIMR, ~mask);
  2108. }
  2109. static int ironlake_irq_postinstall(struct drm_device *dev)
  2110. {
  2111. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2112. /* enable kind of interrupts always enabled */
  2113. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  2114. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  2115. DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
  2116. DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
  2117. u32 render_irqs;
  2118. dev_priv->irq_mask = ~display_mask;
  2119. /* should always can generate irq */
  2120. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2121. I915_WRITE(DEIMR, dev_priv->irq_mask);
  2122. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  2123. POSTING_READ(DEIER);
  2124. dev_priv->gt_irq_mask = ~0;
  2125. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2126. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2127. if (IS_GEN6(dev))
  2128. render_irqs =
  2129. GT_USER_INTERRUPT |
  2130. GEN6_BSD_USER_INTERRUPT |
  2131. GEN6_BLITTER_USER_INTERRUPT;
  2132. else
  2133. render_irqs =
  2134. GT_USER_INTERRUPT |
  2135. GT_PIPE_NOTIFY |
  2136. GT_BSD_USER_INTERRUPT;
  2137. I915_WRITE(GTIER, render_irqs);
  2138. POSTING_READ(GTIER);
  2139. ibx_irq_postinstall(dev);
  2140. if (IS_IRONLAKE_M(dev)) {
  2141. /* Clear & enable PCU event interrupts */
  2142. I915_WRITE(DEIIR, DE_PCU_EVENT);
  2143. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  2144. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  2145. }
  2146. return 0;
  2147. }
  2148. static int ivybridge_irq_postinstall(struct drm_device *dev)
  2149. {
  2150. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2151. /* enable kind of interrupts always enabled */
  2152. u32 display_mask =
  2153. DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
  2154. DE_PLANEC_FLIP_DONE_IVB |
  2155. DE_PLANEB_FLIP_DONE_IVB |
  2156. DE_PLANEA_FLIP_DONE_IVB |
  2157. DE_AUX_CHANNEL_A_IVB |
  2158. DE_ERR_INT_IVB;
  2159. u32 render_irqs;
  2160. dev_priv->irq_mask = ~display_mask;
  2161. /* should always can generate irq */
  2162. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  2163. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2164. I915_WRITE(DEIMR, dev_priv->irq_mask);
  2165. I915_WRITE(DEIER,
  2166. display_mask |
  2167. DE_PIPEC_VBLANK_IVB |
  2168. DE_PIPEB_VBLANK_IVB |
  2169. DE_PIPEA_VBLANK_IVB);
  2170. POSTING_READ(DEIER);
  2171. dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  2172. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2173. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2174. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  2175. GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  2176. I915_WRITE(GTIER, render_irqs);
  2177. POSTING_READ(GTIER);
  2178. ibx_irq_postinstall(dev);
  2179. return 0;
  2180. }
  2181. static int valleyview_irq_postinstall(struct drm_device *dev)
  2182. {
  2183. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2184. u32 enable_mask;
  2185. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  2186. u32 render_irqs;
  2187. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  2188. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2189. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  2190. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2191. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  2192. /*
  2193. *Leave vblank interrupts masked initially. enable/disable will
  2194. * toggle them based on usage.
  2195. */
  2196. dev_priv->irq_mask = (~enable_mask) |
  2197. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  2198. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  2199. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2200. POSTING_READ(PORT_HOTPLUG_EN);
  2201. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  2202. I915_WRITE(VLV_IER, enable_mask);
  2203. I915_WRITE(VLV_IIR, 0xffffffff);
  2204. I915_WRITE(PIPESTAT(0), 0xffff);
  2205. I915_WRITE(PIPESTAT(1), 0xffff);
  2206. POSTING_READ(VLV_IER);
  2207. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  2208. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2209. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  2210. I915_WRITE(VLV_IIR, 0xffffffff);
  2211. I915_WRITE(VLV_IIR, 0xffffffff);
  2212. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2213. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  2214. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  2215. GEN6_BLITTER_USER_INTERRUPT;
  2216. I915_WRITE(GTIER, render_irqs);
  2217. POSTING_READ(GTIER);
  2218. /* ack & enable invalid PTE error interrupts */
  2219. #if 0 /* FIXME: add support to irq handler for checking these bits */
  2220. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  2221. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  2222. #endif
  2223. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  2224. return 0;
  2225. }
  2226. static void valleyview_irq_uninstall(struct drm_device *dev)
  2227. {
  2228. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2229. int pipe;
  2230. if (!dev_priv)
  2231. return;
  2232. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2233. for_each_pipe(pipe)
  2234. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2235. I915_WRITE(HWSTAM, 0xffffffff);
  2236. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2237. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2238. for_each_pipe(pipe)
  2239. I915_WRITE(PIPESTAT(pipe), 0xffff);
  2240. I915_WRITE(VLV_IIR, 0xffffffff);
  2241. I915_WRITE(VLV_IMR, 0xffffffff);
  2242. I915_WRITE(VLV_IER, 0x0);
  2243. POSTING_READ(VLV_IER);
  2244. }
  2245. static void ironlake_irq_uninstall(struct drm_device *dev)
  2246. {
  2247. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2248. if (!dev_priv)
  2249. return;
  2250. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2251. I915_WRITE(HWSTAM, 0xffffffff);
  2252. I915_WRITE(DEIMR, 0xffffffff);
  2253. I915_WRITE(DEIER, 0x0);
  2254. I915_WRITE(DEIIR, I915_READ(DEIIR));
  2255. if (IS_GEN7(dev))
  2256. I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
  2257. I915_WRITE(GTIMR, 0xffffffff);
  2258. I915_WRITE(GTIER, 0x0);
  2259. I915_WRITE(GTIIR, I915_READ(GTIIR));
  2260. if (HAS_PCH_NOP(dev))
  2261. return;
  2262. I915_WRITE(SDEIMR, 0xffffffff);
  2263. I915_WRITE(SDEIER, 0x0);
  2264. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  2265. if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
  2266. I915_WRITE(SERR_INT, I915_READ(SERR_INT));
  2267. }
  2268. static void i8xx_irq_preinstall(struct drm_device * dev)
  2269. {
  2270. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2271. int pipe;
  2272. atomic_set(&dev_priv->irq_received, 0);
  2273. for_each_pipe(pipe)
  2274. I915_WRITE(PIPESTAT(pipe), 0);
  2275. I915_WRITE16(IMR, 0xffff);
  2276. I915_WRITE16(IER, 0x0);
  2277. POSTING_READ16(IER);
  2278. }
  2279. static int i8xx_irq_postinstall(struct drm_device *dev)
  2280. {
  2281. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2282. I915_WRITE16(EMR,
  2283. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2284. /* Unmask the interrupts that we always want on. */
  2285. dev_priv->irq_mask =
  2286. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2287. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2288. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2289. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2290. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2291. I915_WRITE16(IMR, dev_priv->irq_mask);
  2292. I915_WRITE16(IER,
  2293. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2294. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2295. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2296. I915_USER_INTERRUPT);
  2297. POSTING_READ16(IER);
  2298. return 0;
  2299. }
  2300. /*
  2301. * Returns true when a page flip has completed.
  2302. */
  2303. static bool i8xx_handle_vblank(struct drm_device *dev,
  2304. int pipe, u16 iir)
  2305. {
  2306. drm_i915_private_t *dev_priv = dev->dev_private;
  2307. u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
  2308. if (!drm_handle_vblank(dev, pipe))
  2309. return false;
  2310. if ((iir & flip_pending) == 0)
  2311. return false;
  2312. intel_prepare_page_flip(dev, pipe);
  2313. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2314. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2315. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2316. * the flip is completed (no longer pending). Since this doesn't raise
  2317. * an interrupt per se, we watch for the change at vblank.
  2318. */
  2319. if (I915_READ16(ISR) & flip_pending)
  2320. return false;
  2321. intel_finish_page_flip(dev, pipe);
  2322. return true;
  2323. }
  2324. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  2325. {
  2326. struct drm_device *dev = (struct drm_device *) arg;
  2327. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2328. u16 iir, new_iir;
  2329. u32 pipe_stats[2];
  2330. unsigned long irqflags;
  2331. int irq_received;
  2332. int pipe;
  2333. u16 flip_mask =
  2334. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2335. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2336. atomic_inc(&dev_priv->irq_received);
  2337. iir = I915_READ16(IIR);
  2338. if (iir == 0)
  2339. return IRQ_NONE;
  2340. while (iir & ~flip_mask) {
  2341. /* Can't rely on pipestat interrupt bit in iir as it might
  2342. * have been cleared after the pipestat interrupt was received.
  2343. * It doesn't set the bit in iir again, but it still produces
  2344. * interrupts (for non-MSI).
  2345. */
  2346. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2347. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2348. i915_handle_error(dev, false);
  2349. for_each_pipe(pipe) {
  2350. int reg = PIPESTAT(pipe);
  2351. pipe_stats[pipe] = I915_READ(reg);
  2352. /*
  2353. * Clear the PIPE*STAT regs before the IIR
  2354. */
  2355. if (pipe_stats[pipe] & 0x8000ffff) {
  2356. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2357. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2358. pipe_name(pipe));
  2359. I915_WRITE(reg, pipe_stats[pipe]);
  2360. irq_received = 1;
  2361. }
  2362. }
  2363. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2364. I915_WRITE16(IIR, iir & ~flip_mask);
  2365. new_iir = I915_READ16(IIR); /* Flush posted writes */
  2366. i915_update_dri1_breadcrumb(dev);
  2367. if (iir & I915_USER_INTERRUPT)
  2368. notify_ring(dev, &dev_priv->ring[RCS]);
  2369. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2370. i8xx_handle_vblank(dev, 0, iir))
  2371. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
  2372. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2373. i8xx_handle_vblank(dev, 1, iir))
  2374. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
  2375. iir = new_iir;
  2376. }
  2377. return IRQ_HANDLED;
  2378. }
  2379. static void i8xx_irq_uninstall(struct drm_device * dev)
  2380. {
  2381. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2382. int pipe;
  2383. for_each_pipe(pipe) {
  2384. /* Clear enable bits; then clear status bits */
  2385. I915_WRITE(PIPESTAT(pipe), 0);
  2386. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2387. }
  2388. I915_WRITE16(IMR, 0xffff);
  2389. I915_WRITE16(IER, 0x0);
  2390. I915_WRITE16(IIR, I915_READ16(IIR));
  2391. }
  2392. static void i915_irq_preinstall(struct drm_device * dev)
  2393. {
  2394. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2395. int pipe;
  2396. atomic_set(&dev_priv->irq_received, 0);
  2397. if (I915_HAS_HOTPLUG(dev)) {
  2398. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2399. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2400. }
  2401. I915_WRITE16(HWSTAM, 0xeffe);
  2402. for_each_pipe(pipe)
  2403. I915_WRITE(PIPESTAT(pipe), 0);
  2404. I915_WRITE(IMR, 0xffffffff);
  2405. I915_WRITE(IER, 0x0);
  2406. POSTING_READ(IER);
  2407. }
  2408. static int i915_irq_postinstall(struct drm_device *dev)
  2409. {
  2410. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2411. u32 enable_mask;
  2412. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2413. /* Unmask the interrupts that we always want on. */
  2414. dev_priv->irq_mask =
  2415. ~(I915_ASLE_INTERRUPT |
  2416. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2417. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2418. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2419. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2420. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2421. enable_mask =
  2422. I915_ASLE_INTERRUPT |
  2423. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2424. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2425. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2426. I915_USER_INTERRUPT;
  2427. if (I915_HAS_HOTPLUG(dev)) {
  2428. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2429. POSTING_READ(PORT_HOTPLUG_EN);
  2430. /* Enable in IER... */
  2431. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  2432. /* and unmask in IMR */
  2433. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  2434. }
  2435. I915_WRITE(IMR, dev_priv->irq_mask);
  2436. I915_WRITE(IER, enable_mask);
  2437. POSTING_READ(IER);
  2438. i915_enable_asle_pipestat(dev);
  2439. return 0;
  2440. }
  2441. /*
  2442. * Returns true when a page flip has completed.
  2443. */
  2444. static bool i915_handle_vblank(struct drm_device *dev,
  2445. int plane, int pipe, u32 iir)
  2446. {
  2447. drm_i915_private_t *dev_priv = dev->dev_private;
  2448. u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  2449. if (!drm_handle_vblank(dev, pipe))
  2450. return false;
  2451. if ((iir & flip_pending) == 0)
  2452. return false;
  2453. intel_prepare_page_flip(dev, plane);
  2454. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2455. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2456. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2457. * the flip is completed (no longer pending). Since this doesn't raise
  2458. * an interrupt per se, we watch for the change at vblank.
  2459. */
  2460. if (I915_READ(ISR) & flip_pending)
  2461. return false;
  2462. intel_finish_page_flip(dev, pipe);
  2463. return true;
  2464. }
  2465. static irqreturn_t i915_irq_handler(int irq, void *arg)
  2466. {
  2467. struct drm_device *dev = (struct drm_device *) arg;
  2468. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2469. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  2470. unsigned long irqflags;
  2471. u32 flip_mask =
  2472. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2473. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2474. int pipe, ret = IRQ_NONE;
  2475. atomic_inc(&dev_priv->irq_received);
  2476. iir = I915_READ(IIR);
  2477. do {
  2478. bool irq_received = (iir & ~flip_mask) != 0;
  2479. bool blc_event = false;
  2480. /* Can't rely on pipestat interrupt bit in iir as it might
  2481. * have been cleared after the pipestat interrupt was received.
  2482. * It doesn't set the bit in iir again, but it still produces
  2483. * interrupts (for non-MSI).
  2484. */
  2485. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2486. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2487. i915_handle_error(dev, false);
  2488. for_each_pipe(pipe) {
  2489. int reg = PIPESTAT(pipe);
  2490. pipe_stats[pipe] = I915_READ(reg);
  2491. /* Clear the PIPE*STAT regs before the IIR */
  2492. if (pipe_stats[pipe] & 0x8000ffff) {
  2493. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2494. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2495. pipe_name(pipe));
  2496. I915_WRITE(reg, pipe_stats[pipe]);
  2497. irq_received = true;
  2498. }
  2499. }
  2500. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2501. if (!irq_received)
  2502. break;
  2503. /* Consume port. Then clear IIR or we'll miss events */
  2504. if ((I915_HAS_HOTPLUG(dev)) &&
  2505. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  2506. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2507. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  2508. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2509. hotplug_status);
  2510. if (hotplug_trigger) {
  2511. if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
  2512. i915_hpd_irq_setup(dev);
  2513. queue_work(dev_priv->wq,
  2514. &dev_priv->hotplug_work);
  2515. }
  2516. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2517. POSTING_READ(PORT_HOTPLUG_STAT);
  2518. }
  2519. I915_WRITE(IIR, iir & ~flip_mask);
  2520. new_iir = I915_READ(IIR); /* Flush posted writes */
  2521. if (iir & I915_USER_INTERRUPT)
  2522. notify_ring(dev, &dev_priv->ring[RCS]);
  2523. for_each_pipe(pipe) {
  2524. int plane = pipe;
  2525. if (IS_MOBILE(dev))
  2526. plane = !plane;
  2527. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2528. i915_handle_vblank(dev, plane, pipe, iir))
  2529. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  2530. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2531. blc_event = true;
  2532. }
  2533. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2534. intel_opregion_asle_intr(dev);
  2535. /* With MSI, interrupts are only generated when iir
  2536. * transitions from zero to nonzero. If another bit got
  2537. * set while we were handling the existing iir bits, then
  2538. * we would never get another interrupt.
  2539. *
  2540. * This is fine on non-MSI as well, as if we hit this path
  2541. * we avoid exiting the interrupt handler only to generate
  2542. * another one.
  2543. *
  2544. * Note that for MSI this could cause a stray interrupt report
  2545. * if an interrupt landed in the time between writing IIR and
  2546. * the posting read. This should be rare enough to never
  2547. * trigger the 99% of 100,000 interrupts test for disabling
  2548. * stray interrupts.
  2549. */
  2550. ret = IRQ_HANDLED;
  2551. iir = new_iir;
  2552. } while (iir & ~flip_mask);
  2553. i915_update_dri1_breadcrumb(dev);
  2554. return ret;
  2555. }
  2556. static void i915_irq_uninstall(struct drm_device * dev)
  2557. {
  2558. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2559. int pipe;
  2560. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2561. if (I915_HAS_HOTPLUG(dev)) {
  2562. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2563. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2564. }
  2565. I915_WRITE16(HWSTAM, 0xffff);
  2566. for_each_pipe(pipe) {
  2567. /* Clear enable bits; then clear status bits */
  2568. I915_WRITE(PIPESTAT(pipe), 0);
  2569. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2570. }
  2571. I915_WRITE(IMR, 0xffffffff);
  2572. I915_WRITE(IER, 0x0);
  2573. I915_WRITE(IIR, I915_READ(IIR));
  2574. }
  2575. static void i965_irq_preinstall(struct drm_device * dev)
  2576. {
  2577. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2578. int pipe;
  2579. atomic_set(&dev_priv->irq_received, 0);
  2580. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2581. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2582. I915_WRITE(HWSTAM, 0xeffe);
  2583. for_each_pipe(pipe)
  2584. I915_WRITE(PIPESTAT(pipe), 0);
  2585. I915_WRITE(IMR, 0xffffffff);
  2586. I915_WRITE(IER, 0x0);
  2587. POSTING_READ(IER);
  2588. }
  2589. static int i965_irq_postinstall(struct drm_device *dev)
  2590. {
  2591. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2592. u32 enable_mask;
  2593. u32 error_mask;
  2594. /* Unmask the interrupts that we always want on. */
  2595. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2596. I915_DISPLAY_PORT_INTERRUPT |
  2597. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2598. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2599. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2600. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2601. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2602. enable_mask = ~dev_priv->irq_mask;
  2603. enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2604. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  2605. enable_mask |= I915_USER_INTERRUPT;
  2606. if (IS_G4X(dev))
  2607. enable_mask |= I915_BSD_USER_INTERRUPT;
  2608. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2609. /*
  2610. * Enable some error detection, note the instruction error mask
  2611. * bit is reserved, so we leave it masked.
  2612. */
  2613. if (IS_G4X(dev)) {
  2614. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2615. GM45_ERROR_MEM_PRIV |
  2616. GM45_ERROR_CP_PRIV |
  2617. I915_ERROR_MEMORY_REFRESH);
  2618. } else {
  2619. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2620. I915_ERROR_MEMORY_REFRESH);
  2621. }
  2622. I915_WRITE(EMR, error_mask);
  2623. I915_WRITE(IMR, dev_priv->irq_mask);
  2624. I915_WRITE(IER, enable_mask);
  2625. POSTING_READ(IER);
  2626. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2627. POSTING_READ(PORT_HOTPLUG_EN);
  2628. i915_enable_asle_pipestat(dev);
  2629. return 0;
  2630. }
  2631. static void i915_hpd_irq_setup(struct drm_device *dev)
  2632. {
  2633. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2634. struct drm_mode_config *mode_config = &dev->mode_config;
  2635. struct intel_encoder *intel_encoder;
  2636. u32 hotplug_en;
  2637. if (I915_HAS_HOTPLUG(dev)) {
  2638. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  2639. hotplug_en &= ~HOTPLUG_INT_EN_MASK;
  2640. /* Note HDMI and DP share hotplug bits */
  2641. /* enable bits are the same for all generations */
  2642. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  2643. if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
  2644. hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
  2645. /* Programming the CRT detection parameters tends
  2646. to generate a spurious hotplug event about three
  2647. seconds later. So just do it once.
  2648. */
  2649. if (IS_G4X(dev))
  2650. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2651. hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
  2652. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2653. /* Ignore TV since it's buggy */
  2654. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2655. }
  2656. }
  2657. static irqreturn_t i965_irq_handler(int irq, void *arg)
  2658. {
  2659. struct drm_device *dev = (struct drm_device *) arg;
  2660. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2661. u32 iir, new_iir;
  2662. u32 pipe_stats[I915_MAX_PIPES];
  2663. unsigned long irqflags;
  2664. int irq_received;
  2665. int ret = IRQ_NONE, pipe;
  2666. u32 flip_mask =
  2667. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2668. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2669. atomic_inc(&dev_priv->irq_received);
  2670. iir = I915_READ(IIR);
  2671. for (;;) {
  2672. bool blc_event = false;
  2673. irq_received = (iir & ~flip_mask) != 0;
  2674. /* Can't rely on pipestat interrupt bit in iir as it might
  2675. * have been cleared after the pipestat interrupt was received.
  2676. * It doesn't set the bit in iir again, but it still produces
  2677. * interrupts (for non-MSI).
  2678. */
  2679. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2680. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2681. i915_handle_error(dev, false);
  2682. for_each_pipe(pipe) {
  2683. int reg = PIPESTAT(pipe);
  2684. pipe_stats[pipe] = I915_READ(reg);
  2685. /*
  2686. * Clear the PIPE*STAT regs before the IIR
  2687. */
  2688. if (pipe_stats[pipe] & 0x8000ffff) {
  2689. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2690. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2691. pipe_name(pipe));
  2692. I915_WRITE(reg, pipe_stats[pipe]);
  2693. irq_received = 1;
  2694. }
  2695. }
  2696. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2697. if (!irq_received)
  2698. break;
  2699. ret = IRQ_HANDLED;
  2700. /* Consume port. Then clear IIR or we'll miss events */
  2701. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2702. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2703. u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
  2704. HOTPLUG_INT_STATUS_G4X :
  2705. HOTPLUG_INT_STATUS_I965);
  2706. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2707. hotplug_status);
  2708. if (hotplug_trigger) {
  2709. if (hotplug_irq_storm_detect(dev, hotplug_trigger,
  2710. IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
  2711. i915_hpd_irq_setup(dev);
  2712. queue_work(dev_priv->wq,
  2713. &dev_priv->hotplug_work);
  2714. }
  2715. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2716. I915_READ(PORT_HOTPLUG_STAT);
  2717. }
  2718. I915_WRITE(IIR, iir & ~flip_mask);
  2719. new_iir = I915_READ(IIR); /* Flush posted writes */
  2720. if (iir & I915_USER_INTERRUPT)
  2721. notify_ring(dev, &dev_priv->ring[RCS]);
  2722. if (iir & I915_BSD_USER_INTERRUPT)
  2723. notify_ring(dev, &dev_priv->ring[VCS]);
  2724. for_each_pipe(pipe) {
  2725. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2726. i915_handle_vblank(dev, pipe, pipe, iir))
  2727. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  2728. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2729. blc_event = true;
  2730. }
  2731. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2732. intel_opregion_asle_intr(dev);
  2733. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  2734. gmbus_irq_handler(dev);
  2735. /* With MSI, interrupts are only generated when iir
  2736. * transitions from zero to nonzero. If another bit got
  2737. * set while we were handling the existing iir bits, then
  2738. * we would never get another interrupt.
  2739. *
  2740. * This is fine on non-MSI as well, as if we hit this path
  2741. * we avoid exiting the interrupt handler only to generate
  2742. * another one.
  2743. *
  2744. * Note that for MSI this could cause a stray interrupt report
  2745. * if an interrupt landed in the time between writing IIR and
  2746. * the posting read. This should be rare enough to never
  2747. * trigger the 99% of 100,000 interrupts test for disabling
  2748. * stray interrupts.
  2749. */
  2750. iir = new_iir;
  2751. }
  2752. i915_update_dri1_breadcrumb(dev);
  2753. return ret;
  2754. }
  2755. static void i965_irq_uninstall(struct drm_device * dev)
  2756. {
  2757. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2758. int pipe;
  2759. if (!dev_priv)
  2760. return;
  2761. del_timer_sync(&dev_priv->hotplug_reenable_timer);
  2762. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2763. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2764. I915_WRITE(HWSTAM, 0xffffffff);
  2765. for_each_pipe(pipe)
  2766. I915_WRITE(PIPESTAT(pipe), 0);
  2767. I915_WRITE(IMR, 0xffffffff);
  2768. I915_WRITE(IER, 0x0);
  2769. for_each_pipe(pipe)
  2770. I915_WRITE(PIPESTAT(pipe),
  2771. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2772. I915_WRITE(IIR, I915_READ(IIR));
  2773. }
  2774. static void i915_reenable_hotplug_timer_func(unsigned long data)
  2775. {
  2776. drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
  2777. struct drm_device *dev = dev_priv->dev;
  2778. struct drm_mode_config *mode_config = &dev->mode_config;
  2779. unsigned long irqflags;
  2780. int i;
  2781. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2782. for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
  2783. struct drm_connector *connector;
  2784. if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
  2785. continue;
  2786. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2787. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2788. struct intel_connector *intel_connector = to_intel_connector(connector);
  2789. if (intel_connector->encoder->hpd_pin == i) {
  2790. if (connector->polled != intel_connector->polled)
  2791. DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
  2792. drm_get_connector_name(connector));
  2793. connector->polled = intel_connector->polled;
  2794. if (!connector->polled)
  2795. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2796. }
  2797. }
  2798. }
  2799. if (dev_priv->display.hpd_irq_setup)
  2800. dev_priv->display.hpd_irq_setup(dev);
  2801. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2802. }
  2803. void intel_irq_init(struct drm_device *dev)
  2804. {
  2805. struct drm_i915_private *dev_priv = dev->dev_private;
  2806. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2807. INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
  2808. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2809. INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  2810. setup_timer(&dev_priv->gpu_error.hangcheck_timer,
  2811. i915_hangcheck_elapsed,
  2812. (unsigned long) dev);
  2813. setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
  2814. (unsigned long) dev_priv);
  2815. pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
  2816. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2817. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2818. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2819. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2820. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2821. }
  2822. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2823. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2824. else
  2825. dev->driver->get_vblank_timestamp = NULL;
  2826. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2827. if (IS_VALLEYVIEW(dev)) {
  2828. dev->driver->irq_handler = valleyview_irq_handler;
  2829. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2830. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2831. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2832. dev->driver->enable_vblank = valleyview_enable_vblank;
  2833. dev->driver->disable_vblank = valleyview_disable_vblank;
  2834. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2835. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  2836. /* Share pre & uninstall handlers with ILK/SNB */
  2837. dev->driver->irq_handler = ivybridge_irq_handler;
  2838. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2839. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2840. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2841. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2842. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2843. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2844. } else if (HAS_PCH_SPLIT(dev)) {
  2845. dev->driver->irq_handler = ironlake_irq_handler;
  2846. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2847. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2848. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2849. dev->driver->enable_vblank = ironlake_enable_vblank;
  2850. dev->driver->disable_vblank = ironlake_disable_vblank;
  2851. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2852. } else {
  2853. if (INTEL_INFO(dev)->gen == 2) {
  2854. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2855. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2856. dev->driver->irq_handler = i8xx_irq_handler;
  2857. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2858. } else if (INTEL_INFO(dev)->gen == 3) {
  2859. dev->driver->irq_preinstall = i915_irq_preinstall;
  2860. dev->driver->irq_postinstall = i915_irq_postinstall;
  2861. dev->driver->irq_uninstall = i915_irq_uninstall;
  2862. dev->driver->irq_handler = i915_irq_handler;
  2863. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2864. } else {
  2865. dev->driver->irq_preinstall = i965_irq_preinstall;
  2866. dev->driver->irq_postinstall = i965_irq_postinstall;
  2867. dev->driver->irq_uninstall = i965_irq_uninstall;
  2868. dev->driver->irq_handler = i965_irq_handler;
  2869. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2870. }
  2871. dev->driver->enable_vblank = i915_enable_vblank;
  2872. dev->driver->disable_vblank = i915_disable_vblank;
  2873. }
  2874. }
  2875. void intel_hpd_init(struct drm_device *dev)
  2876. {
  2877. struct drm_i915_private *dev_priv = dev->dev_private;
  2878. struct drm_mode_config *mode_config = &dev->mode_config;
  2879. struct drm_connector *connector;
  2880. int i;
  2881. for (i = 1; i < HPD_NUM_PINS; i++) {
  2882. dev_priv->hpd_stats[i].hpd_cnt = 0;
  2883. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2884. }
  2885. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2886. struct intel_connector *intel_connector = to_intel_connector(connector);
  2887. connector->polled = intel_connector->polled;
  2888. if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
  2889. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2890. }
  2891. if (dev_priv->display.hpd_irq_setup)
  2892. dev_priv->display.hpd_irq_setup(dev);
  2893. }