processor.h 9.2 KB

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  1. /*
  2. * include/asm-s390/processor.h
  3. *
  4. * S390 version
  5. * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
  6. * Author(s): Hartmut Penner (hp@de.ibm.com),
  7. * Martin Schwidefsky (schwidefsky@de.ibm.com)
  8. *
  9. * Derived from "include/asm-i386/processor.h"
  10. * Copyright (C) 1994, Linus Torvalds
  11. */
  12. #ifndef __ASM_S390_PROCESSOR_H
  13. #define __ASM_S390_PROCESSOR_H
  14. #include <linux/linkage.h>
  15. #include <linux/irqflags.h>
  16. #include <asm/cpu.h>
  17. #include <asm/page.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/setup.h>
  20. /*
  21. * Default implementation of macro that returns current
  22. * instruction pointer ("program counter").
  23. */
  24. #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  25. static inline void get_cpu_id(struct cpuid *ptr)
  26. {
  27. asm volatile("stidp %0" : "=Q" (*ptr));
  28. }
  29. extern void s390_adjust_jiffies(void);
  30. extern int get_cpu_capability(unsigned int *);
  31. extern const struct seq_operations cpuinfo_op;
  32. extern int sysctl_ieee_emulation_warnings;
  33. /*
  34. * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  35. */
  36. #ifndef CONFIG_64BIT
  37. #define TASK_SIZE (1UL << 31)
  38. #define TASK_UNMAPPED_BASE (1UL << 30)
  39. #else /* CONFIG_64BIT */
  40. #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
  41. #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
  42. (1UL << 30) : (1UL << 41))
  43. #define TASK_SIZE TASK_SIZE_OF(current)
  44. #endif /* CONFIG_64BIT */
  45. #ifndef CONFIG_64BIT
  46. #define STACK_TOP (1UL << 31)
  47. #define STACK_TOP_MAX (1UL << 31)
  48. #else /* CONFIG_64BIT */
  49. #define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  50. #define STACK_TOP_MAX (1UL << 42)
  51. #endif /* CONFIG_64BIT */
  52. #define HAVE_ARCH_PICK_MMAP_LAYOUT
  53. typedef struct {
  54. __u32 ar4;
  55. } mm_segment_t;
  56. /*
  57. * Thread structure
  58. */
  59. struct thread_struct {
  60. s390_fp_regs fp_regs;
  61. unsigned int acrs[NUM_ACRS];
  62. unsigned long ksp; /* kernel stack pointer */
  63. mm_segment_t mm_segment;
  64. unsigned long gmap_addr; /* address of last gmap fault. */
  65. struct per_regs per_user; /* User specified PER registers */
  66. struct per_event per_event; /* Cause of the last PER trap */
  67. /* pfault_wait is used to block the process on a pfault event */
  68. unsigned long pfault_wait;
  69. struct list_head list;
  70. };
  71. typedef struct thread_struct thread_struct;
  72. /*
  73. * Stack layout of a C stack frame.
  74. */
  75. #ifndef __PACK_STACK
  76. struct stack_frame {
  77. unsigned long back_chain;
  78. unsigned long empty1[5];
  79. unsigned long gprs[10];
  80. unsigned int empty2[8];
  81. };
  82. #else
  83. struct stack_frame {
  84. unsigned long empty1[5];
  85. unsigned int empty2[8];
  86. unsigned long gprs[10];
  87. unsigned long back_chain;
  88. };
  89. #endif
  90. #define ARCH_MIN_TASKALIGN 8
  91. #define INIT_THREAD { \
  92. .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
  93. }
  94. /*
  95. * Do necessary setup to start up a new thread.
  96. */
  97. #define start_thread(regs, new_psw, new_stackp) do { \
  98. regs->psw.mask = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA; \
  99. regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
  100. regs->gprs[15] = new_stackp; \
  101. } while (0)
  102. #define start_thread31(regs, new_psw, new_stackp) do { \
  103. regs->psw.mask = psw_user_bits | PSW_MASK_BA; \
  104. regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
  105. regs->gprs[15] = new_stackp; \
  106. crst_table_downgrade(current->mm, 1UL << 31); \
  107. } while (0)
  108. /* Forward declaration, a strange C thing */
  109. struct task_struct;
  110. struct mm_struct;
  111. struct seq_file;
  112. /* Free all resources held by a thread. */
  113. extern void release_thread(struct task_struct *);
  114. extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
  115. /* Prepare to copy thread state - unlazy all lazy status */
  116. #define prepare_to_copy(tsk) do { } while (0)
  117. /*
  118. * Return saved PC of a blocked thread.
  119. */
  120. extern unsigned long thread_saved_pc(struct task_struct *t);
  121. extern void show_code(struct pt_regs *regs);
  122. unsigned long get_wchan(struct task_struct *p);
  123. #define task_pt_regs(tsk) ((struct pt_regs *) \
  124. (task_stack_page(tsk) + THREAD_SIZE) - 1)
  125. #define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
  126. #define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
  127. static inline unsigned short stap(void)
  128. {
  129. unsigned short cpu_address;
  130. asm volatile("stap %0" : "=m" (cpu_address));
  131. return cpu_address;
  132. }
  133. /*
  134. * Give up the time slice of the virtual PU.
  135. */
  136. static inline void cpu_relax(void)
  137. {
  138. if (MACHINE_HAS_DIAG44)
  139. asm volatile("diag 0,0,68");
  140. barrier();
  141. }
  142. static inline void psw_set_key(unsigned int key)
  143. {
  144. asm volatile("spka 0(%0)" : : "d" (key));
  145. }
  146. /*
  147. * Set PSW to specified value.
  148. */
  149. static inline void __load_psw(psw_t psw)
  150. {
  151. #ifndef CONFIG_64BIT
  152. asm volatile("lpsw %0" : : "Q" (psw) : "cc");
  153. #else
  154. asm volatile("lpswe %0" : : "Q" (psw) : "cc");
  155. #endif
  156. }
  157. /*
  158. * Set PSW mask to specified value, while leaving the
  159. * PSW addr pointing to the next instruction.
  160. */
  161. static inline void __load_psw_mask (unsigned long mask)
  162. {
  163. unsigned long addr;
  164. psw_t psw;
  165. psw.mask = mask;
  166. #ifndef CONFIG_64BIT
  167. asm volatile(
  168. " basr %0,0\n"
  169. "0: ahi %0,1f-0b\n"
  170. " st %0,%O1+4(%R1)\n"
  171. " lpsw %1\n"
  172. "1:"
  173. : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
  174. #else /* CONFIG_64BIT */
  175. asm volatile(
  176. " larl %0,1f\n"
  177. " stg %0,%O1+8(%R1)\n"
  178. " lpswe %1\n"
  179. "1:"
  180. : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
  181. #endif /* CONFIG_64BIT */
  182. }
  183. /*
  184. * Rewind PSW instruction address by specified number of bytes.
  185. */
  186. static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
  187. {
  188. #ifndef CONFIG_64BIT
  189. if (psw.addr & PSW_ADDR_AMODE)
  190. /* 31 bit mode */
  191. return (psw.addr - ilc) | PSW_ADDR_AMODE;
  192. /* 24 bit mode */
  193. return (psw.addr - ilc) & ((1UL << 24) - 1);
  194. #else
  195. unsigned long mask;
  196. mask = (psw.mask & PSW_MASK_EA) ? -1UL :
  197. (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
  198. (1UL << 24) - 1;
  199. return (psw.addr - ilc) & mask;
  200. #endif
  201. }
  202. /*
  203. * Function to drop a processor into disabled wait state
  204. */
  205. static inline void __noreturn disabled_wait(unsigned long code)
  206. {
  207. unsigned long ctl_buf;
  208. psw_t dw_psw;
  209. dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
  210. dw_psw.addr = code;
  211. /*
  212. * Store status and then load disabled wait psw,
  213. * the processor is dead afterwards
  214. */
  215. #ifndef CONFIG_64BIT
  216. asm volatile(
  217. " stctl 0,0,0(%2)\n"
  218. " ni 0(%2),0xef\n" /* switch off protection */
  219. " lctl 0,0,0(%2)\n"
  220. " stpt 0xd8\n" /* store timer */
  221. " stckc 0xe0\n" /* store clock comparator */
  222. " stpx 0x108\n" /* store prefix register */
  223. " stam 0,15,0x120\n" /* store access registers */
  224. " std 0,0x160\n" /* store f0 */
  225. " std 2,0x168\n" /* store f2 */
  226. " std 4,0x170\n" /* store f4 */
  227. " std 6,0x178\n" /* store f6 */
  228. " stm 0,15,0x180\n" /* store general registers */
  229. " stctl 0,15,0x1c0\n" /* store control registers */
  230. " oi 0x1c0,0x10\n" /* fake protection bit */
  231. " lpsw 0(%1)"
  232. : "=m" (ctl_buf)
  233. : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
  234. #else /* CONFIG_64BIT */
  235. asm volatile(
  236. " stctg 0,0,0(%2)\n"
  237. " ni 4(%2),0xef\n" /* switch off protection */
  238. " lctlg 0,0,0(%2)\n"
  239. " lghi 1,0x1000\n"
  240. " stpt 0x328(1)\n" /* store timer */
  241. " stckc 0x330(1)\n" /* store clock comparator */
  242. " stpx 0x318(1)\n" /* store prefix register */
  243. " stam 0,15,0x340(1)\n"/* store access registers */
  244. " stfpc 0x31c(1)\n" /* store fpu control */
  245. " std 0,0x200(1)\n" /* store f0 */
  246. " std 1,0x208(1)\n" /* store f1 */
  247. " std 2,0x210(1)\n" /* store f2 */
  248. " std 3,0x218(1)\n" /* store f3 */
  249. " std 4,0x220(1)\n" /* store f4 */
  250. " std 5,0x228(1)\n" /* store f5 */
  251. " std 6,0x230(1)\n" /* store f6 */
  252. " std 7,0x238(1)\n" /* store f7 */
  253. " std 8,0x240(1)\n" /* store f8 */
  254. " std 9,0x248(1)\n" /* store f9 */
  255. " std 10,0x250(1)\n" /* store f10 */
  256. " std 11,0x258(1)\n" /* store f11 */
  257. " std 12,0x260(1)\n" /* store f12 */
  258. " std 13,0x268(1)\n" /* store f13 */
  259. " std 14,0x270(1)\n" /* store f14 */
  260. " std 15,0x278(1)\n" /* store f15 */
  261. " stmg 0,15,0x280(1)\n"/* store general registers */
  262. " stctg 0,15,0x380(1)\n"/* store control registers */
  263. " oi 0x384(1),0x10\n"/* fake protection bit */
  264. " lpswe 0(%1)"
  265. : "=m" (ctl_buf)
  266. : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
  267. #endif /* CONFIG_64BIT */
  268. while (1);
  269. }
  270. /*
  271. * Use to set psw mask except for the first byte which
  272. * won't be changed by this function.
  273. */
  274. static inline void
  275. __set_psw_mask(unsigned long mask)
  276. {
  277. __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
  278. }
  279. #define local_mcck_enable() \
  280. __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
  281. #define local_mcck_disable() \
  282. __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)
  283. /*
  284. * Basic Machine Check/Program Check Handler.
  285. */
  286. extern void s390_base_mcck_handler(void);
  287. extern void s390_base_pgm_handler(void);
  288. extern void s390_base_ext_handler(void);
  289. extern void (*s390_base_mcck_handler_fn)(void);
  290. extern void (*s390_base_pgm_handler_fn)(void);
  291. extern void (*s390_base_ext_handler_fn)(void);
  292. #define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
  293. /*
  294. * Helper macro for exception table entries
  295. */
  296. #ifndef CONFIG_64BIT
  297. #define EX_TABLE(_fault,_target) \
  298. ".section __ex_table,\"a\"\n" \
  299. " .align 4\n" \
  300. " .long " #_fault "," #_target "\n" \
  301. ".previous\n"
  302. #else
  303. #define EX_TABLE(_fault,_target) \
  304. ".section __ex_table,\"a\"\n" \
  305. " .align 8\n" \
  306. " .quad " #_fault "," #_target "\n" \
  307. ".previous\n"
  308. #endif
  309. #endif /* __ASM_S390_PROCESSOR_H */