apply.c 33 KB

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  1. /*
  2. * Copyright (C) 2011 Texas Instruments
  3. * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #define DSS_SUBSYS_NAME "APPLY"
  18. #include <linux/kernel.h>
  19. #include <linux/slab.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/jiffies.h>
  22. #include <video/omapdss.h>
  23. #include "dss.h"
  24. #include "dss_features.h"
  25. /*
  26. * We have 4 levels of cache for the dispc settings. First two are in SW and
  27. * the latter two in HW.
  28. *
  29. * set_info()
  30. * v
  31. * +--------------------+
  32. * | user_info |
  33. * +--------------------+
  34. * v
  35. * apply()
  36. * v
  37. * +--------------------+
  38. * | info |
  39. * +--------------------+
  40. * v
  41. * write_regs()
  42. * v
  43. * +--------------------+
  44. * | shadow registers |
  45. * +--------------------+
  46. * v
  47. * VFP or lcd/digit_enable
  48. * v
  49. * +--------------------+
  50. * | registers |
  51. * +--------------------+
  52. */
  53. struct ovl_priv_data {
  54. bool user_info_dirty;
  55. struct omap_overlay_info user_info;
  56. bool info_dirty;
  57. struct omap_overlay_info info;
  58. bool shadow_info_dirty;
  59. bool extra_info_dirty;
  60. bool shadow_extra_info_dirty;
  61. bool enabled;
  62. enum omap_channel channel;
  63. u32 fifo_low, fifo_high;
  64. /*
  65. * True if overlay is to be enabled. Used to check and calculate configs
  66. * for the overlay before it is enabled in the HW.
  67. */
  68. bool enabling;
  69. };
  70. struct mgr_priv_data {
  71. bool user_info_dirty;
  72. struct omap_overlay_manager_info user_info;
  73. bool info_dirty;
  74. struct omap_overlay_manager_info info;
  75. bool shadow_info_dirty;
  76. /* If true, GO bit is up and shadow registers cannot be written.
  77. * Never true for manual update displays */
  78. bool busy;
  79. /* If true, dispc output is enabled */
  80. bool updating;
  81. /* If true, a display is enabled using this manager */
  82. bool enabled;
  83. bool extra_info_dirty;
  84. bool shadow_extra_info_dirty;
  85. struct omap_video_timings timings;
  86. struct dss_lcd_mgr_config lcd_config;
  87. };
  88. static struct {
  89. struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
  90. struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
  91. bool fifo_merge_dirty;
  92. bool fifo_merge;
  93. bool irq_enabled;
  94. } dss_data;
  95. /* protects dss_data */
  96. static spinlock_t data_lock;
  97. /* lock for blocking functions */
  98. static DEFINE_MUTEX(apply_lock);
  99. static DECLARE_COMPLETION(extra_updated_completion);
  100. static void dss_register_vsync_isr(void);
  101. static struct ovl_priv_data *get_ovl_priv(struct omap_overlay *ovl)
  102. {
  103. return &dss_data.ovl_priv_data_array[ovl->id];
  104. }
  105. static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr)
  106. {
  107. return &dss_data.mgr_priv_data_array[mgr->id];
  108. }
  109. void dss_apply_init(void)
  110. {
  111. const int num_ovls = dss_feat_get_num_ovls();
  112. struct mgr_priv_data *mp;
  113. int i;
  114. spin_lock_init(&data_lock);
  115. for (i = 0; i < num_ovls; ++i) {
  116. struct ovl_priv_data *op;
  117. op = &dss_data.ovl_priv_data_array[i];
  118. op->info.global_alpha = 255;
  119. switch (i) {
  120. case 0:
  121. op->info.zorder = 0;
  122. break;
  123. case 1:
  124. op->info.zorder =
  125. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 3 : 0;
  126. break;
  127. case 2:
  128. op->info.zorder =
  129. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 2 : 0;
  130. break;
  131. case 3:
  132. op->info.zorder =
  133. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 1 : 0;
  134. break;
  135. }
  136. op->user_info = op->info;
  137. }
  138. /*
  139. * Initialize some of the lcd_config fields for TV manager, this lets
  140. * us prevent checking if the manager is LCD or TV at some places
  141. */
  142. mp = &dss_data.mgr_priv_data_array[OMAP_DSS_CHANNEL_DIGIT];
  143. mp->lcd_config.video_port_width = 24;
  144. mp->lcd_config.clock_info.lck_div = 1;
  145. mp->lcd_config.clock_info.pck_div = 1;
  146. }
  147. static bool ovl_manual_update(struct omap_overlay *ovl)
  148. {
  149. return ovl->manager->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
  150. }
  151. static bool mgr_manual_update(struct omap_overlay_manager *mgr)
  152. {
  153. return mgr->device->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE;
  154. }
  155. static int dss_check_settings_low(struct omap_overlay_manager *mgr,
  156. bool applying)
  157. {
  158. struct omap_overlay_info *oi;
  159. struct omap_overlay_manager_info *mi;
  160. struct omap_overlay *ovl;
  161. struct omap_overlay_info *ois[MAX_DSS_OVERLAYS];
  162. struct ovl_priv_data *op;
  163. struct mgr_priv_data *mp;
  164. mp = get_mgr_priv(mgr);
  165. if (!mp->enabled)
  166. return 0;
  167. if (applying && mp->user_info_dirty)
  168. mi = &mp->user_info;
  169. else
  170. mi = &mp->info;
  171. /* collect the infos to be tested into the array */
  172. list_for_each_entry(ovl, &mgr->overlays, list) {
  173. op = get_ovl_priv(ovl);
  174. if (!op->enabled && !op->enabling)
  175. oi = NULL;
  176. else if (applying && op->user_info_dirty)
  177. oi = &op->user_info;
  178. else
  179. oi = &op->info;
  180. ois[ovl->id] = oi;
  181. }
  182. return dss_mgr_check(mgr, mi, &mp->timings, ois);
  183. }
  184. /*
  185. * check manager and overlay settings using overlay_info from data->info
  186. */
  187. static int dss_check_settings(struct omap_overlay_manager *mgr)
  188. {
  189. return dss_check_settings_low(mgr, false);
  190. }
  191. /*
  192. * check manager and overlay settings using overlay_info from ovl->info if
  193. * dirty and from data->info otherwise
  194. */
  195. static int dss_check_settings_apply(struct omap_overlay_manager *mgr)
  196. {
  197. return dss_check_settings_low(mgr, true);
  198. }
  199. static bool need_isr(void)
  200. {
  201. const int num_mgrs = dss_feat_get_num_mgrs();
  202. int i;
  203. for (i = 0; i < num_mgrs; ++i) {
  204. struct omap_overlay_manager *mgr;
  205. struct mgr_priv_data *mp;
  206. struct omap_overlay *ovl;
  207. mgr = omap_dss_get_overlay_manager(i);
  208. mp = get_mgr_priv(mgr);
  209. if (!mp->enabled)
  210. continue;
  211. if (mgr_manual_update(mgr)) {
  212. /* to catch FRAMEDONE */
  213. if (mp->updating)
  214. return true;
  215. } else {
  216. /* to catch GO bit going down */
  217. if (mp->busy)
  218. return true;
  219. /* to write new values to registers */
  220. if (mp->info_dirty)
  221. return true;
  222. /* to set GO bit */
  223. if (mp->shadow_info_dirty)
  224. return true;
  225. /*
  226. * NOTE: we don't check extra_info flags for disabled
  227. * managers, once the manager is enabled, the extra_info
  228. * related manager changes will be taken in by HW.
  229. */
  230. /* to write new values to registers */
  231. if (mp->extra_info_dirty)
  232. return true;
  233. /* to set GO bit */
  234. if (mp->shadow_extra_info_dirty)
  235. return true;
  236. list_for_each_entry(ovl, &mgr->overlays, list) {
  237. struct ovl_priv_data *op;
  238. op = get_ovl_priv(ovl);
  239. /*
  240. * NOTE: we check extra_info flags even for
  241. * disabled overlays, as extra_infos need to be
  242. * always written.
  243. */
  244. /* to write new values to registers */
  245. if (op->extra_info_dirty)
  246. return true;
  247. /* to set GO bit */
  248. if (op->shadow_extra_info_dirty)
  249. return true;
  250. if (!op->enabled)
  251. continue;
  252. /* to write new values to registers */
  253. if (op->info_dirty)
  254. return true;
  255. /* to set GO bit */
  256. if (op->shadow_info_dirty)
  257. return true;
  258. }
  259. }
  260. }
  261. return false;
  262. }
  263. static bool need_go(struct omap_overlay_manager *mgr)
  264. {
  265. struct omap_overlay *ovl;
  266. struct mgr_priv_data *mp;
  267. struct ovl_priv_data *op;
  268. mp = get_mgr_priv(mgr);
  269. if (mp->shadow_info_dirty || mp->shadow_extra_info_dirty)
  270. return true;
  271. list_for_each_entry(ovl, &mgr->overlays, list) {
  272. op = get_ovl_priv(ovl);
  273. if (op->shadow_info_dirty || op->shadow_extra_info_dirty)
  274. return true;
  275. }
  276. return false;
  277. }
  278. /* returns true if an extra_info field is currently being updated */
  279. static bool extra_info_update_ongoing(void)
  280. {
  281. const int num_mgrs = dss_feat_get_num_mgrs();
  282. int i;
  283. for (i = 0; i < num_mgrs; ++i) {
  284. struct omap_overlay_manager *mgr;
  285. struct omap_overlay *ovl;
  286. struct mgr_priv_data *mp;
  287. mgr = omap_dss_get_overlay_manager(i);
  288. mp = get_mgr_priv(mgr);
  289. if (!mp->enabled)
  290. continue;
  291. if (!mp->updating)
  292. continue;
  293. if (mp->extra_info_dirty || mp->shadow_extra_info_dirty)
  294. return true;
  295. list_for_each_entry(ovl, &mgr->overlays, list) {
  296. struct ovl_priv_data *op = get_ovl_priv(ovl);
  297. if (op->extra_info_dirty || op->shadow_extra_info_dirty)
  298. return true;
  299. }
  300. }
  301. return false;
  302. }
  303. /* wait until no extra_info updates are pending */
  304. static void wait_pending_extra_info_updates(void)
  305. {
  306. bool updating;
  307. unsigned long flags;
  308. unsigned long t;
  309. int r;
  310. spin_lock_irqsave(&data_lock, flags);
  311. updating = extra_info_update_ongoing();
  312. if (!updating) {
  313. spin_unlock_irqrestore(&data_lock, flags);
  314. return;
  315. }
  316. init_completion(&extra_updated_completion);
  317. spin_unlock_irqrestore(&data_lock, flags);
  318. t = msecs_to_jiffies(500);
  319. r = wait_for_completion_timeout(&extra_updated_completion, t);
  320. if (r == 0)
  321. DSSWARN("timeout in wait_pending_extra_info_updates\n");
  322. else if (r < 0)
  323. DSSERR("wait_pending_extra_info_updates failed: %d\n", r);
  324. }
  325. int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
  326. {
  327. unsigned long timeout = msecs_to_jiffies(500);
  328. struct mgr_priv_data *mp;
  329. u32 irq;
  330. int r;
  331. int i;
  332. struct omap_dss_device *dssdev = mgr->device;
  333. if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
  334. return 0;
  335. if (mgr_manual_update(mgr))
  336. return 0;
  337. r = dispc_runtime_get();
  338. if (r)
  339. return r;
  340. irq = dispc_mgr_get_vsync_irq(mgr->id);
  341. mp = get_mgr_priv(mgr);
  342. i = 0;
  343. while (1) {
  344. unsigned long flags;
  345. bool shadow_dirty, dirty;
  346. spin_lock_irqsave(&data_lock, flags);
  347. dirty = mp->info_dirty;
  348. shadow_dirty = mp->shadow_info_dirty;
  349. spin_unlock_irqrestore(&data_lock, flags);
  350. if (!dirty && !shadow_dirty) {
  351. r = 0;
  352. break;
  353. }
  354. /* 4 iterations is the worst case:
  355. * 1 - initial iteration, dirty = true (between VFP and VSYNC)
  356. * 2 - first VSYNC, dirty = true
  357. * 3 - dirty = false, shadow_dirty = true
  358. * 4 - shadow_dirty = false */
  359. if (i++ == 3) {
  360. DSSERR("mgr(%d)->wait_for_go() not finishing\n",
  361. mgr->id);
  362. r = 0;
  363. break;
  364. }
  365. r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
  366. if (r == -ERESTARTSYS)
  367. break;
  368. if (r) {
  369. DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id);
  370. break;
  371. }
  372. }
  373. dispc_runtime_put();
  374. return r;
  375. }
  376. int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
  377. {
  378. unsigned long timeout = msecs_to_jiffies(500);
  379. struct ovl_priv_data *op;
  380. struct omap_dss_device *dssdev;
  381. u32 irq;
  382. int r;
  383. int i;
  384. if (!ovl->manager)
  385. return 0;
  386. dssdev = ovl->manager->device;
  387. if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
  388. return 0;
  389. if (ovl_manual_update(ovl))
  390. return 0;
  391. r = dispc_runtime_get();
  392. if (r)
  393. return r;
  394. irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
  395. op = get_ovl_priv(ovl);
  396. i = 0;
  397. while (1) {
  398. unsigned long flags;
  399. bool shadow_dirty, dirty;
  400. spin_lock_irqsave(&data_lock, flags);
  401. dirty = op->info_dirty;
  402. shadow_dirty = op->shadow_info_dirty;
  403. spin_unlock_irqrestore(&data_lock, flags);
  404. if (!dirty && !shadow_dirty) {
  405. r = 0;
  406. break;
  407. }
  408. /* 4 iterations is the worst case:
  409. * 1 - initial iteration, dirty = true (between VFP and VSYNC)
  410. * 2 - first VSYNC, dirty = true
  411. * 3 - dirty = false, shadow_dirty = true
  412. * 4 - shadow_dirty = false */
  413. if (i++ == 3) {
  414. DSSERR("ovl(%d)->wait_for_go() not finishing\n",
  415. ovl->id);
  416. r = 0;
  417. break;
  418. }
  419. r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
  420. if (r == -ERESTARTSYS)
  421. break;
  422. if (r) {
  423. DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id);
  424. break;
  425. }
  426. }
  427. dispc_runtime_put();
  428. return r;
  429. }
  430. static void dss_ovl_write_regs(struct omap_overlay *ovl)
  431. {
  432. struct ovl_priv_data *op = get_ovl_priv(ovl);
  433. struct omap_overlay_info *oi;
  434. bool replication;
  435. struct mgr_priv_data *mp;
  436. int r;
  437. DSSDBGF("%d", ovl->id);
  438. if (!op->enabled || !op->info_dirty)
  439. return;
  440. oi = &op->info;
  441. mp = get_mgr_priv(ovl->manager);
  442. replication = dss_use_replication(ovl->manager->device, oi->color_mode);
  443. r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings);
  444. if (r) {
  445. /*
  446. * We can't do much here, as this function can be called from
  447. * vsync interrupt.
  448. */
  449. DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id);
  450. /* This will leave fifo configurations in a nonoptimal state */
  451. op->enabled = false;
  452. dispc_ovl_enable(ovl->id, false);
  453. return;
  454. }
  455. op->info_dirty = false;
  456. if (mp->updating)
  457. op->shadow_info_dirty = true;
  458. }
  459. static void dss_ovl_write_regs_extra(struct omap_overlay *ovl)
  460. {
  461. struct ovl_priv_data *op = get_ovl_priv(ovl);
  462. struct mgr_priv_data *mp;
  463. DSSDBGF("%d", ovl->id);
  464. if (!op->extra_info_dirty)
  465. return;
  466. /* note: write also when op->enabled == false, so that the ovl gets
  467. * disabled */
  468. dispc_ovl_enable(ovl->id, op->enabled);
  469. dispc_ovl_set_channel_out(ovl->id, op->channel);
  470. dispc_ovl_set_fifo_threshold(ovl->id, op->fifo_low, op->fifo_high);
  471. mp = get_mgr_priv(ovl->manager);
  472. op->extra_info_dirty = false;
  473. if (mp->updating)
  474. op->shadow_extra_info_dirty = true;
  475. }
  476. static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
  477. {
  478. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  479. struct omap_overlay *ovl;
  480. DSSDBGF("%d", mgr->id);
  481. if (!mp->enabled)
  482. return;
  483. WARN_ON(mp->busy);
  484. /* Commit overlay settings */
  485. list_for_each_entry(ovl, &mgr->overlays, list) {
  486. dss_ovl_write_regs(ovl);
  487. dss_ovl_write_regs_extra(ovl);
  488. }
  489. if (mp->info_dirty) {
  490. dispc_mgr_setup(mgr->id, &mp->info);
  491. mp->info_dirty = false;
  492. if (mp->updating)
  493. mp->shadow_info_dirty = true;
  494. }
  495. }
  496. static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
  497. {
  498. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  499. DSSDBGF("%d", mgr->id);
  500. if (!mp->extra_info_dirty)
  501. return;
  502. dispc_mgr_set_timings(mgr->id, &mp->timings);
  503. /* lcd_config parameters */
  504. if (dss_mgr_is_lcd(mgr->id)) {
  505. dispc_mgr_set_io_pad_mode(mp->lcd_config.io_pad_mode);
  506. dispc_mgr_enable_stallmode(mgr->id, mp->lcd_config.stallmode);
  507. dispc_mgr_enable_fifohandcheck(mgr->id,
  508. mp->lcd_config.fifohandcheck);
  509. dispc_mgr_set_clock_div(mgr->id, &mp->lcd_config.clock_info);
  510. dispc_mgr_set_tft_data_lines(mgr->id,
  511. mp->lcd_config.video_port_width);
  512. dispc_lcd_enable_signal_polarity(mp->lcd_config.lcden_sig_polarity);
  513. dispc_mgr_set_lcd_type_tft(mgr->id);
  514. }
  515. mp->extra_info_dirty = false;
  516. if (mp->updating)
  517. mp->shadow_extra_info_dirty = true;
  518. }
  519. static void dss_write_regs_common(void)
  520. {
  521. const int num_mgrs = omap_dss_get_num_overlay_managers();
  522. int i;
  523. if (!dss_data.fifo_merge_dirty)
  524. return;
  525. for (i = 0; i < num_mgrs; ++i) {
  526. struct omap_overlay_manager *mgr;
  527. struct mgr_priv_data *mp;
  528. mgr = omap_dss_get_overlay_manager(i);
  529. mp = get_mgr_priv(mgr);
  530. if (mp->enabled) {
  531. if (dss_data.fifo_merge_dirty) {
  532. dispc_enable_fifomerge(dss_data.fifo_merge);
  533. dss_data.fifo_merge_dirty = false;
  534. }
  535. if (mp->updating)
  536. mp->shadow_info_dirty = true;
  537. }
  538. }
  539. }
  540. static void dss_write_regs(void)
  541. {
  542. const int num_mgrs = omap_dss_get_num_overlay_managers();
  543. int i;
  544. dss_write_regs_common();
  545. for (i = 0; i < num_mgrs; ++i) {
  546. struct omap_overlay_manager *mgr;
  547. struct mgr_priv_data *mp;
  548. int r;
  549. mgr = omap_dss_get_overlay_manager(i);
  550. mp = get_mgr_priv(mgr);
  551. if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
  552. continue;
  553. r = dss_check_settings(mgr);
  554. if (r) {
  555. DSSERR("cannot write registers for manager %s: "
  556. "illegal configuration\n", mgr->name);
  557. continue;
  558. }
  559. dss_mgr_write_regs(mgr);
  560. dss_mgr_write_regs_extra(mgr);
  561. }
  562. }
  563. static void dss_set_go_bits(void)
  564. {
  565. const int num_mgrs = omap_dss_get_num_overlay_managers();
  566. int i;
  567. for (i = 0; i < num_mgrs; ++i) {
  568. struct omap_overlay_manager *mgr;
  569. struct mgr_priv_data *mp;
  570. mgr = omap_dss_get_overlay_manager(i);
  571. mp = get_mgr_priv(mgr);
  572. if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
  573. continue;
  574. if (!need_go(mgr))
  575. continue;
  576. mp->busy = true;
  577. if (!dss_data.irq_enabled && need_isr())
  578. dss_register_vsync_isr();
  579. dispc_mgr_go(mgr->id);
  580. }
  581. }
  582. static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
  583. {
  584. struct omap_overlay *ovl;
  585. struct mgr_priv_data *mp;
  586. struct ovl_priv_data *op;
  587. mp = get_mgr_priv(mgr);
  588. mp->shadow_info_dirty = false;
  589. mp->shadow_extra_info_dirty = false;
  590. list_for_each_entry(ovl, &mgr->overlays, list) {
  591. op = get_ovl_priv(ovl);
  592. op->shadow_info_dirty = false;
  593. op->shadow_extra_info_dirty = false;
  594. }
  595. }
  596. void dss_mgr_start_update(struct omap_overlay_manager *mgr)
  597. {
  598. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  599. unsigned long flags;
  600. int r;
  601. spin_lock_irqsave(&data_lock, flags);
  602. WARN_ON(mp->updating);
  603. r = dss_check_settings(mgr);
  604. if (r) {
  605. DSSERR("cannot start manual update: illegal configuration\n");
  606. spin_unlock_irqrestore(&data_lock, flags);
  607. return;
  608. }
  609. dss_mgr_write_regs(mgr);
  610. dss_mgr_write_regs_extra(mgr);
  611. dss_write_regs_common();
  612. mp->updating = true;
  613. if (!dss_data.irq_enabled && need_isr())
  614. dss_register_vsync_isr();
  615. dispc_mgr_enable(mgr->id, true);
  616. mgr_clear_shadow_dirty(mgr);
  617. spin_unlock_irqrestore(&data_lock, flags);
  618. }
  619. static void dss_apply_irq_handler(void *data, u32 mask);
  620. static void dss_register_vsync_isr(void)
  621. {
  622. const int num_mgrs = dss_feat_get_num_mgrs();
  623. u32 mask;
  624. int r, i;
  625. mask = 0;
  626. for (i = 0; i < num_mgrs; ++i)
  627. mask |= dispc_mgr_get_vsync_irq(i);
  628. for (i = 0; i < num_mgrs; ++i)
  629. mask |= dispc_mgr_get_framedone_irq(i);
  630. r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
  631. WARN_ON(r);
  632. dss_data.irq_enabled = true;
  633. }
  634. static void dss_unregister_vsync_isr(void)
  635. {
  636. const int num_mgrs = dss_feat_get_num_mgrs();
  637. u32 mask;
  638. int r, i;
  639. mask = 0;
  640. for (i = 0; i < num_mgrs; ++i)
  641. mask |= dispc_mgr_get_vsync_irq(i);
  642. for (i = 0; i < num_mgrs; ++i)
  643. mask |= dispc_mgr_get_framedone_irq(i);
  644. r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask);
  645. WARN_ON(r);
  646. dss_data.irq_enabled = false;
  647. }
  648. static void dss_apply_irq_handler(void *data, u32 mask)
  649. {
  650. const int num_mgrs = dss_feat_get_num_mgrs();
  651. int i;
  652. bool extra_updating;
  653. spin_lock(&data_lock);
  654. /* clear busy, updating flags, shadow_dirty flags */
  655. for (i = 0; i < num_mgrs; i++) {
  656. struct omap_overlay_manager *mgr;
  657. struct mgr_priv_data *mp;
  658. bool was_updating;
  659. mgr = omap_dss_get_overlay_manager(i);
  660. mp = get_mgr_priv(mgr);
  661. if (!mp->enabled)
  662. continue;
  663. was_updating = mp->updating;
  664. mp->updating = dispc_mgr_is_enabled(i);
  665. if (!mgr_manual_update(mgr)) {
  666. bool was_busy = mp->busy;
  667. mp->busy = dispc_mgr_go_busy(i);
  668. if (was_busy && !mp->busy)
  669. mgr_clear_shadow_dirty(mgr);
  670. }
  671. }
  672. dss_write_regs();
  673. dss_set_go_bits();
  674. extra_updating = extra_info_update_ongoing();
  675. if (!extra_updating)
  676. complete_all(&extra_updated_completion);
  677. if (!need_isr())
  678. dss_unregister_vsync_isr();
  679. spin_unlock(&data_lock);
  680. }
  681. static void omap_dss_mgr_apply_ovl(struct omap_overlay *ovl)
  682. {
  683. struct ovl_priv_data *op;
  684. op = get_ovl_priv(ovl);
  685. if (!op->user_info_dirty)
  686. return;
  687. op->user_info_dirty = false;
  688. op->info_dirty = true;
  689. op->info = op->user_info;
  690. }
  691. static void omap_dss_mgr_apply_mgr(struct omap_overlay_manager *mgr)
  692. {
  693. struct mgr_priv_data *mp;
  694. mp = get_mgr_priv(mgr);
  695. if (!mp->user_info_dirty)
  696. return;
  697. mp->user_info_dirty = false;
  698. mp->info_dirty = true;
  699. mp->info = mp->user_info;
  700. }
  701. int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
  702. {
  703. unsigned long flags;
  704. struct omap_overlay *ovl;
  705. int r;
  706. DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
  707. spin_lock_irqsave(&data_lock, flags);
  708. r = dss_check_settings_apply(mgr);
  709. if (r) {
  710. spin_unlock_irqrestore(&data_lock, flags);
  711. DSSERR("failed to apply settings: illegal configuration.\n");
  712. return r;
  713. }
  714. /* Configure overlays */
  715. list_for_each_entry(ovl, &mgr->overlays, list)
  716. omap_dss_mgr_apply_ovl(ovl);
  717. /* Configure manager */
  718. omap_dss_mgr_apply_mgr(mgr);
  719. dss_write_regs();
  720. dss_set_go_bits();
  721. spin_unlock_irqrestore(&data_lock, flags);
  722. return 0;
  723. }
  724. static void dss_apply_ovl_enable(struct omap_overlay *ovl, bool enable)
  725. {
  726. struct ovl_priv_data *op;
  727. op = get_ovl_priv(ovl);
  728. if (op->enabled == enable)
  729. return;
  730. op->enabled = enable;
  731. op->extra_info_dirty = true;
  732. }
  733. static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
  734. u32 fifo_low, u32 fifo_high)
  735. {
  736. struct ovl_priv_data *op = get_ovl_priv(ovl);
  737. if (op->fifo_low == fifo_low && op->fifo_high == fifo_high)
  738. return;
  739. op->fifo_low = fifo_low;
  740. op->fifo_high = fifo_high;
  741. op->extra_info_dirty = true;
  742. }
  743. static void dss_apply_fifo_merge(bool use_fifo_merge)
  744. {
  745. if (dss_data.fifo_merge == use_fifo_merge)
  746. return;
  747. dss_data.fifo_merge = use_fifo_merge;
  748. dss_data.fifo_merge_dirty = true;
  749. }
  750. static void dss_ovl_setup_fifo(struct omap_overlay *ovl,
  751. bool use_fifo_merge)
  752. {
  753. struct ovl_priv_data *op = get_ovl_priv(ovl);
  754. u32 fifo_low, fifo_high;
  755. if (!op->enabled && !op->enabling)
  756. return;
  757. dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
  758. use_fifo_merge, ovl_manual_update(ovl));
  759. dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
  760. }
  761. static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr,
  762. bool use_fifo_merge)
  763. {
  764. struct omap_overlay *ovl;
  765. struct mgr_priv_data *mp;
  766. mp = get_mgr_priv(mgr);
  767. if (!mp->enabled)
  768. return;
  769. list_for_each_entry(ovl, &mgr->overlays, list)
  770. dss_ovl_setup_fifo(ovl, use_fifo_merge);
  771. }
  772. static void dss_setup_fifos(bool use_fifo_merge)
  773. {
  774. const int num_mgrs = omap_dss_get_num_overlay_managers();
  775. struct omap_overlay_manager *mgr;
  776. int i;
  777. for (i = 0; i < num_mgrs; ++i) {
  778. mgr = omap_dss_get_overlay_manager(i);
  779. dss_mgr_setup_fifos(mgr, use_fifo_merge);
  780. }
  781. }
  782. static int get_num_used_managers(void)
  783. {
  784. const int num_mgrs = omap_dss_get_num_overlay_managers();
  785. struct omap_overlay_manager *mgr;
  786. struct mgr_priv_data *mp;
  787. int i;
  788. int enabled_mgrs;
  789. enabled_mgrs = 0;
  790. for (i = 0; i < num_mgrs; ++i) {
  791. mgr = omap_dss_get_overlay_manager(i);
  792. mp = get_mgr_priv(mgr);
  793. if (!mp->enabled)
  794. continue;
  795. enabled_mgrs++;
  796. }
  797. return enabled_mgrs;
  798. }
  799. static int get_num_used_overlays(void)
  800. {
  801. const int num_ovls = omap_dss_get_num_overlays();
  802. struct omap_overlay *ovl;
  803. struct ovl_priv_data *op;
  804. struct mgr_priv_data *mp;
  805. int i;
  806. int enabled_ovls;
  807. enabled_ovls = 0;
  808. for (i = 0; i < num_ovls; ++i) {
  809. ovl = omap_dss_get_overlay(i);
  810. op = get_ovl_priv(ovl);
  811. if (!op->enabled && !op->enabling)
  812. continue;
  813. mp = get_mgr_priv(ovl->manager);
  814. if (!mp->enabled)
  815. continue;
  816. enabled_ovls++;
  817. }
  818. return enabled_ovls;
  819. }
  820. static bool get_use_fifo_merge(void)
  821. {
  822. int enabled_mgrs = get_num_used_managers();
  823. int enabled_ovls = get_num_used_overlays();
  824. if (!dss_has_feature(FEAT_FIFO_MERGE))
  825. return false;
  826. /*
  827. * In theory the only requirement for fifomerge is enabled_ovls <= 1.
  828. * However, if we have two managers enabled and set/unset the fifomerge,
  829. * we need to set the GO bits in particular sequence for the managers,
  830. * and wait in between.
  831. *
  832. * This is rather difficult as new apply calls can happen at any time,
  833. * so we simplify the problem by requiring also that enabled_mgrs <= 1.
  834. * In practice this shouldn't matter, because when only one overlay is
  835. * enabled, most likely only one output is enabled.
  836. */
  837. return enabled_mgrs <= 1 && enabled_ovls <= 1;
  838. }
  839. int dss_mgr_enable(struct omap_overlay_manager *mgr)
  840. {
  841. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  842. unsigned long flags;
  843. int r;
  844. bool fifo_merge;
  845. mutex_lock(&apply_lock);
  846. if (mp->enabled)
  847. goto out;
  848. spin_lock_irqsave(&data_lock, flags);
  849. mp->enabled = true;
  850. r = dss_check_settings(mgr);
  851. if (r) {
  852. DSSERR("failed to enable manager %d: check_settings failed\n",
  853. mgr->id);
  854. goto err;
  855. }
  856. /* step 1: setup fifos/fifomerge before enabling the manager */
  857. fifo_merge = get_use_fifo_merge();
  858. dss_setup_fifos(fifo_merge);
  859. dss_apply_fifo_merge(fifo_merge);
  860. dss_write_regs();
  861. dss_set_go_bits();
  862. spin_unlock_irqrestore(&data_lock, flags);
  863. /* wait until fifo config is in */
  864. wait_pending_extra_info_updates();
  865. /* step 2: enable the manager */
  866. spin_lock_irqsave(&data_lock, flags);
  867. if (!mgr_manual_update(mgr))
  868. mp->updating = true;
  869. spin_unlock_irqrestore(&data_lock, flags);
  870. if (!mgr_manual_update(mgr))
  871. dispc_mgr_enable(mgr->id, true);
  872. out:
  873. mutex_unlock(&apply_lock);
  874. return 0;
  875. err:
  876. mp->enabled = false;
  877. spin_unlock_irqrestore(&data_lock, flags);
  878. mutex_unlock(&apply_lock);
  879. return r;
  880. }
  881. void dss_mgr_disable(struct omap_overlay_manager *mgr)
  882. {
  883. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  884. unsigned long flags;
  885. bool fifo_merge;
  886. mutex_lock(&apply_lock);
  887. if (!mp->enabled)
  888. goto out;
  889. if (!mgr_manual_update(mgr))
  890. dispc_mgr_enable(mgr->id, false);
  891. spin_lock_irqsave(&data_lock, flags);
  892. mp->updating = false;
  893. mp->enabled = false;
  894. fifo_merge = get_use_fifo_merge();
  895. dss_setup_fifos(fifo_merge);
  896. dss_apply_fifo_merge(fifo_merge);
  897. dss_write_regs();
  898. dss_set_go_bits();
  899. spin_unlock_irqrestore(&data_lock, flags);
  900. wait_pending_extra_info_updates();
  901. out:
  902. mutex_unlock(&apply_lock);
  903. }
  904. int dss_mgr_set_info(struct omap_overlay_manager *mgr,
  905. struct omap_overlay_manager_info *info)
  906. {
  907. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  908. unsigned long flags;
  909. int r;
  910. r = dss_mgr_simple_check(mgr, info);
  911. if (r)
  912. return r;
  913. spin_lock_irqsave(&data_lock, flags);
  914. mp->user_info = *info;
  915. mp->user_info_dirty = true;
  916. spin_unlock_irqrestore(&data_lock, flags);
  917. return 0;
  918. }
  919. void dss_mgr_get_info(struct omap_overlay_manager *mgr,
  920. struct omap_overlay_manager_info *info)
  921. {
  922. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  923. unsigned long flags;
  924. spin_lock_irqsave(&data_lock, flags);
  925. *info = mp->user_info;
  926. spin_unlock_irqrestore(&data_lock, flags);
  927. }
  928. int dss_mgr_set_device(struct omap_overlay_manager *mgr,
  929. struct omap_dss_device *dssdev)
  930. {
  931. int r;
  932. mutex_lock(&apply_lock);
  933. if (dssdev->manager) {
  934. DSSERR("display '%s' already has a manager '%s'\n",
  935. dssdev->name, dssdev->manager->name);
  936. r = -EINVAL;
  937. goto err;
  938. }
  939. if ((mgr->supported_displays & dssdev->type) == 0) {
  940. DSSERR("display '%s' does not support manager '%s'\n",
  941. dssdev->name, mgr->name);
  942. r = -EINVAL;
  943. goto err;
  944. }
  945. dssdev->manager = mgr;
  946. mgr->device = dssdev;
  947. mutex_unlock(&apply_lock);
  948. return 0;
  949. err:
  950. mutex_unlock(&apply_lock);
  951. return r;
  952. }
  953. int dss_mgr_unset_device(struct omap_overlay_manager *mgr)
  954. {
  955. int r;
  956. mutex_lock(&apply_lock);
  957. if (!mgr->device) {
  958. DSSERR("failed to unset display, display not set.\n");
  959. r = -EINVAL;
  960. goto err;
  961. }
  962. /*
  963. * Don't allow currently enabled displays to have the overlay manager
  964. * pulled out from underneath them
  965. */
  966. if (mgr->device->state != OMAP_DSS_DISPLAY_DISABLED) {
  967. r = -EINVAL;
  968. goto err;
  969. }
  970. mgr->device->manager = NULL;
  971. mgr->device = NULL;
  972. mutex_unlock(&apply_lock);
  973. return 0;
  974. err:
  975. mutex_unlock(&apply_lock);
  976. return r;
  977. }
  978. static void dss_apply_mgr_timings(struct omap_overlay_manager *mgr,
  979. struct omap_video_timings *timings)
  980. {
  981. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  982. mp->timings = *timings;
  983. mp->extra_info_dirty = true;
  984. }
  985. void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
  986. struct omap_video_timings *timings)
  987. {
  988. unsigned long flags;
  989. mutex_lock(&apply_lock);
  990. spin_lock_irqsave(&data_lock, flags);
  991. dss_apply_mgr_timings(mgr, timings);
  992. dss_write_regs();
  993. dss_set_go_bits();
  994. spin_unlock_irqrestore(&data_lock, flags);
  995. wait_pending_extra_info_updates();
  996. mutex_unlock(&apply_lock);
  997. }
  998. static void dss_apply_mgr_lcd_config(struct omap_overlay_manager *mgr,
  999. const struct dss_lcd_mgr_config *config)
  1000. {
  1001. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  1002. mp->lcd_config = *config;
  1003. mp->extra_info_dirty = true;
  1004. }
  1005. void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
  1006. const struct dss_lcd_mgr_config *config)
  1007. {
  1008. unsigned long flags;
  1009. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  1010. mutex_lock(&apply_lock);
  1011. if (mp->enabled) {
  1012. DSSERR("cannot apply lcd config for %s: manager needs to be disabled\n",
  1013. mgr->name);
  1014. goto out;
  1015. }
  1016. spin_lock_irqsave(&data_lock, flags);
  1017. dss_apply_mgr_lcd_config(mgr, config);
  1018. dss_write_regs();
  1019. dss_set_go_bits();
  1020. spin_unlock_irqrestore(&data_lock, flags);
  1021. wait_pending_extra_info_updates();
  1022. out:
  1023. mutex_unlock(&apply_lock);
  1024. }
  1025. int dss_ovl_set_info(struct omap_overlay *ovl,
  1026. struct omap_overlay_info *info)
  1027. {
  1028. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1029. unsigned long flags;
  1030. int r;
  1031. r = dss_ovl_simple_check(ovl, info);
  1032. if (r)
  1033. return r;
  1034. spin_lock_irqsave(&data_lock, flags);
  1035. op->user_info = *info;
  1036. op->user_info_dirty = true;
  1037. spin_unlock_irqrestore(&data_lock, flags);
  1038. return 0;
  1039. }
  1040. void dss_ovl_get_info(struct omap_overlay *ovl,
  1041. struct omap_overlay_info *info)
  1042. {
  1043. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1044. unsigned long flags;
  1045. spin_lock_irqsave(&data_lock, flags);
  1046. *info = op->user_info;
  1047. spin_unlock_irqrestore(&data_lock, flags);
  1048. }
  1049. int dss_ovl_set_manager(struct omap_overlay *ovl,
  1050. struct omap_overlay_manager *mgr)
  1051. {
  1052. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1053. unsigned long flags;
  1054. int r;
  1055. if (!mgr)
  1056. return -EINVAL;
  1057. mutex_lock(&apply_lock);
  1058. if (ovl->manager) {
  1059. DSSERR("overlay '%s' already has a manager '%s'\n",
  1060. ovl->name, ovl->manager->name);
  1061. r = -EINVAL;
  1062. goto err;
  1063. }
  1064. spin_lock_irqsave(&data_lock, flags);
  1065. if (op->enabled) {
  1066. spin_unlock_irqrestore(&data_lock, flags);
  1067. DSSERR("overlay has to be disabled to change the manager\n");
  1068. r = -EINVAL;
  1069. goto err;
  1070. }
  1071. op->channel = mgr->id;
  1072. op->extra_info_dirty = true;
  1073. ovl->manager = mgr;
  1074. list_add_tail(&ovl->list, &mgr->overlays);
  1075. spin_unlock_irqrestore(&data_lock, flags);
  1076. /* XXX: When there is an overlay on a DSI manual update display, and
  1077. * the overlay is first disabled, then moved to tv, and enabled, we
  1078. * seem to get SYNC_LOST_DIGIT error.
  1079. *
  1080. * Waiting doesn't seem to help, but updating the manual update display
  1081. * after disabling the overlay seems to fix this. This hints that the
  1082. * overlay is perhaps somehow tied to the LCD output until the output
  1083. * is updated.
  1084. *
  1085. * Userspace workaround for this is to update the LCD after disabling
  1086. * the overlay, but before moving the overlay to TV.
  1087. */
  1088. mutex_unlock(&apply_lock);
  1089. return 0;
  1090. err:
  1091. mutex_unlock(&apply_lock);
  1092. return r;
  1093. }
  1094. int dss_ovl_unset_manager(struct omap_overlay *ovl)
  1095. {
  1096. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1097. unsigned long flags;
  1098. int r;
  1099. mutex_lock(&apply_lock);
  1100. if (!ovl->manager) {
  1101. DSSERR("failed to detach overlay: manager not set\n");
  1102. r = -EINVAL;
  1103. goto err;
  1104. }
  1105. spin_lock_irqsave(&data_lock, flags);
  1106. if (op->enabled) {
  1107. spin_unlock_irqrestore(&data_lock, flags);
  1108. DSSERR("overlay has to be disabled to unset the manager\n");
  1109. r = -EINVAL;
  1110. goto err;
  1111. }
  1112. op->channel = -1;
  1113. ovl->manager = NULL;
  1114. list_del(&ovl->list);
  1115. spin_unlock_irqrestore(&data_lock, flags);
  1116. mutex_unlock(&apply_lock);
  1117. return 0;
  1118. err:
  1119. mutex_unlock(&apply_lock);
  1120. return r;
  1121. }
  1122. bool dss_ovl_is_enabled(struct omap_overlay *ovl)
  1123. {
  1124. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1125. unsigned long flags;
  1126. bool e;
  1127. spin_lock_irqsave(&data_lock, flags);
  1128. e = op->enabled;
  1129. spin_unlock_irqrestore(&data_lock, flags);
  1130. return e;
  1131. }
  1132. int dss_ovl_enable(struct omap_overlay *ovl)
  1133. {
  1134. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1135. unsigned long flags;
  1136. bool fifo_merge;
  1137. int r;
  1138. mutex_lock(&apply_lock);
  1139. if (op->enabled) {
  1140. r = 0;
  1141. goto err1;
  1142. }
  1143. if (ovl->manager == NULL || ovl->manager->device == NULL) {
  1144. r = -EINVAL;
  1145. goto err1;
  1146. }
  1147. spin_lock_irqsave(&data_lock, flags);
  1148. op->enabling = true;
  1149. r = dss_check_settings(ovl->manager);
  1150. if (r) {
  1151. DSSERR("failed to enable overlay %d: check_settings failed\n",
  1152. ovl->id);
  1153. goto err2;
  1154. }
  1155. /* step 1: configure fifos/fifomerge for currently enabled ovls */
  1156. fifo_merge = get_use_fifo_merge();
  1157. dss_setup_fifos(fifo_merge);
  1158. dss_apply_fifo_merge(fifo_merge);
  1159. dss_write_regs();
  1160. dss_set_go_bits();
  1161. spin_unlock_irqrestore(&data_lock, flags);
  1162. /* wait for fifo configs to go in */
  1163. wait_pending_extra_info_updates();
  1164. /* step 2: enable the overlay */
  1165. spin_lock_irqsave(&data_lock, flags);
  1166. op->enabling = false;
  1167. dss_apply_ovl_enable(ovl, true);
  1168. dss_write_regs();
  1169. dss_set_go_bits();
  1170. spin_unlock_irqrestore(&data_lock, flags);
  1171. /* wait for overlay to be enabled */
  1172. wait_pending_extra_info_updates();
  1173. mutex_unlock(&apply_lock);
  1174. return 0;
  1175. err2:
  1176. op->enabling = false;
  1177. spin_unlock_irqrestore(&data_lock, flags);
  1178. err1:
  1179. mutex_unlock(&apply_lock);
  1180. return r;
  1181. }
  1182. int dss_ovl_disable(struct omap_overlay *ovl)
  1183. {
  1184. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1185. unsigned long flags;
  1186. bool fifo_merge;
  1187. int r;
  1188. mutex_lock(&apply_lock);
  1189. if (!op->enabled) {
  1190. r = 0;
  1191. goto err;
  1192. }
  1193. if (ovl->manager == NULL || ovl->manager->device == NULL) {
  1194. r = -EINVAL;
  1195. goto err;
  1196. }
  1197. /* step 1: disable the overlay */
  1198. spin_lock_irqsave(&data_lock, flags);
  1199. dss_apply_ovl_enable(ovl, false);
  1200. dss_write_regs();
  1201. dss_set_go_bits();
  1202. spin_unlock_irqrestore(&data_lock, flags);
  1203. /* wait for the overlay to be disabled */
  1204. wait_pending_extra_info_updates();
  1205. /* step 2: configure fifos/fifomerge */
  1206. spin_lock_irqsave(&data_lock, flags);
  1207. fifo_merge = get_use_fifo_merge();
  1208. dss_setup_fifos(fifo_merge);
  1209. dss_apply_fifo_merge(fifo_merge);
  1210. dss_write_regs();
  1211. dss_set_go_bits();
  1212. spin_unlock_irqrestore(&data_lock, flags);
  1213. /* wait for fifo config to go in */
  1214. wait_pending_extra_info_updates();
  1215. mutex_unlock(&apply_lock);
  1216. return 0;
  1217. err:
  1218. mutex_unlock(&apply_lock);
  1219. return r;
  1220. }