tsc.c 17 KB

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  1. #include <linux/kernel.h>
  2. #include <linux/sched.h>
  3. #include <linux/init.h>
  4. #include <linux/module.h>
  5. #include <linux/timer.h>
  6. #include <linux/acpi_pmtmr.h>
  7. #include <linux/cpufreq.h>
  8. #include <linux/dmi.h>
  9. #include <linux/delay.h>
  10. #include <linux/clocksource.h>
  11. #include <linux/percpu.h>
  12. #include <asm/hpet.h>
  13. #include <asm/timer.h>
  14. #include <asm/vgtod.h>
  15. #include <asm/time.h>
  16. #include <asm/delay.h>
  17. unsigned int cpu_khz; /* TSC clocks / usec, not used here */
  18. EXPORT_SYMBOL(cpu_khz);
  19. unsigned int tsc_khz;
  20. EXPORT_SYMBOL(tsc_khz);
  21. /*
  22. * TSC can be unstable due to cpufreq or due to unsynced TSCs
  23. */
  24. static int tsc_unstable;
  25. /* native_sched_clock() is called before tsc_init(), so
  26. we must start with the TSC soft disabled to prevent
  27. erroneous rdtsc usage on !cpu_has_tsc processors */
  28. static int tsc_disabled = -1;
  29. /*
  30. * Scheduler clock - returns current time in nanosec units.
  31. */
  32. u64 native_sched_clock(void)
  33. {
  34. u64 this_offset;
  35. /*
  36. * Fall back to jiffies if there's no TSC available:
  37. * ( But note that we still use it if the TSC is marked
  38. * unstable. We do this because unlike Time Of Day,
  39. * the scheduler clock tolerates small errors and it's
  40. * very important for it to be as fast as the platform
  41. * can achive it. )
  42. */
  43. if (unlikely(tsc_disabled)) {
  44. /* No locking but a rare wrong value is not a big deal: */
  45. return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
  46. }
  47. /* read the Time Stamp Counter: */
  48. rdtscll(this_offset);
  49. /* return the value in ns */
  50. return cycles_2_ns(this_offset);
  51. }
  52. /* We need to define a real function for sched_clock, to override the
  53. weak default version */
  54. #ifdef CONFIG_PARAVIRT
  55. unsigned long long sched_clock(void)
  56. {
  57. return paravirt_sched_clock();
  58. }
  59. #else
  60. unsigned long long
  61. sched_clock(void) __attribute__((alias("native_sched_clock")));
  62. #endif
  63. int check_tsc_unstable(void)
  64. {
  65. return tsc_unstable;
  66. }
  67. EXPORT_SYMBOL_GPL(check_tsc_unstable);
  68. #ifdef CONFIG_X86_TSC
  69. int __init notsc_setup(char *str)
  70. {
  71. printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
  72. "cannot disable TSC completely.\n");
  73. tsc_disabled = 1;
  74. return 1;
  75. }
  76. #else
  77. /*
  78. * disable flag for tsc. Takes effect by clearing the TSC cpu flag
  79. * in cpu/common.c
  80. */
  81. int __init notsc_setup(char *str)
  82. {
  83. setup_clear_cpu_cap(X86_FEATURE_TSC);
  84. return 1;
  85. }
  86. #endif
  87. __setup("notsc", notsc_setup);
  88. #define MAX_RETRIES 5
  89. #define SMI_TRESHOLD 50000
  90. /*
  91. * Read TSC and the reference counters. Take care of SMI disturbance
  92. */
  93. static u64 tsc_read_refs(u64 *pm, u64 *hpet)
  94. {
  95. u64 t1, t2;
  96. int i;
  97. for (i = 0; i < MAX_RETRIES; i++) {
  98. t1 = get_cycles();
  99. if (hpet)
  100. *hpet = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
  101. else
  102. *pm = acpi_pm_read_early();
  103. t2 = get_cycles();
  104. if ((t2 - t1) < SMI_TRESHOLD)
  105. return t2;
  106. }
  107. return ULLONG_MAX;
  108. }
  109. /*
  110. * Try to calibrate the TSC against the Programmable
  111. * Interrupt Timer and return the frequency of the TSC
  112. * in kHz.
  113. *
  114. * Return ULONG_MAX on failure to calibrate.
  115. */
  116. static unsigned long pit_calibrate_tsc(void)
  117. {
  118. u64 tsc, t1, t2, delta;
  119. unsigned long tscmin, tscmax;
  120. int pitcnt;
  121. /* Set the Gate high, disable speaker */
  122. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  123. /*
  124. * Setup CTC channel 2* for mode 0, (interrupt on terminal
  125. * count mode), binary count. Set the latch register to 50ms
  126. * (LSB then MSB) to begin countdown.
  127. */
  128. outb(0xb0, 0x43);
  129. outb((CLOCK_TICK_RATE / (1000 / 50)) & 0xff, 0x42);
  130. outb((CLOCK_TICK_RATE / (1000 / 50)) >> 8, 0x42);
  131. tsc = t1 = t2 = get_cycles();
  132. pitcnt = 0;
  133. tscmax = 0;
  134. tscmin = ULONG_MAX;
  135. while ((inb(0x61) & 0x20) == 0) {
  136. t2 = get_cycles();
  137. delta = t2 - tsc;
  138. tsc = t2;
  139. if ((unsigned long) delta < tscmin)
  140. tscmin = (unsigned int) delta;
  141. if ((unsigned long) delta > tscmax)
  142. tscmax = (unsigned int) delta;
  143. pitcnt++;
  144. }
  145. /*
  146. * Sanity checks:
  147. *
  148. * If we were not able to read the PIT more than 5000
  149. * times, then we have been hit by a massive SMI
  150. *
  151. * If the maximum is 10 times larger than the minimum,
  152. * then we got hit by an SMI as well.
  153. */
  154. if (pitcnt < 5000 || tscmax > 10 * tscmin)
  155. return ULONG_MAX;
  156. /* Calculate the PIT value */
  157. delta = t2 - t1;
  158. do_div(delta, 50);
  159. return delta;
  160. }
  161. /**
  162. * native_calibrate_tsc - calibrate the tsc on boot
  163. */
  164. unsigned long native_calibrate_tsc(void)
  165. {
  166. u64 tsc1, tsc2, delta, pm1, pm2, hpet1, hpet2;
  167. unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
  168. unsigned long flags;
  169. int hpet = is_hpet_enabled(), i;
  170. /*
  171. * Run 5 calibration loops to get the lowest frequency value
  172. * (the best estimate). We use two different calibration modes
  173. * here:
  174. *
  175. * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
  176. * load a timeout of 50ms. We read the time right after we
  177. * started the timer and wait until the PIT count down reaches
  178. * zero. In each wait loop iteration we read the TSC and check
  179. * the delta to the previous read. We keep track of the min
  180. * and max values of that delta. The delta is mostly defined
  181. * by the IO time of the PIT access, so we can detect when a
  182. * SMI/SMM disturbance happend between the two reads. If the
  183. * maximum time is significantly larger than the minimum time,
  184. * then we discard the result and have another try.
  185. *
  186. * 2) Reference counter. If available we use the HPET or the
  187. * PMTIMER as a reference to check the sanity of that value.
  188. * We use separate TSC readouts and check inside of the
  189. * reference read for a SMI/SMM disturbance. We dicard
  190. * disturbed values here as well. We do that around the PIT
  191. * calibration delay loop as we have to wait for a certain
  192. * amount of time anyway.
  193. */
  194. for (i = 0; i < 5; i++) {
  195. unsigned long tsc_pit_khz;
  196. /*
  197. * Read the start value and the reference count of
  198. * hpet/pmtimer when available. Then do the PIT
  199. * calibration, which will take at least 50ms, and
  200. * read the end value.
  201. */
  202. local_irq_save(flags);
  203. tsc1 = tsc_read_refs(&pm1, hpet ? &hpet1 : NULL);
  204. tsc_pit_khz = pit_calibrate_tsc();
  205. tsc2 = tsc_read_refs(&pm2, hpet ? &hpet2 : NULL);
  206. local_irq_restore(flags);
  207. /* Pick the lowest PIT TSC calibration so far */
  208. tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
  209. /* hpet or pmtimer available ? */
  210. if (!hpet && !pm1 && !pm2)
  211. continue;
  212. /* Check, whether the sampling was disturbed by an SMI */
  213. if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
  214. continue;
  215. tsc2 = (tsc2 - tsc1) * 1000000LL;
  216. if (hpet) {
  217. if (hpet2 < hpet1)
  218. hpet2 += 0x100000000ULL;
  219. hpet2 -= hpet1;
  220. tsc1 = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
  221. do_div(tsc1, 1000000);
  222. } else {
  223. if (pm2 < pm1)
  224. pm2 += (u64)ACPI_PM_OVRRUN;
  225. pm2 -= pm1;
  226. tsc1 = pm2 * 1000000000LL;
  227. do_div(tsc1, PMTMR_TICKS_PER_SEC);
  228. }
  229. do_div(tsc2, tsc1);
  230. tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
  231. }
  232. /*
  233. * Now check the results.
  234. */
  235. if (tsc_pit_min == ULONG_MAX) {
  236. /* PIT gave no useful value */
  237. printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
  238. /* We don't have an alternative source, disable TSC */
  239. if (!hpet && !pm1 && !pm2) {
  240. printk("TSC: No reference (HPET/PMTIMER) available\n");
  241. return 0;
  242. }
  243. /* The alternative source failed as well, disable TSC */
  244. if (tsc_ref_min == ULONG_MAX) {
  245. printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
  246. "failed due to SMI disturbance.\n");
  247. return 0;
  248. }
  249. /* Use the alternative source */
  250. printk(KERN_INFO "TSC: using %s reference calibration\n",
  251. hpet ? "HPET" : "PMTIMER");
  252. return tsc_ref_min;
  253. }
  254. /* We don't have an alternative source, use the PIT calibration value */
  255. if (!hpet && !pm1 && !pm2) {
  256. printk(KERN_INFO "TSC: Using PIT calibration value\n");
  257. return tsc_pit_min;
  258. }
  259. /* The alternative source failed, use the PIT calibration value */
  260. if (tsc_ref_min == ULONG_MAX) {
  261. printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed due "
  262. "to SMI disturbance. Using PIT calibration\n");
  263. return tsc_pit_min;
  264. }
  265. /* Check the reference deviation */
  266. delta = ((u64) tsc_pit_min) * 100;
  267. do_div(delta, tsc_ref_min);
  268. /*
  269. * If both calibration results are inside a 5% window, the we
  270. * use the lower frequency of those as it is probably the
  271. * closest estimate.
  272. */
  273. if (delta >= 95 && delta <= 105) {
  274. printk(KERN_INFO "TSC: PIT calibration confirmed by %s.\n",
  275. hpet ? "HPET" : "PMTIMER");
  276. printk(KERN_INFO "TSC: using %s calibration value\n",
  277. tsc_pit_min <= tsc_ref_min ? "PIT" :
  278. hpet ? "HPET" : "PMTIMER");
  279. return tsc_pit_min <= tsc_ref_min ? tsc_pit_min : tsc_ref_min;
  280. }
  281. printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
  282. hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
  283. /*
  284. * The calibration values differ too much. In doubt, we use
  285. * the PIT value as we know that there are PMTIMERs around
  286. * running at double speed.
  287. */
  288. printk(KERN_INFO "TSC: Using PIT calibration value\n");
  289. return tsc_pit_min;
  290. }
  291. #ifdef CONFIG_X86_32
  292. /* Only called from the Powernow K7 cpu freq driver */
  293. int recalibrate_cpu_khz(void)
  294. {
  295. #ifndef CONFIG_SMP
  296. unsigned long cpu_khz_old = cpu_khz;
  297. if (cpu_has_tsc) {
  298. tsc_khz = calibrate_tsc();
  299. cpu_khz = tsc_khz;
  300. cpu_data(0).loops_per_jiffy =
  301. cpufreq_scale(cpu_data(0).loops_per_jiffy,
  302. cpu_khz_old, cpu_khz);
  303. return 0;
  304. } else
  305. return -ENODEV;
  306. #else
  307. return -ENODEV;
  308. #endif
  309. }
  310. EXPORT_SYMBOL(recalibrate_cpu_khz);
  311. #endif /* CONFIG_X86_32 */
  312. /* Accelerators for sched_clock()
  313. * convert from cycles(64bits) => nanoseconds (64bits)
  314. * basic equation:
  315. * ns = cycles / (freq / ns_per_sec)
  316. * ns = cycles * (ns_per_sec / freq)
  317. * ns = cycles * (10^9 / (cpu_khz * 10^3))
  318. * ns = cycles * (10^6 / cpu_khz)
  319. *
  320. * Then we use scaling math (suggested by george@mvista.com) to get:
  321. * ns = cycles * (10^6 * SC / cpu_khz) / SC
  322. * ns = cycles * cyc2ns_scale / SC
  323. *
  324. * And since SC is a constant power of two, we can convert the div
  325. * into a shift.
  326. *
  327. * We can use khz divisor instead of mhz to keep a better precision, since
  328. * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
  329. * (mathieu.desnoyers@polymtl.ca)
  330. *
  331. * -johnstul@us.ibm.com "math is hard, lets go shopping!"
  332. */
  333. DEFINE_PER_CPU(unsigned long, cyc2ns);
  334. static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
  335. {
  336. unsigned long long tsc_now, ns_now;
  337. unsigned long flags, *scale;
  338. local_irq_save(flags);
  339. sched_clock_idle_sleep_event();
  340. scale = &per_cpu(cyc2ns, cpu);
  341. rdtscll(tsc_now);
  342. ns_now = __cycles_2_ns(tsc_now);
  343. if (cpu_khz)
  344. *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
  345. sched_clock_idle_wakeup_event(0);
  346. local_irq_restore(flags);
  347. }
  348. #ifdef CONFIG_CPU_FREQ
  349. /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
  350. * changes.
  351. *
  352. * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
  353. * not that important because current Opteron setups do not support
  354. * scaling on SMP anyroads.
  355. *
  356. * Should fix up last_tsc too. Currently gettimeofday in the
  357. * first tick after the change will be slightly wrong.
  358. */
  359. static unsigned int ref_freq;
  360. static unsigned long loops_per_jiffy_ref;
  361. static unsigned long tsc_khz_ref;
  362. static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
  363. void *data)
  364. {
  365. struct cpufreq_freqs *freq = data;
  366. unsigned long *lpj, dummy;
  367. if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
  368. return 0;
  369. lpj = &dummy;
  370. if (!(freq->flags & CPUFREQ_CONST_LOOPS))
  371. #ifdef CONFIG_SMP
  372. lpj = &cpu_data(freq->cpu).loops_per_jiffy;
  373. #else
  374. lpj = &boot_cpu_data.loops_per_jiffy;
  375. #endif
  376. if (!ref_freq) {
  377. ref_freq = freq->old;
  378. loops_per_jiffy_ref = *lpj;
  379. tsc_khz_ref = tsc_khz;
  380. }
  381. if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
  382. (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
  383. (val == CPUFREQ_RESUMECHANGE)) {
  384. *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
  385. tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
  386. if (!(freq->flags & CPUFREQ_CONST_LOOPS))
  387. mark_tsc_unstable("cpufreq changes");
  388. }
  389. set_cyc2ns_scale(tsc_khz, freq->cpu);
  390. return 0;
  391. }
  392. static struct notifier_block time_cpufreq_notifier_block = {
  393. .notifier_call = time_cpufreq_notifier
  394. };
  395. static int __init cpufreq_tsc(void)
  396. {
  397. if (!cpu_has_tsc)
  398. return 0;
  399. if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
  400. return 0;
  401. cpufreq_register_notifier(&time_cpufreq_notifier_block,
  402. CPUFREQ_TRANSITION_NOTIFIER);
  403. return 0;
  404. }
  405. core_initcall(cpufreq_tsc);
  406. #endif /* CONFIG_CPU_FREQ */
  407. /* clocksource code */
  408. static struct clocksource clocksource_tsc;
  409. /*
  410. * We compare the TSC to the cycle_last value in the clocksource
  411. * structure to avoid a nasty time-warp. This can be observed in a
  412. * very small window right after one CPU updated cycle_last under
  413. * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
  414. * is smaller than the cycle_last reference value due to a TSC which
  415. * is slighty behind. This delta is nowhere else observable, but in
  416. * that case it results in a forward time jump in the range of hours
  417. * due to the unsigned delta calculation of the time keeping core
  418. * code, which is necessary to support wrapping clocksources like pm
  419. * timer.
  420. */
  421. static cycle_t read_tsc(void)
  422. {
  423. cycle_t ret = (cycle_t)get_cycles();
  424. return ret >= clocksource_tsc.cycle_last ?
  425. ret : clocksource_tsc.cycle_last;
  426. }
  427. #ifdef CONFIG_X86_64
  428. static cycle_t __vsyscall_fn vread_tsc(void)
  429. {
  430. cycle_t ret = (cycle_t)vget_cycles();
  431. return ret >= __vsyscall_gtod_data.clock.cycle_last ?
  432. ret : __vsyscall_gtod_data.clock.cycle_last;
  433. }
  434. #endif
  435. static struct clocksource clocksource_tsc = {
  436. .name = "tsc",
  437. .rating = 300,
  438. .read = read_tsc,
  439. .mask = CLOCKSOURCE_MASK(64),
  440. .shift = 22,
  441. .flags = CLOCK_SOURCE_IS_CONTINUOUS |
  442. CLOCK_SOURCE_MUST_VERIFY,
  443. #ifdef CONFIG_X86_64
  444. .vread = vread_tsc,
  445. #endif
  446. };
  447. void mark_tsc_unstable(char *reason)
  448. {
  449. if (!tsc_unstable) {
  450. tsc_unstable = 1;
  451. printk("Marking TSC unstable due to %s\n", reason);
  452. /* Change only the rating, when not registered */
  453. if (clocksource_tsc.mult)
  454. clocksource_change_rating(&clocksource_tsc, 0);
  455. else
  456. clocksource_tsc.rating = 0;
  457. }
  458. }
  459. EXPORT_SYMBOL_GPL(mark_tsc_unstable);
  460. static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d)
  461. {
  462. printk(KERN_NOTICE "%s detected: marking TSC unstable.\n",
  463. d->ident);
  464. tsc_unstable = 1;
  465. return 0;
  466. }
  467. /* List of systems that have known TSC problems */
  468. static struct dmi_system_id __initdata bad_tsc_dmi_table[] = {
  469. {
  470. .callback = dmi_mark_tsc_unstable,
  471. .ident = "IBM Thinkpad 380XD",
  472. .matches = {
  473. DMI_MATCH(DMI_BOARD_VENDOR, "IBM"),
  474. DMI_MATCH(DMI_BOARD_NAME, "2635FA0"),
  475. },
  476. },
  477. {}
  478. };
  479. /*
  480. * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
  481. */
  482. #ifdef CONFIG_MGEODE_LX
  483. /* RTSC counts during suspend */
  484. #define RTSC_SUSP 0x100
  485. static void __init check_geode_tsc_reliable(void)
  486. {
  487. unsigned long res_low, res_high;
  488. rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
  489. if (res_low & RTSC_SUSP)
  490. clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
  491. }
  492. #else
  493. static inline void check_geode_tsc_reliable(void) { }
  494. #endif
  495. /*
  496. * Make an educated guess if the TSC is trustworthy and synchronized
  497. * over all CPUs.
  498. */
  499. __cpuinit int unsynchronized_tsc(void)
  500. {
  501. if (!cpu_has_tsc || tsc_unstable)
  502. return 1;
  503. #ifdef CONFIG_SMP
  504. if (apic_is_clustered_box())
  505. return 1;
  506. #endif
  507. if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
  508. return 0;
  509. /*
  510. * Intel systems are normally all synchronized.
  511. * Exceptions must mark TSC as unstable:
  512. */
  513. if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
  514. /* assume multi socket systems are not synchronized: */
  515. if (num_possible_cpus() > 1)
  516. tsc_unstable = 1;
  517. }
  518. return tsc_unstable;
  519. }
  520. static void __init init_tsc_clocksource(void)
  521. {
  522. clocksource_tsc.mult = clocksource_khz2mult(tsc_khz,
  523. clocksource_tsc.shift);
  524. /* lower the rating if we already know its unstable: */
  525. if (check_tsc_unstable()) {
  526. clocksource_tsc.rating = 0;
  527. clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
  528. }
  529. clocksource_register(&clocksource_tsc);
  530. }
  531. void __init tsc_init(void)
  532. {
  533. u64 lpj;
  534. int cpu;
  535. if (!cpu_has_tsc)
  536. return;
  537. tsc_khz = calibrate_tsc();
  538. cpu_khz = tsc_khz;
  539. if (!tsc_khz) {
  540. mark_tsc_unstable("could not calculate TSC khz");
  541. return;
  542. }
  543. #ifdef CONFIG_X86_64
  544. if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) &&
  545. (boot_cpu_data.x86_vendor == X86_VENDOR_AMD))
  546. cpu_khz = calibrate_cpu();
  547. #endif
  548. lpj = ((u64)tsc_khz * 1000);
  549. do_div(lpj, HZ);
  550. lpj_fine = lpj;
  551. printk("Detected %lu.%03lu MHz processor.\n",
  552. (unsigned long)cpu_khz / 1000,
  553. (unsigned long)cpu_khz % 1000);
  554. /*
  555. * Secondary CPUs do not run through tsc_init(), so set up
  556. * all the scale factors for all CPUs, assuming the same
  557. * speed as the bootup CPU. (cpufreq notifiers will fix this
  558. * up if their speed diverges)
  559. */
  560. for_each_possible_cpu(cpu)
  561. set_cyc2ns_scale(cpu_khz, cpu);
  562. if (tsc_disabled > 0)
  563. return;
  564. /* now allow native_sched_clock() to use rdtsc */
  565. tsc_disabled = 0;
  566. use_tsc_delay();
  567. /* Check and install the TSC clocksource */
  568. dmi_check_system(bad_tsc_dmi_table);
  569. if (unsynchronized_tsc())
  570. mark_tsc_unstable("TSCs unsynchronized");
  571. check_geode_tsc_reliable();
  572. init_tsc_clocksource();
  573. }