ezbrd.c 17 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf518/boards/ezbrd.c
  3. * Based on: arch/blackfin/mach-bf527/boards/ezbrd.c
  4. * Author: Bryan Wu <cooloney@kernel.org>
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2005 National ICT Australia (NICTA)
  11. * Copyright 2004-2008 Analog Devices Inc.
  12. *
  13. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, see the file COPYING, or write
  27. * to the Free Software Foundation, Inc.,
  28. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  29. */
  30. #include <linux/device.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/mtd/mtd.h>
  33. #include <linux/mtd/partitions.h>
  34. #include <linux/mtd/physmap.h>
  35. #include <linux/spi/spi.h>
  36. #include <linux/spi/flash.h>
  37. #include <linux/i2c.h>
  38. #include <linux/irq.h>
  39. #include <linux/interrupt.h>
  40. #include <asm/dma.h>
  41. #include <asm/bfin5xx_spi.h>
  42. #include <asm/reboot.h>
  43. #include <asm/portmux.h>
  44. #include <asm/dpmc.h>
  45. #include <asm/bfin_sdh.h>
  46. #include <linux/spi/ad7877.h>
  47. #include <net/dsa.h>
  48. /*
  49. * Name the Board for the /proc/cpuinfo
  50. */
  51. const char bfin_board_name[] = "ADI BF518F-EZBRD";
  52. /*
  53. * Driver needs to know address, irq and flag pin.
  54. */
  55. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  56. static struct mtd_partition ezbrd_partitions[] = {
  57. {
  58. .name = "bootloader(nor)",
  59. .size = 0x40000,
  60. .offset = 0,
  61. }, {
  62. .name = "linux kernel(nor)",
  63. .size = 0x1C0000,
  64. .offset = MTDPART_OFS_APPEND,
  65. }, {
  66. .name = "file system(nor)",
  67. .size = MTDPART_SIZ_FULL,
  68. .offset = MTDPART_OFS_APPEND,
  69. }
  70. };
  71. static struct physmap_flash_data ezbrd_flash_data = {
  72. .width = 2,
  73. .parts = ezbrd_partitions,
  74. .nr_parts = ARRAY_SIZE(ezbrd_partitions),
  75. };
  76. static struct resource ezbrd_flash_resource = {
  77. .start = 0x20000000,
  78. .end = 0x203fffff,
  79. .flags = IORESOURCE_MEM,
  80. };
  81. static struct platform_device ezbrd_flash_device = {
  82. .name = "physmap-flash",
  83. .id = 0,
  84. .dev = {
  85. .platform_data = &ezbrd_flash_data,
  86. },
  87. .num_resources = 1,
  88. .resource = &ezbrd_flash_resource,
  89. };
  90. #endif
  91. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  92. static struct platform_device rtc_device = {
  93. .name = "rtc-bfin",
  94. .id = -1,
  95. };
  96. #endif
  97. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  98. static struct platform_device bfin_mii_bus = {
  99. .name = "bfin_mii_bus",
  100. };
  101. static struct platform_device bfin_mac_device = {
  102. .name = "bfin_mac",
  103. .dev.platform_data = &bfin_mii_bus,
  104. };
  105. #endif
  106. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  107. static struct dsa_platform_data ksz8893m_switch_data = {
  108. .mii_bus = &bfin_mii_bus.dev,
  109. .netdev = &bfin_mac_device.dev,
  110. .port_names[0] = NULL,
  111. .port_names[1] = "eth%d",
  112. .port_names[2] = "eth%d",
  113. .port_names[3] = "cpu",
  114. };
  115. static struct platform_device ksz8893m_switch_device = {
  116. .name = "dsa",
  117. .id = 0,
  118. .num_resources = 0,
  119. .dev.platform_data = &ksz8893m_switch_data,
  120. };
  121. #endif
  122. #if defined(CONFIG_MTD_M25P80) \
  123. || defined(CONFIG_MTD_M25P80_MODULE)
  124. static struct mtd_partition bfin_spi_flash_partitions[] = {
  125. {
  126. .name = "bootloader(spi)",
  127. .size = 0x00040000,
  128. .offset = 0,
  129. .mask_flags = MTD_CAP_ROM
  130. }, {
  131. .name = "linux kernel(spi)",
  132. .size = MTDPART_SIZ_FULL,
  133. .offset = MTDPART_OFS_APPEND,
  134. }
  135. };
  136. static struct flash_platform_data bfin_spi_flash_data = {
  137. .name = "m25p80",
  138. .parts = bfin_spi_flash_partitions,
  139. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  140. .type = "m25p16",
  141. };
  142. /* SPI flash chip (m25p64) */
  143. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  144. .enable_dma = 0, /* use dma transfer with this chip*/
  145. .bits_per_word = 8,
  146. };
  147. #endif
  148. #if defined(CONFIG_SPI_ADC_BF533) \
  149. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  150. /* SPI ADC chip */
  151. static struct bfin5xx_spi_chip spi_adc_chip_info = {
  152. .enable_dma = 1, /* use dma transfer with this chip*/
  153. .bits_per_word = 16,
  154. };
  155. #endif
  156. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  157. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  158. /* SPI SWITCH CHIP */
  159. static struct bfin5xx_spi_chip spi_switch_info = {
  160. .enable_dma = 0,
  161. .bits_per_word = 8,
  162. };
  163. #endif
  164. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  165. static struct bfin5xx_spi_chip spi_mmc_chip_info = {
  166. .enable_dma = 1,
  167. .bits_per_word = 8,
  168. };
  169. #endif
  170. #if defined(CONFIG_PBX)
  171. static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
  172. .ctl_reg = 0x4, /* send zero */
  173. .enable_dma = 0,
  174. .bits_per_word = 8,
  175. .cs_change_per_word = 1,
  176. };
  177. #endif
  178. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  179. static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
  180. .enable_dma = 0,
  181. .bits_per_word = 16,
  182. };
  183. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  184. .model = 7877,
  185. .vref_delay_usecs = 50, /* internal, no capacitor */
  186. .x_plate_ohms = 419,
  187. .y_plate_ohms = 486,
  188. .pressure_max = 1000,
  189. .pressure_min = 0,
  190. .stopacq_polarity = 1,
  191. .first_conversion_delay = 3,
  192. .acquisition_time = 1,
  193. .averaging = 1,
  194. .pen_down_acc_interval = 1,
  195. };
  196. #endif
  197. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  198. && defined(CONFIG_SND_SOC_WM8731_SPI)
  199. static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
  200. .enable_dma = 0,
  201. .bits_per_word = 16,
  202. };
  203. #endif
  204. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  205. static struct bfin5xx_spi_chip spidev_chip_info = {
  206. .enable_dma = 0,
  207. .bits_per_word = 8,
  208. };
  209. #endif
  210. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  211. #if defined(CONFIG_MTD_M25P80) \
  212. || defined(CONFIG_MTD_M25P80_MODULE)
  213. {
  214. /* the modalias must be the same as spi device driver name */
  215. .modalias = "m25p80", /* Name of spi_driver for this device */
  216. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  217. .bus_num = 0, /* Framework bus number */
  218. .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
  219. .platform_data = &bfin_spi_flash_data,
  220. .controller_data = &spi_flash_chip_info,
  221. .mode = SPI_MODE_3,
  222. },
  223. #endif
  224. #if defined(CONFIG_SPI_ADC_BF533) \
  225. || defined(CONFIG_SPI_ADC_BF533_MODULE)
  226. {
  227. .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
  228. .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
  229. .bus_num = 0, /* Framework bus number */
  230. .chip_select = 1, /* Framework chip select. */
  231. .platform_data = NULL, /* No spi_driver specific config */
  232. .controller_data = &spi_adc_chip_info,
  233. },
  234. #endif
  235. #if defined(CONFIG_NET_DSA_KSZ8893M) \
  236. || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  237. {
  238. .modalias = "ksz8893m",
  239. .max_speed_hz = 5000000,
  240. .bus_num = 0,
  241. .chip_select = 1,
  242. .platform_data = NULL,
  243. .controller_data = &spi_switch_info,
  244. .mode = SPI_MODE_3,
  245. },
  246. #endif
  247. #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
  248. {
  249. .modalias = "spi_mmc_dummy",
  250. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  251. .bus_num = 0,
  252. .chip_select = 0,
  253. .platform_data = NULL,
  254. .controller_data = &spi_mmc_chip_info,
  255. .mode = SPI_MODE_3,
  256. },
  257. {
  258. .modalias = "spi_mmc",
  259. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  260. .bus_num = 0,
  261. .chip_select = CONFIG_SPI_MMC_CS_CHAN,
  262. .platform_data = NULL,
  263. .controller_data = &spi_mmc_chip_info,
  264. .mode = SPI_MODE_3,
  265. },
  266. #endif
  267. #if defined(CONFIG_PBX)
  268. {
  269. .modalias = "fxs-spi",
  270. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  271. .bus_num = 0,
  272. .chip_select = 8 - CONFIG_J11_JUMPER,
  273. .controller_data = &spi_si3xxx_chip_info,
  274. .mode = SPI_MODE_3,
  275. },
  276. {
  277. .modalias = "fxo-spi",
  278. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  279. .bus_num = 0,
  280. .chip_select = 8 - CONFIG_J19_JUMPER,
  281. .controller_data = &spi_si3xxx_chip_info,
  282. .mode = SPI_MODE_3,
  283. },
  284. #endif
  285. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  286. {
  287. .modalias = "ad7877",
  288. .platform_data = &bfin_ad7877_ts_info,
  289. .irq = IRQ_PF8,
  290. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  291. .bus_num = 0,
  292. .chip_select = 2,
  293. .controller_data = &spi_ad7877_chip_info,
  294. },
  295. #endif
  296. #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
  297. && defined(CONFIG_SND_SOC_WM8731_SPI)
  298. {
  299. .modalias = "wm8731",
  300. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  301. .bus_num = 0,
  302. .chip_select = 5,
  303. .controller_data = &spi_wm8731_chip_info,
  304. .mode = SPI_MODE_0,
  305. },
  306. #endif
  307. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  308. {
  309. .modalias = "spidev",
  310. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  311. .bus_num = 0,
  312. .chip_select = 1,
  313. .controller_data = &spidev_chip_info,
  314. },
  315. #endif
  316. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  317. {
  318. .modalias = "bfin-lq035q1-spi",
  319. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  320. .bus_num = 0,
  321. .chip_select = 1,
  322. .controller_data = &lq035q1_spi_chip_info,
  323. .mode = SPI_CPHA | SPI_CPOL,
  324. },
  325. #endif
  326. };
  327. /* SPI controller data */
  328. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  329. /* SPI (0) */
  330. static struct bfin5xx_spi_master bfin_spi0_info = {
  331. .num_chipselect = 5,
  332. .enable_dma = 1, /* master has the ability to do dma transfer */
  333. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  334. };
  335. static struct resource bfin_spi0_resource[] = {
  336. [0] = {
  337. .start = SPI0_REGBASE,
  338. .end = SPI0_REGBASE + 0xFF,
  339. .flags = IORESOURCE_MEM,
  340. },
  341. [1] = {
  342. .start = CH_SPI0,
  343. .end = CH_SPI0,
  344. .flags = IORESOURCE_IRQ,
  345. },
  346. };
  347. static struct platform_device bfin_spi0_device = {
  348. .name = "bfin-spi",
  349. .id = 0, /* Bus number */
  350. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  351. .resource = bfin_spi0_resource,
  352. .dev = {
  353. .platform_data = &bfin_spi0_info, /* Passed to driver */
  354. },
  355. };
  356. /* SPI (1) */
  357. static struct bfin5xx_spi_master bfin_spi1_info = {
  358. .num_chipselect = 5,
  359. .enable_dma = 1, /* master has the ability to do dma transfer */
  360. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  361. };
  362. static struct resource bfin_spi1_resource[] = {
  363. [0] = {
  364. .start = SPI1_REGBASE,
  365. .end = SPI1_REGBASE + 0xFF,
  366. .flags = IORESOURCE_MEM,
  367. },
  368. [1] = {
  369. .start = CH_SPI1,
  370. .end = CH_SPI1,
  371. .flags = IORESOURCE_IRQ,
  372. },
  373. };
  374. static struct platform_device bfin_spi1_device = {
  375. .name = "bfin-spi",
  376. .id = 1, /* Bus number */
  377. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  378. .resource = bfin_spi1_resource,
  379. .dev = {
  380. .platform_data = &bfin_spi1_info, /* Passed to driver */
  381. },
  382. };
  383. #endif /* spi master and devices */
  384. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  385. static struct resource bfin_uart_resources[] = {
  386. #ifdef CONFIG_SERIAL_BFIN_UART0
  387. {
  388. .start = 0xFFC00400,
  389. .end = 0xFFC004FF,
  390. .flags = IORESOURCE_MEM,
  391. },
  392. #endif
  393. #ifdef CONFIG_SERIAL_BFIN_UART1
  394. {
  395. .start = 0xFFC02000,
  396. .end = 0xFFC020FF,
  397. .flags = IORESOURCE_MEM,
  398. },
  399. #endif
  400. };
  401. static struct platform_device bfin_uart_device = {
  402. .name = "bfin-uart",
  403. .id = 1,
  404. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  405. .resource = bfin_uart_resources,
  406. };
  407. #endif
  408. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  409. #ifdef CONFIG_BFIN_SIR0
  410. static struct resource bfin_sir0_resources[] = {
  411. {
  412. .start = 0xFFC00400,
  413. .end = 0xFFC004FF,
  414. .flags = IORESOURCE_MEM,
  415. },
  416. {
  417. .start = IRQ_UART0_RX,
  418. .end = IRQ_UART0_RX+1,
  419. .flags = IORESOURCE_IRQ,
  420. },
  421. {
  422. .start = CH_UART0_RX,
  423. .end = CH_UART0_RX+1,
  424. .flags = IORESOURCE_DMA,
  425. },
  426. };
  427. static struct platform_device bfin_sir0_device = {
  428. .name = "bfin_sir",
  429. .id = 0,
  430. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  431. .resource = bfin_sir0_resources,
  432. };
  433. #endif
  434. #ifdef CONFIG_BFIN_SIR1
  435. static struct resource bfin_sir1_resources[] = {
  436. {
  437. .start = 0xFFC02000,
  438. .end = 0xFFC020FF,
  439. .flags = IORESOURCE_MEM,
  440. },
  441. {
  442. .start = IRQ_UART1_RX,
  443. .end = IRQ_UART1_RX+1,
  444. .flags = IORESOURCE_IRQ,
  445. },
  446. {
  447. .start = CH_UART1_RX,
  448. .end = CH_UART1_RX+1,
  449. .flags = IORESOURCE_DMA,
  450. },
  451. };
  452. static struct platform_device bfin_sir1_device = {
  453. .name = "bfin_sir",
  454. .id = 1,
  455. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  456. .resource = bfin_sir1_resources,
  457. };
  458. #endif
  459. #endif
  460. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  461. static struct resource bfin_twi0_resource[] = {
  462. [0] = {
  463. .start = TWI0_REGBASE,
  464. .end = TWI0_REGBASE,
  465. .flags = IORESOURCE_MEM,
  466. },
  467. [1] = {
  468. .start = IRQ_TWI,
  469. .end = IRQ_TWI,
  470. .flags = IORESOURCE_IRQ,
  471. },
  472. };
  473. static struct platform_device i2c_bfin_twi_device = {
  474. .name = "i2c-bfin-twi",
  475. .id = 0,
  476. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  477. .resource = bfin_twi0_resource,
  478. };
  479. #endif
  480. static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
  481. #if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
  482. {
  483. I2C_BOARD_INFO("pcf8574_lcd", 0x22),
  484. },
  485. #endif
  486. #if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
  487. {
  488. I2C_BOARD_INFO("pcf8574_keypad", 0x27),
  489. .irq = IRQ_PF8,
  490. },
  491. #endif
  492. };
  493. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  494. static struct platform_device bfin_sport0_uart_device = {
  495. .name = "bfin-sport-uart",
  496. .id = 0,
  497. };
  498. static struct platform_device bfin_sport1_uart_device = {
  499. .name = "bfin-sport-uart",
  500. .id = 1,
  501. };
  502. #endif
  503. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  504. #include <linux/input.h>
  505. #include <linux/gpio_keys.h>
  506. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  507. {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
  508. {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
  509. };
  510. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  511. .buttons = bfin_gpio_keys_table,
  512. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  513. };
  514. static struct platform_device bfin_device_gpiokeys = {
  515. .name = "gpio-keys",
  516. .dev = {
  517. .platform_data = &bfin_gpio_keys_data,
  518. },
  519. };
  520. #endif
  521. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  522. static struct bfin_sd_host bfin_sdh_data = {
  523. .dma_chan = CH_RSI,
  524. .irq_int0 = IRQ_RSI_INT0,
  525. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  526. };
  527. static struct platform_device bf51x_sdh_device = {
  528. .name = "bfin-sdh",
  529. .id = 0,
  530. .dev = {
  531. .platform_data = &bfin_sdh_data,
  532. },
  533. };
  534. #endif
  535. static struct resource bfin_gpios_resources = {
  536. .start = 0,
  537. .end = MAX_BLACKFIN_GPIOS - 1,
  538. .flags = IORESOURCE_IRQ,
  539. };
  540. static struct platform_device bfin_gpios_device = {
  541. .name = "simple-gpio",
  542. .id = -1,
  543. .num_resources = 1,
  544. .resource = &bfin_gpios_resources,
  545. };
  546. static const unsigned int cclk_vlev_datasheet[] =
  547. {
  548. VRPAIR(VLEV_100, 400000000),
  549. VRPAIR(VLEV_105, 426000000),
  550. VRPAIR(VLEV_110, 500000000),
  551. VRPAIR(VLEV_115, 533000000),
  552. VRPAIR(VLEV_120, 600000000),
  553. };
  554. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  555. .tuple_tab = cclk_vlev_datasheet,
  556. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  557. .vr_settling_time = 25 /* us */,
  558. };
  559. static struct platform_device bfin_dpmc = {
  560. .name = "bfin dpmc",
  561. .dev = {
  562. .platform_data = &bfin_dmpc_vreg_data,
  563. },
  564. };
  565. static struct platform_device *stamp_devices[] __initdata = {
  566. &bfin_dpmc,
  567. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  568. &rtc_device,
  569. #endif
  570. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  571. &bfin_mii_bus,
  572. &bfin_mac_device,
  573. #endif
  574. #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
  575. &ksz8893m_switch_device,
  576. #endif
  577. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  578. &bfin_spi0_device,
  579. &bfin_spi1_device,
  580. #endif
  581. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  582. &bfin_uart_device,
  583. #endif
  584. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  585. #ifdef CONFIG_BFIN_SIR0
  586. &bfin_sir0_device,
  587. #endif
  588. #ifdef CONFIG_BFIN_SIR1
  589. &bfin_sir1_device,
  590. #endif
  591. #endif
  592. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  593. &i2c_bfin_twi_device,
  594. #endif
  595. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  596. &bfin_sport0_uart_device,
  597. &bfin_sport1_uart_device,
  598. #endif
  599. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  600. &bfin_device_gpiokeys,
  601. #endif
  602. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  603. &bf51x_sdh_device,
  604. #endif
  605. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  606. &ezbrd_flash_device,
  607. #endif
  608. &bfin_gpios_device,
  609. };
  610. static int __init ezbrd_init(void)
  611. {
  612. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  613. i2c_register_board_info(0, bfin_i2c_board_info,
  614. ARRAY_SIZE(bfin_i2c_board_info));
  615. platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
  616. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  617. return 0;
  618. }
  619. arch_initcall(ezbrd_init);
  620. void native_machine_restart(char *cmd)
  621. {
  622. /* workaround reboot hang when booting from SPI */
  623. if ((bfin_read_SYSCR() & 0x7) == 0x3)
  624. bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
  625. }
  626. void bfin_get_ether_addr(char *addr)
  627. {
  628. /* the MAC is stored in OTP memory page 0xDF */
  629. u32 ret;
  630. u64 otp_mac;
  631. u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
  632. ret = otp_read(0xDF, 0x00, &otp_mac);
  633. if (!(ret & 0x1)) {
  634. char *otp_mac_p = (char *)&otp_mac;
  635. for (ret = 0; ret < 6; ++ret)
  636. addr[ret] = otp_mac_p[5 - ret];
  637. }
  638. }
  639. EXPORT_SYMBOL(bfin_get_ether_addr);