id.c 6.3 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/id.c
  3. *
  4. * OMAP2 CPU identification code
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Written by Tony Lindgren <tony@atomide.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <asm/cputype.h>
  18. #include <mach/common.h>
  19. #include <mach/control.h>
  20. #include <mach/cpu.h>
  21. static struct omap_chip_id omap_chip;
  22. static unsigned int omap_revision;
  23. unsigned int omap_rev(void)
  24. {
  25. return omap_revision;
  26. }
  27. EXPORT_SYMBOL(omap_rev);
  28. /**
  29. * omap_chip_is - test whether currently running OMAP matches a chip type
  30. * @oc: omap_chip_t to test against
  31. *
  32. * Test whether the currently-running OMAP chip matches the supplied
  33. * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
  34. */
  35. int omap_chip_is(struct omap_chip_id oci)
  36. {
  37. return (oci.oc & omap_chip.oc) ? 1 : 0;
  38. }
  39. EXPORT_SYMBOL(omap_chip_is);
  40. /*----------------------------------------------------------------------------*/
  41. #define OMAP_TAP_IDCODE 0x0204
  42. #define OMAP_TAP_DIE_ID_0 0x0218
  43. #define OMAP_TAP_DIE_ID_1 0x021C
  44. #define OMAP_TAP_DIE_ID_2 0x0220
  45. #define OMAP_TAP_DIE_ID_3 0x0224
  46. #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
  47. struct omap_id {
  48. u16 hawkeye; /* Silicon type (Hawkeye id) */
  49. u8 dev; /* Device type from production_id reg */
  50. u32 type; /* Combined type id copied to omap_revision */
  51. };
  52. /* Register values to detect the OMAP version */
  53. static struct omap_id omap_ids[] __initdata = {
  54. { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
  55. { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
  56. { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
  57. { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
  58. { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
  59. { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
  60. };
  61. static void __iomem *tap_base;
  62. static u16 tap_prod_id;
  63. void __init omap24xx_check_revision(void)
  64. {
  65. int i, j;
  66. u32 idcode, prod_id;
  67. u16 hawkeye;
  68. u8 dev_type, rev;
  69. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  70. prod_id = read_tap_reg(tap_prod_id);
  71. hawkeye = (idcode >> 12) & 0xffff;
  72. rev = (idcode >> 28) & 0x0f;
  73. dev_type = (prod_id >> 16) & 0x0f;
  74. pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
  75. idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
  76. pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
  77. read_tap_reg(OMAP_TAP_DIE_ID_0));
  78. pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
  79. read_tap_reg(OMAP_TAP_DIE_ID_1),
  80. (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
  81. pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
  82. read_tap_reg(OMAP_TAP_DIE_ID_2));
  83. pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
  84. read_tap_reg(OMAP_TAP_DIE_ID_3));
  85. pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
  86. prod_id, dev_type);
  87. /* Check hawkeye ids */
  88. for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
  89. if (hawkeye == omap_ids[i].hawkeye)
  90. break;
  91. }
  92. if (i == ARRAY_SIZE(omap_ids)) {
  93. printk(KERN_ERR "Unknown OMAP CPU id\n");
  94. return;
  95. }
  96. for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
  97. if (dev_type == omap_ids[j].dev)
  98. break;
  99. }
  100. if (j == ARRAY_SIZE(omap_ids)) {
  101. printk(KERN_ERR "Unknown OMAP device type. "
  102. "Handling it as OMAP%04x\n",
  103. omap_ids[i].type >> 16);
  104. j = i;
  105. }
  106. pr_info("OMAP%04x", omap_rev() >> 16);
  107. if ((omap_rev() >> 8) & 0x0f)
  108. pr_info("ES%x", (omap_rev() >> 12) & 0xf);
  109. pr_info("\n");
  110. }
  111. void __init omap34xx_check_revision(void)
  112. {
  113. u32 cpuid, idcode;
  114. u16 hawkeye;
  115. u8 rev;
  116. char *rev_name = "ES1.0";
  117. /*
  118. * We cannot access revision registers on ES1.0.
  119. * If the processor type is Cortex-A8 and the revision is 0x0
  120. * it means its Cortex r0p0 which is 3430 ES1.0.
  121. */
  122. cpuid = read_cpuid(CPUID_ID);
  123. if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
  124. omap_revision = OMAP3430_REV_ES1_0;
  125. goto out;
  126. }
  127. /*
  128. * Detection for 34xx ES2.0 and above can be done with just
  129. * hawkeye and rev. See TRM 1.5.2 Device Identification.
  130. * Note that rev does not map directly to our defined processor
  131. * revision numbers as ES1.0 uses value 0.
  132. */
  133. idcode = read_tap_reg(OMAP_TAP_IDCODE);
  134. hawkeye = (idcode >> 12) & 0xffff;
  135. rev = (idcode >> 28) & 0xff;
  136. if (hawkeye == 0xb7ae) {
  137. switch (rev) {
  138. case 0:
  139. omap_revision = OMAP3430_REV_ES2_0;
  140. rev_name = "ES2.0";
  141. break;
  142. case 2:
  143. omap_revision = OMAP3430_REV_ES2_1;
  144. rev_name = "ES2.1";
  145. break;
  146. case 3:
  147. omap_revision = OMAP3430_REV_ES3_0;
  148. rev_name = "ES3.0";
  149. break;
  150. case 4:
  151. omap_revision = OMAP3430_REV_ES3_1;
  152. rev_name = "ES3.1";
  153. break;
  154. default:
  155. /* Use the latest known revision as default */
  156. omap_revision = OMAP3430_REV_ES3_1;
  157. rev_name = "Unknown revision\n";
  158. }
  159. }
  160. out:
  161. pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
  162. }
  163. /*
  164. * Try to detect the exact revision of the omap we're running on
  165. */
  166. void __init omap2_check_revision(void)
  167. {
  168. /*
  169. * At this point we have an idea about the processor revision set
  170. * earlier with omap2_set_globals_tap().
  171. */
  172. if (cpu_is_omap24xx())
  173. omap24xx_check_revision();
  174. else if (cpu_is_omap34xx())
  175. omap34xx_check_revision();
  176. else
  177. pr_err("OMAP revision unknown, please fix!\n");
  178. /*
  179. * OK, now we know the exact revision. Initialize omap_chip bits
  180. * for powerdowmain and clockdomain code.
  181. */
  182. if (cpu_is_omap243x()) {
  183. /* Currently only supports 2430ES2.1 and 2430-all */
  184. omap_chip.oc |= CHIP_IS_OMAP2430;
  185. } else if (cpu_is_omap242x()) {
  186. /* Currently only supports 2420ES2.1.1 and 2420-all */
  187. omap_chip.oc |= CHIP_IS_OMAP2420;
  188. } else if (cpu_is_omap343x()) {
  189. omap_chip.oc = CHIP_IS_OMAP3430;
  190. if (omap_rev() == OMAP3430_REV_ES1_0)
  191. omap_chip.oc |= CHIP_IS_OMAP3430ES1;
  192. else if (omap_rev() > OMAP3430_REV_ES1_0)
  193. omap_chip.oc |= CHIP_IS_OMAP3430ES2;
  194. } else {
  195. pr_err("Uninitialized omap_chip, please fix!\n");
  196. }
  197. }
  198. /*
  199. * Set up things for map_io and processor detection later on. Gets called
  200. * pretty much first thing from board init. For multi-omap, this gets
  201. * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
  202. * detect the exact revision later on in omap2_detect_revision() once map_io
  203. * is done.
  204. */
  205. void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
  206. {
  207. omap_revision = omap2_globals->class;
  208. tap_base = omap2_globals->tap;
  209. if (cpu_is_omap34xx())
  210. tap_prod_id = 0x0210;
  211. else
  212. tap_prod_id = 0x0208;
  213. }