sn9c102_hv7131r.c 15 KB

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  1. /***************************************************************************
  2. * Plug-in for HV7131R image sensor connected to the SN9C1xx PC Camera *
  3. * Controllers *
  4. * *
  5. * Copyright (C) 2007 by Luca Risolia <luca.risolia@studio.unibo.it> *
  6. * *
  7. * This program is free software; you can redistribute it and/or modify *
  8. * it under the terms of the GNU General Public License as published by *
  9. * the Free Software Foundation; either version 2 of the License, or *
  10. * (at your option) any later version. *
  11. * *
  12. * This program is distributed in the hope that it will be useful, *
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  15. * GNU General Public License for more details. *
  16. * *
  17. * You should have received a copy of the GNU General Public License *
  18. * along with this program; if not, write to the Free Software *
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  20. ***************************************************************************/
  21. #include "sn9c102_sensor.h"
  22. static int hv7131r_init(struct sn9c102_device* cam)
  23. {
  24. int err = 0;
  25. switch (sn9c102_get_bridge(cam)) {
  26. case BRIDGE_SN9C103:
  27. err += sn9c102_write_reg(cam, 0x00, 0x03);
  28. err += sn9c102_write_reg(cam, 0x1a, 0x04);
  29. err += sn9c102_write_reg(cam, 0x20, 0x05);
  30. err += sn9c102_write_reg(cam, 0x20, 0x06);
  31. err += sn9c102_write_reg(cam, 0x03, 0x10);
  32. err += sn9c102_write_reg(cam, 0x00, 0x14);
  33. err += sn9c102_write_reg(cam, 0x60, 0x17);
  34. err += sn9c102_write_reg(cam, 0x0a, 0x18);
  35. err += sn9c102_write_reg(cam, 0xf0, 0x19);
  36. err += sn9c102_write_reg(cam, 0x1d, 0x1a);
  37. err += sn9c102_write_reg(cam, 0x10, 0x1b);
  38. err += sn9c102_write_reg(cam, 0x02, 0x1c);
  39. err += sn9c102_write_reg(cam, 0x03, 0x1d);
  40. err += sn9c102_write_reg(cam, 0x0f, 0x1e);
  41. err += sn9c102_write_reg(cam, 0x0c, 0x1f);
  42. err += sn9c102_write_reg(cam, 0x00, 0x20);
  43. err += sn9c102_write_reg(cam, 0x10, 0x21);
  44. err += sn9c102_write_reg(cam, 0x20, 0x22);
  45. err += sn9c102_write_reg(cam, 0x30, 0x23);
  46. err += sn9c102_write_reg(cam, 0x40, 0x24);
  47. err += sn9c102_write_reg(cam, 0x50, 0x25);
  48. err += sn9c102_write_reg(cam, 0x60, 0x26);
  49. err += sn9c102_write_reg(cam, 0x70, 0x27);
  50. err += sn9c102_write_reg(cam, 0x80, 0x28);
  51. err += sn9c102_write_reg(cam, 0x90, 0x29);
  52. err += sn9c102_write_reg(cam, 0xa0, 0x2a);
  53. err += sn9c102_write_reg(cam, 0xb0, 0x2b);
  54. err += sn9c102_write_reg(cam, 0xc0, 0x2c);
  55. err += sn9c102_write_reg(cam, 0xd0, 0x2d);
  56. err += sn9c102_write_reg(cam, 0xe0, 0x2e);
  57. err += sn9c102_write_reg(cam, 0xf0, 0x2f);
  58. err += sn9c102_write_reg(cam, 0xff, 0x30);
  59. break;
  60. case BRIDGE_SN9C105:
  61. case BRIDGE_SN9C120:
  62. err += sn9c102_write_reg(cam, 0x44, 0x01);
  63. err += sn9c102_write_reg(cam, 0x40, 0x02);
  64. err += sn9c102_write_reg(cam, 0x00, 0x03);
  65. err += sn9c102_write_reg(cam, 0x1a, 0x04);
  66. err += sn9c102_write_reg(cam, 0x44, 0x05);
  67. err += sn9c102_write_reg(cam, 0x3e, 0x06);
  68. err += sn9c102_write_reg(cam, 0x1a, 0x07);
  69. err += sn9c102_write_reg(cam, 0x03, 0x10);
  70. err += sn9c102_write_reg(cam, 0x08, 0x14);
  71. err += sn9c102_write_reg(cam, 0xa3, 0x17);
  72. err += sn9c102_write_reg(cam, 0x4b, 0x18);
  73. err += sn9c102_write_reg(cam, 0x00, 0x19);
  74. err += sn9c102_write_reg(cam, 0x1d, 0x1a);
  75. err += sn9c102_write_reg(cam, 0x10, 0x1b);
  76. err += sn9c102_write_reg(cam, 0x02, 0x1c);
  77. err += sn9c102_write_reg(cam, 0x03, 0x1d);
  78. err += sn9c102_write_reg(cam, 0x0f, 0x1e);
  79. err += sn9c102_write_reg(cam, 0x0c, 0x1f);
  80. err += sn9c102_write_reg(cam, 0x00, 0x20);
  81. err += sn9c102_write_reg(cam, 0x29, 0x21);
  82. err += sn9c102_write_reg(cam, 0x40, 0x22);
  83. err += sn9c102_write_reg(cam, 0x54, 0x23);
  84. err += sn9c102_write_reg(cam, 0x66, 0x24);
  85. err += sn9c102_write_reg(cam, 0x76, 0x25);
  86. err += sn9c102_write_reg(cam, 0x85, 0x26);
  87. err += sn9c102_write_reg(cam, 0x94, 0x27);
  88. err += sn9c102_write_reg(cam, 0xa1, 0x28);
  89. err += sn9c102_write_reg(cam, 0xae, 0x29);
  90. err += sn9c102_write_reg(cam, 0xbb, 0x2a);
  91. err += sn9c102_write_reg(cam, 0xc7, 0x2b);
  92. err += sn9c102_write_reg(cam, 0xd3, 0x2c);
  93. err += sn9c102_write_reg(cam, 0xde, 0x2d);
  94. err += sn9c102_write_reg(cam, 0xea, 0x2e);
  95. err += sn9c102_write_reg(cam, 0xf4, 0x2f);
  96. err += sn9c102_write_reg(cam, 0xff, 0x30);
  97. err += sn9c102_write_reg(cam, 0x00, 0x3F);
  98. err += sn9c102_write_reg(cam, 0xC7, 0x40);
  99. err += sn9c102_write_reg(cam, 0x01, 0x41);
  100. err += sn9c102_write_reg(cam, 0x44, 0x42);
  101. err += sn9c102_write_reg(cam, 0x00, 0x43);
  102. err += sn9c102_write_reg(cam, 0x44, 0x44);
  103. err += sn9c102_write_reg(cam, 0x00, 0x45);
  104. err += sn9c102_write_reg(cam, 0x44, 0x46);
  105. err += sn9c102_write_reg(cam, 0x00, 0x47);
  106. err += sn9c102_write_reg(cam, 0xC7, 0x48);
  107. err += sn9c102_write_reg(cam, 0x01, 0x49);
  108. err += sn9c102_write_reg(cam, 0xC7, 0x4A);
  109. err += sn9c102_write_reg(cam, 0x01, 0x4B);
  110. err += sn9c102_write_reg(cam, 0xC7, 0x4C);
  111. err += sn9c102_write_reg(cam, 0x01, 0x4D);
  112. err += sn9c102_write_reg(cam, 0x44, 0x4E);
  113. err += sn9c102_write_reg(cam, 0x00, 0x4F);
  114. err += sn9c102_write_reg(cam, 0x44, 0x50);
  115. err += sn9c102_write_reg(cam, 0x00, 0x51);
  116. err += sn9c102_write_reg(cam, 0x44, 0x52);
  117. err += sn9c102_write_reg(cam, 0x00, 0x53);
  118. err += sn9c102_write_reg(cam, 0xC7, 0x54);
  119. err += sn9c102_write_reg(cam, 0x01, 0x55);
  120. err += sn9c102_write_reg(cam, 0xC7, 0x56);
  121. err += sn9c102_write_reg(cam, 0x01, 0x57);
  122. err += sn9c102_write_reg(cam, 0xC7, 0x58);
  123. err += sn9c102_write_reg(cam, 0x01, 0x59);
  124. err += sn9c102_write_reg(cam, 0x44, 0x5A);
  125. err += sn9c102_write_reg(cam, 0x00, 0x5B);
  126. err += sn9c102_write_reg(cam, 0x44, 0x5C);
  127. err += sn9c102_write_reg(cam, 0x00, 0x5D);
  128. err += sn9c102_write_reg(cam, 0x44, 0x5E);
  129. err += sn9c102_write_reg(cam, 0x00, 0x5F);
  130. err += sn9c102_write_reg(cam, 0xC7, 0x60);
  131. err += sn9c102_write_reg(cam, 0x01, 0x61);
  132. err += sn9c102_write_reg(cam, 0xC7, 0x62);
  133. err += sn9c102_write_reg(cam, 0x01, 0x63);
  134. err += sn9c102_write_reg(cam, 0xC7, 0x64);
  135. err += sn9c102_write_reg(cam, 0x01, 0x65);
  136. err += sn9c102_write_reg(cam, 0x44, 0x66);
  137. err += sn9c102_write_reg(cam, 0x00, 0x67);
  138. err += sn9c102_write_reg(cam, 0x44, 0x68);
  139. err += sn9c102_write_reg(cam, 0x00, 0x69);
  140. err += sn9c102_write_reg(cam, 0x44, 0x6A);
  141. err += sn9c102_write_reg(cam, 0x00, 0x6B);
  142. err += sn9c102_write_reg(cam, 0xC7, 0x6C);
  143. err += sn9c102_write_reg(cam, 0x01, 0x6D);
  144. err += sn9c102_write_reg(cam, 0xC7, 0x6E);
  145. err += sn9c102_write_reg(cam, 0x01, 0x6F);
  146. err += sn9c102_write_reg(cam, 0xC7, 0x70);
  147. err += sn9c102_write_reg(cam, 0x01, 0x71);
  148. err += sn9c102_write_reg(cam, 0x44, 0x72);
  149. err += sn9c102_write_reg(cam, 0x00, 0x73);
  150. err += sn9c102_write_reg(cam, 0x44, 0x74);
  151. err += sn9c102_write_reg(cam, 0x00, 0x75);
  152. err += sn9c102_write_reg(cam, 0x44, 0x76);
  153. err += sn9c102_write_reg(cam, 0x00, 0x77);
  154. err += sn9c102_write_reg(cam, 0xC7, 0x78);
  155. err += sn9c102_write_reg(cam, 0x01, 0x79);
  156. err += sn9c102_write_reg(cam, 0xC7, 0x7A);
  157. err += sn9c102_write_reg(cam, 0x01, 0x7B);
  158. err += sn9c102_write_reg(cam, 0xC7, 0x7C);
  159. err += sn9c102_write_reg(cam, 0x01, 0x7D);
  160. err += sn9c102_write_reg(cam, 0x44, 0x7E);
  161. err += sn9c102_write_reg(cam, 0x00, 0x7F);
  162. err += sn9c102_write_reg(cam, 0x14, 0x84);
  163. err += sn9c102_write_reg(cam, 0x00, 0x85);
  164. err += sn9c102_write_reg(cam, 0x27, 0x86);
  165. err += sn9c102_write_reg(cam, 0x00, 0x87);
  166. err += sn9c102_write_reg(cam, 0x07, 0x88);
  167. err += sn9c102_write_reg(cam, 0x00, 0x89);
  168. err += sn9c102_write_reg(cam, 0xEC, 0x8A);
  169. err += sn9c102_write_reg(cam, 0x0f, 0x8B);
  170. err += sn9c102_write_reg(cam, 0xD8, 0x8C);
  171. err += sn9c102_write_reg(cam, 0x0f, 0x8D);
  172. err += sn9c102_write_reg(cam, 0x3D, 0x8E);
  173. err += sn9c102_write_reg(cam, 0x00, 0x8F);
  174. err += sn9c102_write_reg(cam, 0x3D, 0x90);
  175. err += sn9c102_write_reg(cam, 0x00, 0x91);
  176. err += sn9c102_write_reg(cam, 0xCD, 0x92);
  177. err += sn9c102_write_reg(cam, 0x0f, 0x93);
  178. err += sn9c102_write_reg(cam, 0xf7, 0x94);
  179. err += sn9c102_write_reg(cam, 0x0f, 0x95);
  180. err += sn9c102_write_reg(cam, 0x0C, 0x96);
  181. err += sn9c102_write_reg(cam, 0x00, 0x97);
  182. err += sn9c102_write_reg(cam, 0x00, 0x98);
  183. err += sn9c102_write_reg(cam, 0x66, 0x99);
  184. err += sn9c102_write_reg(cam, 0x05, 0x9A);
  185. err += sn9c102_write_reg(cam, 0x00, 0x9B);
  186. err += sn9c102_write_reg(cam, 0x04, 0x9C);
  187. err += sn9c102_write_reg(cam, 0x00, 0x9D);
  188. err += sn9c102_write_reg(cam, 0x08, 0x9E);
  189. err += sn9c102_write_reg(cam, 0x00, 0x9F);
  190. err += sn9c102_write_reg(cam, 0x2D, 0xC0);
  191. err += sn9c102_write_reg(cam, 0x2D, 0xC1);
  192. err += sn9c102_write_reg(cam, 0x3A, 0xC2);
  193. err += sn9c102_write_reg(cam, 0x05, 0xC3);
  194. err += sn9c102_write_reg(cam, 0x04, 0xC4);
  195. err += sn9c102_write_reg(cam, 0x3F, 0xC5);
  196. err += sn9c102_write_reg(cam, 0x00, 0xC6);
  197. err += sn9c102_write_reg(cam, 0x00, 0xC7);
  198. err += sn9c102_write_reg(cam, 0x50, 0xC8);
  199. err += sn9c102_write_reg(cam, 0x3C, 0xC9);
  200. err += sn9c102_write_reg(cam, 0x28, 0xCA);
  201. err += sn9c102_write_reg(cam, 0xD8, 0xCB);
  202. err += sn9c102_write_reg(cam, 0x14, 0xCC);
  203. err += sn9c102_write_reg(cam, 0xEC, 0xCD);
  204. err += sn9c102_write_reg(cam, 0x32, 0xCE);
  205. err += sn9c102_write_reg(cam, 0xDD, 0xCF);
  206. err += sn9c102_write_reg(cam, 0x32, 0xD0);
  207. err += sn9c102_write_reg(cam, 0xDD, 0xD1);
  208. err += sn9c102_write_reg(cam, 0x6A, 0xD2);
  209. err += sn9c102_write_reg(cam, 0x50, 0xD3);
  210. err += sn9c102_write_reg(cam, 0x00, 0xD4);
  211. err += sn9c102_write_reg(cam, 0x00, 0xD5);
  212. err += sn9c102_write_reg(cam, 0x00, 0xD6);
  213. break;
  214. default:
  215. break;
  216. }
  217. err += sn9c102_i2c_write(cam, 0x20, 0x00);
  218. err += sn9c102_i2c_write(cam, 0x21, 0xd6);
  219. err += sn9c102_i2c_write(cam, 0x25, 0x06);
  220. return err;
  221. }
  222. static int hv7131r_get_ctrl(struct sn9c102_device* cam,
  223. struct v4l2_control* ctrl)
  224. {
  225. switch (ctrl->id) {
  226. case V4L2_CID_GAIN:
  227. if ((ctrl->value = sn9c102_i2c_read(cam, 0x30)) < 0)
  228. return -EIO;
  229. return 0;
  230. case V4L2_CID_RED_BALANCE:
  231. if ((ctrl->value = sn9c102_i2c_read(cam, 0x31)) < 0)
  232. return -EIO;
  233. ctrl->value = ctrl->value & 0x3f;
  234. return 0;
  235. case V4L2_CID_BLUE_BALANCE:
  236. if ((ctrl->value = sn9c102_i2c_read(cam, 0x33)) < 0)
  237. return -EIO;
  238. ctrl->value = ctrl->value & 0x3f;
  239. return 0;
  240. case SN9C102_V4L2_CID_GREEN_BALANCE:
  241. if ((ctrl->value = sn9c102_i2c_read(cam, 0x32)) < 0)
  242. return -EIO;
  243. ctrl->value = ctrl->value & 0x3f;
  244. return 0;
  245. case V4L2_CID_BLACK_LEVEL:
  246. if ((ctrl->value = sn9c102_i2c_read(cam, 0x01)) < 0)
  247. return -EIO;
  248. ctrl->value = (ctrl->value & 0x08) ? 1 : 0;
  249. return 0;
  250. default:
  251. return -EINVAL;
  252. }
  253. }
  254. static int hv7131r_set_ctrl(struct sn9c102_device* cam,
  255. const struct v4l2_control* ctrl)
  256. {
  257. int err = 0;
  258. switch (ctrl->id) {
  259. case V4L2_CID_GAIN:
  260. err += sn9c102_i2c_write(cam, 0x30, ctrl->value);
  261. break;
  262. case V4L2_CID_RED_BALANCE:
  263. err += sn9c102_i2c_write(cam, 0x31, ctrl->value);
  264. break;
  265. case V4L2_CID_BLUE_BALANCE:
  266. err += sn9c102_i2c_write(cam, 0x33, ctrl->value);
  267. break;
  268. case SN9C102_V4L2_CID_GREEN_BALANCE:
  269. err += sn9c102_i2c_write(cam, 0x32, ctrl->value);
  270. break;
  271. case V4L2_CID_BLACK_LEVEL:
  272. {
  273. int r = sn9c102_i2c_read(cam, 0x01);
  274. if (r < 0)
  275. return -EIO;
  276. err += sn9c102_i2c_write(cam, 0x01,
  277. (ctrl->value<<3) | (r&0xf7));
  278. }
  279. break;
  280. default:
  281. return -EINVAL;
  282. }
  283. return err ? -EIO : 0;
  284. }
  285. static int hv7131r_set_crop(struct sn9c102_device* cam,
  286. const struct v4l2_rect* rect)
  287. {
  288. struct sn9c102_sensor* s = sn9c102_get_sensor(cam);
  289. int err = 0;
  290. u8 h_start = (u8)(rect->left - s->cropcap.bounds.left) + 1,
  291. v_start = (u8)(rect->top - s->cropcap.bounds.top) + 1;
  292. err += sn9c102_write_reg(cam, h_start, 0x12);
  293. err += sn9c102_write_reg(cam, v_start, 0x13);
  294. return err;
  295. }
  296. static int hv7131r_set_pix_format(struct sn9c102_device* cam,
  297. const struct v4l2_pix_format* pix)
  298. {
  299. int err = 0;
  300. switch (sn9c102_get_bridge(cam)) {
  301. case BRIDGE_SN9C103:
  302. if (pix->pixelformat == V4L2_PIX_FMT_SBGGR8) {
  303. err += sn9c102_write_reg(cam, 0xa0, 0x19);
  304. err += sn9c102_i2c_write(cam, 0x01, 0x04);
  305. } else {
  306. err += sn9c102_write_reg(cam, 0x30, 0x19);
  307. err += sn9c102_i2c_write(cam, 0x01, 0x04);
  308. }
  309. break;
  310. case BRIDGE_SN9C105:
  311. case BRIDGE_SN9C120:
  312. if (pix->pixelformat == V4L2_PIX_FMT_SBGGR8) {
  313. err += sn9c102_write_reg(cam, 0xa5, 0x17);
  314. err += sn9c102_i2c_write(cam, 0x01, 0x24);
  315. } else {
  316. err += sn9c102_write_reg(cam, 0xa3, 0x17);
  317. err += sn9c102_i2c_write(cam, 0x01, 0x04);
  318. }
  319. break;
  320. default:
  321. break;
  322. }
  323. return err;
  324. }
  325. static struct sn9c102_sensor hv7131r = {
  326. .name = "HV7131R",
  327. .maintainer = "Luca Risolia <luca.risolia@studio.unibo.it>",
  328. .supported_bridge = BRIDGE_SN9C103 | BRIDGE_SN9C105 | BRIDGE_SN9C120,
  329. .sysfs_ops = SN9C102_I2C_READ | SN9C102_I2C_WRITE,
  330. .frequency = SN9C102_I2C_100KHZ,
  331. .interface = SN9C102_I2C_2WIRES,
  332. .i2c_slave_id = 0x11,
  333. .init = &hv7131r_init,
  334. .qctrl = {
  335. {
  336. .id = V4L2_CID_GAIN,
  337. .type = V4L2_CTRL_TYPE_INTEGER,
  338. .name = "global gain",
  339. .minimum = 0x00,
  340. .maximum = 0xff,
  341. .step = 0x01,
  342. .default_value = 0x40,
  343. .flags = 0,
  344. },
  345. {
  346. .id = V4L2_CID_RED_BALANCE,
  347. .type = V4L2_CTRL_TYPE_INTEGER,
  348. .name = "red balance",
  349. .minimum = 0x00,
  350. .maximum = 0x3f,
  351. .step = 0x01,
  352. .default_value = 0x08,
  353. .flags = 0,
  354. },
  355. {
  356. .id = V4L2_CID_BLUE_BALANCE,
  357. .type = V4L2_CTRL_TYPE_INTEGER,
  358. .name = "blue balance",
  359. .minimum = 0x00,
  360. .maximum = 0x3f,
  361. .step = 0x01,
  362. .default_value = 0x1a,
  363. .flags = 0,
  364. },
  365. {
  366. .id = SN9C102_V4L2_CID_GREEN_BALANCE,
  367. .type = V4L2_CTRL_TYPE_INTEGER,
  368. .name = "green balance",
  369. .minimum = 0x00,
  370. .maximum = 0x3f,
  371. .step = 0x01,
  372. .default_value = 0x2f,
  373. .flags = 0,
  374. },
  375. {
  376. .id = V4L2_CID_BLACK_LEVEL,
  377. .type = V4L2_CTRL_TYPE_BOOLEAN,
  378. .name = "auto black level compensation",
  379. .minimum = 0x00,
  380. .maximum = 0x01,
  381. .step = 0x01,
  382. .default_value = 0x00,
  383. .flags = 0,
  384. },
  385. },
  386. .get_ctrl = &hv7131r_get_ctrl,
  387. .set_ctrl = &hv7131r_set_ctrl,
  388. .cropcap = {
  389. .bounds = {
  390. .left = 0,
  391. .top = 0,
  392. .width = 640,
  393. .height = 480,
  394. },
  395. .defrect = {
  396. .left = 0,
  397. .top = 0,
  398. .width = 640,
  399. .height = 480,
  400. },
  401. },
  402. .set_crop = &hv7131r_set_crop,
  403. .pix_format = {
  404. .width = 640,
  405. .height = 480,
  406. .pixelformat = V4L2_PIX_FMT_SBGGR8,
  407. .priv = 8,
  408. },
  409. .set_pix_format = &hv7131r_set_pix_format
  410. };
  411. int sn9c102_probe_hv7131r(struct sn9c102_device* cam)
  412. {
  413. int devid, err = 0;
  414. err += sn9c102_write_reg(cam, 0x09, 0x01);
  415. err += sn9c102_write_reg(cam, 0x44, 0x02);
  416. err += sn9c102_write_reg(cam, 0x34, 0x01);
  417. err += sn9c102_write_reg(cam, 0x20, 0x17);
  418. err += sn9c102_write_reg(cam, 0x34, 0x01);
  419. err += sn9c102_write_reg(cam, 0x46, 0x01);
  420. if (err)
  421. return -EIO;
  422. devid = sn9c102_i2c_try_read(cam, &hv7131r, 0x00);
  423. if (devid < 0)
  424. return -EIO;
  425. if (devid != 0x02)
  426. return -ENODEV;
  427. sn9c102_attach_sensor(cam, &hv7131r);
  428. return 0;
  429. }