vpx3220.c 15 KB

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  1. /*
  2. * vpx3220a, vpx3216b & vpx3214c video decoder driver version 0.0.1
  3. *
  4. * Copyright (C) 2001 Laurent Pinchart <lpinchart@freegates.be>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/delay.h>
  23. #include <linux/types.h>
  24. #include <asm/uaccess.h>
  25. #include <linux/i2c.h>
  26. #include <linux/videodev2.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-chip-ident.h>
  29. #include <media/v4l2-i2c-drv.h>
  30. MODULE_DESCRIPTION("vpx3220a/vpx3216b/vpx3214c video decoder driver");
  31. MODULE_AUTHOR("Laurent Pinchart");
  32. MODULE_LICENSE("GPL");
  33. static int debug;
  34. module_param(debug, int, 0);
  35. MODULE_PARM_DESC(debug, "Debug level (0-1)");
  36. #define VPX_TIMEOUT_COUNT 10
  37. /* ----------------------------------------------------------------------- */
  38. struct vpx3220 {
  39. struct v4l2_subdev sd;
  40. unsigned char reg[255];
  41. v4l2_std_id norm;
  42. int ident;
  43. int input;
  44. int enable;
  45. int bright;
  46. int contrast;
  47. int hue;
  48. int sat;
  49. };
  50. static inline struct vpx3220 *to_vpx3220(struct v4l2_subdev *sd)
  51. {
  52. return container_of(sd, struct vpx3220, sd);
  53. }
  54. static char *inputs[] = { "internal", "composite", "svideo" };
  55. /* ----------------------------------------------------------------------- */
  56. static inline int vpx3220_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  57. {
  58. struct i2c_client *client = v4l2_get_subdevdata(sd);
  59. struct vpx3220 *decoder = i2c_get_clientdata(client);
  60. decoder->reg[reg] = value;
  61. return i2c_smbus_write_byte_data(client, reg, value);
  62. }
  63. static inline int vpx3220_read(struct v4l2_subdev *sd, u8 reg)
  64. {
  65. struct i2c_client *client = v4l2_get_subdevdata(sd);
  66. return i2c_smbus_read_byte_data(client, reg);
  67. }
  68. static int vpx3220_fp_status(struct v4l2_subdev *sd)
  69. {
  70. unsigned char status;
  71. unsigned int i;
  72. for (i = 0; i < VPX_TIMEOUT_COUNT; i++) {
  73. status = vpx3220_read(sd, 0x29);
  74. if (!(status & 4))
  75. return 0;
  76. udelay(10);
  77. if (need_resched())
  78. cond_resched();
  79. }
  80. return -1;
  81. }
  82. static int vpx3220_fp_write(struct v4l2_subdev *sd, u8 fpaddr, u16 data)
  83. {
  84. struct i2c_client *client = v4l2_get_subdevdata(sd);
  85. /* Write the 16-bit address to the FPWR register */
  86. if (i2c_smbus_write_word_data(client, 0x27, swab16(fpaddr)) == -1) {
  87. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  88. return -1;
  89. }
  90. if (vpx3220_fp_status(sd) < 0)
  91. return -1;
  92. /* Write the 16-bit data to the FPDAT register */
  93. if (i2c_smbus_write_word_data(client, 0x28, swab16(data)) == -1) {
  94. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  95. return -1;
  96. }
  97. return 0;
  98. }
  99. static u16 vpx3220_fp_read(struct v4l2_subdev *sd, u16 fpaddr)
  100. {
  101. struct i2c_client *client = v4l2_get_subdevdata(sd);
  102. s16 data;
  103. /* Write the 16-bit address to the FPRD register */
  104. if (i2c_smbus_write_word_data(client, 0x26, swab16(fpaddr)) == -1) {
  105. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  106. return -1;
  107. }
  108. if (vpx3220_fp_status(sd) < 0)
  109. return -1;
  110. /* Read the 16-bit data from the FPDAT register */
  111. data = i2c_smbus_read_word_data(client, 0x28);
  112. if (data == -1) {
  113. v4l2_dbg(1, debug, sd, "%s: failed\n", __func__);
  114. return -1;
  115. }
  116. return swab16(data);
  117. }
  118. static int vpx3220_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
  119. {
  120. u8 reg;
  121. int ret = -1;
  122. while (len >= 2) {
  123. reg = *data++;
  124. ret = vpx3220_write(sd, reg, *data++);
  125. if (ret < 0)
  126. break;
  127. len -= 2;
  128. }
  129. return ret;
  130. }
  131. static int vpx3220_write_fp_block(struct v4l2_subdev *sd,
  132. const u16 *data, unsigned int len)
  133. {
  134. u8 reg;
  135. int ret = 0;
  136. while (len > 1) {
  137. reg = *data++;
  138. ret |= vpx3220_fp_write(sd, reg, *data++);
  139. len -= 2;
  140. }
  141. return ret;
  142. }
  143. /* ---------------------------------------------------------------------- */
  144. static const unsigned short init_ntsc[] = {
  145. 0x1c, 0x00, /* NTSC tint angle */
  146. 0x88, 17, /* Window 1 vertical */
  147. 0x89, 240, /* Vertical lines in */
  148. 0x8a, 240, /* Vertical lines out */
  149. 0x8b, 000, /* Horizontal begin */
  150. 0x8c, 640, /* Horizontal length */
  151. 0x8d, 640, /* Number of pixels */
  152. 0x8f, 0xc00, /* Disable window 2 */
  153. 0xf0, 0x73, /* 13.5 MHz transport, Forced
  154. * mode, latch windows */
  155. 0xf2, 0x13, /* NTSC M, composite input */
  156. 0xe7, 0x1e1, /* Enable vertical standard
  157. * locking @ 240 lines */
  158. };
  159. static const unsigned short init_pal[] = {
  160. 0x88, 23, /* Window 1 vertical begin */
  161. 0x89, 288, /* Vertical lines in (16 lines
  162. * skipped by the VFE) */
  163. 0x8a, 288, /* Vertical lines out (16 lines
  164. * skipped by the VFE) */
  165. 0x8b, 16, /* Horizontal begin */
  166. 0x8c, 768, /* Horizontal length */
  167. 0x8d, 784, /* Number of pixels
  168. * Must be >= Horizontal begin + Horizontal length */
  169. 0x8f, 0xc00, /* Disable window 2 */
  170. 0xf0, 0x77, /* 13.5 MHz transport, Forced
  171. * mode, latch windows */
  172. 0xf2, 0x3d1, /* PAL B,G,H,I, composite input */
  173. 0xe7, 0x241, /* PAL/SECAM set to 288 lines */
  174. };
  175. static const unsigned short init_secam[] = {
  176. 0x88, 23, /* Window 1 vertical begin */
  177. 0x89, 288, /* Vertical lines in (16 lines
  178. * skipped by the VFE) */
  179. 0x8a, 288, /* Vertical lines out (16 lines
  180. * skipped by the VFE) */
  181. 0x8b, 16, /* Horizontal begin */
  182. 0x8c, 768, /* Horizontal length */
  183. 0x8d, 784, /* Number of pixels
  184. * Must be >= Horizontal begin + Horizontal length */
  185. 0x8f, 0xc00, /* Disable window 2 */
  186. 0xf0, 0x77, /* 13.5 MHz transport, Forced
  187. * mode, latch windows */
  188. 0xf2, 0x3d5, /* SECAM, composite input */
  189. 0xe7, 0x241, /* PAL/SECAM set to 288 lines */
  190. };
  191. static const unsigned char init_common[] = {
  192. 0xf2, 0x00, /* Disable all outputs */
  193. 0x33, 0x0d, /* Luma : VIN2, Chroma : CIN
  194. * (clamp off) */
  195. 0xd8, 0xa8, /* HREF/VREF active high, VREF
  196. * pulse = 2, Odd/Even flag */
  197. 0x20, 0x03, /* IF compensation 0dB/oct */
  198. 0xe0, 0xff, /* Open up all comparators */
  199. 0xe1, 0x00,
  200. 0xe2, 0x7f,
  201. 0xe3, 0x80,
  202. 0xe4, 0x7f,
  203. 0xe5, 0x80,
  204. 0xe6, 0x00, /* Brightness set to 0 */
  205. 0xe7, 0xe0, /* Contrast to 1.0, noise shaping
  206. * 10 to 8 2-bit error diffusion */
  207. 0xe8, 0xf8, /* YUV422, CbCr binary offset,
  208. * ... (p.32) */
  209. 0xea, 0x18, /* LLC2 connected, output FIFO
  210. * reset with VACTintern */
  211. 0xf0, 0x8a, /* Half full level to 10, bus
  212. * shuffler [7:0, 23:16, 15:8] */
  213. 0xf1, 0x18, /* Single clock, sync mode, no
  214. * FE delay, no HLEN counter */
  215. 0xf8, 0x12, /* Port A, PIXCLK, HF# & FE#
  216. * strength to 2 */
  217. 0xf9, 0x24, /* Port B, HREF, VREF, PREF &
  218. * ALPHA strength to 4 */
  219. };
  220. static const unsigned short init_fp[] = {
  221. 0x59, 0,
  222. 0xa0, 2070, /* ACC reference */
  223. 0xa3, 0,
  224. 0xa4, 0,
  225. 0xa8, 30,
  226. 0xb2, 768,
  227. 0xbe, 27,
  228. 0x58, 0,
  229. 0x26, 0,
  230. 0x4b, 0x298, /* PLL gain */
  231. };
  232. static int vpx3220_init(struct v4l2_subdev *sd, u32 val)
  233. {
  234. struct vpx3220 *decoder = to_vpx3220(sd);
  235. vpx3220_write_block(sd, init_common, sizeof(init_common));
  236. vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
  237. if (decoder->norm & V4L2_STD_NTSC)
  238. vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
  239. else if (decoder->norm & V4L2_STD_PAL)
  240. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  241. else if (decoder->norm & V4L2_STD_SECAM)
  242. vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
  243. else
  244. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  245. return 0;
  246. }
  247. static int vpx3220_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)
  248. {
  249. int res = V4L2_IN_ST_NO_SIGNAL, status;
  250. v4l2_std_id std = 0;
  251. status = vpx3220_fp_read(sd, 0x0f3);
  252. v4l2_dbg(1, debug, sd, "status: 0x%04x\n", status);
  253. if (status < 0)
  254. return status;
  255. if ((status & 0x20) == 0) {
  256. res = 0;
  257. switch (status & 0x18) {
  258. case 0x00:
  259. case 0x10:
  260. case 0x14:
  261. case 0x18:
  262. std = V4L2_STD_PAL;
  263. break;
  264. case 0x08:
  265. std = V4L2_STD_SECAM;
  266. break;
  267. case 0x04:
  268. case 0x0c:
  269. case 0x1c:
  270. std = V4L2_STD_NTSC;
  271. break;
  272. }
  273. }
  274. if (pstd)
  275. *pstd = std;
  276. if (pstatus)
  277. *pstatus = status;
  278. return 0;
  279. }
  280. static int vpx3220_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  281. {
  282. v4l2_dbg(1, debug, sd, "querystd\n");
  283. return vpx3220_status(sd, NULL, std);
  284. }
  285. static int vpx3220_g_input_status(struct v4l2_subdev *sd, u32 *status)
  286. {
  287. v4l2_dbg(1, debug, sd, "g_input_status\n");
  288. return vpx3220_status(sd, status, NULL);
  289. }
  290. static int vpx3220_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  291. {
  292. struct vpx3220 *decoder = to_vpx3220(sd);
  293. int temp_input;
  294. /* Here we back up the input selection because it gets
  295. overwritten when we fill the registers with the
  296. choosen video norm */
  297. temp_input = vpx3220_fp_read(sd, 0xf2);
  298. v4l2_dbg(1, debug, sd, "s_std %llx\n", (unsigned long long)std);
  299. if (std & V4L2_STD_NTSC) {
  300. vpx3220_write_fp_block(sd, init_ntsc, sizeof(init_ntsc) >> 1);
  301. v4l2_dbg(1, debug, sd, "norm switched to NTSC\n");
  302. } else if (std & V4L2_STD_PAL) {
  303. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  304. v4l2_dbg(1, debug, sd, "norm switched to PAL\n");
  305. } else if (std & V4L2_STD_SECAM) {
  306. vpx3220_write_fp_block(sd, init_secam, sizeof(init_secam) >> 1);
  307. v4l2_dbg(1, debug, sd, "norm switched to SECAM\n");
  308. } else {
  309. return -EINVAL;
  310. }
  311. decoder->norm = std;
  312. /* And here we set the backed up video input again */
  313. vpx3220_fp_write(sd, 0xf2, temp_input | 0x0010);
  314. udelay(10);
  315. return 0;
  316. }
  317. static int vpx3220_s_routing(struct v4l2_subdev *sd, const struct v4l2_routing *route)
  318. {
  319. int data;
  320. /* RJ: route->input = 0: ST8 (PCTV) input
  321. route->input = 1: COMPOSITE input
  322. route->input = 2: SVHS input */
  323. const int input[3][2] = {
  324. {0x0c, 0},
  325. {0x0d, 0},
  326. {0x0e, 1}
  327. };
  328. if (route->input < 0 || route->input > 2)
  329. return -EINVAL;
  330. v4l2_dbg(1, debug, sd, "input switched to %s\n", inputs[route->input]);
  331. vpx3220_write(sd, 0x33, input[route->input][0]);
  332. data = vpx3220_fp_read(sd, 0xf2) & ~(0x0020);
  333. if (data < 0)
  334. return data;
  335. /* 0x0010 is required to latch the setting */
  336. vpx3220_fp_write(sd, 0xf2,
  337. data | (input[route->input][1] << 5) | 0x0010);
  338. udelay(10);
  339. return 0;
  340. }
  341. static int vpx3220_s_stream(struct v4l2_subdev *sd, int enable)
  342. {
  343. v4l2_dbg(1, debug, sd, "s_stream %s\n", enable ? "on" : "off");
  344. vpx3220_write(sd, 0xf2, (enable ? 0x1b : 0x00));
  345. return 0;
  346. }
  347. static int vpx3220_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
  348. {
  349. switch (qc->id) {
  350. case V4L2_CID_BRIGHTNESS:
  351. v4l2_ctrl_query_fill(qc, -128, 127, 1, 0);
  352. break;
  353. case V4L2_CID_CONTRAST:
  354. v4l2_ctrl_query_fill(qc, 0, 63, 1, 32);
  355. break;
  356. case V4L2_CID_SATURATION:
  357. v4l2_ctrl_query_fill(qc, 0, 4095, 1, 2048);
  358. break;
  359. case V4L2_CID_HUE:
  360. v4l2_ctrl_query_fill(qc, -512, 511, 1, 0);
  361. break;
  362. default:
  363. return -EINVAL;
  364. }
  365. return 0;
  366. }
  367. static int vpx3220_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  368. {
  369. struct vpx3220 *decoder = to_vpx3220(sd);
  370. switch (ctrl->id) {
  371. case V4L2_CID_BRIGHTNESS:
  372. ctrl->value = decoder->bright;
  373. break;
  374. case V4L2_CID_CONTRAST:
  375. ctrl->value = decoder->contrast;
  376. break;
  377. case V4L2_CID_SATURATION:
  378. ctrl->value = decoder->sat;
  379. break;
  380. case V4L2_CID_HUE:
  381. ctrl->value = decoder->hue;
  382. break;
  383. default:
  384. return -EINVAL;
  385. }
  386. return 0;
  387. }
  388. static int vpx3220_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
  389. {
  390. struct vpx3220 *decoder = to_vpx3220(sd);
  391. switch (ctrl->id) {
  392. case V4L2_CID_BRIGHTNESS:
  393. if (decoder->bright != ctrl->value) {
  394. decoder->bright = ctrl->value;
  395. vpx3220_write(sd, 0xe6, decoder->bright);
  396. }
  397. break;
  398. case V4L2_CID_CONTRAST:
  399. if (decoder->contrast != ctrl->value) {
  400. /* Bit 7 and 8 is for noise shaping */
  401. decoder->contrast = ctrl->value;
  402. vpx3220_write(sd, 0xe7, decoder->contrast + 192);
  403. }
  404. break;
  405. case V4L2_CID_SATURATION:
  406. if (decoder->sat != ctrl->value) {
  407. decoder->sat = ctrl->value;
  408. vpx3220_fp_write(sd, 0xa0, decoder->sat);
  409. }
  410. break;
  411. case V4L2_CID_HUE:
  412. if (decoder->hue != ctrl->value) {
  413. decoder->hue = ctrl->value;
  414. vpx3220_fp_write(sd, 0x1c, decoder->hue);
  415. }
  416. break;
  417. default:
  418. return -EINVAL;
  419. }
  420. return 0;
  421. }
  422. static int vpx3220_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
  423. {
  424. struct vpx3220 *decoder = to_vpx3220(sd);
  425. struct i2c_client *client = v4l2_get_subdevdata(sd);
  426. return v4l2_chip_ident_i2c_client(client, chip, decoder->ident, 0);
  427. }
  428. /* ----------------------------------------------------------------------- */
  429. static const struct v4l2_subdev_core_ops vpx3220_core_ops = {
  430. .g_chip_ident = vpx3220_g_chip_ident,
  431. .init = vpx3220_init,
  432. .g_ctrl = vpx3220_g_ctrl,
  433. .s_ctrl = vpx3220_s_ctrl,
  434. .queryctrl = vpx3220_queryctrl,
  435. .s_std = vpx3220_s_std,
  436. };
  437. static const struct v4l2_subdev_video_ops vpx3220_video_ops = {
  438. .s_routing = vpx3220_s_routing,
  439. .s_stream = vpx3220_s_stream,
  440. .querystd = vpx3220_querystd,
  441. .g_input_status = vpx3220_g_input_status,
  442. };
  443. static const struct v4l2_subdev_ops vpx3220_ops = {
  444. .core = &vpx3220_core_ops,
  445. .video = &vpx3220_video_ops,
  446. };
  447. /* -----------------------------------------------------------------------
  448. * Client management code
  449. */
  450. static int vpx3220_probe(struct i2c_client *client,
  451. const struct i2c_device_id *id)
  452. {
  453. struct vpx3220 *decoder;
  454. struct v4l2_subdev *sd;
  455. const char *name = NULL;
  456. u8 ver;
  457. u16 pn;
  458. /* Check if the adapter supports the needed features */
  459. if (!i2c_check_functionality(client->adapter,
  460. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
  461. return -ENODEV;
  462. decoder = kzalloc(sizeof(struct vpx3220), GFP_KERNEL);
  463. if (decoder == NULL)
  464. return -ENOMEM;
  465. sd = &decoder->sd;
  466. v4l2_i2c_subdev_init(sd, client, &vpx3220_ops);
  467. decoder->norm = V4L2_STD_PAL;
  468. decoder->input = 0;
  469. decoder->enable = 1;
  470. decoder->bright = 32768;
  471. decoder->contrast = 32768;
  472. decoder->hue = 32768;
  473. decoder->sat = 32768;
  474. ver = i2c_smbus_read_byte_data(client, 0x00);
  475. pn = (i2c_smbus_read_byte_data(client, 0x02) << 8) +
  476. i2c_smbus_read_byte_data(client, 0x01);
  477. decoder->ident = V4L2_IDENT_VPX3220A;
  478. if (ver == 0xec) {
  479. switch (pn) {
  480. case 0x4680:
  481. name = "vpx3220a";
  482. break;
  483. case 0x4260:
  484. name = "vpx3216b";
  485. decoder->ident = V4L2_IDENT_VPX3216B;
  486. break;
  487. case 0x4280:
  488. name = "vpx3214c";
  489. decoder->ident = V4L2_IDENT_VPX3214C;
  490. break;
  491. }
  492. }
  493. if (name)
  494. v4l2_info(sd, "%s found @ 0x%x (%s)\n", name,
  495. client->addr << 1, client->adapter->name);
  496. else
  497. v4l2_info(sd, "chip (%02x:%04x) found @ 0x%x (%s)\n",
  498. ver, pn, client->addr << 1, client->adapter->name);
  499. vpx3220_write_block(sd, init_common, sizeof(init_common));
  500. vpx3220_write_fp_block(sd, init_fp, sizeof(init_fp) >> 1);
  501. /* Default to PAL */
  502. vpx3220_write_fp_block(sd, init_pal, sizeof(init_pal) >> 1);
  503. return 0;
  504. }
  505. static int vpx3220_remove(struct i2c_client *client)
  506. {
  507. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  508. v4l2_device_unregister_subdev(sd);
  509. kfree(to_vpx3220(sd));
  510. return 0;
  511. }
  512. static const struct i2c_device_id vpx3220_id[] = {
  513. { "vpx3220a", 0 },
  514. { "vpx3216b", 0 },
  515. { "vpx3214c", 0 },
  516. { }
  517. };
  518. MODULE_DEVICE_TABLE(i2c, vpx3220_id);
  519. static struct v4l2_i2c_driver_data v4l2_i2c_data = {
  520. .name = "vpx3220",
  521. .probe = vpx3220_probe,
  522. .remove = vpx3220_remove,
  523. .id_table = vpx3220_id,
  524. };