setup-r8a7779.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231
  1. /*
  2. * r8a7779 processor support
  3. *
  4. * Copyright (C) 2011 Renesas Solutions Corp.
  5. * Copyright (C) 2011 Magnus Damm
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/delay.h>
  26. #include <linux/input.h>
  27. #include <linux/io.h>
  28. #include <linux/serial_sci.h>
  29. #include <linux/sh_intc.h>
  30. #include <linux/sh_timer.h>
  31. #include <mach/hardware.h>
  32. #include <mach/r8a7779.h>
  33. #include <asm/mach-types.h>
  34. #include <asm/mach/arch.h>
  35. static struct plat_sci_port scif0_platform_data = {
  36. .mapbase = 0xffe40000,
  37. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  38. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  39. .scbrr_algo_id = SCBRR_ALGO_2,
  40. .type = PORT_SCIF,
  41. .irqs = { gic_spi(88), gic_spi(88),
  42. gic_spi(88), gic_spi(88) },
  43. };
  44. static struct platform_device scif0_device = {
  45. .name = "sh-sci",
  46. .id = 0,
  47. .dev = {
  48. .platform_data = &scif0_platform_data,
  49. },
  50. };
  51. static struct plat_sci_port scif1_platform_data = {
  52. .mapbase = 0xffe41000,
  53. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  54. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  55. .scbrr_algo_id = SCBRR_ALGO_2,
  56. .type = PORT_SCIF,
  57. .irqs = { gic_spi(89), gic_spi(89),
  58. gic_spi(89), gic_spi(89) },
  59. };
  60. static struct platform_device scif1_device = {
  61. .name = "sh-sci",
  62. .id = 1,
  63. .dev = {
  64. .platform_data = &scif1_platform_data,
  65. },
  66. };
  67. static struct plat_sci_port scif2_platform_data = {
  68. .mapbase = 0xffe42000,
  69. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  70. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  71. .scbrr_algo_id = SCBRR_ALGO_2,
  72. .type = PORT_SCIF,
  73. .irqs = { gic_spi(90), gic_spi(90),
  74. gic_spi(90), gic_spi(90) },
  75. };
  76. static struct platform_device scif2_device = {
  77. .name = "sh-sci",
  78. .id = 2,
  79. .dev = {
  80. .platform_data = &scif2_platform_data,
  81. },
  82. };
  83. static struct plat_sci_port scif3_platform_data = {
  84. .mapbase = 0xffe43000,
  85. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  86. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  87. .scbrr_algo_id = SCBRR_ALGO_2,
  88. .type = PORT_SCIF,
  89. .irqs = { gic_spi(91), gic_spi(91),
  90. gic_spi(91), gic_spi(91) },
  91. };
  92. static struct platform_device scif3_device = {
  93. .name = "sh-sci",
  94. .id = 3,
  95. .dev = {
  96. .platform_data = &scif3_platform_data,
  97. },
  98. };
  99. static struct plat_sci_port scif4_platform_data = {
  100. .mapbase = 0xffe44000,
  101. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  102. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  103. .scbrr_algo_id = SCBRR_ALGO_2,
  104. .type = PORT_SCIF,
  105. .irqs = { gic_spi(92), gic_spi(92),
  106. gic_spi(92), gic_spi(92) },
  107. };
  108. static struct platform_device scif4_device = {
  109. .name = "sh-sci",
  110. .id = 4,
  111. .dev = {
  112. .platform_data = &scif4_platform_data,
  113. },
  114. };
  115. static struct plat_sci_port scif5_platform_data = {
  116. .mapbase = 0xffe45000,
  117. .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
  118. .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  119. .scbrr_algo_id = SCBRR_ALGO_2,
  120. .type = PORT_SCIF,
  121. .irqs = { gic_spi(93), gic_spi(93),
  122. gic_spi(93), gic_spi(93) },
  123. };
  124. static struct platform_device scif5_device = {
  125. .name = "sh-sci",
  126. .id = 5,
  127. .dev = {
  128. .platform_data = &scif5_platform_data,
  129. },
  130. };
  131. /* TMU */
  132. static struct sh_timer_config tmu00_platform_data = {
  133. .name = "TMU00",
  134. .channel_offset = 0x4,
  135. .timer_bit = 0,
  136. .clockevent_rating = 200,
  137. };
  138. static struct resource tmu00_resources[] = {
  139. [0] = {
  140. .name = "TMU00",
  141. .start = 0xffd80008,
  142. .end = 0xffd80013,
  143. .flags = IORESOURCE_MEM,
  144. },
  145. [1] = {
  146. .start = gic_spi(32),
  147. .flags = IORESOURCE_IRQ,
  148. },
  149. };
  150. static struct platform_device tmu00_device = {
  151. .name = "sh_tmu",
  152. .id = 0,
  153. .dev = {
  154. .platform_data = &tmu00_platform_data,
  155. },
  156. .resource = tmu00_resources,
  157. .num_resources = ARRAY_SIZE(tmu00_resources),
  158. };
  159. static struct sh_timer_config tmu01_platform_data = {
  160. .name = "TMU01",
  161. .channel_offset = 0x10,
  162. .timer_bit = 1,
  163. .clocksource_rating = 200,
  164. };
  165. static struct resource tmu01_resources[] = {
  166. [0] = {
  167. .name = "TMU01",
  168. .start = 0xffd80014,
  169. .end = 0xffd8001f,
  170. .flags = IORESOURCE_MEM,
  171. },
  172. [1] = {
  173. .start = gic_spi(33),
  174. .flags = IORESOURCE_IRQ,
  175. },
  176. };
  177. static struct platform_device tmu01_device = {
  178. .name = "sh_tmu",
  179. .id = 1,
  180. .dev = {
  181. .platform_data = &tmu01_platform_data,
  182. },
  183. .resource = tmu01_resources,
  184. .num_resources = ARRAY_SIZE(tmu01_resources),
  185. };
  186. static struct platform_device *r8a7779_early_devices[] __initdata = {
  187. &scif0_device,
  188. &scif1_device,
  189. &scif2_device,
  190. &scif3_device,
  191. &scif4_device,
  192. &scif5_device,
  193. &tmu00_device,
  194. &tmu01_device,
  195. };
  196. static struct platform_device *r8a7779_late_devices[] __initdata = {
  197. };
  198. void __init r8a7779_add_standard_devices(void)
  199. {
  200. platform_add_devices(r8a7779_early_devices,
  201. ARRAY_SIZE(r8a7779_early_devices));
  202. platform_add_devices(r8a7779_late_devices,
  203. ARRAY_SIZE(r8a7779_late_devices));
  204. }
  205. void __init r8a7779_add_early_devices(void)
  206. {
  207. early_platform_add_devices(r8a7779_early_devices,
  208. ARRAY_SIZE(r8a7779_early_devices));
  209. }