be_main.c 68 KB

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  1. /*
  2. * Copyright (C) 2005 - 2010 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. static unsigned int num_vfs;
  27. module_param(rx_frag_size, uint, S_IRUGO);
  28. module_param(num_vfs, uint, S_IRUGO);
  29. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  30. MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
  31. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  32. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  33. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  34. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  35. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  36. { 0 }
  37. };
  38. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  39. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  40. {
  41. struct be_dma_mem *mem = &q->dma_mem;
  42. if (mem->va)
  43. pci_free_consistent(adapter->pdev, mem->size,
  44. mem->va, mem->dma);
  45. }
  46. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  47. u16 len, u16 entry_size)
  48. {
  49. struct be_dma_mem *mem = &q->dma_mem;
  50. memset(q, 0, sizeof(*q));
  51. q->len = len;
  52. q->entry_size = entry_size;
  53. mem->size = len * entry_size;
  54. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  55. if (!mem->va)
  56. return -1;
  57. memset(mem->va, 0, mem->size);
  58. return 0;
  59. }
  60. static void be_intr_set(struct be_adapter *adapter, bool enable)
  61. {
  62. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  63. u32 reg = ioread32(addr);
  64. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  65. if (adapter->eeh_err)
  66. return;
  67. if (!enabled && enable)
  68. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  69. else if (enabled && !enable)
  70. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  71. else
  72. return;
  73. iowrite32(reg, addr);
  74. }
  75. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  76. {
  77. u32 val = 0;
  78. val |= qid & DB_RQ_RING_ID_MASK;
  79. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  80. wmb();
  81. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  82. }
  83. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  84. {
  85. u32 val = 0;
  86. val |= qid & DB_TXULP_RING_ID_MASK;
  87. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  88. wmb();
  89. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  90. }
  91. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  92. bool arm, bool clear_int, u16 num_popped)
  93. {
  94. u32 val = 0;
  95. val |= qid & DB_EQ_RING_ID_MASK;
  96. if (adapter->eeh_err)
  97. return;
  98. if (arm)
  99. val |= 1 << DB_EQ_REARM_SHIFT;
  100. if (clear_int)
  101. val |= 1 << DB_EQ_CLR_SHIFT;
  102. val |= 1 << DB_EQ_EVNT_SHIFT;
  103. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  104. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  105. }
  106. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  107. {
  108. u32 val = 0;
  109. val |= qid & DB_CQ_RING_ID_MASK;
  110. if (adapter->eeh_err)
  111. return;
  112. if (arm)
  113. val |= 1 << DB_CQ_REARM_SHIFT;
  114. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  115. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  116. }
  117. static int be_mac_addr_set(struct net_device *netdev, void *p)
  118. {
  119. struct be_adapter *adapter = netdev_priv(netdev);
  120. struct sockaddr *addr = p;
  121. int status = 0;
  122. if (!is_valid_ether_addr(addr->sa_data))
  123. return -EADDRNOTAVAIL;
  124. /* MAC addr configuration will be done in hardware for VFs
  125. * by their corresponding PFs. Just copy to netdev addr here
  126. */
  127. if (!be_physfn(adapter))
  128. goto netdev_addr;
  129. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  130. if (status)
  131. return status;
  132. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  133. adapter->if_handle, &adapter->pmac_id);
  134. netdev_addr:
  135. if (!status)
  136. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  137. return status;
  138. }
  139. void netdev_stats_update(struct be_adapter *adapter)
  140. {
  141. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  142. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  143. struct be_port_rxf_stats *port_stats =
  144. &rxf_stats->port[adapter->port_num];
  145. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  146. struct be_erx_stats *erx_stats = &hw_stats->erx;
  147. dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
  148. dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
  149. dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
  150. dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
  151. /* bad pkts received */
  152. dev_stats->rx_errors = port_stats->rx_crc_errors +
  153. port_stats->rx_alignment_symbol_errors +
  154. port_stats->rx_in_range_errors +
  155. port_stats->rx_out_range_errors +
  156. port_stats->rx_frame_too_long +
  157. port_stats->rx_dropped_too_small +
  158. port_stats->rx_dropped_too_short +
  159. port_stats->rx_dropped_header_too_small +
  160. port_stats->rx_dropped_tcp_length +
  161. port_stats->rx_dropped_runt +
  162. port_stats->rx_tcp_checksum_errs +
  163. port_stats->rx_ip_checksum_errs +
  164. port_stats->rx_udp_checksum_errs;
  165. /* no space in linux buffers: best possible approximation */
  166. dev_stats->rx_dropped =
  167. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  168. /* detailed rx errors */
  169. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  170. port_stats->rx_out_range_errors +
  171. port_stats->rx_frame_too_long;
  172. /* receive ring buffer overflow */
  173. dev_stats->rx_over_errors = 0;
  174. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  175. /* frame alignment errors */
  176. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  177. /* receiver fifo overrun */
  178. /* drops_no_pbuf is no per i/f, it's per BE card */
  179. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  180. port_stats->rx_input_fifo_overflow +
  181. rxf_stats->rx_drops_no_pbuf;
  182. /* receiver missed packetd */
  183. dev_stats->rx_missed_errors = 0;
  184. /* packet transmit problems */
  185. dev_stats->tx_errors = 0;
  186. /* no space available in linux */
  187. dev_stats->tx_dropped = 0;
  188. dev_stats->multicast = port_stats->rx_multicast_frames;
  189. dev_stats->collisions = 0;
  190. /* detailed tx_errors */
  191. dev_stats->tx_aborted_errors = 0;
  192. dev_stats->tx_carrier_errors = 0;
  193. dev_stats->tx_fifo_errors = 0;
  194. dev_stats->tx_heartbeat_errors = 0;
  195. dev_stats->tx_window_errors = 0;
  196. }
  197. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  198. {
  199. struct net_device *netdev = adapter->netdev;
  200. /* If link came up or went down */
  201. if (adapter->link_up != link_up) {
  202. adapter->link_speed = -1;
  203. if (link_up) {
  204. netif_start_queue(netdev);
  205. netif_carrier_on(netdev);
  206. printk(KERN_INFO "%s: Link up\n", netdev->name);
  207. } else {
  208. netif_stop_queue(netdev);
  209. netif_carrier_off(netdev);
  210. printk(KERN_INFO "%s: Link down\n", netdev->name);
  211. }
  212. adapter->link_up = link_up;
  213. }
  214. }
  215. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  216. static void be_rx_eqd_update(struct be_adapter *adapter)
  217. {
  218. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  219. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  220. ulong now = jiffies;
  221. u32 eqd;
  222. if (!rx_eq->enable_aic)
  223. return;
  224. /* Wrapped around */
  225. if (time_before(now, stats->rx_fps_jiffies)) {
  226. stats->rx_fps_jiffies = now;
  227. return;
  228. }
  229. /* Update once a second */
  230. if ((now - stats->rx_fps_jiffies) < HZ)
  231. return;
  232. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  233. ((now - stats->rx_fps_jiffies) / HZ);
  234. stats->rx_fps_jiffies = now;
  235. stats->be_prev_rx_frags = stats->be_rx_frags;
  236. eqd = stats->be_rx_fps / 110000;
  237. eqd = eqd << 3;
  238. if (eqd > rx_eq->max_eqd)
  239. eqd = rx_eq->max_eqd;
  240. if (eqd < rx_eq->min_eqd)
  241. eqd = rx_eq->min_eqd;
  242. if (eqd < 10)
  243. eqd = 0;
  244. if (eqd != rx_eq->cur_eqd)
  245. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  246. rx_eq->cur_eqd = eqd;
  247. }
  248. static struct net_device_stats *be_get_stats(struct net_device *dev)
  249. {
  250. return &dev->stats;
  251. }
  252. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  253. {
  254. u64 rate = bytes;
  255. do_div(rate, ticks / HZ);
  256. rate <<= 3; /* bytes/sec -> bits/sec */
  257. do_div(rate, 1000000ul); /* MB/Sec */
  258. return rate;
  259. }
  260. static void be_tx_rate_update(struct be_adapter *adapter)
  261. {
  262. struct be_drvr_stats *stats = drvr_stats(adapter);
  263. ulong now = jiffies;
  264. /* Wrapped around? */
  265. if (time_before(now, stats->be_tx_jiffies)) {
  266. stats->be_tx_jiffies = now;
  267. return;
  268. }
  269. /* Update tx rate once in two seconds */
  270. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  271. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  272. - stats->be_tx_bytes_prev,
  273. now - stats->be_tx_jiffies);
  274. stats->be_tx_jiffies = now;
  275. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  276. }
  277. }
  278. static void be_tx_stats_update(struct be_adapter *adapter,
  279. u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
  280. {
  281. struct be_drvr_stats *stats = drvr_stats(adapter);
  282. stats->be_tx_reqs++;
  283. stats->be_tx_wrbs += wrb_cnt;
  284. stats->be_tx_bytes += copied;
  285. stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
  286. if (stopped)
  287. stats->be_tx_stops++;
  288. }
  289. /* Determine number of WRB entries needed to xmit data in an skb */
  290. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  291. {
  292. int cnt = (skb->len > skb->data_len);
  293. cnt += skb_shinfo(skb)->nr_frags;
  294. /* to account for hdr wrb */
  295. cnt++;
  296. if (cnt & 1) {
  297. /* add a dummy to make it an even num */
  298. cnt++;
  299. *dummy = true;
  300. } else
  301. *dummy = false;
  302. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  303. return cnt;
  304. }
  305. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  306. {
  307. wrb->frag_pa_hi = upper_32_bits(addr);
  308. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  309. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  310. }
  311. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  312. bool vlan, u32 wrb_cnt, u32 len)
  313. {
  314. memset(hdr, 0, sizeof(*hdr));
  315. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  316. if (skb_is_gso(skb)) {
  317. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  318. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  319. hdr, skb_shinfo(skb)->gso_size);
  320. if (skb_is_gso_v6(skb))
  321. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
  322. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  323. if (is_tcp_pkt(skb))
  324. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  325. else if (is_udp_pkt(skb))
  326. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  327. }
  328. if (vlan && vlan_tx_tag_present(skb)) {
  329. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  330. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  331. hdr, vlan_tx_tag_get(skb));
  332. }
  333. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  334. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  335. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  336. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  337. }
  338. static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
  339. bool unmap_single)
  340. {
  341. dma_addr_t dma;
  342. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  343. dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
  344. if (wrb->frag_len) {
  345. if (unmap_single)
  346. pci_unmap_single(pdev, dma, wrb->frag_len,
  347. PCI_DMA_TODEVICE);
  348. else
  349. pci_unmap_page(pdev, dma, wrb->frag_len,
  350. PCI_DMA_TODEVICE);
  351. }
  352. }
  353. static int make_tx_wrbs(struct be_adapter *adapter,
  354. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  355. {
  356. dma_addr_t busaddr;
  357. int i, copied = 0;
  358. struct pci_dev *pdev = adapter->pdev;
  359. struct sk_buff *first_skb = skb;
  360. struct be_queue_info *txq = &adapter->tx_obj.q;
  361. struct be_eth_wrb *wrb;
  362. struct be_eth_hdr_wrb *hdr;
  363. bool map_single = false;
  364. u16 map_head;
  365. hdr = queue_head_node(txq);
  366. queue_head_inc(txq);
  367. map_head = txq->head;
  368. if (skb->len > skb->data_len) {
  369. int len = skb_headlen(skb);
  370. busaddr = pci_map_single(pdev, skb->data, len,
  371. PCI_DMA_TODEVICE);
  372. if (pci_dma_mapping_error(pdev, busaddr))
  373. goto dma_err;
  374. map_single = true;
  375. wrb = queue_head_node(txq);
  376. wrb_fill(wrb, busaddr, len);
  377. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  378. queue_head_inc(txq);
  379. copied += len;
  380. }
  381. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  382. struct skb_frag_struct *frag =
  383. &skb_shinfo(skb)->frags[i];
  384. busaddr = pci_map_page(pdev, frag->page,
  385. frag->page_offset,
  386. frag->size, PCI_DMA_TODEVICE);
  387. if (pci_dma_mapping_error(pdev, busaddr))
  388. goto dma_err;
  389. wrb = queue_head_node(txq);
  390. wrb_fill(wrb, busaddr, frag->size);
  391. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  392. queue_head_inc(txq);
  393. copied += frag->size;
  394. }
  395. if (dummy_wrb) {
  396. wrb = queue_head_node(txq);
  397. wrb_fill(wrb, 0, 0);
  398. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  399. queue_head_inc(txq);
  400. }
  401. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  402. wrb_cnt, copied);
  403. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  404. return copied;
  405. dma_err:
  406. txq->head = map_head;
  407. while (copied) {
  408. wrb = queue_head_node(txq);
  409. unmap_tx_frag(pdev, wrb, map_single);
  410. map_single = false;
  411. copied -= wrb->frag_len;
  412. queue_head_inc(txq);
  413. }
  414. return 0;
  415. }
  416. static netdev_tx_t be_xmit(struct sk_buff *skb,
  417. struct net_device *netdev)
  418. {
  419. struct be_adapter *adapter = netdev_priv(netdev);
  420. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  421. struct be_queue_info *txq = &tx_obj->q;
  422. u32 wrb_cnt = 0, copied = 0;
  423. u32 start = txq->head;
  424. bool dummy_wrb, stopped = false;
  425. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  426. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  427. if (copied) {
  428. /* record the sent skb in the sent_skb table */
  429. BUG_ON(tx_obj->sent_skb_list[start]);
  430. tx_obj->sent_skb_list[start] = skb;
  431. /* Ensure txq has space for the next skb; Else stop the queue
  432. * *BEFORE* ringing the tx doorbell, so that we serialze the
  433. * tx compls of the current transmit which'll wake up the queue
  434. */
  435. atomic_add(wrb_cnt, &txq->used);
  436. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  437. txq->len) {
  438. netif_stop_queue(netdev);
  439. stopped = true;
  440. }
  441. be_txq_notify(adapter, txq->id, wrb_cnt);
  442. be_tx_stats_update(adapter, wrb_cnt, copied,
  443. skb_shinfo(skb)->gso_segs, stopped);
  444. } else {
  445. txq->head = start;
  446. dev_kfree_skb_any(skb);
  447. }
  448. return NETDEV_TX_OK;
  449. }
  450. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  451. {
  452. struct be_adapter *adapter = netdev_priv(netdev);
  453. if (new_mtu < BE_MIN_MTU ||
  454. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  455. (ETH_HLEN + ETH_FCS_LEN))) {
  456. dev_info(&adapter->pdev->dev,
  457. "MTU must be between %d and %d bytes\n",
  458. BE_MIN_MTU,
  459. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  460. return -EINVAL;
  461. }
  462. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  463. netdev->mtu, new_mtu);
  464. netdev->mtu = new_mtu;
  465. return 0;
  466. }
  467. /*
  468. * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
  469. * If the user configures more, place BE in vlan promiscuous mode.
  470. */
  471. static int be_vid_config(struct be_adapter *adapter)
  472. {
  473. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  474. u16 ntags = 0, i;
  475. int status = 0;
  476. if (adapter->vlans_added <= adapter->max_vlans) {
  477. /* Construct VLAN Table to give to HW */
  478. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  479. if (adapter->vlan_tag[i]) {
  480. vtag[ntags] = cpu_to_le16(i);
  481. ntags++;
  482. }
  483. }
  484. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  485. vtag, ntags, 1, 0);
  486. } else {
  487. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  488. NULL, 0, 1, 1);
  489. }
  490. return status;
  491. }
  492. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  493. {
  494. struct be_adapter *adapter = netdev_priv(netdev);
  495. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  496. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  497. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  498. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  499. adapter->vlan_grp = grp;
  500. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  501. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  502. }
  503. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  504. {
  505. struct be_adapter *adapter = netdev_priv(netdev);
  506. if (!be_physfn(adapter))
  507. return;
  508. adapter->vlan_tag[vid] = 1;
  509. adapter->vlans_added++;
  510. if (adapter->vlans_added <= (adapter->max_vlans + 1))
  511. be_vid_config(adapter);
  512. }
  513. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  514. {
  515. struct be_adapter *adapter = netdev_priv(netdev);
  516. if (!be_physfn(adapter))
  517. return;
  518. adapter->vlan_tag[vid] = 0;
  519. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  520. adapter->vlans_added--;
  521. if (adapter->vlans_added <= adapter->max_vlans)
  522. be_vid_config(adapter);
  523. }
  524. static void be_set_multicast_list(struct net_device *netdev)
  525. {
  526. struct be_adapter *adapter = netdev_priv(netdev);
  527. if (netdev->flags & IFF_PROMISC) {
  528. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  529. adapter->promiscuous = true;
  530. goto done;
  531. }
  532. /* BE was previously in promiscous mode; disable it */
  533. if (adapter->promiscuous) {
  534. adapter->promiscuous = false;
  535. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  536. }
  537. /* Enable multicast promisc if num configured exceeds what we support */
  538. if (netdev->flags & IFF_ALLMULTI ||
  539. netdev_mc_count(netdev) > BE_MAX_MC) {
  540. be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
  541. &adapter->mc_cmd_mem);
  542. goto done;
  543. }
  544. be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
  545. &adapter->mc_cmd_mem);
  546. done:
  547. return;
  548. }
  549. static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
  550. {
  551. struct be_adapter *adapter = netdev_priv(netdev);
  552. int status;
  553. if (!adapter->sriov_enabled)
  554. return -EPERM;
  555. if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
  556. return -EINVAL;
  557. status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
  558. adapter->vf_pmac_id[vf]);
  559. status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
  560. &adapter->vf_pmac_id[vf]);
  561. if (!status)
  562. dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
  563. mac, vf);
  564. return status;
  565. }
  566. static void be_rx_rate_update(struct be_adapter *adapter)
  567. {
  568. struct be_drvr_stats *stats = drvr_stats(adapter);
  569. ulong now = jiffies;
  570. /* Wrapped around */
  571. if (time_before(now, stats->be_rx_jiffies)) {
  572. stats->be_rx_jiffies = now;
  573. return;
  574. }
  575. /* Update the rate once in two seconds */
  576. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  577. return;
  578. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  579. - stats->be_rx_bytes_prev,
  580. now - stats->be_rx_jiffies);
  581. stats->be_rx_jiffies = now;
  582. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  583. }
  584. static void be_rx_stats_update(struct be_adapter *adapter,
  585. u32 pktsize, u16 numfrags)
  586. {
  587. struct be_drvr_stats *stats = drvr_stats(adapter);
  588. stats->be_rx_compl++;
  589. stats->be_rx_frags += numfrags;
  590. stats->be_rx_bytes += pktsize;
  591. stats->be_rx_pkts++;
  592. }
  593. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  594. {
  595. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  596. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  597. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  598. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  599. if (ip_version) {
  600. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  601. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  602. }
  603. ipv6_chk = (ip_version && (tcpf || udpf));
  604. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  605. }
  606. static struct be_rx_page_info *
  607. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  608. {
  609. struct be_rx_page_info *rx_page_info;
  610. struct be_queue_info *rxq = &adapter->rx_obj.q;
  611. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  612. BUG_ON(!rx_page_info->page);
  613. if (rx_page_info->last_page_user) {
  614. pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
  615. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  616. rx_page_info->last_page_user = false;
  617. }
  618. atomic_dec(&rxq->used);
  619. return rx_page_info;
  620. }
  621. /* Throwaway the data in the Rx completion */
  622. static void be_rx_compl_discard(struct be_adapter *adapter,
  623. struct be_eth_rx_compl *rxcp)
  624. {
  625. struct be_queue_info *rxq = &adapter->rx_obj.q;
  626. struct be_rx_page_info *page_info;
  627. u16 rxq_idx, i, num_rcvd;
  628. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  629. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  630. for (i = 0; i < num_rcvd; i++) {
  631. page_info = get_rx_page_info(adapter, rxq_idx);
  632. put_page(page_info->page);
  633. memset(page_info, 0, sizeof(*page_info));
  634. index_inc(&rxq_idx, rxq->len);
  635. }
  636. }
  637. /*
  638. * skb_fill_rx_data forms a complete skb for an ether frame
  639. * indicated by rxcp.
  640. */
  641. static void skb_fill_rx_data(struct be_adapter *adapter,
  642. struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
  643. u16 num_rcvd)
  644. {
  645. struct be_queue_info *rxq = &adapter->rx_obj.q;
  646. struct be_rx_page_info *page_info;
  647. u16 rxq_idx, i, j;
  648. u32 pktsize, hdr_len, curr_frag_len, size;
  649. u8 *start;
  650. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  651. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  652. page_info = get_rx_page_info(adapter, rxq_idx);
  653. start = page_address(page_info->page) + page_info->page_offset;
  654. prefetch(start);
  655. /* Copy data in the first descriptor of this completion */
  656. curr_frag_len = min(pktsize, rx_frag_size);
  657. /* Copy the header portion into skb_data */
  658. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  659. memcpy(skb->data, start, hdr_len);
  660. skb->len = curr_frag_len;
  661. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  662. /* Complete packet has now been moved to data */
  663. put_page(page_info->page);
  664. skb->data_len = 0;
  665. skb->tail += curr_frag_len;
  666. } else {
  667. skb_shinfo(skb)->nr_frags = 1;
  668. skb_shinfo(skb)->frags[0].page = page_info->page;
  669. skb_shinfo(skb)->frags[0].page_offset =
  670. page_info->page_offset + hdr_len;
  671. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  672. skb->data_len = curr_frag_len - hdr_len;
  673. skb->tail += hdr_len;
  674. }
  675. page_info->page = NULL;
  676. if (pktsize <= rx_frag_size) {
  677. BUG_ON(num_rcvd != 1);
  678. goto done;
  679. }
  680. /* More frags present for this completion */
  681. size = pktsize;
  682. for (i = 1, j = 0; i < num_rcvd; i++) {
  683. size -= curr_frag_len;
  684. index_inc(&rxq_idx, rxq->len);
  685. page_info = get_rx_page_info(adapter, rxq_idx);
  686. curr_frag_len = min(size, rx_frag_size);
  687. /* Coalesce all frags from the same physical page in one slot */
  688. if (page_info->page_offset == 0) {
  689. /* Fresh page */
  690. j++;
  691. skb_shinfo(skb)->frags[j].page = page_info->page;
  692. skb_shinfo(skb)->frags[j].page_offset =
  693. page_info->page_offset;
  694. skb_shinfo(skb)->frags[j].size = 0;
  695. skb_shinfo(skb)->nr_frags++;
  696. } else {
  697. put_page(page_info->page);
  698. }
  699. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  700. skb->len += curr_frag_len;
  701. skb->data_len += curr_frag_len;
  702. page_info->page = NULL;
  703. }
  704. BUG_ON(j > MAX_SKB_FRAGS);
  705. done:
  706. be_rx_stats_update(adapter, pktsize, num_rcvd);
  707. }
  708. /* Process the RX completion indicated by rxcp when GRO is disabled */
  709. static void be_rx_compl_process(struct be_adapter *adapter,
  710. struct be_eth_rx_compl *rxcp)
  711. {
  712. struct sk_buff *skb;
  713. u32 vlanf, vid;
  714. u16 num_rcvd;
  715. u8 vtm;
  716. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  717. /* Is it a flush compl that has no data */
  718. if (unlikely(num_rcvd == 0))
  719. return;
  720. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  721. if (unlikely(!skb)) {
  722. if (net_ratelimit())
  723. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  724. be_rx_compl_discard(adapter, rxcp);
  725. return;
  726. }
  727. skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
  728. if (do_pkt_csum(rxcp, adapter->rx_csum))
  729. skb->ip_summed = CHECKSUM_NONE;
  730. else
  731. skb->ip_summed = CHECKSUM_UNNECESSARY;
  732. skb->truesize = skb->len + sizeof(struct sk_buff);
  733. skb->protocol = eth_type_trans(skb, adapter->netdev);
  734. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  735. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  736. /* vlanf could be wrongly set in some cards.
  737. * ignore if vtm is not set */
  738. if ((adapter->cap & 0x400) && !vtm)
  739. vlanf = 0;
  740. if (unlikely(vlanf)) {
  741. if (!adapter->vlan_grp || adapter->vlans_added == 0) {
  742. kfree_skb(skb);
  743. return;
  744. }
  745. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  746. vid = swab16(vid);
  747. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  748. } else {
  749. netif_receive_skb(skb);
  750. }
  751. }
  752. /* Process the RX completion indicated by rxcp when GRO is enabled */
  753. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  754. struct be_eth_rx_compl *rxcp)
  755. {
  756. struct be_rx_page_info *page_info;
  757. struct sk_buff *skb = NULL;
  758. struct be_queue_info *rxq = &adapter->rx_obj.q;
  759. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  760. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  761. u16 i, rxq_idx = 0, vid, j;
  762. u8 vtm;
  763. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  764. /* Is it a flush compl that has no data */
  765. if (unlikely(num_rcvd == 0))
  766. return;
  767. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  768. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  769. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  770. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  771. /* vlanf could be wrongly set in some cards.
  772. * ignore if vtm is not set */
  773. if ((adapter->cap & 0x400) && !vtm)
  774. vlanf = 0;
  775. skb = napi_get_frags(&eq_obj->napi);
  776. if (!skb) {
  777. be_rx_compl_discard(adapter, rxcp);
  778. return;
  779. }
  780. remaining = pkt_size;
  781. for (i = 0, j = -1; i < num_rcvd; i++) {
  782. page_info = get_rx_page_info(adapter, rxq_idx);
  783. curr_frag_len = min(remaining, rx_frag_size);
  784. /* Coalesce all frags from the same physical page in one slot */
  785. if (i == 0 || page_info->page_offset == 0) {
  786. /* First frag or Fresh page */
  787. j++;
  788. skb_shinfo(skb)->frags[j].page = page_info->page;
  789. skb_shinfo(skb)->frags[j].page_offset =
  790. page_info->page_offset;
  791. skb_shinfo(skb)->frags[j].size = 0;
  792. } else {
  793. put_page(page_info->page);
  794. }
  795. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  796. remaining -= curr_frag_len;
  797. index_inc(&rxq_idx, rxq->len);
  798. memset(page_info, 0, sizeof(*page_info));
  799. }
  800. BUG_ON(j > MAX_SKB_FRAGS);
  801. skb_shinfo(skb)->nr_frags = j + 1;
  802. skb->len = pkt_size;
  803. skb->data_len = pkt_size;
  804. skb->truesize += pkt_size;
  805. skb->ip_summed = CHECKSUM_UNNECESSARY;
  806. if (likely(!vlanf)) {
  807. napi_gro_frags(&eq_obj->napi);
  808. } else {
  809. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  810. vid = swab16(vid);
  811. if (!adapter->vlan_grp || adapter->vlans_added == 0)
  812. return;
  813. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  814. }
  815. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  816. }
  817. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  818. {
  819. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  820. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  821. return NULL;
  822. rmb();
  823. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  824. queue_tail_inc(&adapter->rx_obj.cq);
  825. return rxcp;
  826. }
  827. /* To reset the valid bit, we need to reset the whole word as
  828. * when walking the queue the valid entries are little-endian
  829. * and invalid entries are host endian
  830. */
  831. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  832. {
  833. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  834. }
  835. static inline struct page *be_alloc_pages(u32 size)
  836. {
  837. gfp_t alloc_flags = GFP_ATOMIC;
  838. u32 order = get_order(size);
  839. if (order > 0)
  840. alloc_flags |= __GFP_COMP;
  841. return alloc_pages(alloc_flags, order);
  842. }
  843. /*
  844. * Allocate a page, split it to fragments of size rx_frag_size and post as
  845. * receive buffers to BE
  846. */
  847. static void be_post_rx_frags(struct be_adapter *adapter)
  848. {
  849. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  850. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  851. struct be_queue_info *rxq = &adapter->rx_obj.q;
  852. struct page *pagep = NULL;
  853. struct be_eth_rx_d *rxd;
  854. u64 page_dmaaddr = 0, frag_dmaaddr;
  855. u32 posted, page_offset = 0;
  856. page_info = &page_info_tbl[rxq->head];
  857. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  858. if (!pagep) {
  859. pagep = be_alloc_pages(adapter->big_page_size);
  860. if (unlikely(!pagep)) {
  861. drvr_stats(adapter)->be_ethrx_post_fail++;
  862. break;
  863. }
  864. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  865. adapter->big_page_size,
  866. PCI_DMA_FROMDEVICE);
  867. page_info->page_offset = 0;
  868. } else {
  869. get_page(pagep);
  870. page_info->page_offset = page_offset + rx_frag_size;
  871. }
  872. page_offset = page_info->page_offset;
  873. page_info->page = pagep;
  874. dma_unmap_addr_set(page_info, bus, page_dmaaddr);
  875. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  876. rxd = queue_head_node(rxq);
  877. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  878. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  879. /* Any space left in the current big page for another frag? */
  880. if ((page_offset + rx_frag_size + rx_frag_size) >
  881. adapter->big_page_size) {
  882. pagep = NULL;
  883. page_info->last_page_user = true;
  884. }
  885. prev_page_info = page_info;
  886. queue_head_inc(rxq);
  887. page_info = &page_info_tbl[rxq->head];
  888. }
  889. if (pagep)
  890. prev_page_info->last_page_user = true;
  891. if (posted) {
  892. atomic_add(posted, &rxq->used);
  893. be_rxq_notify(adapter, rxq->id, posted);
  894. } else if (atomic_read(&rxq->used) == 0) {
  895. /* Let be_worker replenish when memory is available */
  896. adapter->rx_post_starved = true;
  897. }
  898. }
  899. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  900. {
  901. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  902. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  903. return NULL;
  904. rmb();
  905. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  906. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  907. queue_tail_inc(tx_cq);
  908. return txcp;
  909. }
  910. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  911. {
  912. struct be_queue_info *txq = &adapter->tx_obj.q;
  913. struct be_eth_wrb *wrb;
  914. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  915. struct sk_buff *sent_skb;
  916. u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
  917. bool unmap_skb_hdr = true;
  918. sent_skb = sent_skbs[txq->tail];
  919. BUG_ON(!sent_skb);
  920. sent_skbs[txq->tail] = NULL;
  921. /* skip header wrb */
  922. queue_tail_inc(txq);
  923. do {
  924. cur_index = txq->tail;
  925. wrb = queue_tail_node(txq);
  926. unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
  927. skb_headlen(sent_skb)));
  928. unmap_skb_hdr = false;
  929. num_wrbs++;
  930. queue_tail_inc(txq);
  931. } while (cur_index != last_index);
  932. atomic_sub(num_wrbs, &txq->used);
  933. kfree_skb(sent_skb);
  934. }
  935. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  936. {
  937. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  938. if (!eqe->evt)
  939. return NULL;
  940. rmb();
  941. eqe->evt = le32_to_cpu(eqe->evt);
  942. queue_tail_inc(&eq_obj->q);
  943. return eqe;
  944. }
  945. static int event_handle(struct be_adapter *adapter,
  946. struct be_eq_obj *eq_obj)
  947. {
  948. struct be_eq_entry *eqe;
  949. u16 num = 0;
  950. while ((eqe = event_get(eq_obj)) != NULL) {
  951. eqe->evt = 0;
  952. num++;
  953. }
  954. /* Deal with any spurious interrupts that come
  955. * without events
  956. */
  957. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  958. if (num)
  959. napi_schedule(&eq_obj->napi);
  960. return num;
  961. }
  962. /* Just read and notify events without processing them.
  963. * Used at the time of destroying event queues */
  964. static void be_eq_clean(struct be_adapter *adapter,
  965. struct be_eq_obj *eq_obj)
  966. {
  967. struct be_eq_entry *eqe;
  968. u16 num = 0;
  969. while ((eqe = event_get(eq_obj)) != NULL) {
  970. eqe->evt = 0;
  971. num++;
  972. }
  973. if (num)
  974. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  975. }
  976. static void be_rx_q_clean(struct be_adapter *adapter)
  977. {
  978. struct be_rx_page_info *page_info;
  979. struct be_queue_info *rxq = &adapter->rx_obj.q;
  980. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  981. struct be_eth_rx_compl *rxcp;
  982. u16 tail;
  983. /* First cleanup pending rx completions */
  984. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  985. be_rx_compl_discard(adapter, rxcp);
  986. be_rx_compl_reset(rxcp);
  987. be_cq_notify(adapter, rx_cq->id, true, 1);
  988. }
  989. /* Then free posted rx buffer that were not used */
  990. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  991. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  992. page_info = get_rx_page_info(adapter, tail);
  993. put_page(page_info->page);
  994. memset(page_info, 0, sizeof(*page_info));
  995. }
  996. BUG_ON(atomic_read(&rxq->used));
  997. }
  998. static void be_tx_compl_clean(struct be_adapter *adapter)
  999. {
  1000. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1001. struct be_queue_info *txq = &adapter->tx_obj.q;
  1002. struct be_eth_tx_compl *txcp;
  1003. u16 end_idx, cmpl = 0, timeo = 0;
  1004. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  1005. struct sk_buff *sent_skb;
  1006. bool dummy_wrb;
  1007. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  1008. do {
  1009. while ((txcp = be_tx_compl_get(tx_cq))) {
  1010. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1011. wrb_index, txcp);
  1012. be_tx_compl_process(adapter, end_idx);
  1013. cmpl++;
  1014. }
  1015. if (cmpl) {
  1016. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  1017. cmpl = 0;
  1018. }
  1019. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  1020. break;
  1021. mdelay(1);
  1022. } while (true);
  1023. if (atomic_read(&txq->used))
  1024. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  1025. atomic_read(&txq->used));
  1026. /* free posted tx for which compls will never arrive */
  1027. while (atomic_read(&txq->used)) {
  1028. sent_skb = sent_skbs[txq->tail];
  1029. end_idx = txq->tail;
  1030. index_adv(&end_idx,
  1031. wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
  1032. be_tx_compl_process(adapter, end_idx);
  1033. }
  1034. }
  1035. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  1036. {
  1037. struct be_queue_info *q;
  1038. q = &adapter->mcc_obj.q;
  1039. if (q->created)
  1040. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  1041. be_queue_free(adapter, q);
  1042. q = &adapter->mcc_obj.cq;
  1043. if (q->created)
  1044. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1045. be_queue_free(adapter, q);
  1046. }
  1047. /* Must be called only after TX qs are created as MCC shares TX EQ */
  1048. static int be_mcc_queues_create(struct be_adapter *adapter)
  1049. {
  1050. struct be_queue_info *q, *cq;
  1051. /* Alloc MCC compl queue */
  1052. cq = &adapter->mcc_obj.cq;
  1053. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  1054. sizeof(struct be_mcc_compl)))
  1055. goto err;
  1056. /* Ask BE to create MCC compl queue; share TX's eq */
  1057. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  1058. goto mcc_cq_free;
  1059. /* Alloc MCC queue */
  1060. q = &adapter->mcc_obj.q;
  1061. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  1062. goto mcc_cq_destroy;
  1063. /* Ask BE to create MCC queue */
  1064. if (be_cmd_mccq_create(adapter, q, cq))
  1065. goto mcc_q_free;
  1066. return 0;
  1067. mcc_q_free:
  1068. be_queue_free(adapter, q);
  1069. mcc_cq_destroy:
  1070. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1071. mcc_cq_free:
  1072. be_queue_free(adapter, cq);
  1073. err:
  1074. return -1;
  1075. }
  1076. static void be_tx_queues_destroy(struct be_adapter *adapter)
  1077. {
  1078. struct be_queue_info *q;
  1079. q = &adapter->tx_obj.q;
  1080. if (q->created)
  1081. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1082. be_queue_free(adapter, q);
  1083. q = &adapter->tx_obj.cq;
  1084. if (q->created)
  1085. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1086. be_queue_free(adapter, q);
  1087. /* Clear any residual events */
  1088. be_eq_clean(adapter, &adapter->tx_eq);
  1089. q = &adapter->tx_eq.q;
  1090. if (q->created)
  1091. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1092. be_queue_free(adapter, q);
  1093. }
  1094. static int be_tx_queues_create(struct be_adapter *adapter)
  1095. {
  1096. struct be_queue_info *eq, *q, *cq;
  1097. adapter->tx_eq.max_eqd = 0;
  1098. adapter->tx_eq.min_eqd = 0;
  1099. adapter->tx_eq.cur_eqd = 96;
  1100. adapter->tx_eq.enable_aic = false;
  1101. /* Alloc Tx Event queue */
  1102. eq = &adapter->tx_eq.q;
  1103. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1104. return -1;
  1105. /* Ask BE to create Tx Event queue */
  1106. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1107. goto tx_eq_free;
  1108. adapter->base_eq_id = adapter->tx_eq.q.id;
  1109. /* Alloc TX eth compl queue */
  1110. cq = &adapter->tx_obj.cq;
  1111. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1112. sizeof(struct be_eth_tx_compl)))
  1113. goto tx_eq_destroy;
  1114. /* Ask BE to create Tx eth compl queue */
  1115. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1116. goto tx_cq_free;
  1117. /* Alloc TX eth queue */
  1118. q = &adapter->tx_obj.q;
  1119. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1120. goto tx_cq_destroy;
  1121. /* Ask BE to create Tx eth queue */
  1122. if (be_cmd_txq_create(adapter, q, cq))
  1123. goto tx_q_free;
  1124. return 0;
  1125. tx_q_free:
  1126. be_queue_free(adapter, q);
  1127. tx_cq_destroy:
  1128. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1129. tx_cq_free:
  1130. be_queue_free(adapter, cq);
  1131. tx_eq_destroy:
  1132. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1133. tx_eq_free:
  1134. be_queue_free(adapter, eq);
  1135. return -1;
  1136. }
  1137. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1138. {
  1139. struct be_queue_info *q;
  1140. q = &adapter->rx_obj.q;
  1141. if (q->created) {
  1142. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1143. /* After the rxq is invalidated, wait for a grace time
  1144. * of 1ms for all dma to end and the flush compl to arrive
  1145. */
  1146. mdelay(1);
  1147. be_rx_q_clean(adapter);
  1148. }
  1149. be_queue_free(adapter, q);
  1150. q = &adapter->rx_obj.cq;
  1151. if (q->created)
  1152. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1153. be_queue_free(adapter, q);
  1154. /* Clear any residual events */
  1155. be_eq_clean(adapter, &adapter->rx_eq);
  1156. q = &adapter->rx_eq.q;
  1157. if (q->created)
  1158. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1159. be_queue_free(adapter, q);
  1160. }
  1161. static int be_rx_queues_create(struct be_adapter *adapter)
  1162. {
  1163. struct be_queue_info *eq, *q, *cq;
  1164. int rc;
  1165. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1166. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1167. adapter->rx_eq.min_eqd = 0;
  1168. adapter->rx_eq.cur_eqd = 0;
  1169. adapter->rx_eq.enable_aic = true;
  1170. /* Alloc Rx Event queue */
  1171. eq = &adapter->rx_eq.q;
  1172. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1173. sizeof(struct be_eq_entry));
  1174. if (rc)
  1175. return rc;
  1176. /* Ask BE to create Rx Event queue */
  1177. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1178. if (rc)
  1179. goto rx_eq_free;
  1180. /* Alloc RX eth compl queue */
  1181. cq = &adapter->rx_obj.cq;
  1182. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1183. sizeof(struct be_eth_rx_compl));
  1184. if (rc)
  1185. goto rx_eq_destroy;
  1186. /* Ask BE to create Rx eth compl queue */
  1187. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1188. if (rc)
  1189. goto rx_cq_free;
  1190. /* Alloc RX eth queue */
  1191. q = &adapter->rx_obj.q;
  1192. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1193. if (rc)
  1194. goto rx_cq_destroy;
  1195. /* Ask BE to create Rx eth queue */
  1196. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1197. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1198. if (rc)
  1199. goto rx_q_free;
  1200. return 0;
  1201. rx_q_free:
  1202. be_queue_free(adapter, q);
  1203. rx_cq_destroy:
  1204. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1205. rx_cq_free:
  1206. be_queue_free(adapter, cq);
  1207. rx_eq_destroy:
  1208. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1209. rx_eq_free:
  1210. be_queue_free(adapter, eq);
  1211. return rc;
  1212. }
  1213. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1214. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1215. {
  1216. return eq_id - adapter->base_eq_id;
  1217. }
  1218. static irqreturn_t be_intx(int irq, void *dev)
  1219. {
  1220. struct be_adapter *adapter = dev;
  1221. int isr;
  1222. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1223. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1224. if (!isr)
  1225. return IRQ_NONE;
  1226. event_handle(adapter, &adapter->tx_eq);
  1227. event_handle(adapter, &adapter->rx_eq);
  1228. return IRQ_HANDLED;
  1229. }
  1230. static irqreturn_t be_msix_rx(int irq, void *dev)
  1231. {
  1232. struct be_adapter *adapter = dev;
  1233. event_handle(adapter, &adapter->rx_eq);
  1234. return IRQ_HANDLED;
  1235. }
  1236. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1237. {
  1238. struct be_adapter *adapter = dev;
  1239. event_handle(adapter, &adapter->tx_eq);
  1240. return IRQ_HANDLED;
  1241. }
  1242. static inline bool do_gro(struct be_adapter *adapter,
  1243. struct be_eth_rx_compl *rxcp)
  1244. {
  1245. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1246. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1247. if (err)
  1248. drvr_stats(adapter)->be_rxcp_err++;
  1249. return (tcp_frame && !err) ? true : false;
  1250. }
  1251. int be_poll_rx(struct napi_struct *napi, int budget)
  1252. {
  1253. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1254. struct be_adapter *adapter =
  1255. container_of(rx_eq, struct be_adapter, rx_eq);
  1256. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1257. struct be_eth_rx_compl *rxcp;
  1258. u32 work_done;
  1259. adapter->stats.drvr_stats.be_rx_polls++;
  1260. for (work_done = 0; work_done < budget; work_done++) {
  1261. rxcp = be_rx_compl_get(adapter);
  1262. if (!rxcp)
  1263. break;
  1264. if (do_gro(adapter, rxcp))
  1265. be_rx_compl_process_gro(adapter, rxcp);
  1266. else
  1267. be_rx_compl_process(adapter, rxcp);
  1268. be_rx_compl_reset(rxcp);
  1269. }
  1270. /* Refill the queue */
  1271. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1272. be_post_rx_frags(adapter);
  1273. /* All consumed */
  1274. if (work_done < budget) {
  1275. napi_complete(napi);
  1276. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1277. } else {
  1278. /* More to be consumed; continue with interrupts disabled */
  1279. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1280. }
  1281. return work_done;
  1282. }
  1283. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1284. * For TX/MCC we don't honour budget; consume everything
  1285. */
  1286. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1287. {
  1288. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1289. struct be_adapter *adapter =
  1290. container_of(tx_eq, struct be_adapter, tx_eq);
  1291. struct be_queue_info *txq = &adapter->tx_obj.q;
  1292. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1293. struct be_eth_tx_compl *txcp;
  1294. int tx_compl = 0, mcc_compl, status = 0;
  1295. u16 end_idx;
  1296. while ((txcp = be_tx_compl_get(tx_cq))) {
  1297. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1298. wrb_index, txcp);
  1299. be_tx_compl_process(adapter, end_idx);
  1300. tx_compl++;
  1301. }
  1302. mcc_compl = be_process_mcc(adapter, &status);
  1303. napi_complete(napi);
  1304. if (mcc_compl) {
  1305. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  1306. be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
  1307. }
  1308. if (tx_compl) {
  1309. be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
  1310. /* As Tx wrbs have been freed up, wake up netdev queue if
  1311. * it was stopped due to lack of tx wrbs.
  1312. */
  1313. if (netif_queue_stopped(adapter->netdev) &&
  1314. atomic_read(&txq->used) < txq->len / 2) {
  1315. netif_wake_queue(adapter->netdev);
  1316. }
  1317. drvr_stats(adapter)->be_tx_events++;
  1318. drvr_stats(adapter)->be_tx_compl += tx_compl;
  1319. }
  1320. return 1;
  1321. }
  1322. static void be_worker(struct work_struct *work)
  1323. {
  1324. struct be_adapter *adapter =
  1325. container_of(work, struct be_adapter, work.work);
  1326. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1327. /* Set EQ delay */
  1328. be_rx_eqd_update(adapter);
  1329. be_tx_rate_update(adapter);
  1330. be_rx_rate_update(adapter);
  1331. if (adapter->rx_post_starved) {
  1332. adapter->rx_post_starved = false;
  1333. be_post_rx_frags(adapter);
  1334. }
  1335. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1336. }
  1337. static void be_msix_disable(struct be_adapter *adapter)
  1338. {
  1339. if (adapter->msix_enabled) {
  1340. pci_disable_msix(adapter->pdev);
  1341. adapter->msix_enabled = false;
  1342. }
  1343. }
  1344. static void be_msix_enable(struct be_adapter *adapter)
  1345. {
  1346. int i, status;
  1347. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1348. adapter->msix_entries[i].entry = i;
  1349. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1350. BE_NUM_MSIX_VECTORS);
  1351. if (status == 0)
  1352. adapter->msix_enabled = true;
  1353. }
  1354. static void be_sriov_enable(struct be_adapter *adapter)
  1355. {
  1356. #ifdef CONFIG_PCI_IOV
  1357. int status;
  1358. if (be_physfn(adapter) && num_vfs) {
  1359. status = pci_enable_sriov(adapter->pdev, num_vfs);
  1360. adapter->sriov_enabled = status ? false : true;
  1361. }
  1362. #endif
  1363. }
  1364. static void be_sriov_disable(struct be_adapter *adapter)
  1365. {
  1366. #ifdef CONFIG_PCI_IOV
  1367. if (adapter->sriov_enabled) {
  1368. pci_disable_sriov(adapter->pdev);
  1369. adapter->sriov_enabled = false;
  1370. }
  1371. #endif
  1372. }
  1373. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1374. {
  1375. return adapter->msix_entries[
  1376. be_evt_bit_get(adapter, eq_id)].vector;
  1377. }
  1378. static int be_request_irq(struct be_adapter *adapter,
  1379. struct be_eq_obj *eq_obj,
  1380. void *handler, char *desc)
  1381. {
  1382. struct net_device *netdev = adapter->netdev;
  1383. int vec;
  1384. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1385. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1386. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1387. }
  1388. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1389. {
  1390. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1391. free_irq(vec, adapter);
  1392. }
  1393. static int be_msix_register(struct be_adapter *adapter)
  1394. {
  1395. int status;
  1396. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1397. if (status)
  1398. goto err;
  1399. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1400. if (status)
  1401. goto free_tx_irq;
  1402. return 0;
  1403. free_tx_irq:
  1404. be_free_irq(adapter, &adapter->tx_eq);
  1405. err:
  1406. dev_warn(&adapter->pdev->dev,
  1407. "MSIX Request IRQ failed - err %d\n", status);
  1408. pci_disable_msix(adapter->pdev);
  1409. adapter->msix_enabled = false;
  1410. return status;
  1411. }
  1412. static int be_irq_register(struct be_adapter *adapter)
  1413. {
  1414. struct net_device *netdev = adapter->netdev;
  1415. int status;
  1416. if (adapter->msix_enabled) {
  1417. status = be_msix_register(adapter);
  1418. if (status == 0)
  1419. goto done;
  1420. /* INTx is not supported for VF */
  1421. if (!be_physfn(adapter))
  1422. return status;
  1423. }
  1424. /* INTx */
  1425. netdev->irq = adapter->pdev->irq;
  1426. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1427. adapter);
  1428. if (status) {
  1429. dev_err(&adapter->pdev->dev,
  1430. "INTx request IRQ failed - err %d\n", status);
  1431. return status;
  1432. }
  1433. done:
  1434. adapter->isr_registered = true;
  1435. return 0;
  1436. }
  1437. static void be_irq_unregister(struct be_adapter *adapter)
  1438. {
  1439. struct net_device *netdev = adapter->netdev;
  1440. if (!adapter->isr_registered)
  1441. return;
  1442. /* INTx */
  1443. if (!adapter->msix_enabled) {
  1444. free_irq(netdev->irq, adapter);
  1445. goto done;
  1446. }
  1447. /* MSIx */
  1448. be_free_irq(adapter, &adapter->tx_eq);
  1449. be_free_irq(adapter, &adapter->rx_eq);
  1450. done:
  1451. adapter->isr_registered = false;
  1452. }
  1453. static int be_close(struct net_device *netdev)
  1454. {
  1455. struct be_adapter *adapter = netdev_priv(netdev);
  1456. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1457. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1458. int vec;
  1459. cancel_delayed_work_sync(&adapter->work);
  1460. be_async_mcc_disable(adapter);
  1461. netif_stop_queue(netdev);
  1462. netif_carrier_off(netdev);
  1463. adapter->link_up = false;
  1464. be_intr_set(adapter, false);
  1465. if (adapter->msix_enabled) {
  1466. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1467. synchronize_irq(vec);
  1468. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1469. synchronize_irq(vec);
  1470. } else {
  1471. synchronize_irq(netdev->irq);
  1472. }
  1473. be_irq_unregister(adapter);
  1474. napi_disable(&rx_eq->napi);
  1475. napi_disable(&tx_eq->napi);
  1476. /* Wait for all pending tx completions to arrive so that
  1477. * all tx skbs are freed.
  1478. */
  1479. be_tx_compl_clean(adapter);
  1480. return 0;
  1481. }
  1482. static int be_open(struct net_device *netdev)
  1483. {
  1484. struct be_adapter *adapter = netdev_priv(netdev);
  1485. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1486. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1487. bool link_up;
  1488. int status;
  1489. u8 mac_speed;
  1490. u16 link_speed;
  1491. /* First time posting */
  1492. be_post_rx_frags(adapter);
  1493. napi_enable(&rx_eq->napi);
  1494. napi_enable(&tx_eq->napi);
  1495. be_irq_register(adapter);
  1496. be_intr_set(adapter, true);
  1497. /* The evt queues are created in unarmed state; arm them */
  1498. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1499. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1500. /* Rx compl queue may be in unarmed state; rearm it */
  1501. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1502. /* Now that interrupts are on we can process async mcc */
  1503. be_async_mcc_enable(adapter);
  1504. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1505. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1506. &link_speed);
  1507. if (status)
  1508. goto err;
  1509. be_link_status_update(adapter, link_up);
  1510. if (be_physfn(adapter)) {
  1511. status = be_vid_config(adapter);
  1512. if (status)
  1513. goto err;
  1514. status = be_cmd_set_flow_control(adapter,
  1515. adapter->tx_fc, adapter->rx_fc);
  1516. if (status)
  1517. goto err;
  1518. }
  1519. return 0;
  1520. err:
  1521. be_close(adapter->netdev);
  1522. return -EIO;
  1523. }
  1524. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1525. {
  1526. struct be_dma_mem cmd;
  1527. int status = 0;
  1528. u8 mac[ETH_ALEN];
  1529. memset(mac, 0, ETH_ALEN);
  1530. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1531. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1532. if (cmd.va == NULL)
  1533. return -1;
  1534. memset(cmd.va, 0, cmd.size);
  1535. if (enable) {
  1536. status = pci_write_config_dword(adapter->pdev,
  1537. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1538. if (status) {
  1539. dev_err(&adapter->pdev->dev,
  1540. "Could not enable Wake-on-lan\n");
  1541. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1542. cmd.dma);
  1543. return status;
  1544. }
  1545. status = be_cmd_enable_magic_wol(adapter,
  1546. adapter->netdev->dev_addr, &cmd);
  1547. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1548. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1549. } else {
  1550. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1551. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1552. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1553. }
  1554. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1555. return status;
  1556. }
  1557. static int be_setup(struct be_adapter *adapter)
  1558. {
  1559. struct net_device *netdev = adapter->netdev;
  1560. u32 cap_flags, en_flags, vf = 0;
  1561. int status;
  1562. u8 mac[ETH_ALEN];
  1563. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
  1564. if (be_physfn(adapter)) {
  1565. cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1566. BE_IF_FLAGS_PROMISCUOUS |
  1567. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1568. en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1569. }
  1570. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1571. netdev->dev_addr, false/* pmac_invalid */,
  1572. &adapter->if_handle, &adapter->pmac_id, 0);
  1573. if (status != 0)
  1574. goto do_none;
  1575. if (be_physfn(adapter)) {
  1576. while (vf < num_vfs) {
  1577. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
  1578. | BE_IF_FLAGS_BROADCAST;
  1579. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1580. mac, true, &adapter->vf_if_handle[vf],
  1581. NULL, vf+1);
  1582. if (status) {
  1583. dev_err(&adapter->pdev->dev,
  1584. "Interface Create failed for VF %d\n", vf);
  1585. goto if_destroy;
  1586. }
  1587. vf++;
  1588. }
  1589. } else if (!be_physfn(adapter)) {
  1590. status = be_cmd_mac_addr_query(adapter, mac,
  1591. MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
  1592. if (!status) {
  1593. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1594. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1595. }
  1596. }
  1597. status = be_tx_queues_create(adapter);
  1598. if (status != 0)
  1599. goto if_destroy;
  1600. status = be_rx_queues_create(adapter);
  1601. if (status != 0)
  1602. goto tx_qs_destroy;
  1603. status = be_mcc_queues_create(adapter);
  1604. if (status != 0)
  1605. goto rx_qs_destroy;
  1606. adapter->link_speed = -1;
  1607. return 0;
  1608. rx_qs_destroy:
  1609. be_rx_queues_destroy(adapter);
  1610. tx_qs_destroy:
  1611. be_tx_queues_destroy(adapter);
  1612. if_destroy:
  1613. for (vf = 0; vf < num_vfs; vf++)
  1614. if (adapter->vf_if_handle[vf])
  1615. be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
  1616. be_cmd_if_destroy(adapter, adapter->if_handle);
  1617. do_none:
  1618. return status;
  1619. }
  1620. static int be_clear(struct be_adapter *adapter)
  1621. {
  1622. be_mcc_queues_destroy(adapter);
  1623. be_rx_queues_destroy(adapter);
  1624. be_tx_queues_destroy(adapter);
  1625. be_cmd_if_destroy(adapter, adapter->if_handle);
  1626. /* tell fw we're done with firing cmds */
  1627. be_cmd_fw_clean(adapter);
  1628. return 0;
  1629. }
  1630. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1631. char flash_cookie[2][16] = {"*** SE FLAS",
  1632. "H DIRECTORY *** "};
  1633. static bool be_flash_redboot(struct be_adapter *adapter,
  1634. const u8 *p, u32 img_start, int image_size,
  1635. int hdr_size)
  1636. {
  1637. u32 crc_offset;
  1638. u8 flashed_crc[4];
  1639. int status;
  1640. crc_offset = hdr_size + img_start + image_size - 4;
  1641. p += crc_offset;
  1642. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1643. (image_size - 4));
  1644. if (status) {
  1645. dev_err(&adapter->pdev->dev,
  1646. "could not get crc from flash, not flashing redboot\n");
  1647. return false;
  1648. }
  1649. /*update redboot only if crc does not match*/
  1650. if (!memcmp(flashed_crc, p, 4))
  1651. return false;
  1652. else
  1653. return true;
  1654. }
  1655. static int be_flash_data(struct be_adapter *adapter,
  1656. const struct firmware *fw,
  1657. struct be_dma_mem *flash_cmd, int num_of_images)
  1658. {
  1659. int status = 0, i, filehdr_size = 0;
  1660. u32 total_bytes = 0, flash_op;
  1661. int num_bytes;
  1662. const u8 *p = fw->data;
  1663. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1664. struct flash_comp *pflashcomp;
  1665. int num_comp;
  1666. struct flash_comp gen3_flash_types[9] = {
  1667. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1668. FLASH_IMAGE_MAX_SIZE_g3},
  1669. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1670. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1671. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1672. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1673. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1674. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1675. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1676. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1677. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1678. FLASH_IMAGE_MAX_SIZE_g3},
  1679. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1680. FLASH_IMAGE_MAX_SIZE_g3},
  1681. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1682. FLASH_IMAGE_MAX_SIZE_g3},
  1683. { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
  1684. FLASH_NCSI_IMAGE_MAX_SIZE_g3}
  1685. };
  1686. struct flash_comp gen2_flash_types[8] = {
  1687. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1688. FLASH_IMAGE_MAX_SIZE_g2},
  1689. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1690. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1691. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1692. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1693. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1694. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1695. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1696. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1697. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1698. FLASH_IMAGE_MAX_SIZE_g2},
  1699. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1700. FLASH_IMAGE_MAX_SIZE_g2},
  1701. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1702. FLASH_IMAGE_MAX_SIZE_g2}
  1703. };
  1704. if (adapter->generation == BE_GEN3) {
  1705. pflashcomp = gen3_flash_types;
  1706. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1707. num_comp = 9;
  1708. } else {
  1709. pflashcomp = gen2_flash_types;
  1710. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1711. num_comp = 8;
  1712. }
  1713. for (i = 0; i < num_comp; i++) {
  1714. if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
  1715. memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
  1716. continue;
  1717. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1718. (!be_flash_redboot(adapter, fw->data,
  1719. pflashcomp[i].offset, pflashcomp[i].size,
  1720. filehdr_size)))
  1721. continue;
  1722. p = fw->data;
  1723. p += filehdr_size + pflashcomp[i].offset
  1724. + (num_of_images * sizeof(struct image_hdr));
  1725. if (p + pflashcomp[i].size > fw->data + fw->size)
  1726. return -1;
  1727. total_bytes = pflashcomp[i].size;
  1728. while (total_bytes) {
  1729. if (total_bytes > 32*1024)
  1730. num_bytes = 32*1024;
  1731. else
  1732. num_bytes = total_bytes;
  1733. total_bytes -= num_bytes;
  1734. if (!total_bytes)
  1735. flash_op = FLASHROM_OPER_FLASH;
  1736. else
  1737. flash_op = FLASHROM_OPER_SAVE;
  1738. memcpy(req->params.data_buf, p, num_bytes);
  1739. p += num_bytes;
  1740. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1741. pflashcomp[i].optype, flash_op, num_bytes);
  1742. if (status) {
  1743. dev_err(&adapter->pdev->dev,
  1744. "cmd to write to flash rom failed.\n");
  1745. return -1;
  1746. }
  1747. yield();
  1748. }
  1749. }
  1750. return 0;
  1751. }
  1752. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1753. {
  1754. if (fhdr == NULL)
  1755. return 0;
  1756. if (fhdr->build[0] == '3')
  1757. return BE_GEN3;
  1758. else if (fhdr->build[0] == '2')
  1759. return BE_GEN2;
  1760. else
  1761. return 0;
  1762. }
  1763. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1764. {
  1765. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1766. const struct firmware *fw;
  1767. struct flash_file_hdr_g2 *fhdr;
  1768. struct flash_file_hdr_g3 *fhdr3;
  1769. struct image_hdr *img_hdr_ptr = NULL;
  1770. struct be_dma_mem flash_cmd;
  1771. int status, i = 0, num_imgs = 0;
  1772. const u8 *p;
  1773. strcpy(fw_file, func);
  1774. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1775. if (status)
  1776. goto fw_exit;
  1777. p = fw->data;
  1778. fhdr = (struct flash_file_hdr_g2 *) p;
  1779. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1780. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1781. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1782. &flash_cmd.dma);
  1783. if (!flash_cmd.va) {
  1784. status = -ENOMEM;
  1785. dev_err(&adapter->pdev->dev,
  1786. "Memory allocation failure while flashing\n");
  1787. goto fw_exit;
  1788. }
  1789. if ((adapter->generation == BE_GEN3) &&
  1790. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1791. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1792. num_imgs = le32_to_cpu(fhdr3->num_imgs);
  1793. for (i = 0; i < num_imgs; i++) {
  1794. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1795. (sizeof(struct flash_file_hdr_g3) +
  1796. i * sizeof(struct image_hdr)));
  1797. if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
  1798. status = be_flash_data(adapter, fw, &flash_cmd,
  1799. num_imgs);
  1800. }
  1801. } else if ((adapter->generation == BE_GEN2) &&
  1802. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1803. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1804. } else {
  1805. dev_err(&adapter->pdev->dev,
  1806. "UFI and Interface are not compatible for flashing\n");
  1807. status = -1;
  1808. }
  1809. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1810. flash_cmd.dma);
  1811. if (status) {
  1812. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1813. goto fw_exit;
  1814. }
  1815. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1816. fw_exit:
  1817. release_firmware(fw);
  1818. return status;
  1819. }
  1820. static struct net_device_ops be_netdev_ops = {
  1821. .ndo_open = be_open,
  1822. .ndo_stop = be_close,
  1823. .ndo_start_xmit = be_xmit,
  1824. .ndo_get_stats = be_get_stats,
  1825. .ndo_set_rx_mode = be_set_multicast_list,
  1826. .ndo_set_mac_address = be_mac_addr_set,
  1827. .ndo_change_mtu = be_change_mtu,
  1828. .ndo_validate_addr = eth_validate_addr,
  1829. .ndo_vlan_rx_register = be_vlan_register,
  1830. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1831. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1832. .ndo_set_vf_mac = be_set_vf_mac
  1833. };
  1834. static void be_netdev_init(struct net_device *netdev)
  1835. {
  1836. struct be_adapter *adapter = netdev_priv(netdev);
  1837. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1838. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1839. NETIF_F_GRO | NETIF_F_TSO6;
  1840. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1841. netdev->flags |= IFF_MULTICAST;
  1842. adapter->rx_csum = true;
  1843. /* Default settings for Rx and Tx flow control */
  1844. adapter->rx_fc = true;
  1845. adapter->tx_fc = true;
  1846. netif_set_gso_max_size(netdev, 65535);
  1847. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1848. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1849. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1850. BE_NAPI_WEIGHT);
  1851. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1852. BE_NAPI_WEIGHT);
  1853. netif_carrier_off(netdev);
  1854. netif_stop_queue(netdev);
  1855. }
  1856. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1857. {
  1858. if (adapter->csr)
  1859. iounmap(adapter->csr);
  1860. if (adapter->db)
  1861. iounmap(adapter->db);
  1862. if (adapter->pcicfg && be_physfn(adapter))
  1863. iounmap(adapter->pcicfg);
  1864. }
  1865. static int be_map_pci_bars(struct be_adapter *adapter)
  1866. {
  1867. u8 __iomem *addr;
  1868. int pcicfg_reg, db_reg;
  1869. if (be_physfn(adapter)) {
  1870. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1871. pci_resource_len(adapter->pdev, 2));
  1872. if (addr == NULL)
  1873. return -ENOMEM;
  1874. adapter->csr = addr;
  1875. }
  1876. if (adapter->generation == BE_GEN2) {
  1877. pcicfg_reg = 1;
  1878. db_reg = 4;
  1879. } else {
  1880. pcicfg_reg = 0;
  1881. if (be_physfn(adapter))
  1882. db_reg = 4;
  1883. else
  1884. db_reg = 0;
  1885. }
  1886. addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
  1887. pci_resource_len(adapter->pdev, db_reg));
  1888. if (addr == NULL)
  1889. goto pci_map_err;
  1890. adapter->db = addr;
  1891. if (be_physfn(adapter)) {
  1892. addr = ioremap_nocache(
  1893. pci_resource_start(adapter->pdev, pcicfg_reg),
  1894. pci_resource_len(adapter->pdev, pcicfg_reg));
  1895. if (addr == NULL)
  1896. goto pci_map_err;
  1897. adapter->pcicfg = addr;
  1898. } else
  1899. adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
  1900. return 0;
  1901. pci_map_err:
  1902. be_unmap_pci_bars(adapter);
  1903. return -ENOMEM;
  1904. }
  1905. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1906. {
  1907. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1908. be_unmap_pci_bars(adapter);
  1909. if (mem->va)
  1910. pci_free_consistent(adapter->pdev, mem->size,
  1911. mem->va, mem->dma);
  1912. mem = &adapter->mc_cmd_mem;
  1913. if (mem->va)
  1914. pci_free_consistent(adapter->pdev, mem->size,
  1915. mem->va, mem->dma);
  1916. }
  1917. static int be_ctrl_init(struct be_adapter *adapter)
  1918. {
  1919. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1920. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1921. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1922. int status;
  1923. status = be_map_pci_bars(adapter);
  1924. if (status)
  1925. goto done;
  1926. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1927. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1928. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1929. if (!mbox_mem_alloc->va) {
  1930. status = -ENOMEM;
  1931. goto unmap_pci_bars;
  1932. }
  1933. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1934. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1935. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1936. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1937. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1938. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1939. &mc_cmd_mem->dma);
  1940. if (mc_cmd_mem->va == NULL) {
  1941. status = -ENOMEM;
  1942. goto free_mbox;
  1943. }
  1944. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1945. spin_lock_init(&adapter->mbox_lock);
  1946. spin_lock_init(&adapter->mcc_lock);
  1947. spin_lock_init(&adapter->mcc_cq_lock);
  1948. init_completion(&adapter->flash_compl);
  1949. pci_save_state(adapter->pdev);
  1950. return 0;
  1951. free_mbox:
  1952. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1953. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1954. unmap_pci_bars:
  1955. be_unmap_pci_bars(adapter);
  1956. done:
  1957. return status;
  1958. }
  1959. static void be_stats_cleanup(struct be_adapter *adapter)
  1960. {
  1961. struct be_stats_obj *stats = &adapter->stats;
  1962. struct be_dma_mem *cmd = &stats->cmd;
  1963. if (cmd->va)
  1964. pci_free_consistent(adapter->pdev, cmd->size,
  1965. cmd->va, cmd->dma);
  1966. }
  1967. static int be_stats_init(struct be_adapter *adapter)
  1968. {
  1969. struct be_stats_obj *stats = &adapter->stats;
  1970. struct be_dma_mem *cmd = &stats->cmd;
  1971. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1972. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1973. if (cmd->va == NULL)
  1974. return -1;
  1975. memset(cmd->va, 0, cmd->size);
  1976. return 0;
  1977. }
  1978. static void __devexit be_remove(struct pci_dev *pdev)
  1979. {
  1980. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1981. if (!adapter)
  1982. return;
  1983. unregister_netdev(adapter->netdev);
  1984. be_clear(adapter);
  1985. be_stats_cleanup(adapter);
  1986. be_ctrl_cleanup(adapter);
  1987. be_sriov_disable(adapter);
  1988. be_msix_disable(adapter);
  1989. pci_set_drvdata(pdev, NULL);
  1990. pci_release_regions(pdev);
  1991. pci_disable_device(pdev);
  1992. free_netdev(adapter->netdev);
  1993. }
  1994. static int be_get_config(struct be_adapter *adapter)
  1995. {
  1996. int status;
  1997. u8 mac[ETH_ALEN];
  1998. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  1999. if (status)
  2000. return status;
  2001. status = be_cmd_query_fw_cfg(adapter,
  2002. &adapter->port_num, &adapter->cap);
  2003. if (status)
  2004. return status;
  2005. memset(mac, 0, ETH_ALEN);
  2006. if (be_physfn(adapter)) {
  2007. status = be_cmd_mac_addr_query(adapter, mac,
  2008. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  2009. if (status)
  2010. return status;
  2011. if (!is_valid_ether_addr(mac))
  2012. return -EADDRNOTAVAIL;
  2013. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  2014. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  2015. }
  2016. if (adapter->cap & 0x400)
  2017. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
  2018. else
  2019. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
  2020. return 0;
  2021. }
  2022. static int __devinit be_probe(struct pci_dev *pdev,
  2023. const struct pci_device_id *pdev_id)
  2024. {
  2025. int status = 0;
  2026. struct be_adapter *adapter;
  2027. struct net_device *netdev;
  2028. status = pci_enable_device(pdev);
  2029. if (status)
  2030. goto do_none;
  2031. status = pci_request_regions(pdev, DRV_NAME);
  2032. if (status)
  2033. goto disable_dev;
  2034. pci_set_master(pdev);
  2035. netdev = alloc_etherdev(sizeof(struct be_adapter));
  2036. if (netdev == NULL) {
  2037. status = -ENOMEM;
  2038. goto rel_reg;
  2039. }
  2040. adapter = netdev_priv(netdev);
  2041. switch (pdev->device) {
  2042. case BE_DEVICE_ID1:
  2043. case OC_DEVICE_ID1:
  2044. adapter->generation = BE_GEN2;
  2045. break;
  2046. case BE_DEVICE_ID2:
  2047. case OC_DEVICE_ID2:
  2048. adapter->generation = BE_GEN3;
  2049. break;
  2050. default:
  2051. adapter->generation = 0;
  2052. }
  2053. adapter->pdev = pdev;
  2054. pci_set_drvdata(pdev, adapter);
  2055. adapter->netdev = netdev;
  2056. be_netdev_init(netdev);
  2057. SET_NETDEV_DEV(netdev, &pdev->dev);
  2058. be_msix_enable(adapter);
  2059. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  2060. if (!status) {
  2061. netdev->features |= NETIF_F_HIGHDMA;
  2062. } else {
  2063. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2064. if (status) {
  2065. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  2066. goto free_netdev;
  2067. }
  2068. }
  2069. be_sriov_enable(adapter);
  2070. status = be_ctrl_init(adapter);
  2071. if (status)
  2072. goto free_netdev;
  2073. /* sync up with fw's ready state */
  2074. if (be_physfn(adapter)) {
  2075. status = be_cmd_POST(adapter);
  2076. if (status)
  2077. goto ctrl_clean;
  2078. }
  2079. /* tell fw we're ready to fire cmds */
  2080. status = be_cmd_fw_init(adapter);
  2081. if (status)
  2082. goto ctrl_clean;
  2083. if (be_physfn(adapter)) {
  2084. status = be_cmd_reset_function(adapter);
  2085. if (status)
  2086. goto ctrl_clean;
  2087. }
  2088. status = be_stats_init(adapter);
  2089. if (status)
  2090. goto ctrl_clean;
  2091. status = be_get_config(adapter);
  2092. if (status)
  2093. goto stats_clean;
  2094. INIT_DELAYED_WORK(&adapter->work, be_worker);
  2095. status = be_setup(adapter);
  2096. if (status)
  2097. goto stats_clean;
  2098. status = register_netdev(netdev);
  2099. if (status != 0)
  2100. goto unsetup;
  2101. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  2102. return 0;
  2103. unsetup:
  2104. be_clear(adapter);
  2105. stats_clean:
  2106. be_stats_cleanup(adapter);
  2107. ctrl_clean:
  2108. be_ctrl_cleanup(adapter);
  2109. free_netdev:
  2110. be_msix_disable(adapter);
  2111. be_sriov_disable(adapter);
  2112. free_netdev(adapter->netdev);
  2113. pci_set_drvdata(pdev, NULL);
  2114. rel_reg:
  2115. pci_release_regions(pdev);
  2116. disable_dev:
  2117. pci_disable_device(pdev);
  2118. do_none:
  2119. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  2120. return status;
  2121. }
  2122. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  2123. {
  2124. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2125. struct net_device *netdev = adapter->netdev;
  2126. if (adapter->wol)
  2127. be_setup_wol(adapter, true);
  2128. netif_device_detach(netdev);
  2129. if (netif_running(netdev)) {
  2130. rtnl_lock();
  2131. be_close(netdev);
  2132. rtnl_unlock();
  2133. }
  2134. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  2135. be_clear(adapter);
  2136. pci_save_state(pdev);
  2137. pci_disable_device(pdev);
  2138. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2139. return 0;
  2140. }
  2141. static int be_resume(struct pci_dev *pdev)
  2142. {
  2143. int status = 0;
  2144. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2145. struct net_device *netdev = adapter->netdev;
  2146. netif_device_detach(netdev);
  2147. status = pci_enable_device(pdev);
  2148. if (status)
  2149. return status;
  2150. pci_set_power_state(pdev, 0);
  2151. pci_restore_state(pdev);
  2152. /* tell fw we're ready to fire cmds */
  2153. status = be_cmd_fw_init(adapter);
  2154. if (status)
  2155. return status;
  2156. be_setup(adapter);
  2157. if (netif_running(netdev)) {
  2158. rtnl_lock();
  2159. be_open(netdev);
  2160. rtnl_unlock();
  2161. }
  2162. netif_device_attach(netdev);
  2163. if (adapter->wol)
  2164. be_setup_wol(adapter, false);
  2165. return 0;
  2166. }
  2167. /*
  2168. * An FLR will stop BE from DMAing any data.
  2169. */
  2170. static void be_shutdown(struct pci_dev *pdev)
  2171. {
  2172. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2173. struct net_device *netdev = adapter->netdev;
  2174. netif_device_detach(netdev);
  2175. be_cmd_reset_function(adapter);
  2176. if (adapter->wol)
  2177. be_setup_wol(adapter, true);
  2178. pci_disable_device(pdev);
  2179. }
  2180. static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
  2181. pci_channel_state_t state)
  2182. {
  2183. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2184. struct net_device *netdev = adapter->netdev;
  2185. dev_err(&adapter->pdev->dev, "EEH error detected\n");
  2186. adapter->eeh_err = true;
  2187. netif_device_detach(netdev);
  2188. if (netif_running(netdev)) {
  2189. rtnl_lock();
  2190. be_close(netdev);
  2191. rtnl_unlock();
  2192. }
  2193. be_clear(adapter);
  2194. if (state == pci_channel_io_perm_failure)
  2195. return PCI_ERS_RESULT_DISCONNECT;
  2196. pci_disable_device(pdev);
  2197. return PCI_ERS_RESULT_NEED_RESET;
  2198. }
  2199. static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
  2200. {
  2201. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2202. int status;
  2203. dev_info(&adapter->pdev->dev, "EEH reset\n");
  2204. adapter->eeh_err = false;
  2205. status = pci_enable_device(pdev);
  2206. if (status)
  2207. return PCI_ERS_RESULT_DISCONNECT;
  2208. pci_set_master(pdev);
  2209. pci_set_power_state(pdev, 0);
  2210. pci_restore_state(pdev);
  2211. /* Check if card is ok and fw is ready */
  2212. status = be_cmd_POST(adapter);
  2213. if (status)
  2214. return PCI_ERS_RESULT_DISCONNECT;
  2215. return PCI_ERS_RESULT_RECOVERED;
  2216. }
  2217. static void be_eeh_resume(struct pci_dev *pdev)
  2218. {
  2219. int status = 0;
  2220. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2221. struct net_device *netdev = adapter->netdev;
  2222. dev_info(&adapter->pdev->dev, "EEH resume\n");
  2223. pci_save_state(pdev);
  2224. /* tell fw we're ready to fire cmds */
  2225. status = be_cmd_fw_init(adapter);
  2226. if (status)
  2227. goto err;
  2228. status = be_setup(adapter);
  2229. if (status)
  2230. goto err;
  2231. if (netif_running(netdev)) {
  2232. status = be_open(netdev);
  2233. if (status)
  2234. goto err;
  2235. }
  2236. netif_device_attach(netdev);
  2237. return;
  2238. err:
  2239. dev_err(&adapter->pdev->dev, "EEH resume failed\n");
  2240. }
  2241. static struct pci_error_handlers be_eeh_handlers = {
  2242. .error_detected = be_eeh_err_detected,
  2243. .slot_reset = be_eeh_reset,
  2244. .resume = be_eeh_resume,
  2245. };
  2246. static struct pci_driver be_driver = {
  2247. .name = DRV_NAME,
  2248. .id_table = be_dev_ids,
  2249. .probe = be_probe,
  2250. .remove = be_remove,
  2251. .suspend = be_suspend,
  2252. .resume = be_resume,
  2253. .shutdown = be_shutdown,
  2254. .err_handler = &be_eeh_handlers
  2255. };
  2256. static int __init be_init_module(void)
  2257. {
  2258. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2259. rx_frag_size != 2048) {
  2260. printk(KERN_WARNING DRV_NAME
  2261. " : Module param rx_frag_size must be 2048/4096/8192."
  2262. " Using 2048\n");
  2263. rx_frag_size = 2048;
  2264. }
  2265. if (num_vfs > 32) {
  2266. printk(KERN_WARNING DRV_NAME
  2267. " : Module param num_vfs must not be greater than 32."
  2268. "Using 32\n");
  2269. num_vfs = 32;
  2270. }
  2271. return pci_register_driver(&be_driver);
  2272. }
  2273. module_init(be_init_module);
  2274. static void __exit be_exit_module(void)
  2275. {
  2276. pci_unregister_driver(&be_driver);
  2277. }
  2278. module_exit(be_exit_module);