bna_tx_rx.c 91 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfi.h"
  20. /**
  21. * IB
  22. */
  23. static void
  24. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  25. {
  26. ib->coalescing_timeo = coalescing_timeo;
  27. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  28. (u32)ib->coalescing_timeo, 0);
  29. }
  30. /**
  31. * RXF
  32. */
  33. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  34. do { \
  35. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  36. (rxf)->vlan_strip_pending = true; \
  37. } while (0)
  38. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  39. do { \
  40. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  41. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  42. BNA_RSS_F_CFG_PENDING | \
  43. BNA_RSS_F_STATUS_PENDING); \
  44. } while (0)
  45. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  46. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  47. static int bna_rxf_fltr_clear(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  49. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  50. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  51. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  52. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  55. enum bna_cleanup_type cleanup);
  56. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  57. enum bna_cleanup_type cleanup);
  58. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, paused, struct bna_rxf,
  61. enum bna_rxf_event);
  62. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  63. enum bna_rxf_event);
  64. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  65. enum bna_rxf_event);
  66. bfa_fsm_state_decl(bna_rxf, fltr_clr_wait, struct bna_rxf,
  67. enum bna_rxf_event);
  68. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  69. enum bna_rxf_event);
  70. static void
  71. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  72. {
  73. call_rxf_stop_cbfn(rxf);
  74. }
  75. static void
  76. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  77. {
  78. switch (event) {
  79. case RXF_E_START:
  80. if (rxf->flags & BNA_RXF_F_PAUSED) {
  81. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  82. call_rxf_start_cbfn(rxf);
  83. } else
  84. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  85. break;
  86. case RXF_E_STOP:
  87. call_rxf_stop_cbfn(rxf);
  88. break;
  89. case RXF_E_FAIL:
  90. /* No-op */
  91. break;
  92. case RXF_E_CONFIG:
  93. call_rxf_cam_fltr_cbfn(rxf);
  94. break;
  95. case RXF_E_PAUSE:
  96. rxf->flags |= BNA_RXF_F_PAUSED;
  97. call_rxf_pause_cbfn(rxf);
  98. break;
  99. case RXF_E_RESUME:
  100. rxf->flags &= ~BNA_RXF_F_PAUSED;
  101. call_rxf_resume_cbfn(rxf);
  102. break;
  103. default:
  104. bfa_sm_fault(event);
  105. }
  106. }
  107. static void
  108. bna_rxf_sm_paused_entry(struct bna_rxf *rxf)
  109. {
  110. call_rxf_pause_cbfn(rxf);
  111. }
  112. static void
  113. bna_rxf_sm_paused(struct bna_rxf *rxf, enum bna_rxf_event event)
  114. {
  115. switch (event) {
  116. case RXF_E_STOP:
  117. case RXF_E_FAIL:
  118. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  119. break;
  120. case RXF_E_CONFIG:
  121. call_rxf_cam_fltr_cbfn(rxf);
  122. break;
  123. case RXF_E_RESUME:
  124. rxf->flags &= ~BNA_RXF_F_PAUSED;
  125. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  126. break;
  127. default:
  128. bfa_sm_fault(event);
  129. }
  130. }
  131. static void
  132. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  133. {
  134. if (!bna_rxf_cfg_apply(rxf)) {
  135. /* No more pending config updates */
  136. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  137. }
  138. }
  139. static void
  140. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  141. {
  142. switch (event) {
  143. case RXF_E_STOP:
  144. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  145. break;
  146. case RXF_E_FAIL:
  147. bna_rxf_cfg_reset(rxf);
  148. call_rxf_start_cbfn(rxf);
  149. call_rxf_cam_fltr_cbfn(rxf);
  150. call_rxf_resume_cbfn(rxf);
  151. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  152. break;
  153. case RXF_E_CONFIG:
  154. /* No-op */
  155. break;
  156. case RXF_E_PAUSE:
  157. rxf->flags |= BNA_RXF_F_PAUSED;
  158. call_rxf_start_cbfn(rxf);
  159. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  160. break;
  161. case RXF_E_FW_RESP:
  162. if (!bna_rxf_cfg_apply(rxf)) {
  163. /* No more pending config updates */
  164. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  165. }
  166. break;
  167. default:
  168. bfa_sm_fault(event);
  169. }
  170. }
  171. static void
  172. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  173. {
  174. call_rxf_start_cbfn(rxf);
  175. call_rxf_cam_fltr_cbfn(rxf);
  176. call_rxf_resume_cbfn(rxf);
  177. }
  178. static void
  179. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  180. {
  181. switch (event) {
  182. case RXF_E_STOP:
  183. case RXF_E_FAIL:
  184. bna_rxf_cfg_reset(rxf);
  185. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  186. break;
  187. case RXF_E_CONFIG:
  188. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  189. break;
  190. case RXF_E_PAUSE:
  191. rxf->flags |= BNA_RXF_F_PAUSED;
  192. if (!bna_rxf_fltr_clear(rxf))
  193. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  194. else
  195. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  196. break;
  197. default:
  198. bfa_sm_fault(event);
  199. }
  200. }
  201. static void
  202. bna_rxf_sm_fltr_clr_wait_entry(struct bna_rxf *rxf)
  203. {
  204. }
  205. static void
  206. bna_rxf_sm_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  207. {
  208. switch (event) {
  209. case RXF_E_FAIL:
  210. bna_rxf_cfg_reset(rxf);
  211. call_rxf_pause_cbfn(rxf);
  212. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  213. break;
  214. case RXF_E_FW_RESP:
  215. if (!bna_rxf_fltr_clear(rxf)) {
  216. /* No more pending CAM entries to clear */
  217. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  218. }
  219. break;
  220. default:
  221. bfa_sm_fault(event);
  222. }
  223. }
  224. static void
  225. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  226. {
  227. }
  228. static void
  229. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  230. {
  231. switch (event) {
  232. case RXF_E_FAIL:
  233. case RXF_E_FW_RESP:
  234. bna_rxf_cfg_reset(rxf);
  235. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  236. break;
  237. default:
  238. bfa_sm_fault(event);
  239. }
  240. }
  241. static void
  242. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  243. enum bfi_enet_h2i_msgs req_type)
  244. {
  245. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  246. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  247. req->mh.num_entries = htons(
  248. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  249. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  250. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  251. sizeof(struct bfi_enet_ucast_req), &req->mh);
  252. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  253. }
  254. static void
  255. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  256. {
  257. struct bfi_enet_mcast_add_req *req =
  258. &rxf->bfi_enet_cmd.mcast_add_req;
  259. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  260. 0, rxf->rx->rid);
  261. req->mh.num_entries = htons(
  262. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  263. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  264. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  265. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  266. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  267. }
  268. static void
  269. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  270. {
  271. struct bfi_enet_mcast_del_req *req =
  272. &rxf->bfi_enet_cmd.mcast_del_req;
  273. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  274. 0, rxf->rx->rid);
  275. req->mh.num_entries = htons(
  276. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  277. req->handle = htons(handle);
  278. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  279. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  280. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  281. }
  282. static void
  283. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  284. {
  285. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  286. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  287. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  288. req->mh.num_entries = htons(
  289. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  290. req->enable = status;
  291. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  292. sizeof(struct bfi_enet_enable_req), &req->mh);
  293. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  294. }
  295. static void
  296. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  297. {
  298. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  299. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  300. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  301. req->mh.num_entries = htons(
  302. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  303. req->enable = status;
  304. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  305. sizeof(struct bfi_enet_enable_req), &req->mh);
  306. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  307. }
  308. static void
  309. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  310. {
  311. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  312. int i;
  313. int j;
  314. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  315. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  316. req->mh.num_entries = htons(
  317. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  318. req->block_idx = block_idx;
  319. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  320. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  321. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  322. req->bit_mask[i] =
  323. htonl(rxf->vlan_filter_table[j]);
  324. else
  325. req->bit_mask[i] = 0xFFFFFFFF;
  326. }
  327. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  328. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  329. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  330. }
  331. static void
  332. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  333. {
  334. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  335. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  336. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  337. req->mh.num_entries = htons(
  338. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  339. req->enable = rxf->vlan_strip_status;
  340. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  341. sizeof(struct bfi_enet_enable_req), &req->mh);
  342. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  343. }
  344. static void
  345. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  346. {
  347. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  348. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  349. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  350. req->mh.num_entries = htons(
  351. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  352. req->size = htons(rxf->rit_size);
  353. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  354. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  355. sizeof(struct bfi_enet_rit_req), &req->mh);
  356. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  357. }
  358. static void
  359. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  360. {
  361. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  362. int i;
  363. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  364. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  365. req->mh.num_entries = htons(
  366. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  367. req->cfg.type = rxf->rss_cfg.hash_type;
  368. req->cfg.mask = rxf->rss_cfg.hash_mask;
  369. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  370. req->cfg.key[i] =
  371. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  372. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  373. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  374. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  375. }
  376. static void
  377. bna_bfi_rss_enable(struct bna_rxf *rxf)
  378. {
  379. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  380. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  381. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  382. req->mh.num_entries = htons(
  383. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  384. req->enable = rxf->rss_status;
  385. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  386. sizeof(struct bfi_enet_enable_req), &req->mh);
  387. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  388. }
  389. /* This function gets the multicast MAC that has already been added to CAM */
  390. static struct bna_mac *
  391. bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
  392. {
  393. struct bna_mac *mac;
  394. struct list_head *qe;
  395. list_for_each(qe, &rxf->mcast_active_q) {
  396. mac = (struct bna_mac *)qe;
  397. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  398. return mac;
  399. }
  400. list_for_each(qe, &rxf->mcast_pending_del_q) {
  401. mac = (struct bna_mac *)qe;
  402. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  403. return mac;
  404. }
  405. return NULL;
  406. }
  407. static struct bna_mcam_handle *
  408. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  409. {
  410. struct bna_mcam_handle *mchandle;
  411. struct list_head *qe;
  412. list_for_each(qe, &rxf->mcast_handle_q) {
  413. mchandle = (struct bna_mcam_handle *)qe;
  414. if (mchandle->handle == handle)
  415. return mchandle;
  416. }
  417. return NULL;
  418. }
  419. static void
  420. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  421. {
  422. struct bna_mac *mcmac;
  423. struct bna_mcam_handle *mchandle;
  424. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  425. mchandle = bna_rxf_mchandle_get(rxf, handle);
  426. if (mchandle == NULL) {
  427. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  428. mchandle->handle = handle;
  429. mchandle->refcnt = 0;
  430. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  431. }
  432. mchandle->refcnt++;
  433. mcmac->handle = mchandle;
  434. }
  435. static int
  436. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  437. enum bna_cleanup_type cleanup)
  438. {
  439. struct bna_mcam_handle *mchandle;
  440. int ret = 0;
  441. mchandle = mac->handle;
  442. if (mchandle == NULL)
  443. return ret;
  444. mchandle->refcnt--;
  445. if (mchandle->refcnt == 0) {
  446. if (cleanup == BNA_HARD_CLEANUP) {
  447. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  448. ret = 1;
  449. }
  450. list_del(&mchandle->qe);
  451. bfa_q_qe_init(&mchandle->qe);
  452. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  453. }
  454. mac->handle = NULL;
  455. return ret;
  456. }
  457. static int
  458. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  459. {
  460. struct bna_mac *mac = NULL;
  461. struct list_head *qe;
  462. int ret;
  463. /* Delete multicast entries previousely added */
  464. while (!list_empty(&rxf->mcast_pending_del_q)) {
  465. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  466. bfa_q_qe_init(qe);
  467. mac = (struct bna_mac *)qe;
  468. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  469. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  470. if (ret)
  471. return ret;
  472. }
  473. /* Add multicast entries */
  474. if (!list_empty(&rxf->mcast_pending_add_q)) {
  475. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  476. bfa_q_qe_init(qe);
  477. mac = (struct bna_mac *)qe;
  478. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  479. bna_bfi_mcast_add_req(rxf, mac);
  480. return 1;
  481. }
  482. return 0;
  483. }
  484. static int
  485. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  486. {
  487. u8 vlan_pending_bitmask;
  488. int block_idx = 0;
  489. if (rxf->vlan_pending_bitmask) {
  490. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  491. while (!(vlan_pending_bitmask & 0x1)) {
  492. block_idx++;
  493. vlan_pending_bitmask >>= 1;
  494. }
  495. rxf->vlan_pending_bitmask &= ~(1 << block_idx);
  496. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  497. return 1;
  498. }
  499. return 0;
  500. }
  501. static int
  502. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  503. {
  504. struct list_head *qe;
  505. struct bna_mac *mac;
  506. int ret;
  507. /* Throw away delete pending mcast entries */
  508. while (!list_empty(&rxf->mcast_pending_del_q)) {
  509. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  510. bfa_q_qe_init(qe);
  511. mac = (struct bna_mac *)qe;
  512. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  513. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  514. if (ret)
  515. return ret;
  516. }
  517. /* Move active mcast entries to pending_add_q */
  518. while (!list_empty(&rxf->mcast_active_q)) {
  519. bfa_q_deq(&rxf->mcast_active_q, &qe);
  520. bfa_q_qe_init(qe);
  521. list_add_tail(qe, &rxf->mcast_pending_add_q);
  522. mac = (struct bna_mac *)qe;
  523. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  524. return 1;
  525. }
  526. return 0;
  527. }
  528. static int
  529. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  530. {
  531. if (rxf->rss_pending) {
  532. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  533. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  534. bna_bfi_rit_cfg(rxf);
  535. return 1;
  536. }
  537. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  538. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  539. bna_bfi_rss_cfg(rxf);
  540. return 1;
  541. }
  542. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  543. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  544. bna_bfi_rss_enable(rxf);
  545. return 1;
  546. }
  547. }
  548. return 0;
  549. }
  550. static int
  551. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  552. {
  553. if (bna_rxf_ucast_cfg_apply(rxf))
  554. return 1;
  555. if (bna_rxf_mcast_cfg_apply(rxf))
  556. return 1;
  557. if (bna_rxf_promisc_cfg_apply(rxf))
  558. return 1;
  559. if (bna_rxf_allmulti_cfg_apply(rxf))
  560. return 1;
  561. if (bna_rxf_vlan_cfg_apply(rxf))
  562. return 1;
  563. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  564. return 1;
  565. if (bna_rxf_rss_cfg_apply(rxf))
  566. return 1;
  567. return 0;
  568. }
  569. /* Only software reset */
  570. static int
  571. bna_rxf_fltr_clear(struct bna_rxf *rxf)
  572. {
  573. if (bna_rxf_ucast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  574. return 1;
  575. if (bna_rxf_mcast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  576. return 1;
  577. if (bna_rxf_promisc_cfg_reset(rxf, BNA_HARD_CLEANUP))
  578. return 1;
  579. if (bna_rxf_allmulti_cfg_reset(rxf, BNA_HARD_CLEANUP))
  580. return 1;
  581. return 0;
  582. }
  583. static void
  584. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  585. {
  586. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  587. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  588. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  589. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  590. bna_rxf_vlan_cfg_soft_reset(rxf);
  591. bna_rxf_rss_cfg_soft_reset(rxf);
  592. }
  593. static void
  594. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  595. {
  596. struct bna_rx *rx = rxf->rx;
  597. struct bna_rxp *rxp;
  598. struct list_head *qe;
  599. int offset = 0;
  600. rxf->rit_size = rit_size;
  601. list_for_each(qe, &rx->rxp_q) {
  602. rxp = (struct bna_rxp *)qe;
  603. rxf->rit[offset] = rxp->cq.ccb->id;
  604. offset++;
  605. }
  606. }
  607. void
  608. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  609. {
  610. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  611. }
  612. void
  613. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  614. struct bfi_msgq_mhdr *msghdr)
  615. {
  616. struct bfi_enet_mcast_add_req *req =
  617. &rxf->bfi_enet_cmd.mcast_add_req;
  618. struct bfi_enet_mcast_add_rsp *rsp =
  619. (struct bfi_enet_mcast_add_rsp *)msghdr;
  620. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  621. ntohs(rsp->handle));
  622. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  623. }
  624. static void
  625. bna_rxf_init(struct bna_rxf *rxf,
  626. struct bna_rx *rx,
  627. struct bna_rx_config *q_config,
  628. struct bna_res_info *res_info)
  629. {
  630. rxf->rx = rx;
  631. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  632. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  633. rxf->ucast_pending_set = 0;
  634. rxf->ucast_active_set = 0;
  635. INIT_LIST_HEAD(&rxf->ucast_active_q);
  636. rxf->ucast_pending_mac = NULL;
  637. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  638. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  639. INIT_LIST_HEAD(&rxf->mcast_active_q);
  640. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  641. if (q_config->paused)
  642. rxf->flags |= BNA_RXF_F_PAUSED;
  643. rxf->rit = (u8 *)
  644. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  645. bna_rit_init(rxf, q_config->num_paths);
  646. rxf->rss_status = q_config->rss_status;
  647. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  648. rxf->rss_cfg = q_config->rss_config;
  649. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  650. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  651. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  652. }
  653. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  654. memset(rxf->vlan_filter_table, 0,
  655. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  656. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  657. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  658. rxf->vlan_strip_status = q_config->vlan_strip_status;
  659. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  660. }
  661. static void
  662. bna_rxf_uninit(struct bna_rxf *rxf)
  663. {
  664. struct bna_mac *mac;
  665. rxf->ucast_pending_set = 0;
  666. rxf->ucast_active_set = 0;
  667. while (!list_empty(&rxf->ucast_pending_add_q)) {
  668. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  669. bfa_q_qe_init(&mac->qe);
  670. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  671. }
  672. if (rxf->ucast_pending_mac) {
  673. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  674. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
  675. rxf->ucast_pending_mac);
  676. rxf->ucast_pending_mac = NULL;
  677. }
  678. while (!list_empty(&rxf->mcast_pending_add_q)) {
  679. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  680. bfa_q_qe_init(&mac->qe);
  681. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  682. }
  683. rxf->rxmode_pending = 0;
  684. rxf->rxmode_pending_bitmask = 0;
  685. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  686. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  687. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  688. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  689. rxf->rss_pending = 0;
  690. rxf->vlan_strip_pending = false;
  691. rxf->flags = 0;
  692. rxf->rx = NULL;
  693. }
  694. static void
  695. bna_rx_cb_rxf_started(struct bna_rx *rx)
  696. {
  697. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  698. }
  699. static void
  700. bna_rxf_start(struct bna_rxf *rxf)
  701. {
  702. rxf->start_cbfn = bna_rx_cb_rxf_started;
  703. rxf->start_cbarg = rxf->rx;
  704. bfa_fsm_send_event(rxf, RXF_E_START);
  705. }
  706. static void
  707. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  708. {
  709. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  710. }
  711. static void
  712. bna_rxf_stop(struct bna_rxf *rxf)
  713. {
  714. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  715. rxf->stop_cbarg = rxf->rx;
  716. bfa_fsm_send_event(rxf, RXF_E_STOP);
  717. }
  718. static void
  719. bna_rxf_fail(struct bna_rxf *rxf)
  720. {
  721. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  722. }
  723. enum bna_cb_status
  724. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  725. void (*cbfn)(struct bnad *, struct bna_rx *))
  726. {
  727. struct bna_rxf *rxf = &rx->rxf;
  728. if (rxf->ucast_pending_mac == NULL) {
  729. rxf->ucast_pending_mac =
  730. bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
  731. if (rxf->ucast_pending_mac == NULL)
  732. return BNA_CB_UCAST_CAM_FULL;
  733. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  734. }
  735. memcpy(rxf->ucast_pending_mac->addr, ucmac, ETH_ALEN);
  736. rxf->ucast_pending_set = 1;
  737. rxf->cam_fltr_cbfn = cbfn;
  738. rxf->cam_fltr_cbarg = rx->bna->bnad;
  739. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  740. return BNA_CB_SUCCESS;
  741. }
  742. enum bna_cb_status
  743. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  744. void (*cbfn)(struct bnad *, struct bna_rx *))
  745. {
  746. struct bna_rxf *rxf = &rx->rxf;
  747. struct bna_mac *mac;
  748. /* Check if already added or pending addition */
  749. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  750. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  751. if (cbfn)
  752. cbfn(rx->bna->bnad, rx);
  753. return BNA_CB_SUCCESS;
  754. }
  755. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  756. if (mac == NULL)
  757. return BNA_CB_MCAST_LIST_FULL;
  758. bfa_q_qe_init(&mac->qe);
  759. memcpy(mac->addr, addr, ETH_ALEN);
  760. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  761. rxf->cam_fltr_cbfn = cbfn;
  762. rxf->cam_fltr_cbarg = rx->bna->bnad;
  763. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  764. return BNA_CB_SUCCESS;
  765. }
  766. enum bna_cb_status
  767. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  768. void (*cbfn)(struct bnad *, struct bna_rx *))
  769. {
  770. struct bna_rxf *rxf = &rx->rxf;
  771. struct list_head list_head;
  772. struct list_head *qe;
  773. u8 *mcaddr;
  774. struct bna_mac *mac;
  775. int i;
  776. /* Allocate nodes */
  777. INIT_LIST_HEAD(&list_head);
  778. for (i = 0, mcaddr = mclist; i < count; i++) {
  779. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  780. if (mac == NULL)
  781. goto err_return;
  782. bfa_q_qe_init(&mac->qe);
  783. memcpy(mac->addr, mcaddr, ETH_ALEN);
  784. list_add_tail(&mac->qe, &list_head);
  785. mcaddr += ETH_ALEN;
  786. }
  787. /* Purge the pending_add_q */
  788. while (!list_empty(&rxf->mcast_pending_add_q)) {
  789. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  790. bfa_q_qe_init(qe);
  791. mac = (struct bna_mac *)qe;
  792. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  793. }
  794. /* Schedule active_q entries for deletion */
  795. while (!list_empty(&rxf->mcast_active_q)) {
  796. bfa_q_deq(&rxf->mcast_active_q, &qe);
  797. mac = (struct bna_mac *)qe;
  798. bfa_q_qe_init(&mac->qe);
  799. list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
  800. }
  801. /* Add the new entries */
  802. while (!list_empty(&list_head)) {
  803. bfa_q_deq(&list_head, &qe);
  804. mac = (struct bna_mac *)qe;
  805. bfa_q_qe_init(&mac->qe);
  806. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  807. }
  808. rxf->cam_fltr_cbfn = cbfn;
  809. rxf->cam_fltr_cbarg = rx->bna->bnad;
  810. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  811. return BNA_CB_SUCCESS;
  812. err_return:
  813. while (!list_empty(&list_head)) {
  814. bfa_q_deq(&list_head, &qe);
  815. mac = (struct bna_mac *)qe;
  816. bfa_q_qe_init(&mac->qe);
  817. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  818. }
  819. return BNA_CB_MCAST_LIST_FULL;
  820. }
  821. void
  822. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  823. {
  824. struct bna_rxf *rxf = &rx->rxf;
  825. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  826. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  827. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  828. rxf->vlan_filter_table[index] |= bit;
  829. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  830. rxf->vlan_pending_bitmask |= (1 << group_id);
  831. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  832. }
  833. }
  834. void
  835. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  836. {
  837. struct bna_rxf *rxf = &rx->rxf;
  838. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  839. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  840. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  841. rxf->vlan_filter_table[index] &= ~bit;
  842. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  843. rxf->vlan_pending_bitmask |= (1 << group_id);
  844. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  845. }
  846. }
  847. static int
  848. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  849. {
  850. struct bna_mac *mac = NULL;
  851. struct list_head *qe;
  852. /* Delete MAC addresses previousely added */
  853. if (!list_empty(&rxf->ucast_pending_del_q)) {
  854. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  855. bfa_q_qe_init(qe);
  856. mac = (struct bna_mac *)qe;
  857. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  858. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  859. return 1;
  860. }
  861. /* Set default unicast MAC */
  862. if (rxf->ucast_pending_set) {
  863. rxf->ucast_pending_set = 0;
  864. memcpy(rxf->ucast_active_mac.addr,
  865. rxf->ucast_pending_mac->addr, ETH_ALEN);
  866. rxf->ucast_active_set = 1;
  867. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  868. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  869. return 1;
  870. }
  871. /* Add additional MAC entries */
  872. if (!list_empty(&rxf->ucast_pending_add_q)) {
  873. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  874. bfa_q_qe_init(qe);
  875. mac = (struct bna_mac *)qe;
  876. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  877. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  878. return 1;
  879. }
  880. return 0;
  881. }
  882. static int
  883. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  884. {
  885. struct list_head *qe;
  886. struct bna_mac *mac;
  887. /* Throw away delete pending ucast entries */
  888. while (!list_empty(&rxf->ucast_pending_del_q)) {
  889. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  890. bfa_q_qe_init(qe);
  891. mac = (struct bna_mac *)qe;
  892. if (cleanup == BNA_SOFT_CLEANUP)
  893. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  894. else {
  895. bna_bfi_ucast_req(rxf, mac,
  896. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  897. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  898. return 1;
  899. }
  900. }
  901. /* Move active ucast entries to pending_add_q */
  902. while (!list_empty(&rxf->ucast_active_q)) {
  903. bfa_q_deq(&rxf->ucast_active_q, &qe);
  904. bfa_q_qe_init(qe);
  905. list_add_tail(qe, &rxf->ucast_pending_add_q);
  906. if (cleanup == BNA_HARD_CLEANUP) {
  907. mac = (struct bna_mac *)qe;
  908. bna_bfi_ucast_req(rxf, mac,
  909. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  910. return 1;
  911. }
  912. }
  913. if (rxf->ucast_active_set) {
  914. rxf->ucast_pending_set = 1;
  915. rxf->ucast_active_set = 0;
  916. if (cleanup == BNA_HARD_CLEANUP) {
  917. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  918. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  919. return 1;
  920. }
  921. }
  922. return 0;
  923. }
  924. static int
  925. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  926. {
  927. struct bna *bna = rxf->rx->bna;
  928. /* Enable/disable promiscuous mode */
  929. if (is_promisc_enable(rxf->rxmode_pending,
  930. rxf->rxmode_pending_bitmask)) {
  931. /* move promisc configuration from pending -> active */
  932. promisc_inactive(rxf->rxmode_pending,
  933. rxf->rxmode_pending_bitmask);
  934. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  935. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  936. return 1;
  937. } else if (is_promisc_disable(rxf->rxmode_pending,
  938. rxf->rxmode_pending_bitmask)) {
  939. /* move promisc configuration from pending -> active */
  940. promisc_inactive(rxf->rxmode_pending,
  941. rxf->rxmode_pending_bitmask);
  942. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  943. bna->promisc_rid = BFI_INVALID_RID;
  944. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  945. return 1;
  946. }
  947. return 0;
  948. }
  949. static int
  950. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  951. {
  952. struct bna *bna = rxf->rx->bna;
  953. /* Clear pending promisc mode disable */
  954. if (is_promisc_disable(rxf->rxmode_pending,
  955. rxf->rxmode_pending_bitmask)) {
  956. promisc_inactive(rxf->rxmode_pending,
  957. rxf->rxmode_pending_bitmask);
  958. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  959. bna->promisc_rid = BFI_INVALID_RID;
  960. if (cleanup == BNA_HARD_CLEANUP) {
  961. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  962. return 1;
  963. }
  964. }
  965. /* Move promisc mode config from active -> pending */
  966. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  967. promisc_enable(rxf->rxmode_pending,
  968. rxf->rxmode_pending_bitmask);
  969. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  970. if (cleanup == BNA_HARD_CLEANUP) {
  971. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  972. return 1;
  973. }
  974. }
  975. return 0;
  976. }
  977. static int
  978. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  979. {
  980. /* Enable/disable allmulti mode */
  981. if (is_allmulti_enable(rxf->rxmode_pending,
  982. rxf->rxmode_pending_bitmask)) {
  983. /* move allmulti configuration from pending -> active */
  984. allmulti_inactive(rxf->rxmode_pending,
  985. rxf->rxmode_pending_bitmask);
  986. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  987. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  988. return 1;
  989. } else if (is_allmulti_disable(rxf->rxmode_pending,
  990. rxf->rxmode_pending_bitmask)) {
  991. /* move allmulti configuration from pending -> active */
  992. allmulti_inactive(rxf->rxmode_pending,
  993. rxf->rxmode_pending_bitmask);
  994. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  995. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  996. return 1;
  997. }
  998. return 0;
  999. }
  1000. static int
  1001. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  1002. {
  1003. /* Clear pending allmulti mode disable */
  1004. if (is_allmulti_disable(rxf->rxmode_pending,
  1005. rxf->rxmode_pending_bitmask)) {
  1006. allmulti_inactive(rxf->rxmode_pending,
  1007. rxf->rxmode_pending_bitmask);
  1008. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1009. if (cleanup == BNA_HARD_CLEANUP) {
  1010. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1011. return 1;
  1012. }
  1013. }
  1014. /* Move allmulti mode config from active -> pending */
  1015. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1016. allmulti_enable(rxf->rxmode_pending,
  1017. rxf->rxmode_pending_bitmask);
  1018. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1019. if (cleanup == BNA_HARD_CLEANUP) {
  1020. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1021. return 1;
  1022. }
  1023. }
  1024. return 0;
  1025. }
  1026. static int
  1027. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  1028. {
  1029. struct bna *bna = rxf->rx->bna;
  1030. int ret = 0;
  1031. if (is_promisc_enable(rxf->rxmode_pending,
  1032. rxf->rxmode_pending_bitmask) ||
  1033. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  1034. /* Do nothing if pending enable or already enabled */
  1035. } else if (is_promisc_disable(rxf->rxmode_pending,
  1036. rxf->rxmode_pending_bitmask)) {
  1037. /* Turn off pending disable command */
  1038. promisc_inactive(rxf->rxmode_pending,
  1039. rxf->rxmode_pending_bitmask);
  1040. } else {
  1041. /* Schedule enable */
  1042. promisc_enable(rxf->rxmode_pending,
  1043. rxf->rxmode_pending_bitmask);
  1044. bna->promisc_rid = rxf->rx->rid;
  1045. ret = 1;
  1046. }
  1047. return ret;
  1048. }
  1049. static int
  1050. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1051. {
  1052. struct bna *bna = rxf->rx->bna;
  1053. int ret = 0;
  1054. if (is_promisc_disable(rxf->rxmode_pending,
  1055. rxf->rxmode_pending_bitmask) ||
  1056. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1057. /* Do nothing if pending disable or already disabled */
  1058. } else if (is_promisc_enable(rxf->rxmode_pending,
  1059. rxf->rxmode_pending_bitmask)) {
  1060. /* Turn off pending enable command */
  1061. promisc_inactive(rxf->rxmode_pending,
  1062. rxf->rxmode_pending_bitmask);
  1063. bna->promisc_rid = BFI_INVALID_RID;
  1064. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1065. /* Schedule disable */
  1066. promisc_disable(rxf->rxmode_pending,
  1067. rxf->rxmode_pending_bitmask);
  1068. ret = 1;
  1069. }
  1070. return ret;
  1071. }
  1072. static int
  1073. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1074. {
  1075. int ret = 0;
  1076. if (is_allmulti_enable(rxf->rxmode_pending,
  1077. rxf->rxmode_pending_bitmask) ||
  1078. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1079. /* Do nothing if pending enable or already enabled */
  1080. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1081. rxf->rxmode_pending_bitmask)) {
  1082. /* Turn off pending disable command */
  1083. allmulti_inactive(rxf->rxmode_pending,
  1084. rxf->rxmode_pending_bitmask);
  1085. } else {
  1086. /* Schedule enable */
  1087. allmulti_enable(rxf->rxmode_pending,
  1088. rxf->rxmode_pending_bitmask);
  1089. ret = 1;
  1090. }
  1091. return ret;
  1092. }
  1093. static int
  1094. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1095. {
  1096. int ret = 0;
  1097. if (is_allmulti_disable(rxf->rxmode_pending,
  1098. rxf->rxmode_pending_bitmask) ||
  1099. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1100. /* Do nothing if pending disable or already disabled */
  1101. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1102. rxf->rxmode_pending_bitmask)) {
  1103. /* Turn off pending enable command */
  1104. allmulti_inactive(rxf->rxmode_pending,
  1105. rxf->rxmode_pending_bitmask);
  1106. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1107. /* Schedule disable */
  1108. allmulti_disable(rxf->rxmode_pending,
  1109. rxf->rxmode_pending_bitmask);
  1110. ret = 1;
  1111. }
  1112. return ret;
  1113. }
  1114. static int
  1115. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1116. {
  1117. if (rxf->vlan_strip_pending) {
  1118. rxf->vlan_strip_pending = false;
  1119. bna_bfi_vlan_strip_enable(rxf);
  1120. return 1;
  1121. }
  1122. return 0;
  1123. }
  1124. /**
  1125. * RX
  1126. */
  1127. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1128. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1129. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1130. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1131. #define call_rx_stop_cbfn(rx) \
  1132. do { \
  1133. if ((rx)->stop_cbfn) { \
  1134. void (*cbfn)(void *, struct bna_rx *); \
  1135. void *cbarg; \
  1136. cbfn = (rx)->stop_cbfn; \
  1137. cbarg = (rx)->stop_cbarg; \
  1138. (rx)->stop_cbfn = NULL; \
  1139. (rx)->stop_cbarg = NULL; \
  1140. cbfn(cbarg, rx); \
  1141. } \
  1142. } while (0)
  1143. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1144. do { \
  1145. struct bna_dma_addr cur_q_addr = \
  1146. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1147. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1148. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1149. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1150. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1151. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1152. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1153. } while (0)
  1154. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1155. static void bna_rx_enet_stop(struct bna_rx *rx);
  1156. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1157. bfa_fsm_state_decl(bna_rx, stopped,
  1158. struct bna_rx, enum bna_rx_event);
  1159. bfa_fsm_state_decl(bna_rx, start_wait,
  1160. struct bna_rx, enum bna_rx_event);
  1161. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1162. struct bna_rx, enum bna_rx_event);
  1163. bfa_fsm_state_decl(bna_rx, started,
  1164. struct bna_rx, enum bna_rx_event);
  1165. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1166. struct bna_rx, enum bna_rx_event);
  1167. bfa_fsm_state_decl(bna_rx, stop_wait,
  1168. struct bna_rx, enum bna_rx_event);
  1169. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1170. struct bna_rx, enum bna_rx_event);
  1171. bfa_fsm_state_decl(bna_rx, failed,
  1172. struct bna_rx, enum bna_rx_event);
  1173. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1174. struct bna_rx, enum bna_rx_event);
  1175. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1176. {
  1177. call_rx_stop_cbfn(rx);
  1178. }
  1179. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1180. enum bna_rx_event event)
  1181. {
  1182. switch (event) {
  1183. case RX_E_START:
  1184. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1185. break;
  1186. case RX_E_STOP:
  1187. call_rx_stop_cbfn(rx);
  1188. break;
  1189. case RX_E_FAIL:
  1190. /* no-op */
  1191. break;
  1192. default:
  1193. bfa_sm_fault(event);
  1194. break;
  1195. }
  1196. }
  1197. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1198. {
  1199. bna_bfi_rx_enet_start(rx);
  1200. }
  1201. void
  1202. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1203. {
  1204. }
  1205. static void
  1206. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1207. {
  1208. switch (event) {
  1209. case RX_E_FAIL:
  1210. case RX_E_STOPPED:
  1211. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1212. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1213. break;
  1214. case RX_E_STARTED:
  1215. bna_rx_enet_stop(rx);
  1216. break;
  1217. default:
  1218. bfa_sm_fault(event);
  1219. break;
  1220. }
  1221. }
  1222. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1223. enum bna_rx_event event)
  1224. {
  1225. switch (event) {
  1226. case RX_E_STOP:
  1227. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1228. break;
  1229. case RX_E_FAIL:
  1230. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1231. break;
  1232. case RX_E_STARTED:
  1233. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1234. break;
  1235. default:
  1236. bfa_sm_fault(event);
  1237. break;
  1238. }
  1239. }
  1240. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1241. {
  1242. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1243. bna_rxf_start(&rx->rxf);
  1244. }
  1245. void
  1246. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1247. {
  1248. }
  1249. static void
  1250. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1251. {
  1252. switch (event) {
  1253. case RX_E_FAIL:
  1254. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1255. bna_rxf_fail(&rx->rxf);
  1256. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1257. break;
  1258. case RX_E_RXF_STARTED:
  1259. bna_rxf_stop(&rx->rxf);
  1260. break;
  1261. case RX_E_RXF_STOPPED:
  1262. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1263. bna_rx_enet_stop(rx);
  1264. break;
  1265. default:
  1266. bfa_sm_fault(event);
  1267. break;
  1268. }
  1269. }
  1270. void
  1271. bna_rx_sm_started_entry(struct bna_rx *rx)
  1272. {
  1273. struct bna_rxp *rxp;
  1274. struct list_head *qe_rxp;
  1275. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1276. /* Start IB */
  1277. list_for_each(qe_rxp, &rx->rxp_q) {
  1278. rxp = (struct bna_rxp *)qe_rxp;
  1279. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1280. }
  1281. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1282. }
  1283. static void
  1284. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1285. {
  1286. switch (event) {
  1287. case RX_E_STOP:
  1288. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1289. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1290. bna_rxf_stop(&rx->rxf);
  1291. break;
  1292. case RX_E_FAIL:
  1293. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1294. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1295. bna_rxf_fail(&rx->rxf);
  1296. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1297. break;
  1298. default:
  1299. bfa_sm_fault(event);
  1300. break;
  1301. }
  1302. }
  1303. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1304. enum bna_rx_event event)
  1305. {
  1306. switch (event) {
  1307. case RX_E_STOP:
  1308. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1309. break;
  1310. case RX_E_FAIL:
  1311. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1312. bna_rxf_fail(&rx->rxf);
  1313. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1314. break;
  1315. case RX_E_RXF_STARTED:
  1316. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1317. break;
  1318. default:
  1319. bfa_sm_fault(event);
  1320. break;
  1321. }
  1322. }
  1323. void
  1324. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1325. {
  1326. }
  1327. void
  1328. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1329. {
  1330. switch (event) {
  1331. case RX_E_FAIL:
  1332. case RX_E_RXF_STOPPED:
  1333. /* No-op */
  1334. break;
  1335. case RX_E_CLEANUP_DONE:
  1336. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1337. break;
  1338. default:
  1339. bfa_sm_fault(event);
  1340. break;
  1341. }
  1342. }
  1343. static void
  1344. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1345. {
  1346. }
  1347. static void
  1348. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1349. {
  1350. switch (event) {
  1351. case RX_E_START:
  1352. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1353. break;
  1354. case RX_E_STOP:
  1355. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1356. break;
  1357. case RX_E_FAIL:
  1358. case RX_E_RXF_STARTED:
  1359. case RX_E_RXF_STOPPED:
  1360. /* No-op */
  1361. break;
  1362. case RX_E_CLEANUP_DONE:
  1363. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1364. break;
  1365. default:
  1366. bfa_sm_fault(event);
  1367. break;
  1368. } }
  1369. static void
  1370. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1371. {
  1372. }
  1373. static void
  1374. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1375. {
  1376. switch (event) {
  1377. case RX_E_STOP:
  1378. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1379. break;
  1380. case RX_E_FAIL:
  1381. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1382. break;
  1383. case RX_E_CLEANUP_DONE:
  1384. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1385. break;
  1386. default:
  1387. bfa_sm_fault(event);
  1388. break;
  1389. }
  1390. }
  1391. static void
  1392. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1393. {
  1394. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1395. struct bna_rxp *rxp = NULL;
  1396. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1397. struct list_head *rxp_qe;
  1398. int i;
  1399. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1400. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1401. cfg_req->mh.num_entries = htons(
  1402. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1403. cfg_req->num_queue_sets = rx->num_paths;
  1404. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1405. i < rx->num_paths;
  1406. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1407. rxp = (struct bna_rxp *)rxp_qe;
  1408. GET_RXQS(rxp, q0, q1);
  1409. switch (rxp->type) {
  1410. case BNA_RXP_SLR:
  1411. case BNA_RXP_HDS:
  1412. /* Small RxQ */
  1413. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1414. &q1->qpt);
  1415. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1416. htons((u16)q1->buffer_size);
  1417. /* Fall through */
  1418. case BNA_RXP_SINGLE:
  1419. /* Large/Single RxQ */
  1420. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1421. &q0->qpt);
  1422. q0->buffer_size =
  1423. bna_enet_mtu_get(&rx->bna->enet);
  1424. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1425. htons((u16)q0->buffer_size);
  1426. break;
  1427. default:
  1428. BUG_ON(1);
  1429. }
  1430. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1431. &rxp->cq.qpt);
  1432. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1433. rxp->cq.ib.ib_seg_host_addr.lsb;
  1434. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1435. rxp->cq.ib.ib_seg_host_addr.msb;
  1436. cfg_req->q_cfg[i].ib.intr.msix_index =
  1437. htons((u16)rxp->cq.ib.intr_vector);
  1438. }
  1439. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1440. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1441. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1442. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1443. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1444. ? BNA_STATUS_T_ENABLED :
  1445. BNA_STATUS_T_DISABLED;
  1446. cfg_req->ib_cfg.coalescing_timeout =
  1447. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1448. cfg_req->ib_cfg.inter_pkt_timeout =
  1449. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1450. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1451. switch (rxp->type) {
  1452. case BNA_RXP_SLR:
  1453. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1454. break;
  1455. case BNA_RXP_HDS:
  1456. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1457. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1458. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1459. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1460. break;
  1461. case BNA_RXP_SINGLE:
  1462. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1463. break;
  1464. default:
  1465. BUG_ON(1);
  1466. }
  1467. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1468. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1469. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1470. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1471. }
  1472. static void
  1473. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1474. {
  1475. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1476. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1477. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1478. req->mh.num_entries = htons(
  1479. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1480. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1481. &req->mh);
  1482. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1483. }
  1484. static void
  1485. bna_rx_enet_stop(struct bna_rx *rx)
  1486. {
  1487. struct bna_rxp *rxp;
  1488. struct list_head *qe_rxp;
  1489. /* Stop IB */
  1490. list_for_each(qe_rxp, &rx->rxp_q) {
  1491. rxp = (struct bna_rxp *)qe_rxp;
  1492. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1493. }
  1494. bna_bfi_rx_enet_stop(rx);
  1495. }
  1496. static int
  1497. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1498. {
  1499. if ((rx_mod->rx_free_count == 0) ||
  1500. (rx_mod->rxp_free_count == 0) ||
  1501. (rx_mod->rxq_free_count == 0))
  1502. return 0;
  1503. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1504. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1505. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1506. return 0;
  1507. } else {
  1508. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1509. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1510. return 0;
  1511. }
  1512. return 1;
  1513. }
  1514. static struct bna_rxq *
  1515. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1516. {
  1517. struct bna_rxq *rxq = NULL;
  1518. struct list_head *qe = NULL;
  1519. bfa_q_deq(&rx_mod->rxq_free_q, &qe);
  1520. rx_mod->rxq_free_count--;
  1521. rxq = (struct bna_rxq *)qe;
  1522. bfa_q_qe_init(&rxq->qe);
  1523. return rxq;
  1524. }
  1525. static void
  1526. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1527. {
  1528. bfa_q_qe_init(&rxq->qe);
  1529. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1530. rx_mod->rxq_free_count++;
  1531. }
  1532. static struct bna_rxp *
  1533. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1534. {
  1535. struct list_head *qe = NULL;
  1536. struct bna_rxp *rxp = NULL;
  1537. bfa_q_deq(&rx_mod->rxp_free_q, &qe);
  1538. rx_mod->rxp_free_count--;
  1539. rxp = (struct bna_rxp *)qe;
  1540. bfa_q_qe_init(&rxp->qe);
  1541. return rxp;
  1542. }
  1543. static void
  1544. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1545. {
  1546. bfa_q_qe_init(&rxp->qe);
  1547. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1548. rx_mod->rxp_free_count++;
  1549. }
  1550. static struct bna_rx *
  1551. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1552. {
  1553. struct list_head *qe = NULL;
  1554. struct bna_rx *rx = NULL;
  1555. if (type == BNA_RX_T_REGULAR) {
  1556. bfa_q_deq(&rx_mod->rx_free_q, &qe);
  1557. } else
  1558. bfa_q_deq_tail(&rx_mod->rx_free_q, &qe);
  1559. rx_mod->rx_free_count--;
  1560. rx = (struct bna_rx *)qe;
  1561. bfa_q_qe_init(&rx->qe);
  1562. list_add_tail(&rx->qe, &rx_mod->rx_active_q);
  1563. rx->type = type;
  1564. return rx;
  1565. }
  1566. static void
  1567. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1568. {
  1569. struct list_head *prev_qe = NULL;
  1570. struct list_head *qe;
  1571. bfa_q_qe_init(&rx->qe);
  1572. list_for_each(qe, &rx_mod->rx_free_q) {
  1573. if (((struct bna_rx *)qe)->rid < rx->rid)
  1574. prev_qe = qe;
  1575. else
  1576. break;
  1577. }
  1578. if (prev_qe == NULL) {
  1579. /* This is the first entry */
  1580. bfa_q_enq_head(&rx_mod->rx_free_q, &rx->qe);
  1581. } else if (bfa_q_next(prev_qe) == &rx_mod->rx_free_q) {
  1582. /* This is the last entry */
  1583. list_add_tail(&rx->qe, &rx_mod->rx_free_q);
  1584. } else {
  1585. /* Somewhere in the middle */
  1586. bfa_q_next(&rx->qe) = bfa_q_next(prev_qe);
  1587. bfa_q_prev(&rx->qe) = prev_qe;
  1588. bfa_q_next(prev_qe) = &rx->qe;
  1589. bfa_q_prev(bfa_q_next(&rx->qe)) = &rx->qe;
  1590. }
  1591. rx_mod->rx_free_count++;
  1592. }
  1593. static void
  1594. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1595. struct bna_rxq *q1)
  1596. {
  1597. switch (rxp->type) {
  1598. case BNA_RXP_SINGLE:
  1599. rxp->rxq.single.only = q0;
  1600. rxp->rxq.single.reserved = NULL;
  1601. break;
  1602. case BNA_RXP_SLR:
  1603. rxp->rxq.slr.large = q0;
  1604. rxp->rxq.slr.small = q1;
  1605. break;
  1606. case BNA_RXP_HDS:
  1607. rxp->rxq.hds.data = q0;
  1608. rxp->rxq.hds.hdr = q1;
  1609. break;
  1610. default:
  1611. break;
  1612. }
  1613. }
  1614. static void
  1615. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1616. struct bna_rxp *rxp,
  1617. u32 page_count,
  1618. u32 page_size,
  1619. struct bna_mem_descr *qpt_mem,
  1620. struct bna_mem_descr *swqpt_mem,
  1621. struct bna_mem_descr *page_mem)
  1622. {
  1623. int i;
  1624. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1625. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1626. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1627. rxq->qpt.page_count = page_count;
  1628. rxq->qpt.page_size = page_size;
  1629. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1630. for (i = 0; i < rxq->qpt.page_count; i++) {
  1631. rxq->rcb->sw_qpt[i] = page_mem[i].kva;
  1632. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1633. page_mem[i].dma.lsb;
  1634. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1635. page_mem[i].dma.msb;
  1636. }
  1637. }
  1638. static void
  1639. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1640. u32 page_count,
  1641. u32 page_size,
  1642. struct bna_mem_descr *qpt_mem,
  1643. struct bna_mem_descr *swqpt_mem,
  1644. struct bna_mem_descr *page_mem)
  1645. {
  1646. int i;
  1647. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1648. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1649. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1650. rxp->cq.qpt.page_count = page_count;
  1651. rxp->cq.qpt.page_size = page_size;
  1652. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1653. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1654. rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva;
  1655. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1656. page_mem[i].dma.lsb;
  1657. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1658. page_mem[i].dma.msb;
  1659. }
  1660. }
  1661. static void
  1662. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1663. {
  1664. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1665. bfa_wc_down(&rx_mod->rx_stop_wc);
  1666. }
  1667. static void
  1668. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1669. {
  1670. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1671. if (rx_mod->stop_cbfn)
  1672. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1673. rx_mod->stop_cbfn = NULL;
  1674. }
  1675. static void
  1676. bna_rx_start(struct bna_rx *rx)
  1677. {
  1678. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1679. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1680. bfa_fsm_send_event(rx, RX_E_START);
  1681. }
  1682. static void
  1683. bna_rx_stop(struct bna_rx *rx)
  1684. {
  1685. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1686. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1687. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1688. else {
  1689. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1690. rx->stop_cbarg = &rx->bna->rx_mod;
  1691. bfa_fsm_send_event(rx, RX_E_STOP);
  1692. }
  1693. }
  1694. static void
  1695. bna_rx_fail(struct bna_rx *rx)
  1696. {
  1697. /* Indicate Enet is not enabled, and failed */
  1698. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1699. bfa_fsm_send_event(rx, RX_E_FAIL);
  1700. }
  1701. void
  1702. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1703. {
  1704. struct bna_rx *rx;
  1705. struct list_head *qe;
  1706. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1707. if (type == BNA_RX_T_LOOPBACK)
  1708. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1709. list_for_each(qe, &rx_mod->rx_active_q) {
  1710. rx = (struct bna_rx *)qe;
  1711. if (rx->type == type)
  1712. bna_rx_start(rx);
  1713. }
  1714. }
  1715. void
  1716. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1717. {
  1718. struct bna_rx *rx;
  1719. struct list_head *qe;
  1720. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1721. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1722. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1723. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1724. list_for_each(qe, &rx_mod->rx_active_q) {
  1725. rx = (struct bna_rx *)qe;
  1726. if (rx->type == type) {
  1727. bfa_wc_up(&rx_mod->rx_stop_wc);
  1728. bna_rx_stop(rx);
  1729. }
  1730. }
  1731. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1732. }
  1733. void
  1734. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1735. {
  1736. struct bna_rx *rx;
  1737. struct list_head *qe;
  1738. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1739. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1740. list_for_each(qe, &rx_mod->rx_active_q) {
  1741. rx = (struct bna_rx *)qe;
  1742. bna_rx_fail(rx);
  1743. }
  1744. }
  1745. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1746. struct bna_res_info *res_info)
  1747. {
  1748. int index;
  1749. struct bna_rx *rx_ptr;
  1750. struct bna_rxp *rxp_ptr;
  1751. struct bna_rxq *rxq_ptr;
  1752. rx_mod->bna = bna;
  1753. rx_mod->flags = 0;
  1754. rx_mod->rx = (struct bna_rx *)
  1755. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1756. rx_mod->rxp = (struct bna_rxp *)
  1757. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1758. rx_mod->rxq = (struct bna_rxq *)
  1759. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1760. /* Initialize the queues */
  1761. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1762. rx_mod->rx_free_count = 0;
  1763. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1764. rx_mod->rxq_free_count = 0;
  1765. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1766. rx_mod->rxp_free_count = 0;
  1767. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1768. /* Build RX queues */
  1769. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1770. rx_ptr = &rx_mod->rx[index];
  1771. bfa_q_qe_init(&rx_ptr->qe);
  1772. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1773. rx_ptr->bna = NULL;
  1774. rx_ptr->rid = index;
  1775. rx_ptr->stop_cbfn = NULL;
  1776. rx_ptr->stop_cbarg = NULL;
  1777. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1778. rx_mod->rx_free_count++;
  1779. }
  1780. /* build RX-path queue */
  1781. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1782. rxp_ptr = &rx_mod->rxp[index];
  1783. bfa_q_qe_init(&rxp_ptr->qe);
  1784. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1785. rx_mod->rxp_free_count++;
  1786. }
  1787. /* build RXQ queue */
  1788. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1789. rxq_ptr = &rx_mod->rxq[index];
  1790. bfa_q_qe_init(&rxq_ptr->qe);
  1791. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1792. rx_mod->rxq_free_count++;
  1793. }
  1794. }
  1795. void
  1796. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1797. {
  1798. struct list_head *qe;
  1799. int i;
  1800. i = 0;
  1801. list_for_each(qe, &rx_mod->rx_free_q)
  1802. i++;
  1803. i = 0;
  1804. list_for_each(qe, &rx_mod->rxp_free_q)
  1805. i++;
  1806. i = 0;
  1807. list_for_each(qe, &rx_mod->rxq_free_q)
  1808. i++;
  1809. rx_mod->bna = NULL;
  1810. }
  1811. void
  1812. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1813. {
  1814. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1815. struct bna_rxp *rxp = NULL;
  1816. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1817. struct list_head *rxp_qe;
  1818. int i;
  1819. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1820. sizeof(struct bfi_enet_rx_cfg_rsp));
  1821. rx->hw_id = cfg_rsp->hw_id;
  1822. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1823. i < rx->num_paths;
  1824. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1825. rxp = (struct bna_rxp *)rxp_qe;
  1826. GET_RXQS(rxp, q0, q1);
  1827. /* Setup doorbells */
  1828. rxp->cq.ccb->i_dbell->doorbell_addr =
  1829. rx->bna->pcidev.pci_bar_kva
  1830. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1831. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1832. q0->rcb->q_dbell =
  1833. rx->bna->pcidev.pci_bar_kva
  1834. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  1835. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  1836. if (q1) {
  1837. q1->rcb->q_dbell =
  1838. rx->bna->pcidev.pci_bar_kva
  1839. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  1840. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  1841. }
  1842. /* Initialize producer/consumer indexes */
  1843. (*rxp->cq.ccb->hw_producer_index) = 0;
  1844. rxp->cq.ccb->producer_index = 0;
  1845. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  1846. if (q1)
  1847. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  1848. }
  1849. bfa_fsm_send_event(rx, RX_E_STARTED);
  1850. }
  1851. void
  1852. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1853. {
  1854. bfa_fsm_send_event(rx, RX_E_STOPPED);
  1855. }
  1856. void
  1857. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  1858. {
  1859. u32 cq_size, hq_size, dq_size;
  1860. u32 cpage_count, hpage_count, dpage_count;
  1861. struct bna_mem_info *mem_info;
  1862. u32 cq_depth;
  1863. u32 hq_depth;
  1864. u32 dq_depth;
  1865. dq_depth = q_cfg->q_depth;
  1866. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
  1867. cq_depth = dq_depth + hq_depth;
  1868. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  1869. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  1870. cq_size = ALIGN(cq_size, PAGE_SIZE);
  1871. cpage_count = SIZE_TO_PAGES(cq_size);
  1872. BNA_TO_POWER_OF_2_HIGH(dq_depth);
  1873. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  1874. dq_size = ALIGN(dq_size, PAGE_SIZE);
  1875. dpage_count = SIZE_TO_PAGES(dq_size);
  1876. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  1877. BNA_TO_POWER_OF_2_HIGH(hq_depth);
  1878. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  1879. hq_size = ALIGN(hq_size, PAGE_SIZE);
  1880. hpage_count = SIZE_TO_PAGES(hq_size);
  1881. } else
  1882. hpage_count = 0;
  1883. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  1884. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  1885. mem_info->mem_type = BNA_MEM_T_KVA;
  1886. mem_info->len = sizeof(struct bna_ccb);
  1887. mem_info->num = q_cfg->num_paths;
  1888. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  1889. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  1890. mem_info->mem_type = BNA_MEM_T_KVA;
  1891. mem_info->len = sizeof(struct bna_rcb);
  1892. mem_info->num = BNA_GET_RXQS(q_cfg);
  1893. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  1894. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  1895. mem_info->mem_type = BNA_MEM_T_DMA;
  1896. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  1897. mem_info->num = q_cfg->num_paths;
  1898. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  1899. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  1900. mem_info->mem_type = BNA_MEM_T_KVA;
  1901. mem_info->len = cpage_count * sizeof(void *);
  1902. mem_info->num = q_cfg->num_paths;
  1903. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  1904. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  1905. mem_info->mem_type = BNA_MEM_T_DMA;
  1906. mem_info->len = PAGE_SIZE;
  1907. mem_info->num = cpage_count * q_cfg->num_paths;
  1908. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  1909. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  1910. mem_info->mem_type = BNA_MEM_T_DMA;
  1911. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  1912. mem_info->num = q_cfg->num_paths;
  1913. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  1914. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  1915. mem_info->mem_type = BNA_MEM_T_KVA;
  1916. mem_info->len = dpage_count * sizeof(void *);
  1917. mem_info->num = q_cfg->num_paths;
  1918. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  1919. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  1920. mem_info->mem_type = BNA_MEM_T_DMA;
  1921. mem_info->len = PAGE_SIZE;
  1922. mem_info->num = dpage_count * q_cfg->num_paths;
  1923. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  1924. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  1925. mem_info->mem_type = BNA_MEM_T_DMA;
  1926. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  1927. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1928. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  1929. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  1930. mem_info->mem_type = BNA_MEM_T_KVA;
  1931. mem_info->len = hpage_count * sizeof(void *);
  1932. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1933. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  1934. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  1935. mem_info->mem_type = BNA_MEM_T_DMA;
  1936. mem_info->len = (hpage_count ? PAGE_SIZE : 0);
  1937. mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0);
  1938. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  1939. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  1940. mem_info->mem_type = BNA_MEM_T_DMA;
  1941. mem_info->len = BFI_IBIDX_SIZE;
  1942. mem_info->num = q_cfg->num_paths;
  1943. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  1944. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  1945. mem_info->mem_type = BNA_MEM_T_KVA;
  1946. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  1947. mem_info->num = 1;
  1948. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  1949. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  1950. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  1951. }
  1952. struct bna_rx *
  1953. bna_rx_create(struct bna *bna, struct bnad *bnad,
  1954. struct bna_rx_config *rx_cfg,
  1955. struct bna_rx_event_cbfn *rx_cbfn,
  1956. struct bna_res_info *res_info,
  1957. void *priv)
  1958. {
  1959. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  1960. struct bna_rx *rx;
  1961. struct bna_rxp *rxp;
  1962. struct bna_rxq *q0;
  1963. struct bna_rxq *q1;
  1964. struct bna_intr_info *intr_info;
  1965. u32 page_count;
  1966. struct bna_mem_descr *ccb_mem;
  1967. struct bna_mem_descr *rcb_mem;
  1968. struct bna_mem_descr *unmapq_mem;
  1969. struct bna_mem_descr *cqpt_mem;
  1970. struct bna_mem_descr *cswqpt_mem;
  1971. struct bna_mem_descr *cpage_mem;
  1972. struct bna_mem_descr *hqpt_mem;
  1973. struct bna_mem_descr *dqpt_mem;
  1974. struct bna_mem_descr *hsqpt_mem;
  1975. struct bna_mem_descr *dsqpt_mem;
  1976. struct bna_mem_descr *hpage_mem;
  1977. struct bna_mem_descr *dpage_mem;
  1978. int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0;
  1979. int dpage_count, hpage_count, rcb_idx;
  1980. if (!bna_rx_res_check(rx_mod, rx_cfg))
  1981. return NULL;
  1982. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  1983. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  1984. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  1985. unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
  1986. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  1987. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  1988. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  1989. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  1990. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  1991. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  1992. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  1993. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  1994. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  1995. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num /
  1996. rx_cfg->num_paths;
  1997. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num /
  1998. rx_cfg->num_paths;
  1999. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num /
  2000. rx_cfg->num_paths;
  2001. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  2002. rx->bna = bna;
  2003. rx->rx_flags = 0;
  2004. INIT_LIST_HEAD(&rx->rxp_q);
  2005. rx->stop_cbfn = NULL;
  2006. rx->stop_cbarg = NULL;
  2007. rx->priv = priv;
  2008. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  2009. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  2010. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  2011. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  2012. /* Following callbacks are mandatory */
  2013. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  2014. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  2015. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  2016. switch (rx->type) {
  2017. case BNA_RX_T_REGULAR:
  2018. if (!(rx->bna->rx_mod.flags &
  2019. BNA_RX_MOD_F_ENET_LOOPBACK))
  2020. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2021. break;
  2022. case BNA_RX_T_LOOPBACK:
  2023. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  2024. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2025. break;
  2026. }
  2027. }
  2028. rx->num_paths = rx_cfg->num_paths;
  2029. for (i = 0, rcb_idx = 0; i < rx->num_paths; i++) {
  2030. rxp = bna_rxp_get(rx_mod);
  2031. list_add_tail(&rxp->qe, &rx->rxp_q);
  2032. rxp->type = rx_cfg->rxp_type;
  2033. rxp->rx = rx;
  2034. rxp->cq.rx = rx;
  2035. q0 = bna_rxq_get(rx_mod);
  2036. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  2037. q1 = NULL;
  2038. else
  2039. q1 = bna_rxq_get(rx_mod);
  2040. if (1 == intr_info->num)
  2041. rxp->vector = intr_info->idl[0].vector;
  2042. else
  2043. rxp->vector = intr_info->idl[i].vector;
  2044. /* Setup IB */
  2045. rxp->cq.ib.ib_seg_host_addr.lsb =
  2046. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2047. rxp->cq.ib.ib_seg_host_addr.msb =
  2048. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2049. rxp->cq.ib.ib_seg_host_addr_kva =
  2050. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2051. rxp->cq.ib.intr_type = intr_info->intr_type;
  2052. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2053. rxp->cq.ib.intr_vector = rxp->vector;
  2054. else
  2055. rxp->cq.ib.intr_vector = (1 << rxp->vector);
  2056. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2057. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2058. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2059. bna_rxp_add_rxqs(rxp, q0, q1);
  2060. /* Setup large Q */
  2061. q0->rx = rx;
  2062. q0->rxp = rxp;
  2063. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2064. q0->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2065. rcb_idx++;
  2066. q0->rcb->q_depth = rx_cfg->q_depth;
  2067. q0->rcb->rxq = q0;
  2068. q0->rcb->bnad = bna->bnad;
  2069. q0->rcb->id = 0;
  2070. q0->rx_packets = q0->rx_bytes = 0;
  2071. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2072. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2073. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]);
  2074. q0->rcb->page_idx = dpage_idx;
  2075. q0->rcb->page_count = dpage_count;
  2076. dpage_idx += dpage_count;
  2077. if (rx->rcb_setup_cbfn)
  2078. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2079. /* Setup small Q */
  2080. if (q1) {
  2081. q1->rx = rx;
  2082. q1->rxp = rxp;
  2083. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2084. q1->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2085. rcb_idx++;
  2086. q1->rcb->q_depth = rx_cfg->q_depth;
  2087. q1->rcb->rxq = q1;
  2088. q1->rcb->bnad = bna->bnad;
  2089. q1->rcb->id = 1;
  2090. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2091. rx_cfg->hds_config.forced_offset
  2092. : rx_cfg->small_buff_size;
  2093. q1->rx_packets = q1->rx_bytes = 0;
  2094. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2095. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2096. &hqpt_mem[i], &hsqpt_mem[i],
  2097. &hpage_mem[hpage_idx]);
  2098. q1->rcb->page_idx = hpage_idx;
  2099. q1->rcb->page_count = hpage_count;
  2100. hpage_idx += hpage_count;
  2101. if (rx->rcb_setup_cbfn)
  2102. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2103. }
  2104. /* Setup CQ */
  2105. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2106. rxp->cq.ccb->q_depth = rx_cfg->q_depth +
  2107. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2108. 0 : rx_cfg->q_depth);
  2109. rxp->cq.ccb->cq = &rxp->cq;
  2110. rxp->cq.ccb->rcb[0] = q0->rcb;
  2111. q0->rcb->ccb = rxp->cq.ccb;
  2112. if (q1) {
  2113. rxp->cq.ccb->rcb[1] = q1->rcb;
  2114. q1->rcb->ccb = rxp->cq.ccb;
  2115. }
  2116. rxp->cq.ccb->hw_producer_index =
  2117. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2118. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2119. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2120. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2121. rxp->cq.ccb->rx_coalescing_timeo =
  2122. rxp->cq.ib.coalescing_timeo;
  2123. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2124. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2125. rxp->cq.ccb->bnad = bna->bnad;
  2126. rxp->cq.ccb->id = i;
  2127. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2128. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]);
  2129. rxp->cq.ccb->page_idx = cpage_idx;
  2130. rxp->cq.ccb->page_count = page_count;
  2131. cpage_idx += page_count;
  2132. if (rx->ccb_setup_cbfn)
  2133. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2134. }
  2135. rx->hds_cfg = rx_cfg->hds_config;
  2136. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2137. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2138. rx_mod->rid_mask |= (1 << rx->rid);
  2139. return rx;
  2140. }
  2141. void
  2142. bna_rx_destroy(struct bna_rx *rx)
  2143. {
  2144. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2145. struct bna_rxq *q0 = NULL;
  2146. struct bna_rxq *q1 = NULL;
  2147. struct bna_rxp *rxp;
  2148. struct list_head *qe;
  2149. bna_rxf_uninit(&rx->rxf);
  2150. while (!list_empty(&rx->rxp_q)) {
  2151. bfa_q_deq(&rx->rxp_q, &rxp);
  2152. GET_RXQS(rxp, q0, q1);
  2153. if (rx->rcb_destroy_cbfn)
  2154. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2155. q0->rcb = NULL;
  2156. q0->rxp = NULL;
  2157. q0->rx = NULL;
  2158. bna_rxq_put(rx_mod, q0);
  2159. if (q1) {
  2160. if (rx->rcb_destroy_cbfn)
  2161. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2162. q1->rcb = NULL;
  2163. q1->rxp = NULL;
  2164. q1->rx = NULL;
  2165. bna_rxq_put(rx_mod, q1);
  2166. }
  2167. rxp->rxq.slr.large = NULL;
  2168. rxp->rxq.slr.small = NULL;
  2169. if (rx->ccb_destroy_cbfn)
  2170. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2171. rxp->cq.ccb = NULL;
  2172. rxp->rx = NULL;
  2173. bna_rxp_put(rx_mod, rxp);
  2174. }
  2175. list_for_each(qe, &rx_mod->rx_active_q) {
  2176. if (qe == &rx->qe) {
  2177. list_del(&rx->qe);
  2178. bfa_q_qe_init(&rx->qe);
  2179. break;
  2180. }
  2181. }
  2182. rx_mod->rid_mask &= ~(1 << rx->rid);
  2183. rx->bna = NULL;
  2184. rx->priv = NULL;
  2185. bna_rx_put(rx_mod, rx);
  2186. }
  2187. void
  2188. bna_rx_enable(struct bna_rx *rx)
  2189. {
  2190. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2191. return;
  2192. rx->rx_flags |= BNA_RX_F_ENABLED;
  2193. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2194. bfa_fsm_send_event(rx, RX_E_START);
  2195. }
  2196. void
  2197. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2198. void (*cbfn)(void *, struct bna_rx *))
  2199. {
  2200. if (type == BNA_SOFT_CLEANUP) {
  2201. /* h/w should not be accessed. Treat we're stopped */
  2202. (*cbfn)(rx->bna->bnad, rx);
  2203. } else {
  2204. rx->stop_cbfn = cbfn;
  2205. rx->stop_cbarg = rx->bna->bnad;
  2206. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2207. bfa_fsm_send_event(rx, RX_E_STOP);
  2208. }
  2209. }
  2210. void
  2211. bna_rx_cleanup_complete(struct bna_rx *rx)
  2212. {
  2213. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2214. }
  2215. enum bna_cb_status
  2216. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2217. enum bna_rxmode bitmask,
  2218. void (*cbfn)(struct bnad *, struct bna_rx *))
  2219. {
  2220. struct bna_rxf *rxf = &rx->rxf;
  2221. int need_hw_config = 0;
  2222. /* Error checks */
  2223. if (is_promisc_enable(new_mode, bitmask)) {
  2224. /* If promisc mode is already enabled elsewhere in the system */
  2225. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2226. (rx->bna->promisc_rid != rxf->rx->rid))
  2227. goto err_return;
  2228. /* If default mode is already enabled in the system */
  2229. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2230. goto err_return;
  2231. /* Trying to enable promiscuous and default mode together */
  2232. if (is_default_enable(new_mode, bitmask))
  2233. goto err_return;
  2234. }
  2235. if (is_default_enable(new_mode, bitmask)) {
  2236. /* If default mode is already enabled elsewhere in the system */
  2237. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2238. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2239. goto err_return;
  2240. }
  2241. /* If promiscuous mode is already enabled in the system */
  2242. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2243. goto err_return;
  2244. }
  2245. /* Process the commands */
  2246. if (is_promisc_enable(new_mode, bitmask)) {
  2247. if (bna_rxf_promisc_enable(rxf))
  2248. need_hw_config = 1;
  2249. } else if (is_promisc_disable(new_mode, bitmask)) {
  2250. if (bna_rxf_promisc_disable(rxf))
  2251. need_hw_config = 1;
  2252. }
  2253. if (is_allmulti_enable(new_mode, bitmask)) {
  2254. if (bna_rxf_allmulti_enable(rxf))
  2255. need_hw_config = 1;
  2256. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2257. if (bna_rxf_allmulti_disable(rxf))
  2258. need_hw_config = 1;
  2259. }
  2260. /* Trigger h/w if needed */
  2261. if (need_hw_config) {
  2262. rxf->cam_fltr_cbfn = cbfn;
  2263. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2264. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2265. } else if (cbfn)
  2266. (*cbfn)(rx->bna->bnad, rx);
  2267. return BNA_CB_SUCCESS;
  2268. err_return:
  2269. return BNA_CB_FAIL;
  2270. }
  2271. void
  2272. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2273. {
  2274. struct bna_rxf *rxf = &rx->rxf;
  2275. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2276. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2277. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2278. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2279. }
  2280. }
  2281. void
  2282. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2283. {
  2284. struct bna_rxp *rxp;
  2285. struct list_head *qe;
  2286. list_for_each(qe, &rx->rxp_q) {
  2287. rxp = (struct bna_rxp *)qe;
  2288. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2289. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2290. }
  2291. }
  2292. void
  2293. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2294. {
  2295. int i, j;
  2296. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2297. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2298. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2299. }
  2300. void
  2301. bna_rx_dim_update(struct bna_ccb *ccb)
  2302. {
  2303. struct bna *bna = ccb->cq->rx->bna;
  2304. u32 load, bias;
  2305. u32 pkt_rt, small_rt, large_rt;
  2306. u8 coalescing_timeo;
  2307. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2308. (ccb->pkt_rate.large_pkt_cnt == 0))
  2309. return;
  2310. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2311. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2312. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2313. pkt_rt = small_rt + large_rt;
  2314. if (pkt_rt < BNA_PKT_RATE_10K)
  2315. load = BNA_LOAD_T_LOW_4;
  2316. else if (pkt_rt < BNA_PKT_RATE_20K)
  2317. load = BNA_LOAD_T_LOW_3;
  2318. else if (pkt_rt < BNA_PKT_RATE_30K)
  2319. load = BNA_LOAD_T_LOW_2;
  2320. else if (pkt_rt < BNA_PKT_RATE_40K)
  2321. load = BNA_LOAD_T_LOW_1;
  2322. else if (pkt_rt < BNA_PKT_RATE_50K)
  2323. load = BNA_LOAD_T_HIGH_1;
  2324. else if (pkt_rt < BNA_PKT_RATE_60K)
  2325. load = BNA_LOAD_T_HIGH_2;
  2326. else if (pkt_rt < BNA_PKT_RATE_80K)
  2327. load = BNA_LOAD_T_HIGH_3;
  2328. else
  2329. load = BNA_LOAD_T_HIGH_4;
  2330. if (small_rt > (large_rt << 1))
  2331. bias = 0;
  2332. else
  2333. bias = 1;
  2334. ccb->pkt_rate.small_pkt_cnt = 0;
  2335. ccb->pkt_rate.large_pkt_cnt = 0;
  2336. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2337. ccb->rx_coalescing_timeo = coalescing_timeo;
  2338. /* Set it to IB */
  2339. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2340. }
  2341. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2342. {12, 12},
  2343. {6, 10},
  2344. {5, 10},
  2345. {4, 8},
  2346. {3, 6},
  2347. {3, 6},
  2348. {2, 4},
  2349. {1, 2},
  2350. };
  2351. /**
  2352. * TX
  2353. */
  2354. #define call_tx_stop_cbfn(tx) \
  2355. do { \
  2356. if ((tx)->stop_cbfn) { \
  2357. void (*cbfn)(void *, struct bna_tx *); \
  2358. void *cbarg; \
  2359. cbfn = (tx)->stop_cbfn; \
  2360. cbarg = (tx)->stop_cbarg; \
  2361. (tx)->stop_cbfn = NULL; \
  2362. (tx)->stop_cbarg = NULL; \
  2363. cbfn(cbarg, (tx)); \
  2364. } \
  2365. } while (0)
  2366. #define call_tx_prio_change_cbfn(tx) \
  2367. do { \
  2368. if ((tx)->prio_change_cbfn) { \
  2369. void (*cbfn)(struct bnad *, struct bna_tx *); \
  2370. cbfn = (tx)->prio_change_cbfn; \
  2371. (tx)->prio_change_cbfn = NULL; \
  2372. cbfn((tx)->bna->bnad, (tx)); \
  2373. } \
  2374. } while (0)
  2375. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2376. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2377. static void bna_tx_enet_stop(struct bna_tx *tx);
  2378. enum bna_tx_event {
  2379. TX_E_START = 1,
  2380. TX_E_STOP = 2,
  2381. TX_E_FAIL = 3,
  2382. TX_E_STARTED = 4,
  2383. TX_E_STOPPED = 5,
  2384. TX_E_PRIO_CHANGE = 6,
  2385. TX_E_CLEANUP_DONE = 7,
  2386. TX_E_BW_UPDATE = 8,
  2387. };
  2388. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2389. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2390. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2391. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2392. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2393. enum bna_tx_event);
  2394. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2395. enum bna_tx_event);
  2396. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2397. enum bna_tx_event);
  2398. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2399. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2400. enum bna_tx_event);
  2401. static void
  2402. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2403. {
  2404. call_tx_stop_cbfn(tx);
  2405. }
  2406. static void
  2407. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2408. {
  2409. switch (event) {
  2410. case TX_E_START:
  2411. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2412. break;
  2413. case TX_E_STOP:
  2414. call_tx_stop_cbfn(tx);
  2415. break;
  2416. case TX_E_FAIL:
  2417. /* No-op */
  2418. break;
  2419. case TX_E_PRIO_CHANGE:
  2420. call_tx_prio_change_cbfn(tx);
  2421. break;
  2422. case TX_E_BW_UPDATE:
  2423. /* No-op */
  2424. break;
  2425. default:
  2426. bfa_sm_fault(event);
  2427. }
  2428. }
  2429. static void
  2430. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2431. {
  2432. bna_bfi_tx_enet_start(tx);
  2433. }
  2434. static void
  2435. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2436. {
  2437. switch (event) {
  2438. case TX_E_STOP:
  2439. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2440. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2441. break;
  2442. case TX_E_FAIL:
  2443. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2444. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2445. break;
  2446. case TX_E_STARTED:
  2447. if (tx->flags & (BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED)) {
  2448. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED |
  2449. BNA_TX_F_BW_UPDATED);
  2450. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2451. } else
  2452. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2453. break;
  2454. case TX_E_PRIO_CHANGE:
  2455. tx->flags |= BNA_TX_F_PRIO_CHANGED;
  2456. break;
  2457. case TX_E_BW_UPDATE:
  2458. tx->flags |= BNA_TX_F_BW_UPDATED;
  2459. break;
  2460. default:
  2461. bfa_sm_fault(event);
  2462. }
  2463. }
  2464. static void
  2465. bna_tx_sm_started_entry(struct bna_tx *tx)
  2466. {
  2467. struct bna_txq *txq;
  2468. struct list_head *qe;
  2469. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2470. list_for_each(qe, &tx->txq_q) {
  2471. txq = (struct bna_txq *)qe;
  2472. txq->tcb->priority = txq->priority;
  2473. /* Start IB */
  2474. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2475. }
  2476. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2477. }
  2478. static void
  2479. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2480. {
  2481. switch (event) {
  2482. case TX_E_STOP:
  2483. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2484. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2485. bna_tx_enet_stop(tx);
  2486. break;
  2487. case TX_E_FAIL:
  2488. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2489. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2490. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2491. break;
  2492. case TX_E_PRIO_CHANGE:
  2493. case TX_E_BW_UPDATE:
  2494. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2495. break;
  2496. default:
  2497. bfa_sm_fault(event);
  2498. }
  2499. }
  2500. static void
  2501. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2502. {
  2503. }
  2504. static void
  2505. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2506. {
  2507. switch (event) {
  2508. case TX_E_FAIL:
  2509. case TX_E_STOPPED:
  2510. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2511. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2512. break;
  2513. case TX_E_STARTED:
  2514. /**
  2515. * We are here due to start_wait -> stop_wait transition on
  2516. * TX_E_STOP event
  2517. */
  2518. bna_tx_enet_stop(tx);
  2519. break;
  2520. case TX_E_PRIO_CHANGE:
  2521. case TX_E_BW_UPDATE:
  2522. /* No-op */
  2523. break;
  2524. default:
  2525. bfa_sm_fault(event);
  2526. }
  2527. }
  2528. static void
  2529. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2530. {
  2531. }
  2532. static void
  2533. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2534. {
  2535. switch (event) {
  2536. case TX_E_FAIL:
  2537. case TX_E_PRIO_CHANGE:
  2538. case TX_E_BW_UPDATE:
  2539. /* No-op */
  2540. break;
  2541. case TX_E_CLEANUP_DONE:
  2542. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2543. break;
  2544. default:
  2545. bfa_sm_fault(event);
  2546. }
  2547. }
  2548. static void
  2549. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2550. {
  2551. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2552. bna_tx_enet_stop(tx);
  2553. }
  2554. static void
  2555. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2556. {
  2557. switch (event) {
  2558. case TX_E_STOP:
  2559. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2560. break;
  2561. case TX_E_FAIL:
  2562. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2563. call_tx_prio_change_cbfn(tx);
  2564. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2565. break;
  2566. case TX_E_STOPPED:
  2567. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2568. break;
  2569. case TX_E_PRIO_CHANGE:
  2570. case TX_E_BW_UPDATE:
  2571. /* No-op */
  2572. break;
  2573. default:
  2574. bfa_sm_fault(event);
  2575. }
  2576. }
  2577. static void
  2578. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2579. {
  2580. call_tx_prio_change_cbfn(tx);
  2581. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2582. }
  2583. static void
  2584. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2585. {
  2586. switch (event) {
  2587. case TX_E_STOP:
  2588. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2589. break;
  2590. case TX_E_FAIL:
  2591. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2592. break;
  2593. case TX_E_PRIO_CHANGE:
  2594. case TX_E_BW_UPDATE:
  2595. /* No-op */
  2596. break;
  2597. case TX_E_CLEANUP_DONE:
  2598. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2599. break;
  2600. default:
  2601. bfa_sm_fault(event);
  2602. }
  2603. }
  2604. static void
  2605. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2606. {
  2607. }
  2608. static void
  2609. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2610. {
  2611. switch (event) {
  2612. case TX_E_START:
  2613. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2614. break;
  2615. case TX_E_STOP:
  2616. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2617. break;
  2618. case TX_E_FAIL:
  2619. /* No-op */
  2620. break;
  2621. case TX_E_CLEANUP_DONE:
  2622. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2623. break;
  2624. default:
  2625. bfa_sm_fault(event);
  2626. }
  2627. }
  2628. static void
  2629. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2630. {
  2631. }
  2632. static void
  2633. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2634. {
  2635. switch (event) {
  2636. case TX_E_STOP:
  2637. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2638. break;
  2639. case TX_E_FAIL:
  2640. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2641. break;
  2642. case TX_E_CLEANUP_DONE:
  2643. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2644. break;
  2645. case TX_E_BW_UPDATE:
  2646. /* No-op */
  2647. break;
  2648. default:
  2649. bfa_sm_fault(event);
  2650. }
  2651. }
  2652. static void
  2653. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2654. {
  2655. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2656. struct bna_txq *txq = NULL;
  2657. struct list_head *qe;
  2658. int i;
  2659. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2660. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2661. cfg_req->mh.num_entries = htons(
  2662. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2663. cfg_req->num_queues = tx->num_txq;
  2664. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2665. i < tx->num_txq;
  2666. i++, qe = bfa_q_next(qe)) {
  2667. txq = (struct bna_txq *)qe;
  2668. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2669. cfg_req->q_cfg[i].q.priority = txq->priority;
  2670. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2671. txq->ib.ib_seg_host_addr.lsb;
  2672. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2673. txq->ib.ib_seg_host_addr.msb;
  2674. cfg_req->q_cfg[i].ib.intr.msix_index =
  2675. htons((u16)txq->ib.intr_vector);
  2676. }
  2677. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2678. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2679. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2680. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2681. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2682. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2683. cfg_req->ib_cfg.coalescing_timeout =
  2684. htonl((u32)txq->ib.coalescing_timeo);
  2685. cfg_req->ib_cfg.inter_pkt_timeout =
  2686. htonl((u32)txq->ib.interpkt_timeo);
  2687. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2688. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2689. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2690. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_DISABLED;
  2691. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2692. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2693. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2694. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2695. }
  2696. static void
  2697. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2698. {
  2699. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2700. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2701. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2702. req->mh.num_entries = htons(
  2703. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2704. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2705. &req->mh);
  2706. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2707. }
  2708. static void
  2709. bna_tx_enet_stop(struct bna_tx *tx)
  2710. {
  2711. struct bna_txq *txq;
  2712. struct list_head *qe;
  2713. /* Stop IB */
  2714. list_for_each(qe, &tx->txq_q) {
  2715. txq = (struct bna_txq *)qe;
  2716. bna_ib_stop(tx->bna, &txq->ib);
  2717. }
  2718. bna_bfi_tx_enet_stop(tx);
  2719. }
  2720. static void
  2721. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2722. struct bna_mem_descr *qpt_mem,
  2723. struct bna_mem_descr *swqpt_mem,
  2724. struct bna_mem_descr *page_mem)
  2725. {
  2726. int i;
  2727. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2728. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2729. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2730. txq->qpt.page_count = page_count;
  2731. txq->qpt.page_size = page_size;
  2732. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2733. for (i = 0; i < page_count; i++) {
  2734. txq->tcb->sw_qpt[i] = page_mem[i].kva;
  2735. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2736. page_mem[i].dma.lsb;
  2737. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2738. page_mem[i].dma.msb;
  2739. }
  2740. }
  2741. static struct bna_tx *
  2742. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2743. {
  2744. struct list_head *qe = NULL;
  2745. struct bna_tx *tx = NULL;
  2746. if (list_empty(&tx_mod->tx_free_q))
  2747. return NULL;
  2748. if (type == BNA_TX_T_REGULAR) {
  2749. bfa_q_deq(&tx_mod->tx_free_q, &qe);
  2750. } else {
  2751. bfa_q_deq_tail(&tx_mod->tx_free_q, &qe);
  2752. }
  2753. tx = (struct bna_tx *)qe;
  2754. bfa_q_qe_init(&tx->qe);
  2755. tx->type = type;
  2756. return tx;
  2757. }
  2758. static void
  2759. bna_tx_free(struct bna_tx *tx)
  2760. {
  2761. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2762. struct bna_txq *txq;
  2763. struct list_head *prev_qe;
  2764. struct list_head *qe;
  2765. while (!list_empty(&tx->txq_q)) {
  2766. bfa_q_deq(&tx->txq_q, &txq);
  2767. bfa_q_qe_init(&txq->qe);
  2768. txq->tcb = NULL;
  2769. txq->tx = NULL;
  2770. list_add_tail(&txq->qe, &tx_mod->txq_free_q);
  2771. }
  2772. list_for_each(qe, &tx_mod->tx_active_q) {
  2773. if (qe == &tx->qe) {
  2774. list_del(&tx->qe);
  2775. bfa_q_qe_init(&tx->qe);
  2776. break;
  2777. }
  2778. }
  2779. tx->bna = NULL;
  2780. tx->priv = NULL;
  2781. prev_qe = NULL;
  2782. list_for_each(qe, &tx_mod->tx_free_q) {
  2783. if (((struct bna_tx *)qe)->rid < tx->rid)
  2784. prev_qe = qe;
  2785. else {
  2786. break;
  2787. }
  2788. }
  2789. if (prev_qe == NULL) {
  2790. /* This is the first entry */
  2791. bfa_q_enq_head(&tx_mod->tx_free_q, &tx->qe);
  2792. } else if (bfa_q_next(prev_qe) == &tx_mod->tx_free_q) {
  2793. /* This is the last entry */
  2794. list_add_tail(&tx->qe, &tx_mod->tx_free_q);
  2795. } else {
  2796. /* Somewhere in the middle */
  2797. bfa_q_next(&tx->qe) = bfa_q_next(prev_qe);
  2798. bfa_q_prev(&tx->qe) = prev_qe;
  2799. bfa_q_next(prev_qe) = &tx->qe;
  2800. bfa_q_prev(bfa_q_next(&tx->qe)) = &tx->qe;
  2801. }
  2802. }
  2803. static void
  2804. bna_tx_start(struct bna_tx *tx)
  2805. {
  2806. tx->flags |= BNA_TX_F_ENET_STARTED;
  2807. if (tx->flags & BNA_TX_F_ENABLED)
  2808. bfa_fsm_send_event(tx, TX_E_START);
  2809. }
  2810. static void
  2811. bna_tx_stop(struct bna_tx *tx)
  2812. {
  2813. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  2814. tx->stop_cbarg = &tx->bna->tx_mod;
  2815. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2816. bfa_fsm_send_event(tx, TX_E_STOP);
  2817. }
  2818. static void
  2819. bna_tx_fail(struct bna_tx *tx)
  2820. {
  2821. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2822. bfa_fsm_send_event(tx, TX_E_FAIL);
  2823. }
  2824. void
  2825. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2826. {
  2827. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  2828. struct bna_txq *txq = NULL;
  2829. struct list_head *qe;
  2830. int i;
  2831. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  2832. sizeof(struct bfi_enet_tx_cfg_rsp));
  2833. tx->hw_id = cfg_rsp->hw_id;
  2834. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2835. i < tx->num_txq; i++, qe = bfa_q_next(qe)) {
  2836. txq = (struct bna_txq *)qe;
  2837. /* Setup doorbells */
  2838. txq->tcb->i_dbell->doorbell_addr =
  2839. tx->bna->pcidev.pci_bar_kva
  2840. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  2841. txq->tcb->q_dbell =
  2842. tx->bna->pcidev.pci_bar_kva
  2843. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  2844. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  2845. /* Initialize producer/consumer indexes */
  2846. (*txq->tcb->hw_consumer_index) = 0;
  2847. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  2848. }
  2849. bfa_fsm_send_event(tx, TX_E_STARTED);
  2850. }
  2851. void
  2852. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2853. {
  2854. bfa_fsm_send_event(tx, TX_E_STOPPED);
  2855. }
  2856. void
  2857. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  2858. {
  2859. struct bna_tx *tx;
  2860. struct list_head *qe;
  2861. list_for_each(qe, &tx_mod->tx_active_q) {
  2862. tx = (struct bna_tx *)qe;
  2863. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  2864. }
  2865. }
  2866. void
  2867. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  2868. {
  2869. u32 q_size;
  2870. u32 page_count;
  2871. struct bna_mem_info *mem_info;
  2872. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  2873. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  2874. mem_info->mem_type = BNA_MEM_T_KVA;
  2875. mem_info->len = sizeof(struct bna_tcb);
  2876. mem_info->num = num_txq;
  2877. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  2878. q_size = ALIGN(q_size, PAGE_SIZE);
  2879. page_count = q_size >> PAGE_SHIFT;
  2880. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  2881. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  2882. mem_info->mem_type = BNA_MEM_T_DMA;
  2883. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  2884. mem_info->num = num_txq;
  2885. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  2886. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  2887. mem_info->mem_type = BNA_MEM_T_KVA;
  2888. mem_info->len = page_count * sizeof(void *);
  2889. mem_info->num = num_txq;
  2890. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  2891. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  2892. mem_info->mem_type = BNA_MEM_T_DMA;
  2893. mem_info->len = PAGE_SIZE;
  2894. mem_info->num = num_txq * page_count;
  2895. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2896. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  2897. mem_info->mem_type = BNA_MEM_T_DMA;
  2898. mem_info->len = BFI_IBIDX_SIZE;
  2899. mem_info->num = num_txq;
  2900. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  2901. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  2902. BNA_INTR_T_MSIX;
  2903. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  2904. }
  2905. struct bna_tx *
  2906. bna_tx_create(struct bna *bna, struct bnad *bnad,
  2907. struct bna_tx_config *tx_cfg,
  2908. struct bna_tx_event_cbfn *tx_cbfn,
  2909. struct bna_res_info *res_info, void *priv)
  2910. {
  2911. struct bna_intr_info *intr_info;
  2912. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  2913. struct bna_tx *tx;
  2914. struct bna_txq *txq;
  2915. struct list_head *qe;
  2916. int page_count;
  2917. int page_size;
  2918. int page_idx;
  2919. int i;
  2920. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  2921. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) /
  2922. tx_cfg->num_txq;
  2923. page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len;
  2924. /**
  2925. * Get resources
  2926. */
  2927. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  2928. return NULL;
  2929. /* Tx */
  2930. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  2931. if (!tx)
  2932. return NULL;
  2933. tx->bna = bna;
  2934. tx->priv = priv;
  2935. /* TxQs */
  2936. INIT_LIST_HEAD(&tx->txq_q);
  2937. for (i = 0; i < tx_cfg->num_txq; i++) {
  2938. if (list_empty(&tx_mod->txq_free_q))
  2939. goto err_return;
  2940. bfa_q_deq(&tx_mod->txq_free_q, &txq);
  2941. bfa_q_qe_init(&txq->qe);
  2942. list_add_tail(&txq->qe, &tx->txq_q);
  2943. txq->tx = tx;
  2944. }
  2945. /*
  2946. * Initialize
  2947. */
  2948. /* Tx */
  2949. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  2950. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  2951. /* Following callbacks are mandatory */
  2952. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  2953. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  2954. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  2955. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  2956. tx->num_txq = tx_cfg->num_txq;
  2957. tx->flags = 0;
  2958. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  2959. switch (tx->type) {
  2960. case BNA_TX_T_REGULAR:
  2961. if (!(tx->bna->tx_mod.flags &
  2962. BNA_TX_MOD_F_ENET_LOOPBACK))
  2963. tx->flags |= BNA_TX_F_ENET_STARTED;
  2964. break;
  2965. case BNA_TX_T_LOOPBACK:
  2966. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  2967. tx->flags |= BNA_TX_F_ENET_STARTED;
  2968. break;
  2969. }
  2970. }
  2971. /* TxQ */
  2972. i = 0;
  2973. page_idx = 0;
  2974. list_for_each(qe, &tx->txq_q) {
  2975. txq = (struct bna_txq *)qe;
  2976. txq->tcb = (struct bna_tcb *)
  2977. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  2978. txq->tx_packets = 0;
  2979. txq->tx_bytes = 0;
  2980. /* IB */
  2981. txq->ib.ib_seg_host_addr.lsb =
  2982. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2983. txq->ib.ib_seg_host_addr.msb =
  2984. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2985. txq->ib.ib_seg_host_addr_kva =
  2986. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2987. txq->ib.intr_type = intr_info->intr_type;
  2988. txq->ib.intr_vector = (intr_info->num == 1) ?
  2989. intr_info->idl[0].vector :
  2990. intr_info->idl[i].vector;
  2991. if (intr_info->intr_type == BNA_INTR_T_INTX)
  2992. txq->ib.intr_vector = (1 << txq->ib.intr_vector);
  2993. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  2994. txq->ib.interpkt_timeo = 0; /* Not used */
  2995. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  2996. /* TCB */
  2997. txq->tcb->q_depth = tx_cfg->txq_depth;
  2998. txq->tcb->unmap_q = (void *)
  2999. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  3000. txq->tcb->hw_consumer_index =
  3001. (u32 *)txq->ib.ib_seg_host_addr_kva;
  3002. txq->tcb->i_dbell = &txq->ib.door_bell;
  3003. txq->tcb->intr_type = txq->ib.intr_type;
  3004. txq->tcb->intr_vector = txq->ib.intr_vector;
  3005. txq->tcb->txq = txq;
  3006. txq->tcb->bnad = bnad;
  3007. txq->tcb->id = i;
  3008. /* QPT, SWQPT, Pages */
  3009. bna_txq_qpt_setup(txq, page_count, page_size,
  3010. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  3011. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  3012. &res_info[BNA_TX_RES_MEM_T_PAGE].
  3013. res_u.mem_info.mdl[page_idx]);
  3014. txq->tcb->page_idx = page_idx;
  3015. txq->tcb->page_count = page_count;
  3016. page_idx += page_count;
  3017. /* Callback to bnad for setting up TCB */
  3018. if (tx->tcb_setup_cbfn)
  3019. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  3020. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  3021. txq->priority = txq->tcb->id;
  3022. else
  3023. txq->priority = tx_mod->default_prio;
  3024. i++;
  3025. }
  3026. tx->txf_vlan_id = 0;
  3027. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  3028. tx_mod->rid_mask |= (1 << tx->rid);
  3029. return tx;
  3030. err_return:
  3031. bna_tx_free(tx);
  3032. return NULL;
  3033. }
  3034. void
  3035. bna_tx_destroy(struct bna_tx *tx)
  3036. {
  3037. struct bna_txq *txq;
  3038. struct list_head *qe;
  3039. list_for_each(qe, &tx->txq_q) {
  3040. txq = (struct bna_txq *)qe;
  3041. if (tx->tcb_destroy_cbfn)
  3042. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  3043. }
  3044. tx->bna->tx_mod.rid_mask &= ~(1 << tx->rid);
  3045. bna_tx_free(tx);
  3046. }
  3047. void
  3048. bna_tx_enable(struct bna_tx *tx)
  3049. {
  3050. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  3051. return;
  3052. tx->flags |= BNA_TX_F_ENABLED;
  3053. if (tx->flags & BNA_TX_F_ENET_STARTED)
  3054. bfa_fsm_send_event(tx, TX_E_START);
  3055. }
  3056. void
  3057. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  3058. void (*cbfn)(void *, struct bna_tx *))
  3059. {
  3060. if (type == BNA_SOFT_CLEANUP) {
  3061. (*cbfn)(tx->bna->bnad, tx);
  3062. return;
  3063. }
  3064. tx->stop_cbfn = cbfn;
  3065. tx->stop_cbarg = tx->bna->bnad;
  3066. tx->flags &= ~BNA_TX_F_ENABLED;
  3067. bfa_fsm_send_event(tx, TX_E_STOP);
  3068. }
  3069. void
  3070. bna_tx_cleanup_complete(struct bna_tx *tx)
  3071. {
  3072. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  3073. }
  3074. static void
  3075. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  3076. {
  3077. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3078. bfa_wc_down(&tx_mod->tx_stop_wc);
  3079. }
  3080. static void
  3081. bna_tx_mod_cb_tx_stopped_all(void *arg)
  3082. {
  3083. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3084. if (tx_mod->stop_cbfn)
  3085. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3086. tx_mod->stop_cbfn = NULL;
  3087. }
  3088. void
  3089. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3090. struct bna_res_info *res_info)
  3091. {
  3092. int i;
  3093. tx_mod->bna = bna;
  3094. tx_mod->flags = 0;
  3095. tx_mod->tx = (struct bna_tx *)
  3096. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3097. tx_mod->txq = (struct bna_txq *)
  3098. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3099. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3100. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3101. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3102. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3103. tx_mod->tx[i].rid = i;
  3104. bfa_q_qe_init(&tx_mod->tx[i].qe);
  3105. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3106. bfa_q_qe_init(&tx_mod->txq[i].qe);
  3107. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3108. }
  3109. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3110. tx_mod->default_prio = 0;
  3111. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3112. tx_mod->iscsi_prio = -1;
  3113. }
  3114. void
  3115. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3116. {
  3117. struct list_head *qe;
  3118. int i;
  3119. i = 0;
  3120. list_for_each(qe, &tx_mod->tx_free_q)
  3121. i++;
  3122. i = 0;
  3123. list_for_each(qe, &tx_mod->txq_free_q)
  3124. i++;
  3125. tx_mod->bna = NULL;
  3126. }
  3127. void
  3128. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3129. {
  3130. struct bna_tx *tx;
  3131. struct list_head *qe;
  3132. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3133. if (type == BNA_TX_T_LOOPBACK)
  3134. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3135. list_for_each(qe, &tx_mod->tx_active_q) {
  3136. tx = (struct bna_tx *)qe;
  3137. if (tx->type == type)
  3138. bna_tx_start(tx);
  3139. }
  3140. }
  3141. void
  3142. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3143. {
  3144. struct bna_tx *tx;
  3145. struct list_head *qe;
  3146. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3147. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3148. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3149. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3150. list_for_each(qe, &tx_mod->tx_active_q) {
  3151. tx = (struct bna_tx *)qe;
  3152. if (tx->type == type) {
  3153. bfa_wc_up(&tx_mod->tx_stop_wc);
  3154. bna_tx_stop(tx);
  3155. }
  3156. }
  3157. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3158. }
  3159. void
  3160. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3161. {
  3162. struct bna_tx *tx;
  3163. struct list_head *qe;
  3164. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3165. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3166. list_for_each(qe, &tx_mod->tx_active_q) {
  3167. tx = (struct bna_tx *)qe;
  3168. bna_tx_fail(tx);
  3169. }
  3170. }
  3171. void
  3172. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3173. {
  3174. struct bna_txq *txq;
  3175. struct list_head *qe;
  3176. list_for_each(qe, &tx->txq_q) {
  3177. txq = (struct bna_txq *)qe;
  3178. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3179. }
  3180. }