cs5535.h 4.6 KB

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  1. /*
  2. * AMD CS5535/CS5536 definitions
  3. * Copyright (C) 2006 Advanced Micro Devices, Inc.
  4. * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of version 2 of the GNU General Public License
  8. * as published by the Free Software Foundation.
  9. */
  10. #ifndef _CS5535_H
  11. #define _CS5535_H
  12. /* MSRs */
  13. #define MSR_GLIU_P2D_RO0 0x10000029
  14. #define MSR_LX_GLD_MSR_CONFIG 0x48002001
  15. #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
  16. * sheet has the wrong value */
  17. #define MSR_GLCP_SYS_RSTPLL 0x4C000014
  18. #define MSR_GLCP_DOTPLL 0x4C000015
  19. #define MSR_LBAR_SMB 0x5140000B
  20. #define MSR_LBAR_GPIO 0x5140000C
  21. #define MSR_LBAR_MFGPT 0x5140000D
  22. #define MSR_LBAR_ACPI 0x5140000E
  23. #define MSR_LBAR_PMS 0x5140000F
  24. #define MSR_DIVIL_SOFT_RESET 0x51400017
  25. #define MSR_PIC_YSEL_LOW 0x51400020
  26. #define MSR_PIC_YSEL_HIGH 0x51400021
  27. #define MSR_PIC_ZSEL_LOW 0x51400022
  28. #define MSR_PIC_ZSEL_HIGH 0x51400023
  29. #define MSR_PIC_IRQM_LPC 0x51400025
  30. #define MSR_MFGPT_IRQ 0x51400028
  31. #define MSR_MFGPT_NR 0x51400029
  32. #define MSR_MFGPT_SETUP 0x5140002B
  33. #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
  34. #define MSR_GX_GLD_MSR_CONFIG 0xC0002001
  35. #define MSR_GX_MSR_PADSEL 0xC0002011
  36. /* resource sizes */
  37. #define LBAR_GPIO_SIZE 0xFF
  38. #define LBAR_MFGPT_SIZE 0x40
  39. #define LBAR_ACPI_SIZE 0x40
  40. #define LBAR_PMS_SIZE 0x80
  41. /* VSA2 magic values */
  42. #define VSA_VRC_INDEX 0xAC1C
  43. #define VSA_VRC_DATA 0xAC1E
  44. #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
  45. #define VSA_VR_SIGNATURE 0x0003
  46. #define VSA_VR_MEM_SIZE 0x0200
  47. #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
  48. #define GSW_VSA_SIG 0x534d /* General Software signature */
  49. #include <linux/io.h>
  50. static inline int cs5535_has_vsa2(void)
  51. {
  52. static int has_vsa2 = -1;
  53. if (has_vsa2 == -1) {
  54. uint16_t val;
  55. /*
  56. * The VSA has virtual registers that we can query for a
  57. * signature.
  58. */
  59. outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
  60. outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
  61. val = inw(VSA_VRC_DATA);
  62. has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
  63. }
  64. return has_vsa2;
  65. }
  66. /* GPIOs */
  67. #define GPIO_OUTPUT_VAL 0x00
  68. #define GPIO_OUTPUT_ENABLE 0x04
  69. #define GPIO_OUTPUT_OPEN_DRAIN 0x08
  70. #define GPIO_OUTPUT_INVERT 0x0C
  71. #define GPIO_OUTPUT_AUX1 0x10
  72. #define GPIO_OUTPUT_AUX2 0x14
  73. #define GPIO_PULL_UP 0x18
  74. #define GPIO_PULL_DOWN 0x1C
  75. #define GPIO_INPUT_ENABLE 0x20
  76. #define GPIO_INPUT_INVERT 0x24
  77. #define GPIO_INPUT_FILTER 0x28
  78. #define GPIO_INPUT_EVENT_COUNT 0x2C
  79. #define GPIO_READ_BACK 0x30
  80. #define GPIO_INPUT_AUX1 0x34
  81. #define GPIO_EVENTS_ENABLE 0x38
  82. #define GPIO_LOCK_ENABLE 0x3C
  83. #define GPIO_POSITIVE_EDGE_EN 0x40
  84. #define GPIO_NEGATIVE_EDGE_EN 0x44
  85. #define GPIO_POSITIVE_EDGE_STS 0x48
  86. #define GPIO_NEGATIVE_EDGE_STS 0x4C
  87. #define GPIO_MAP_X 0xE0
  88. #define GPIO_MAP_Y 0xE4
  89. #define GPIO_MAP_Z 0xE8
  90. #define GPIO_MAP_W 0xEC
  91. void cs5535_gpio_set(unsigned offset, unsigned int reg);
  92. void cs5535_gpio_clear(unsigned offset, unsigned int reg);
  93. int cs5535_gpio_isset(unsigned offset, unsigned int reg);
  94. /* MFGPTs */
  95. #define MFGPT_MAX_TIMERS 8
  96. #define MFGPT_TIMER_ANY (-1)
  97. #define MFGPT_DOMAIN_WORKING 1
  98. #define MFGPT_DOMAIN_STANDBY 2
  99. #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
  100. #define MFGPT_CMP1 0
  101. #define MFGPT_CMP2 1
  102. #define MFGPT_EVENT_IRQ 0
  103. #define MFGPT_EVENT_NMI 1
  104. #define MFGPT_EVENT_RESET 3
  105. #define MFGPT_REG_CMP1 0
  106. #define MFGPT_REG_CMP2 2
  107. #define MFGPT_REG_COUNTER 4
  108. #define MFGPT_REG_SETUP 6
  109. #define MFGPT_SETUP_CNTEN (1 << 15)
  110. #define MFGPT_SETUP_CMP2 (1 << 14)
  111. #define MFGPT_SETUP_CMP1 (1 << 13)
  112. #define MFGPT_SETUP_SETUP (1 << 12)
  113. #define MFGPT_SETUP_STOPEN (1 << 11)
  114. #define MFGPT_SETUP_EXTEN (1 << 10)
  115. #define MFGPT_SETUP_REVEN (1 << 5)
  116. #define MFGPT_SETUP_CLKSEL (1 << 4)
  117. struct cs5535_mfgpt_timer;
  118. extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
  119. uint16_t reg);
  120. extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
  121. uint16_t value);
  122. extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
  123. int event, int enable);
  124. extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
  125. int *irq, int enable);
  126. extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
  127. int domain);
  128. extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
  129. static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
  130. int cmp, int *irq)
  131. {
  132. return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
  133. }
  134. static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
  135. int cmp, int *irq)
  136. {
  137. return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
  138. }
  139. #endif