kprobes-thumb.c 16 KB

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  1. /*
  2. * arch/arm/kernel/kprobes-thumb.c
  3. *
  4. * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/kprobes.h>
  12. #include "kprobes.h"
  13. /*
  14. * True if current instruction is in an IT block.
  15. */
  16. #define in_it_block(cpsr) ((cpsr & 0x06000c00) != 0x00000000)
  17. /*
  18. * Return the condition code to check for the currently executing instruction.
  19. * This is in ITSTATE<7:4> which is in CPSR<15:12> but is only valid if
  20. * in_it_block returns true.
  21. */
  22. #define current_cond(cpsr) ((cpsr >> 12) & 0xf)
  23. /*
  24. * Return the PC value for a probe in thumb code.
  25. * This is the address of the probed instruction plus 4.
  26. * We subtract one because the address will have bit zero set to indicate
  27. * a pointer to thumb code.
  28. */
  29. static inline unsigned long __kprobes thumb_probe_pc(struct kprobe *p)
  30. {
  31. return (unsigned long)p->addr - 1 + 4;
  32. }
  33. static const union decode_item t32_table_1111_0xxx___1[] = {
  34. /* Branches and miscellaneous control */
  35. /* YIELD 1111 0011 1010 xxxx 10x0 x000 0000 0001 */
  36. DECODE_OR (0xfff0d7ff, 0xf3a08001),
  37. /* SEV 1111 0011 1010 xxxx 10x0 x000 0000 0100 */
  38. DECODE_EMULATE (0xfff0d7ff, 0xf3a08004, kprobe_emulate_none),
  39. /* NOP 1111 0011 1010 xxxx 10x0 x000 0000 0000 */
  40. /* WFE 1111 0011 1010 xxxx 10x0 x000 0000 0010 */
  41. /* WFI 1111 0011 1010 xxxx 10x0 x000 0000 0011 */
  42. DECODE_SIMULATE (0xfff0d7fc, 0xf3a08000, kprobe_simulate_nop),
  43. DECODE_END
  44. };
  45. const union decode_item kprobe_decode_thumb32_table[] = {
  46. /*
  47. * Branches and miscellaneous control
  48. * 1111 0xxx xxxx xxxx 1xxx xxxx xxxx xxxx
  49. */
  50. DECODE_TABLE (0xf8008000, 0xf0008000, t32_table_1111_0xxx___1),
  51. DECODE_END
  52. };
  53. static void __kprobes
  54. t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
  55. {
  56. kprobe_opcode_t insn = p->opcode;
  57. unsigned long pc = thumb_probe_pc(p);
  58. int rm = (insn >> 3) & 0xf;
  59. unsigned long rmv = (rm == 15) ? pc : regs->uregs[rm];
  60. if (insn & (1 << 7)) /* BLX ? */
  61. regs->ARM_lr = (unsigned long)p->addr + 2;
  62. bx_write_pc(rmv, regs);
  63. }
  64. static void __kprobes
  65. t16_simulate_ldr_literal(struct kprobe *p, struct pt_regs *regs)
  66. {
  67. kprobe_opcode_t insn = p->opcode;
  68. unsigned long* base = (unsigned long *)(thumb_probe_pc(p) & ~3);
  69. long index = insn & 0xff;
  70. int rt = (insn >> 8) & 0x7;
  71. regs->uregs[rt] = base[index];
  72. }
  73. static void __kprobes
  74. t16_simulate_ldrstr_sp_relative(struct kprobe *p, struct pt_regs *regs)
  75. {
  76. kprobe_opcode_t insn = p->opcode;
  77. unsigned long* base = (unsigned long *)regs->ARM_sp;
  78. long index = insn & 0xff;
  79. int rt = (insn >> 8) & 0x7;
  80. if (insn & 0x800) /* LDR */
  81. regs->uregs[rt] = base[index];
  82. else /* STR */
  83. base[index] = regs->uregs[rt];
  84. }
  85. static void __kprobes
  86. t16_simulate_reladr(struct kprobe *p, struct pt_regs *regs)
  87. {
  88. kprobe_opcode_t insn = p->opcode;
  89. unsigned long base = (insn & 0x800) ? regs->ARM_sp
  90. : (thumb_probe_pc(p) & ~3);
  91. long offset = insn & 0xff;
  92. int rt = (insn >> 8) & 0x7;
  93. regs->uregs[rt] = base + offset * 4;
  94. }
  95. static void __kprobes
  96. t16_simulate_add_sp_imm(struct kprobe *p, struct pt_regs *regs)
  97. {
  98. kprobe_opcode_t insn = p->opcode;
  99. long imm = insn & 0x7f;
  100. if (insn & 0x80) /* SUB */
  101. regs->ARM_sp -= imm * 4;
  102. else /* ADD */
  103. regs->ARM_sp += imm * 4;
  104. }
  105. static void __kprobes
  106. t16_simulate_cbz(struct kprobe *p, struct pt_regs *regs)
  107. {
  108. kprobe_opcode_t insn = p->opcode;
  109. int rn = insn & 0x7;
  110. kprobe_opcode_t nonzero = regs->uregs[rn] ? insn : ~insn;
  111. if (nonzero & 0x800) {
  112. long i = insn & 0x200;
  113. long imm5 = insn & 0xf8;
  114. unsigned long pc = thumb_probe_pc(p);
  115. regs->ARM_pc = pc + (i >> 3) + (imm5 >> 2);
  116. }
  117. }
  118. static void __kprobes
  119. t16_simulate_it(struct kprobe *p, struct pt_regs *regs)
  120. {
  121. /*
  122. * The 8 IT state bits are split into two parts in CPSR:
  123. * ITSTATE<1:0> are in CPSR<26:25>
  124. * ITSTATE<7:2> are in CPSR<15:10>
  125. * The new IT state is in the lower byte of insn.
  126. */
  127. kprobe_opcode_t insn = p->opcode;
  128. unsigned long cpsr = regs->ARM_cpsr;
  129. cpsr &= ~PSR_IT_MASK;
  130. cpsr |= (insn & 0xfc) << 8;
  131. cpsr |= (insn & 0x03) << 25;
  132. regs->ARM_cpsr = cpsr;
  133. }
  134. static void __kprobes
  135. t16_singlestep_it(struct kprobe *p, struct pt_regs *regs)
  136. {
  137. regs->ARM_pc += 2;
  138. t16_simulate_it(p, regs);
  139. }
  140. static enum kprobe_insn __kprobes
  141. t16_decode_it(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  142. {
  143. asi->insn_singlestep = t16_singlestep_it;
  144. return INSN_GOOD_NO_SLOT;
  145. }
  146. static void __kprobes
  147. t16_simulate_cond_branch(struct kprobe *p, struct pt_regs *regs)
  148. {
  149. kprobe_opcode_t insn = p->opcode;
  150. unsigned long pc = thumb_probe_pc(p);
  151. long offset = insn & 0x7f;
  152. offset -= insn & 0x80; /* Apply sign bit */
  153. regs->ARM_pc = pc + (offset * 2);
  154. }
  155. static enum kprobe_insn __kprobes
  156. t16_decode_cond_branch(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  157. {
  158. int cc = (insn >> 8) & 0xf;
  159. asi->insn_check_cc = kprobe_condition_checks[cc];
  160. asi->insn_handler = t16_simulate_cond_branch;
  161. return INSN_GOOD_NO_SLOT;
  162. }
  163. static void __kprobes
  164. t16_simulate_branch(struct kprobe *p, struct pt_regs *regs)
  165. {
  166. kprobe_opcode_t insn = p->opcode;
  167. unsigned long pc = thumb_probe_pc(p);
  168. long offset = insn & 0x3ff;
  169. offset -= insn & 0x400; /* Apply sign bit */
  170. regs->ARM_pc = pc + (offset * 2);
  171. }
  172. static unsigned long __kprobes
  173. t16_emulate_loregs(struct kprobe *p, struct pt_regs *regs)
  174. {
  175. unsigned long oldcpsr = regs->ARM_cpsr;
  176. unsigned long newcpsr;
  177. __asm__ __volatile__ (
  178. "msr cpsr_fs, %[oldcpsr] \n\t"
  179. "ldmia %[regs], {r0-r7} \n\t"
  180. "blx %[fn] \n\t"
  181. "stmia %[regs], {r0-r7} \n\t"
  182. "mrs %[newcpsr], cpsr \n\t"
  183. : [newcpsr] "=r" (newcpsr)
  184. : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs),
  185. [fn] "r" (p->ainsn.insn_fn)
  186. : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  187. "lr", "memory", "cc"
  188. );
  189. return (oldcpsr & ~APSR_MASK) | (newcpsr & APSR_MASK);
  190. }
  191. static void __kprobes
  192. t16_emulate_loregs_rwflags(struct kprobe *p, struct pt_regs *regs)
  193. {
  194. regs->ARM_cpsr = t16_emulate_loregs(p, regs);
  195. }
  196. static void __kprobes
  197. t16_emulate_loregs_noitrwflags(struct kprobe *p, struct pt_regs *regs)
  198. {
  199. unsigned long cpsr = t16_emulate_loregs(p, regs);
  200. if (!in_it_block(cpsr))
  201. regs->ARM_cpsr = cpsr;
  202. }
  203. static void __kprobes
  204. t16_emulate_hiregs(struct kprobe *p, struct pt_regs *regs)
  205. {
  206. kprobe_opcode_t insn = p->opcode;
  207. unsigned long pc = thumb_probe_pc(p);
  208. int rdn = (insn & 0x7) | ((insn & 0x80) >> 4);
  209. int rm = (insn >> 3) & 0xf;
  210. register unsigned long rdnv asm("r1");
  211. register unsigned long rmv asm("r0");
  212. unsigned long cpsr = regs->ARM_cpsr;
  213. rdnv = (rdn == 15) ? pc : regs->uregs[rdn];
  214. rmv = (rm == 15) ? pc : regs->uregs[rm];
  215. __asm__ __volatile__ (
  216. "msr cpsr_fs, %[cpsr] \n\t"
  217. "blx %[fn] \n\t"
  218. "mrs %[cpsr], cpsr \n\t"
  219. : "=r" (rdnv), [cpsr] "=r" (cpsr)
  220. : "0" (rdnv), "r" (rmv), "1" (cpsr), [fn] "r" (p->ainsn.insn_fn)
  221. : "lr", "memory", "cc"
  222. );
  223. if (rdn == 15)
  224. rdnv &= ~1;
  225. regs->uregs[rdn] = rdnv;
  226. regs->ARM_cpsr = (regs->ARM_cpsr & ~APSR_MASK) | (cpsr & APSR_MASK);
  227. }
  228. static enum kprobe_insn __kprobes
  229. t16_decode_hiregs(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  230. {
  231. insn &= ~0x00ff;
  232. insn |= 0x001; /* Set Rdn = R1 and Rm = R0 */
  233. ((u16 *)asi->insn)[0] = insn;
  234. asi->insn_handler = t16_emulate_hiregs;
  235. return INSN_GOOD;
  236. }
  237. static void __kprobes
  238. t16_emulate_push(struct kprobe *p, struct pt_regs *regs)
  239. {
  240. __asm__ __volatile__ (
  241. "ldr r9, [%[regs], #13*4] \n\t"
  242. "ldr r8, [%[regs], #14*4] \n\t"
  243. "ldmia %[regs], {r0-r7} \n\t"
  244. "blx %[fn] \n\t"
  245. "str r9, [%[regs], #13*4] \n\t"
  246. :
  247. : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
  248. : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
  249. "lr", "memory", "cc"
  250. );
  251. }
  252. static enum kprobe_insn __kprobes
  253. t16_decode_push(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  254. {
  255. /*
  256. * To simulate a PUSH we use a Thumb-2 "STMDB R9!, {registers}"
  257. * and call it with R9=SP and LR in the register list represented
  258. * by R8.
  259. */
  260. ((u16 *)asi->insn)[0] = 0xe929; /* 1st half STMDB R9!,{} */
  261. ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
  262. asi->insn_handler = t16_emulate_push;
  263. return INSN_GOOD;
  264. }
  265. static void __kprobes
  266. t16_emulate_pop_nopc(struct kprobe *p, struct pt_regs *regs)
  267. {
  268. __asm__ __volatile__ (
  269. "ldr r9, [%[regs], #13*4] \n\t"
  270. "ldmia %[regs], {r0-r7} \n\t"
  271. "blx %[fn] \n\t"
  272. "stmia %[regs], {r0-r7} \n\t"
  273. "str r9, [%[regs], #13*4] \n\t"
  274. :
  275. : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
  276. : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
  277. "lr", "memory", "cc"
  278. );
  279. }
  280. static void __kprobes
  281. t16_emulate_pop_pc(struct kprobe *p, struct pt_regs *regs)
  282. {
  283. register unsigned long pc asm("r8");
  284. __asm__ __volatile__ (
  285. "ldr r9, [%[regs], #13*4] \n\t"
  286. "ldmia %[regs], {r0-r7} \n\t"
  287. "blx %[fn] \n\t"
  288. "stmia %[regs], {r0-r7} \n\t"
  289. "str r9, [%[regs], #13*4] \n\t"
  290. : "=r" (pc)
  291. : [regs] "r" (regs), [fn] "r" (p->ainsn.insn_fn)
  292. : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9",
  293. "lr", "memory", "cc"
  294. );
  295. bx_write_pc(pc, regs);
  296. }
  297. static enum kprobe_insn __kprobes
  298. t16_decode_pop(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  299. {
  300. /*
  301. * To simulate a POP we use a Thumb-2 "LDMDB R9!, {registers}"
  302. * and call it with R9=SP and PC in the register list represented
  303. * by R8.
  304. */
  305. ((u16 *)asi->insn)[0] = 0xe8b9; /* 1st half LDMIA R9!,{} */
  306. ((u16 *)asi->insn)[1] = insn & 0x1ff; /* 2nd half (register list) */
  307. asi->insn_handler = insn & 0x100 ? t16_emulate_pop_pc
  308. : t16_emulate_pop_nopc;
  309. return INSN_GOOD;
  310. }
  311. static const union decode_item t16_table_1011[] = {
  312. /* Miscellaneous 16-bit instructions */
  313. /* ADD (SP plus immediate) 1011 0000 0xxx xxxx */
  314. /* SUB (SP minus immediate) 1011 0000 1xxx xxxx */
  315. DECODE_SIMULATE (0xff00, 0xb000, t16_simulate_add_sp_imm),
  316. /* CBZ 1011 00x1 xxxx xxxx */
  317. /* CBNZ 1011 10x1 xxxx xxxx */
  318. DECODE_SIMULATE (0xf500, 0xb100, t16_simulate_cbz),
  319. /* SXTH 1011 0010 00xx xxxx */
  320. /* SXTB 1011 0010 01xx xxxx */
  321. /* UXTH 1011 0010 10xx xxxx */
  322. /* UXTB 1011 0010 11xx xxxx */
  323. /* REV 1011 1010 00xx xxxx */
  324. /* REV16 1011 1010 01xx xxxx */
  325. /* ??? 1011 1010 10xx xxxx */
  326. /* REVSH 1011 1010 11xx xxxx */
  327. DECODE_REJECT (0xffc0, 0xba80),
  328. DECODE_EMULATE (0xf500, 0xb000, t16_emulate_loregs_rwflags),
  329. /* PUSH 1011 010x xxxx xxxx */
  330. DECODE_CUSTOM (0xfe00, 0xb400, t16_decode_push),
  331. /* POP 1011 110x xxxx xxxx */
  332. DECODE_CUSTOM (0xfe00, 0xbc00, t16_decode_pop),
  333. /*
  334. * If-Then, and hints
  335. * 1011 1111 xxxx xxxx
  336. */
  337. /* YIELD 1011 1111 0001 0000 */
  338. DECODE_OR (0xffff, 0xbf10),
  339. /* SEV 1011 1111 0100 0000 */
  340. DECODE_EMULATE (0xffff, 0xbf40, kprobe_emulate_none),
  341. /* NOP 1011 1111 0000 0000 */
  342. /* WFE 1011 1111 0010 0000 */
  343. /* WFI 1011 1111 0011 0000 */
  344. DECODE_SIMULATE (0xffcf, 0xbf00, kprobe_simulate_nop),
  345. /* Unassigned hints 1011 1111 xxxx 0000 */
  346. DECODE_REJECT (0xff0f, 0xbf00),
  347. /* IT 1011 1111 xxxx xxxx */
  348. DECODE_CUSTOM (0xff00, 0xbf00, t16_decode_it),
  349. /* SETEND 1011 0110 010x xxxx */
  350. /* CPS 1011 0110 011x xxxx */
  351. /* BKPT 1011 1110 xxxx xxxx */
  352. /* And unallocated instructions... */
  353. DECODE_END
  354. };
  355. const union decode_item kprobe_decode_thumb16_table[] = {
  356. /*
  357. * Shift (immediate), add, subtract, move, and compare
  358. * 00xx xxxx xxxx xxxx
  359. */
  360. /* CMP (immediate) 0010 1xxx xxxx xxxx */
  361. DECODE_EMULATE (0xf800, 0x2800, t16_emulate_loregs_rwflags),
  362. /* ADD (register) 0001 100x xxxx xxxx */
  363. /* SUB (register) 0001 101x xxxx xxxx */
  364. /* LSL (immediate) 0000 0xxx xxxx xxxx */
  365. /* LSR (immediate) 0000 1xxx xxxx xxxx */
  366. /* ASR (immediate) 0001 0xxx xxxx xxxx */
  367. /* ADD (immediate, Thumb) 0001 110x xxxx xxxx */
  368. /* SUB (immediate, Thumb) 0001 111x xxxx xxxx */
  369. /* MOV (immediate) 0010 0xxx xxxx xxxx */
  370. /* ADD (immediate, Thumb) 0011 0xxx xxxx xxxx */
  371. /* SUB (immediate, Thumb) 0011 1xxx xxxx xxxx */
  372. DECODE_EMULATE (0xc000, 0x0000, t16_emulate_loregs_noitrwflags),
  373. /*
  374. * 16-bit Thumb data-processing instructions
  375. * 0100 00xx xxxx xxxx
  376. */
  377. /* TST (register) 0100 0010 00xx xxxx */
  378. DECODE_EMULATE (0xffc0, 0x4200, t16_emulate_loregs_rwflags),
  379. /* CMP (register) 0100 0010 10xx xxxx */
  380. /* CMN (register) 0100 0010 11xx xxxx */
  381. DECODE_EMULATE (0xff80, 0x4280, t16_emulate_loregs_rwflags),
  382. /* AND (register) 0100 0000 00xx xxxx */
  383. /* EOR (register) 0100 0000 01xx xxxx */
  384. /* LSL (register) 0100 0000 10xx xxxx */
  385. /* LSR (register) 0100 0000 11xx xxxx */
  386. /* ASR (register) 0100 0001 00xx xxxx */
  387. /* ADC (register) 0100 0001 01xx xxxx */
  388. /* SBC (register) 0100 0001 10xx xxxx */
  389. /* ROR (register) 0100 0001 11xx xxxx */
  390. /* RSB (immediate) 0100 0010 01xx xxxx */
  391. /* ORR (register) 0100 0011 00xx xxxx */
  392. /* MUL 0100 0011 00xx xxxx */
  393. /* BIC (register) 0100 0011 10xx xxxx */
  394. /* MVN (register) 0100 0011 10xx xxxx */
  395. DECODE_EMULATE (0xfc00, 0x4000, t16_emulate_loregs_noitrwflags),
  396. /*
  397. * Special data instructions and branch and exchange
  398. * 0100 01xx xxxx xxxx
  399. */
  400. /* BLX pc 0100 0111 1111 1xxx */
  401. DECODE_REJECT (0xfff8, 0x47f8),
  402. /* BX (register) 0100 0111 0xxx xxxx */
  403. /* BLX (register) 0100 0111 1xxx xxxx */
  404. DECODE_SIMULATE (0xff00, 0x4700, t16_simulate_bxblx),
  405. /* ADD pc, pc 0100 0100 1111 1111 */
  406. DECODE_REJECT (0xffff, 0x44ff),
  407. /* ADD (register) 0100 0100 xxxx xxxx */
  408. /* CMP (register) 0100 0101 xxxx xxxx */
  409. /* MOV (register) 0100 0110 xxxx xxxx */
  410. DECODE_CUSTOM (0xfc00, 0x4400, t16_decode_hiregs),
  411. /*
  412. * Load from Literal Pool
  413. * LDR (literal) 0100 1xxx xxxx xxxx
  414. */
  415. DECODE_SIMULATE (0xf800, 0x4800, t16_simulate_ldr_literal),
  416. /*
  417. * 16-bit Thumb Load/store instructions
  418. * 0101 xxxx xxxx xxxx
  419. * 011x xxxx xxxx xxxx
  420. * 100x xxxx xxxx xxxx
  421. */
  422. /* STR (register) 0101 000x xxxx xxxx */
  423. /* STRH (register) 0101 001x xxxx xxxx */
  424. /* STRB (register) 0101 010x xxxx xxxx */
  425. /* LDRSB (register) 0101 011x xxxx xxxx */
  426. /* LDR (register) 0101 100x xxxx xxxx */
  427. /* LDRH (register) 0101 101x xxxx xxxx */
  428. /* LDRB (register) 0101 110x xxxx xxxx */
  429. /* LDRSH (register) 0101 111x xxxx xxxx */
  430. /* STR (immediate, Thumb) 0110 0xxx xxxx xxxx */
  431. /* LDR (immediate, Thumb) 0110 1xxx xxxx xxxx */
  432. /* STRB (immediate, Thumb) 0111 0xxx xxxx xxxx */
  433. /* LDRB (immediate, Thumb) 0111 1xxx xxxx xxxx */
  434. DECODE_EMULATE (0xc000, 0x4000, t16_emulate_loregs_rwflags),
  435. /* STRH (immediate, Thumb) 1000 0xxx xxxx xxxx */
  436. /* LDRH (immediate, Thumb) 1000 1xxx xxxx xxxx */
  437. DECODE_EMULATE (0xf000, 0x8000, t16_emulate_loregs_rwflags),
  438. /* STR (immediate, Thumb) 1001 0xxx xxxx xxxx */
  439. /* LDR (immediate, Thumb) 1001 1xxx xxxx xxxx */
  440. DECODE_SIMULATE (0xf000, 0x9000, t16_simulate_ldrstr_sp_relative),
  441. /*
  442. * Generate PC-/SP-relative address
  443. * ADR (literal) 1010 0xxx xxxx xxxx
  444. * ADD (SP plus immediate) 1010 1xxx xxxx xxxx
  445. */
  446. DECODE_SIMULATE (0xf000, 0xa000, t16_simulate_reladr),
  447. /*
  448. * Miscellaneous 16-bit instructions
  449. * 1011 xxxx xxxx xxxx
  450. */
  451. DECODE_TABLE (0xf000, 0xb000, t16_table_1011),
  452. /* STM 1100 0xxx xxxx xxxx */
  453. /* LDM 1100 1xxx xxxx xxxx */
  454. DECODE_EMULATE (0xf000, 0xc000, t16_emulate_loregs_rwflags),
  455. /*
  456. * Conditional branch, and Supervisor Call
  457. */
  458. /* Permanently UNDEFINED 1101 1110 xxxx xxxx */
  459. /* SVC 1101 1111 xxxx xxxx */
  460. DECODE_REJECT (0xfe00, 0xde00),
  461. /* Conditional branch 1101 xxxx xxxx xxxx */
  462. DECODE_CUSTOM (0xf000, 0xd000, t16_decode_cond_branch),
  463. /*
  464. * Unconditional branch
  465. * B 1110 0xxx xxxx xxxx
  466. */
  467. DECODE_SIMULATE (0xf800, 0xe000, t16_simulate_branch),
  468. DECODE_END
  469. };
  470. static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
  471. {
  472. if (unlikely(in_it_block(cpsr)))
  473. return kprobe_condition_checks[current_cond(cpsr)](cpsr);
  474. return true;
  475. }
  476. static void __kprobes thumb16_singlestep(struct kprobe *p, struct pt_regs *regs)
  477. {
  478. regs->ARM_pc += 2;
  479. p->ainsn.insn_handler(p, regs);
  480. regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
  481. }
  482. static void __kprobes thumb32_singlestep(struct kprobe *p, struct pt_regs *regs)
  483. {
  484. regs->ARM_pc += 4;
  485. p->ainsn.insn_handler(p, regs);
  486. regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
  487. }
  488. enum kprobe_insn __kprobes
  489. thumb16_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  490. {
  491. asi->insn_singlestep = thumb16_singlestep;
  492. asi->insn_check_cc = thumb_check_cc;
  493. return kprobe_decode_insn(insn, asi, kprobe_decode_thumb16_table, true);
  494. }
  495. enum kprobe_insn __kprobes
  496. thumb32_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
  497. {
  498. asi->insn_singlestep = thumb32_singlestep;
  499. asi->insn_check_cc = thumb_check_cc;
  500. return kprobe_decode_insn(insn, asi, kprobe_decode_thumb32_table, true);
  501. }