perf_event_p4.c 15 KB

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  1. /*
  2. * Netburst Perfomance Events (P4, old Xeon)
  3. *
  4. * Copyright (C) 2010 Parallels, Inc., Cyrill Gorcunov <gorcunov@openvz.org>
  5. * Copyright (C) 2010 Intel Corporation, Lin Ming <ming.m.lin@intel.com>
  6. *
  7. * For licencing details see kernel-base/COPYING
  8. */
  9. #ifdef CONFIG_CPU_SUP_INTEL
  10. #include <asm/perf_event_p4.h>
  11. /*
  12. * array indices: 0,1 - HT threads, used with HT enabled cpu
  13. */
  14. struct p4_event_template {
  15. u32 opcode; /* ESCR event + CCCR selector */
  16. u64 config; /* packed predefined bits */
  17. int dep; /* upstream dependency event index */
  18. int key; /* index into p4_templates */
  19. unsigned int emask; /* ESCR EventMask */
  20. unsigned int escr_msr[2]; /* ESCR MSR for this event */
  21. unsigned int cntr[2]; /* counter index (offset) */
  22. };
  23. struct p4_pmu_res {
  24. /* maps hw_conf::idx into template for ESCR sake */
  25. struct p4_event_template *tpl[ARCH_P4_MAX_CCCR];
  26. };
  27. static DEFINE_PER_CPU(struct p4_pmu_res, p4_pmu_config);
  28. /*
  29. * WARN: CCCR1 doesn't have a working enable bit so try to not
  30. * use it if possible
  31. *
  32. * Also as only we start to support raw events we will need to
  33. * append _all_ P4_EVENT_PACK'ed events here
  34. */
  35. struct p4_event_template p4_templates[] = {
  36. [0] = {
  37. .opcode = P4_GLOBAL_POWER_EVENTS,
  38. .config = 0,
  39. .dep = -1,
  40. .key = 0,
  41. .emask =
  42. P4_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING),
  43. .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
  44. .cntr = { 0, 2 },
  45. },
  46. [1] = {
  47. .opcode = P4_INSTR_RETIRED,
  48. .config = 0,
  49. .dep = -1, /* needs front-end tagging */
  50. .key = 1,
  51. .emask =
  52. P4_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG) |
  53. P4_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG),
  54. .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
  55. .cntr = { 12, 14 },
  56. },
  57. [2] = {
  58. .opcode = P4_BSQ_CACHE_REFERENCE,
  59. .config = 0,
  60. .dep = -1,
  61. .key = 2,
  62. .emask =
  63. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS) |
  64. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE) |
  65. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM) |
  66. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS) |
  67. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE) |
  68. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM),
  69. .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
  70. .cntr = { 0, 2 },
  71. },
  72. [3] = {
  73. .opcode = P4_BSQ_CACHE_REFERENCE,
  74. .config = 0,
  75. .dep = -1,
  76. .key = 3,
  77. .emask =
  78. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS) |
  79. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS) |
  80. P4_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS),
  81. .escr_msr = { MSR_P4_BSU_ESCR0, MSR_P4_BSU_ESCR1 },
  82. .cntr = { 0, 3 },
  83. },
  84. [4] = {
  85. .opcode = P4_RETIRED_BRANCH_TYPE,
  86. .config = 0,
  87. .dep = -1,
  88. .key = 4,
  89. .emask =
  90. P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL) |
  91. P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL) |
  92. P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN) |
  93. P4_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT),
  94. .escr_msr = { MSR_P4_TBPU_ESCR0, MSR_P4_TBPU_ESCR1 },
  95. .cntr = { 4, 6 },
  96. },
  97. [5] = {
  98. .opcode = P4_MISPRED_BRANCH_RETIRED,
  99. .config = 0,
  100. .dep = -1,
  101. .key = 5,
  102. .emask =
  103. P4_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS),
  104. .escr_msr = { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
  105. .cntr = { 12, 14 },
  106. },
  107. [6] = {
  108. .opcode = P4_FSB_DATA_ACTIVITY,
  109. .config = p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
  110. .dep = -1,
  111. .key = 6,
  112. .emask =
  113. P4_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV) |
  114. P4_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN),
  115. .escr_msr = { MSR_P4_FSB_ESCR0, MSR_P4_FSB_ESCR1 },
  116. .cntr = { 0, 2 },
  117. },
  118. [7] = {
  119. .opcode = P4_UOP_TYPE,
  120. .config = 0,
  121. .dep = -1,
  122. .key = 7,
  123. .emask =
  124. P4_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS) |
  125. P4_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES),
  126. .escr_msr = { MSR_P4_RAT_ESCR0, MSR_P4_RAT_ESCR1 },
  127. .cntr = { 16, 17 },
  128. },
  129. };
  130. static u64 p4_pmu_event_map(int hw_event)
  131. {
  132. struct p4_event_template *tpl;
  133. u64 config;
  134. if (hw_event > ARRAY_SIZE(p4_templates)) {
  135. printk_once(KERN_ERR "PMU: Incorrect event index\n");
  136. return 0;
  137. }
  138. tpl = &p4_templates[hw_event];
  139. /*
  140. * fill config up according to
  141. * a predefined event template
  142. */
  143. config = tpl->config;
  144. config |= p4_config_pack_escr(P4_EVENT_UNPACK_EVENT(tpl->opcode) << P4_EVNTSEL_EVENT_SHIFT);
  145. config |= p4_config_pack_escr(tpl->emask << P4_EVNTSEL_EVENTMASK_SHIFT);
  146. config |= p4_config_pack_cccr(P4_EVENT_UNPACK_SELECTOR(tpl->opcode) << P4_CCCR_ESCR_SELECT_SHIFT);
  147. config |= p4_config_pack_cccr(hw_event & P4_CCCR_RESERVED);
  148. /* on HT machine we need a special bit */
  149. if (p4_ht_active() && p4_ht_thread(raw_smp_processor_id()))
  150. config = p4_set_ht_bit(config);
  151. return config;
  152. }
  153. /*
  154. * Note that we still have 5 events (from global events SDM list)
  155. * intersected in opcode+emask bits so we will need another
  156. * scheme there do distinguish templates.
  157. */
  158. static inline int p4_pmu_emask_match(unsigned int dst, unsigned int src)
  159. {
  160. return dst & src;
  161. }
  162. static struct p4_event_template *p4_pmu_template_lookup(u64 config)
  163. {
  164. int key = p4_config_unpack_key(config);
  165. if (key < ARRAY_SIZE(p4_templates))
  166. return &p4_templates[key];
  167. else
  168. return NULL;
  169. }
  170. /*
  171. * We don't control raw events so it's up to the caller
  172. * to pass sane values (and we don't count the thread number
  173. * on HT machine but allow HT-compatible specifics to be
  174. * passed on)
  175. */
  176. static u64 p4_pmu_raw_event(u64 hw_event)
  177. {
  178. return hw_event &
  179. (p4_config_pack_escr(P4_EVNTSEL_MASK_HT) |
  180. p4_config_pack_cccr(P4_CCCR_MASK_HT));
  181. }
  182. static int p4_hw_config(struct perf_event_attr *attr, struct hw_perf_event *hwc)
  183. {
  184. int cpu = raw_smp_processor_id();
  185. /*
  186. * the reason we use cpu that early is that: if we get scheduled
  187. * first time on the same cpu -- we will not need swap thread
  188. * specific flags in config (and will save some cpu cycles)
  189. */
  190. /* CCCR by default */
  191. hwc->config = p4_config_pack_cccr(p4_default_cccr_conf(cpu));
  192. /* Count user and OS events unless not requested to */
  193. hwc->config |= p4_config_pack_escr(p4_default_escr_conf(cpu, attr->exclude_kernel,
  194. attr->exclude_user));
  195. return 0;
  196. }
  197. static inline void p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
  198. {
  199. unsigned long dummy;
  200. rdmsrl(hwc->config_base + hwc->idx, dummy);
  201. if (dummy & P4_CCCR_OVF) {
  202. (void)checking_wrmsrl(hwc->config_base + hwc->idx,
  203. ((u64)dummy) & ~P4_CCCR_OVF);
  204. }
  205. }
  206. static inline void p4_pmu_disable_event(struct perf_event *event)
  207. {
  208. struct hw_perf_event *hwc = &event->hw;
  209. /*
  210. * If event gets disabled while counter is in overflowed
  211. * state we need to clear P4_CCCR_OVF, otherwise interrupt get
  212. * asserted again and again
  213. */
  214. (void)checking_wrmsrl(hwc->config_base + hwc->idx,
  215. (u64)(p4_config_unpack_cccr(hwc->config)) &
  216. ~P4_CCCR_ENABLE & ~P4_CCCR_OVF);
  217. }
  218. static void p4_pmu_disable_all(void)
  219. {
  220. struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
  221. int idx;
  222. for (idx = 0; idx < x86_pmu.num_events; idx++) {
  223. struct perf_event *event = cpuc->events[idx];
  224. if (!test_bit(idx, cpuc->active_mask))
  225. continue;
  226. p4_pmu_disable_event(event);
  227. }
  228. }
  229. static void p4_pmu_enable_event(struct perf_event *event)
  230. {
  231. struct hw_perf_event *hwc = &event->hw;
  232. int thread = p4_ht_config_thread(hwc->config);
  233. u64 escr_conf = p4_config_unpack_escr(p4_clear_ht_bit(hwc->config));
  234. u64 escr_base;
  235. struct p4_event_template *tpl;
  236. struct p4_pmu_res *c;
  237. /*
  238. * some preparation work from per-cpu private fields
  239. * since we need to find out which ESCR to use
  240. */
  241. c = &__get_cpu_var(p4_pmu_config);
  242. tpl = c->tpl[hwc->idx];
  243. if (!tpl) {
  244. pr_crit("%s: Wrong index: %d\n", __func__, hwc->idx);
  245. return;
  246. }
  247. escr_base = (u64)tpl->escr_msr[thread];
  248. /*
  249. * - we dont support cascaded counters yet
  250. * - and counter 1 is broken (erratum)
  251. */
  252. WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
  253. WARN_ON_ONCE(hwc->idx == 1);
  254. (void)checking_wrmsrl(escr_base, escr_conf);
  255. (void)checking_wrmsrl(hwc->config_base + hwc->idx,
  256. (u64)(p4_config_unpack_cccr(hwc->config)) | P4_CCCR_ENABLE);
  257. }
  258. static void p4_pmu_enable_all(void)
  259. {
  260. struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
  261. int idx;
  262. for (idx = 0; idx < x86_pmu.num_events; idx++) {
  263. struct perf_event *event = cpuc->events[idx];
  264. if (!test_bit(idx, cpuc->active_mask))
  265. continue;
  266. p4_pmu_enable_event(event);
  267. }
  268. }
  269. static int p4_pmu_handle_irq(struct pt_regs *regs)
  270. {
  271. struct perf_sample_data data;
  272. struct cpu_hw_events *cpuc;
  273. struct perf_event *event;
  274. struct hw_perf_event *hwc;
  275. int idx, handled = 0;
  276. u64 val;
  277. data.addr = 0;
  278. data.raw = NULL;
  279. cpuc = &__get_cpu_var(cpu_hw_events);
  280. for (idx = 0; idx < x86_pmu.num_events; idx++) {
  281. if (!test_bit(idx, cpuc->active_mask))
  282. continue;
  283. event = cpuc->events[idx];
  284. hwc = &event->hw;
  285. WARN_ON_ONCE(hwc->idx != idx);
  286. /*
  287. * FIXME: Redundant call, actually not needed
  288. * but just to check if we're screwed
  289. */
  290. p4_pmu_clear_cccr_ovf(hwc);
  291. val = x86_perf_event_update(event);
  292. if (val & (1ULL << (x86_pmu.event_bits - 1)))
  293. continue;
  294. /*
  295. * event overflow
  296. */
  297. handled = 1;
  298. data.period = event->hw.last_period;
  299. if (!x86_perf_event_set_period(event))
  300. continue;
  301. if (perf_event_overflow(event, 1, &data, regs))
  302. p4_pmu_disable_event(event);
  303. }
  304. if (handled) {
  305. /* p4 quirk: unmask it again */
  306. apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
  307. inc_irq_stat(apic_perf_irqs);
  308. }
  309. return handled;
  310. }
  311. /*
  312. * swap thread specific fields according to a thread
  313. * we are going to run on
  314. */
  315. static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
  316. {
  317. u32 escr, cccr;
  318. /*
  319. * we either lucky and continue on same cpu or no HT support
  320. */
  321. if (!p4_should_swap_ts(hwc->config, cpu))
  322. return;
  323. /*
  324. * the event is migrated from an another logical
  325. * cpu, so we need to swap thread specific flags
  326. */
  327. escr = p4_config_unpack_escr(hwc->config);
  328. cccr = p4_config_unpack_cccr(hwc->config);
  329. if (p4_ht_thread(cpu)) {
  330. cccr &= ~P4_CCCR_OVF_PMI_T0;
  331. cccr |= P4_CCCR_OVF_PMI_T1;
  332. if (escr & P4_EVNTSEL_T0_OS) {
  333. escr &= ~P4_EVNTSEL_T0_OS;
  334. escr |= P4_EVNTSEL_T1_OS;
  335. }
  336. if (escr & P4_EVNTSEL_T0_USR) {
  337. escr &= ~P4_EVNTSEL_T0_USR;
  338. escr |= P4_EVNTSEL_T1_USR;
  339. }
  340. hwc->config = p4_config_pack_escr(escr);
  341. hwc->config |= p4_config_pack_cccr(cccr);
  342. hwc->config |= P4_CONFIG_HT;
  343. } else {
  344. cccr &= ~P4_CCCR_OVF_PMI_T1;
  345. cccr |= P4_CCCR_OVF_PMI_T0;
  346. if (escr & P4_EVNTSEL_T1_OS) {
  347. escr &= ~P4_EVNTSEL_T1_OS;
  348. escr |= P4_EVNTSEL_T0_OS;
  349. }
  350. if (escr & P4_EVNTSEL_T1_USR) {
  351. escr &= ~P4_EVNTSEL_T1_USR;
  352. escr |= P4_EVNTSEL_T0_USR;
  353. }
  354. hwc->config = p4_config_pack_escr(escr);
  355. hwc->config |= p4_config_pack_cccr(cccr);
  356. hwc->config &= ~P4_CONFIG_HT;
  357. }
  358. }
  359. /* ESCRs are not sequential in memory so we need a map */
  360. static unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {
  361. MSR_P4_ALF_ESCR0, /* 0 */
  362. MSR_P4_ALF_ESCR1, /* 1 */
  363. MSR_P4_BPU_ESCR0, /* 2 */
  364. MSR_P4_BPU_ESCR1, /* 3 */
  365. MSR_P4_BSU_ESCR0, /* 4 */
  366. MSR_P4_BSU_ESCR1, /* 5 */
  367. MSR_P4_CRU_ESCR0, /* 6 */
  368. MSR_P4_CRU_ESCR1, /* 7 */
  369. MSR_P4_CRU_ESCR2, /* 8 */
  370. MSR_P4_CRU_ESCR3, /* 9 */
  371. MSR_P4_CRU_ESCR4, /* 10 */
  372. MSR_P4_CRU_ESCR5, /* 11 */
  373. MSR_P4_DAC_ESCR0, /* 12 */
  374. MSR_P4_DAC_ESCR1, /* 13 */
  375. MSR_P4_FIRM_ESCR0, /* 14 */
  376. MSR_P4_FIRM_ESCR1, /* 15 */
  377. MSR_P4_FLAME_ESCR0, /* 16 */
  378. MSR_P4_FLAME_ESCR1, /* 17 */
  379. MSR_P4_FSB_ESCR0, /* 18 */
  380. MSR_P4_FSB_ESCR1, /* 19 */
  381. MSR_P4_IQ_ESCR0, /* 20 */
  382. MSR_P4_IQ_ESCR1, /* 21 */
  383. MSR_P4_IS_ESCR0, /* 22 */
  384. MSR_P4_IS_ESCR1, /* 23 */
  385. MSR_P4_ITLB_ESCR0, /* 24 */
  386. MSR_P4_ITLB_ESCR1, /* 25 */
  387. MSR_P4_IX_ESCR0, /* 26 */
  388. MSR_P4_IX_ESCR1, /* 27 */
  389. MSR_P4_MOB_ESCR0, /* 28 */
  390. MSR_P4_MOB_ESCR1, /* 29 */
  391. MSR_P4_MS_ESCR0, /* 30 */
  392. MSR_P4_MS_ESCR1, /* 31 */
  393. MSR_P4_PMH_ESCR0, /* 32 */
  394. MSR_P4_PMH_ESCR1, /* 33 */
  395. MSR_P4_RAT_ESCR0, /* 34 */
  396. MSR_P4_RAT_ESCR1, /* 35 */
  397. MSR_P4_SAAT_ESCR0, /* 36 */
  398. MSR_P4_SAAT_ESCR1, /* 37 */
  399. MSR_P4_SSU_ESCR0, /* 38 */
  400. MSR_P4_SSU_ESCR1, /* 39 */
  401. MSR_P4_TBPU_ESCR0, /* 40 */
  402. MSR_P4_TBPU_ESCR1, /* 41 */
  403. MSR_P4_TC_ESCR0, /* 42 */
  404. MSR_P4_TC_ESCR1, /* 43 */
  405. MSR_P4_U2L_ESCR0, /* 44 */
  406. MSR_P4_U2L_ESCR1, /* 45 */
  407. };
  408. static int p4_get_escr_idx(unsigned int addr)
  409. {
  410. unsigned int i;
  411. for (i = 0; i < ARRAY_SIZE(p4_escr_map); i++) {
  412. if (addr == p4_escr_map[i])
  413. return i;
  414. }
  415. return -1;
  416. }
  417. static int p4_pmu_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
  418. {
  419. unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  420. unsigned long escr_mask[BITS_TO_LONGS(ARCH_P4_TOTAL_ESCR)];
  421. struct hw_perf_event *hwc;
  422. struct p4_event_template *tpl;
  423. struct p4_pmu_res *c;
  424. int cpu = raw_smp_processor_id();
  425. int escr_idx, thread, i, num;
  426. bitmap_zero(used_mask, X86_PMC_IDX_MAX);
  427. bitmap_zero(escr_mask, ARCH_P4_TOTAL_ESCR);
  428. c = &__get_cpu_var(p4_pmu_config);
  429. /*
  430. * Firstly find out which resource events are going
  431. * to use, if ESCR+CCCR tuple is already borrowed
  432. * then get out of here
  433. */
  434. for (i = 0, num = n; i < n; i++, num--) {
  435. hwc = &cpuc->event_list[i]->hw;
  436. tpl = p4_pmu_template_lookup(hwc->config);
  437. if (!tpl)
  438. goto done;
  439. thread = p4_ht_thread(cpu);
  440. escr_idx = p4_get_escr_idx(tpl->escr_msr[thread]);
  441. if (escr_idx == -1)
  442. goto done;
  443. /* already allocated and remains on the same cpu */
  444. if (hwc->idx != -1 && !p4_should_swap_ts(hwc->config, cpu)) {
  445. if (assign)
  446. assign[i] = hwc->idx;
  447. /* upstream dependent event */
  448. if (unlikely(tpl->dep != -1))
  449. printk_once(KERN_WARNING "PMU: Dep events are "
  450. "not implemented yet\n");
  451. goto reserve;
  452. }
  453. /* it may be already borrowed */
  454. if (test_bit(tpl->cntr[thread], used_mask) ||
  455. test_bit(escr_idx, escr_mask))
  456. goto done;
  457. /*
  458. * ESCR+CCCR+COUNTERs are available to use lets swap
  459. * thread specific bits, push assigned bits
  460. * back and save template into per-cpu
  461. * area (which will allow us to find out the ESCR
  462. * to be used at moment of "enable event via real MSR")
  463. */
  464. p4_pmu_swap_config_ts(hwc, cpu);
  465. if (assign) {
  466. assign[i] = tpl->cntr[thread];
  467. c->tpl[assign[i]] = tpl;
  468. }
  469. reserve:
  470. set_bit(tpl->cntr[thread], used_mask);
  471. set_bit(escr_idx, escr_mask);
  472. }
  473. done:
  474. return num ? -ENOSPC : 0;
  475. }
  476. static __initconst struct x86_pmu p4_pmu = {
  477. .name = "Netburst P4/Xeon",
  478. .handle_irq = p4_pmu_handle_irq,
  479. .disable_all = p4_pmu_disable_all,
  480. .enable_all = p4_pmu_enable_all,
  481. .enable = p4_pmu_enable_event,
  482. .disable = p4_pmu_disable_event,
  483. .eventsel = MSR_P4_BPU_CCCR0,
  484. .perfctr = MSR_P4_BPU_PERFCTR0,
  485. .event_map = p4_pmu_event_map,
  486. .raw_event = p4_pmu_raw_event,
  487. .max_events = ARRAY_SIZE(p4_templates),
  488. .get_event_constraints = x86_get_event_constraints,
  489. /*
  490. * IF HT disabled we may need to use all
  491. * ARCH_P4_MAX_CCCR counters simulaneously
  492. * though leave it restricted at moment assuming
  493. * HT is on
  494. */
  495. .num_events = ARCH_P4_MAX_CCCR,
  496. .apic = 1,
  497. .event_bits = 40,
  498. .event_mask = (1ULL << 40) - 1,
  499. .max_period = (1ULL << 39) - 1,
  500. .hw_config = p4_hw_config,
  501. .schedule_events = p4_pmu_schedule_events,
  502. };
  503. static __init int p4_pmu_init(void)
  504. {
  505. unsigned int low, high;
  506. /* If we get stripped -- indexig fails */
  507. BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC);
  508. rdmsr(MSR_IA32_MISC_ENABLE, low, high);
  509. if (!(low & (1 << 7))) {
  510. pr_cont("unsupported Netburst CPU model %d ",
  511. boot_cpu_data.x86_model);
  512. return -ENODEV;
  513. }
  514. pr_cont("Netburst events, ");
  515. x86_pmu = p4_pmu;
  516. return 0;
  517. }
  518. #endif /* CONFIG_CPU_SUP_INTEL */