iwl-rx.c 39 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. unsigned long flags;
  126. u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
  127. u32 reg;
  128. spin_lock_irqsave(&q->lock, flags);
  129. if (q->need_update == 0)
  130. goto exit_unlock;
  131. /* If power-saving is in use, make sure device is awake */
  132. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  133. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  134. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  135. IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n",
  136. reg);
  137. iwl_set_bit(priv, CSR_GP_CNTRL,
  138. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  139. goto exit_unlock;
  140. }
  141. q->write_actual = (q->write & ~0x7);
  142. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  143. /* Else device is assumed to be awake */
  144. } else {
  145. /* Device expects a multiple of 8 */
  146. q->write_actual = (q->write & ~0x7);
  147. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  148. }
  149. q->need_update = 0;
  150. exit_unlock:
  151. spin_unlock_irqrestore(&q->lock, flags);
  152. }
  153. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  154. /**
  155. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  156. */
  157. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  158. dma_addr_t dma_addr)
  159. {
  160. return cpu_to_le32((u32)(dma_addr >> 8));
  161. }
  162. /**
  163. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  164. *
  165. * If there are slots in the RX queue that need to be restocked,
  166. * and we have free pre-allocated buffers, fill the ranks as much
  167. * as we can, pulling from rx_free.
  168. *
  169. * This moves the 'write' index forward to catch up with 'processed', and
  170. * also updates the memory address in the firmware to reference the new
  171. * target buffer.
  172. */
  173. void iwl_rx_queue_restock(struct iwl_priv *priv)
  174. {
  175. struct iwl_rx_queue *rxq = &priv->rxq;
  176. struct list_head *element;
  177. struct iwl_rx_mem_buffer *rxb;
  178. unsigned long flags;
  179. int write;
  180. spin_lock_irqsave(&rxq->lock, flags);
  181. write = rxq->write & ~0x7;
  182. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  183. /* Get next free Rx buffer, remove from free list */
  184. element = rxq->rx_free.next;
  185. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  186. list_del(element);
  187. /* Point to Rx buffer via next RBD in circular buffer */
  188. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma);
  189. rxq->queue[rxq->write] = rxb;
  190. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  191. rxq->free_count--;
  192. }
  193. spin_unlock_irqrestore(&rxq->lock, flags);
  194. /* If the pre-allocated buffer pool is dropping low, schedule to
  195. * refill it */
  196. if (rxq->free_count <= RX_LOW_WATERMARK)
  197. queue_work(priv->workqueue, &priv->rx_replenish);
  198. /* If we've added more space for the firmware to place data, tell it.
  199. * Increment device's write pointer in multiples of 8. */
  200. if (rxq->write_actual != (rxq->write & ~0x7)) {
  201. spin_lock_irqsave(&rxq->lock, flags);
  202. rxq->need_update = 1;
  203. spin_unlock_irqrestore(&rxq->lock, flags);
  204. iwl_rx_queue_update_write_ptr(priv, rxq);
  205. }
  206. }
  207. EXPORT_SYMBOL(iwl_rx_queue_restock);
  208. /**
  209. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  210. *
  211. * When moving to rx_free an SKB is allocated for the slot.
  212. *
  213. * Also restock the Rx queue via iwl_rx_queue_restock.
  214. * This is called as a scheduled work item (except for during initialization)
  215. */
  216. void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  217. {
  218. struct iwl_rx_queue *rxq = &priv->rxq;
  219. struct list_head *element;
  220. struct iwl_rx_mem_buffer *rxb;
  221. struct page *page;
  222. unsigned long flags;
  223. gfp_t gfp_mask = priority;
  224. while (1) {
  225. spin_lock_irqsave(&rxq->lock, flags);
  226. if (list_empty(&rxq->rx_used)) {
  227. spin_unlock_irqrestore(&rxq->lock, flags);
  228. return;
  229. }
  230. spin_unlock_irqrestore(&rxq->lock, flags);
  231. if (rxq->free_count > RX_LOW_WATERMARK)
  232. gfp_mask |= __GFP_NOWARN;
  233. if (priv->hw_params.rx_page_order > 0)
  234. gfp_mask |= __GFP_COMP;
  235. /* Alloc a new receive buffer */
  236. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  237. if (!page) {
  238. if (net_ratelimit())
  239. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  240. "order: %d\n",
  241. priv->hw_params.rx_page_order);
  242. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  243. net_ratelimit())
  244. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  245. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  246. rxq->free_count);
  247. /* We don't reschedule replenish work here -- we will
  248. * call the restock method and if it still needs
  249. * more buffers it will schedule replenish */
  250. return;
  251. }
  252. spin_lock_irqsave(&rxq->lock, flags);
  253. if (list_empty(&rxq->rx_used)) {
  254. spin_unlock_irqrestore(&rxq->lock, flags);
  255. __free_pages(page, priv->hw_params.rx_page_order);
  256. return;
  257. }
  258. element = rxq->rx_used.next;
  259. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  260. list_del(element);
  261. spin_unlock_irqrestore(&rxq->lock, flags);
  262. rxb->page = page;
  263. /* Get physical address of the RB */
  264. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  265. PAGE_SIZE << priv->hw_params.rx_page_order,
  266. PCI_DMA_FROMDEVICE);
  267. /* dma address must be no more than 36 bits */
  268. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  269. /* and also 256 byte aligned! */
  270. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  271. spin_lock_irqsave(&rxq->lock, flags);
  272. list_add_tail(&rxb->list, &rxq->rx_free);
  273. rxq->free_count++;
  274. priv->alloc_rxb_page++;
  275. spin_unlock_irqrestore(&rxq->lock, flags);
  276. }
  277. }
  278. void iwl_rx_replenish(struct iwl_priv *priv)
  279. {
  280. unsigned long flags;
  281. iwl_rx_allocate(priv, GFP_KERNEL);
  282. spin_lock_irqsave(&priv->lock, flags);
  283. iwl_rx_queue_restock(priv);
  284. spin_unlock_irqrestore(&priv->lock, flags);
  285. }
  286. EXPORT_SYMBOL(iwl_rx_replenish);
  287. void iwl_rx_replenish_now(struct iwl_priv *priv)
  288. {
  289. iwl_rx_allocate(priv, GFP_ATOMIC);
  290. iwl_rx_queue_restock(priv);
  291. }
  292. EXPORT_SYMBOL(iwl_rx_replenish_now);
  293. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  294. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  295. * This free routine walks the list of POOL entries and if SKB is set to
  296. * non NULL it is unmapped and freed
  297. */
  298. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  299. {
  300. int i;
  301. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  302. if (rxq->pool[i].page != NULL) {
  303. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  304. PAGE_SIZE << priv->hw_params.rx_page_order,
  305. PCI_DMA_FROMDEVICE);
  306. __iwl_free_pages(priv, rxq->pool[i].page);
  307. rxq->pool[i].page = NULL;
  308. }
  309. }
  310. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  311. rxq->dma_addr);
  312. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  313. rxq->rb_stts, rxq->rb_stts_dma);
  314. rxq->bd = NULL;
  315. rxq->rb_stts = NULL;
  316. }
  317. EXPORT_SYMBOL(iwl_rx_queue_free);
  318. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  319. {
  320. struct iwl_rx_queue *rxq = &priv->rxq;
  321. struct device *dev = &priv->pci_dev->dev;
  322. int i;
  323. spin_lock_init(&rxq->lock);
  324. INIT_LIST_HEAD(&rxq->rx_free);
  325. INIT_LIST_HEAD(&rxq->rx_used);
  326. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  327. rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr,
  328. GFP_KERNEL);
  329. if (!rxq->bd)
  330. goto err_bd;
  331. rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct iwl_rb_status),
  332. &rxq->rb_stts_dma, GFP_KERNEL);
  333. if (!rxq->rb_stts)
  334. goto err_rb;
  335. /* Fill the rx_used queue with _all_ of the Rx buffers */
  336. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  337. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  338. /* Set us so that we have processed and used all buffers, but have
  339. * not restocked the Rx queue with fresh buffers */
  340. rxq->read = rxq->write = 0;
  341. rxq->write_actual = 0;
  342. rxq->free_count = 0;
  343. rxq->need_update = 0;
  344. return 0;
  345. err_rb:
  346. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  347. rxq->dma_addr);
  348. err_bd:
  349. return -ENOMEM;
  350. }
  351. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  352. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  353. {
  354. unsigned long flags;
  355. int i;
  356. spin_lock_irqsave(&rxq->lock, flags);
  357. INIT_LIST_HEAD(&rxq->rx_free);
  358. INIT_LIST_HEAD(&rxq->rx_used);
  359. /* Fill the rx_used queue with _all_ of the Rx buffers */
  360. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  361. /* In the reset function, these buffers may have been allocated
  362. * to an SKB, so we need to unmap and free potential storage */
  363. if (rxq->pool[i].page != NULL) {
  364. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  365. PAGE_SIZE << priv->hw_params.rx_page_order,
  366. PCI_DMA_FROMDEVICE);
  367. __iwl_free_pages(priv, rxq->pool[i].page);
  368. rxq->pool[i].page = NULL;
  369. }
  370. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  371. }
  372. /* Set us so that we have processed and used all buffers, but have
  373. * not restocked the Rx queue with fresh buffers */
  374. rxq->read = rxq->write = 0;
  375. rxq->write_actual = 0;
  376. rxq->free_count = 0;
  377. spin_unlock_irqrestore(&rxq->lock, flags);
  378. }
  379. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  380. {
  381. u32 rb_size;
  382. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  383. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  384. if (!priv->cfg->use_isr_legacy)
  385. rb_timeout = RX_RB_TIMEOUT;
  386. if (priv->cfg->mod_params->amsdu_size_8K)
  387. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  388. else
  389. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  390. /* Stop Rx DMA */
  391. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  392. /* Reset driver's Rx queue write index */
  393. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  394. /* Tell device where to find RBD circular buffer in DRAM */
  395. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  396. (u32)(rxq->dma_addr >> 8));
  397. /* Tell device where in DRAM to update its Rx status */
  398. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  399. rxq->rb_stts_dma >> 4);
  400. /* Enable Rx DMA
  401. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  402. * the credit mechanism in 5000 HW RX FIFO
  403. * Direct rx interrupts to hosts
  404. * Rx buffer size 4 or 8k
  405. * RB timeout 0x10
  406. * 256 RBDs
  407. */
  408. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  409. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  410. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  411. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  412. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  413. rb_size|
  414. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  415. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  416. /* Set interrupt coalescing timer to default (2048 usecs) */
  417. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  418. return 0;
  419. }
  420. int iwl_rxq_stop(struct iwl_priv *priv)
  421. {
  422. /* stop Rx DMA */
  423. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  424. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  425. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  426. return 0;
  427. }
  428. EXPORT_SYMBOL(iwl_rxq_stop);
  429. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  430. struct iwl_rx_mem_buffer *rxb)
  431. {
  432. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  433. struct iwl_missed_beacon_notif *missed_beacon;
  434. missed_beacon = &pkt->u.missed_beacon;
  435. if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
  436. priv->missed_beacon_threshold) {
  437. IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  438. le32_to_cpu(missed_beacon->consecutive_missed_beacons),
  439. le32_to_cpu(missed_beacon->total_missed_becons),
  440. le32_to_cpu(missed_beacon->num_recvd_beacons),
  441. le32_to_cpu(missed_beacon->num_expected_beacons));
  442. if (!test_bit(STATUS_SCANNING, &priv->status))
  443. iwl_init_sensitivity(priv);
  444. }
  445. }
  446. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  447. void iwl_rx_spectrum_measure_notif(struct iwl_priv *priv,
  448. struct iwl_rx_mem_buffer *rxb)
  449. {
  450. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  451. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  452. if (!report->state) {
  453. IWL_DEBUG_11H(priv,
  454. "Spectrum Measure Notification: Start\n");
  455. return;
  456. }
  457. memcpy(&priv->measure_report, report, sizeof(*report));
  458. priv->measurement_status |= MEASUREMENT_READY;
  459. }
  460. EXPORT_SYMBOL(iwl_rx_spectrum_measure_notif);
  461. /* Calculate noise level, based on measurements during network silence just
  462. * before arriving beacon. This measurement can be done only if we know
  463. * exactly when to expect beacons, therefore only when we're associated. */
  464. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  465. {
  466. struct statistics_rx_non_phy *rx_info
  467. = &(priv->statistics.rx.general);
  468. int num_active_rx = 0;
  469. int total_silence = 0;
  470. int bcn_silence_a =
  471. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  472. int bcn_silence_b =
  473. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  474. int bcn_silence_c =
  475. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  476. if (bcn_silence_a) {
  477. total_silence += bcn_silence_a;
  478. num_active_rx++;
  479. }
  480. if (bcn_silence_b) {
  481. total_silence += bcn_silence_b;
  482. num_active_rx++;
  483. }
  484. if (bcn_silence_c) {
  485. total_silence += bcn_silence_c;
  486. num_active_rx++;
  487. }
  488. /* Average among active antennas */
  489. if (num_active_rx)
  490. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  491. else
  492. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  493. IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
  494. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  495. priv->last_rx_noise);
  496. }
  497. #ifdef CONFIG_IWLWIFI_DEBUG
  498. /*
  499. * based on the assumption of all statistics counter are in DWORD
  500. * FIXME: This function is for debugging, do not deal with
  501. * the case of counters roll-over.
  502. */
  503. static void iwl_accumulative_statistics(struct iwl_priv *priv,
  504. __le32 *stats)
  505. {
  506. int i;
  507. __le32 *prev_stats;
  508. u32 *accum_stats;
  509. u32 *delta, *max_delta;
  510. prev_stats = (__le32 *)&priv->statistics;
  511. accum_stats = (u32 *)&priv->accum_statistics;
  512. delta = (u32 *)&priv->delta_statistics;
  513. max_delta = (u32 *)&priv->max_delta;
  514. for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics);
  515. i += sizeof(__le32), stats++, prev_stats++, delta++,
  516. max_delta++, accum_stats++) {
  517. if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
  518. *delta = (le32_to_cpu(*stats) -
  519. le32_to_cpu(*prev_stats));
  520. *accum_stats += *delta;
  521. if (*delta > *max_delta)
  522. *max_delta = *delta;
  523. }
  524. }
  525. /* reset accumulative statistics for "no-counter" type statistics */
  526. priv->accum_statistics.general.temperature =
  527. priv->statistics.general.temperature;
  528. priv->accum_statistics.general.temperature_m =
  529. priv->statistics.general.temperature_m;
  530. priv->accum_statistics.general.ttl_timestamp =
  531. priv->statistics.general.ttl_timestamp;
  532. priv->accum_statistics.tx.tx_power.ant_a =
  533. priv->statistics.tx.tx_power.ant_a;
  534. priv->accum_statistics.tx.tx_power.ant_b =
  535. priv->statistics.tx.tx_power.ant_b;
  536. priv->accum_statistics.tx.tx_power.ant_c =
  537. priv->statistics.tx.tx_power.ant_c;
  538. }
  539. #endif
  540. #define REG_RECALIB_PERIOD (60)
  541. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  542. #define ACK_CNT_RATIO (50)
  543. #define BA_TIMEOUT_CNT (5)
  544. #define BA_TIMEOUT_MAX (16)
  545. #define PLCP_MSG "plcp_err exceeded %u, %u, %u, %u, %u, %d, %u mSecs\n"
  546. void iwl_rx_statistics(struct iwl_priv *priv,
  547. struct iwl_rx_mem_buffer *rxb)
  548. {
  549. int change;
  550. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  551. int combined_plcp_delta;
  552. unsigned int plcp_msec;
  553. unsigned long plcp_received_jiffies;
  554. int actual_ack_cnt_delta;
  555. int expected_ack_cnt_delta;
  556. int ba_timeout_delta;
  557. IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
  558. (int)sizeof(priv->statistics),
  559. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  560. change = ((priv->statistics.general.temperature !=
  561. pkt->u.stats.general.temperature) ||
  562. ((priv->statistics.flag &
  563. STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
  564. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
  565. #ifdef CONFIG_IWLWIFI_DEBUG
  566. iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
  567. #endif
  568. actual_ack_cnt_delta = le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  569. le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
  570. expected_ack_cnt_delta = le32_to_cpu(
  571. pkt->u.stats.tx.expected_ack_cnt) -
  572. le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
  573. ba_timeout_delta = le32_to_cpu(
  574. pkt->u.stats.tx.agg.ba_timeout) -
  575. le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
  576. if ((priv->agg_tids_count > 0) &&
  577. (expected_ack_cnt_delta > 0) &&
  578. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) <
  579. ACK_CNT_RATIO) &&
  580. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  581. IWL_DEBUG_RADIO(priv,
  582. "actual_ack_cnt delta = %d, expected_ack_cnt = %d\n",
  583. actual_ack_cnt_delta, expected_ack_cnt_delta);
  584. #ifdef CONFIG_IWLWIFI_DEBUG
  585. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  586. priv->delta_statistics.tx.rx_detected_cnt);
  587. IWL_DEBUG_RADIO(priv,
  588. "ack_or_ba_timeout_collision delta = %d\n",
  589. priv->delta_statistics.tx.ack_or_ba_timeout_collision);
  590. #endif
  591. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  592. ba_timeout_delta);
  593. if ((actual_ack_cnt_delta == 0) &&
  594. (ba_timeout_delta >=
  595. BA_TIMEOUT_MAX)) {
  596. IWL_DEBUG_RADIO(priv,
  597. "call iwl_force_reset(IWL_FW_RESET)\n");
  598. iwl_force_reset(priv, IWL_FW_RESET);
  599. } else {
  600. IWL_DEBUG_RADIO(priv,
  601. "call iwl_force_reset(IWL_RF_RESET)\n");
  602. iwl_force_reset(priv, IWL_RF_RESET);
  603. }
  604. }
  605. /*
  606. * check for plcp_err and trigger radio reset if it exceeds
  607. * the plcp error threshold plcp_delta.
  608. */
  609. plcp_received_jiffies = jiffies;
  610. plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
  611. (long) priv->plcp_jiffies);
  612. priv->plcp_jiffies = plcp_received_jiffies;
  613. /*
  614. * check to make sure plcp_msec is not 0 to prevent division
  615. * by zero.
  616. */
  617. if (plcp_msec) {
  618. combined_plcp_delta =
  619. (le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err) -
  620. le32_to_cpu(priv->statistics.rx.ofdm.plcp_err)) +
  621. (le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err) -
  622. le32_to_cpu(priv->statistics.rx.ofdm_ht.plcp_err));
  623. if ((combined_plcp_delta > 0) &&
  624. ((combined_plcp_delta * 100) / plcp_msec) >
  625. priv->cfg->plcp_delta_threshold) {
  626. /*
  627. * if plcp_err exceed the threshold, the following
  628. * data is printed in csv format:
  629. * Text: plcp_err exceeded %d,
  630. * Received ofdm.plcp_err,
  631. * Current ofdm.plcp_err,
  632. * Received ofdm_ht.plcp_err,
  633. * Current ofdm_ht.plcp_err,
  634. * combined_plcp_delta,
  635. * plcp_msec
  636. */
  637. IWL_DEBUG_RADIO(priv, PLCP_MSG,
  638. priv->cfg->plcp_delta_threshold,
  639. le32_to_cpu(pkt->u.stats.rx.ofdm.plcp_err),
  640. le32_to_cpu(priv->statistics.rx.ofdm.plcp_err),
  641. le32_to_cpu(pkt->u.stats.rx.ofdm_ht.plcp_err),
  642. le32_to_cpu(
  643. priv->statistics.rx.ofdm_ht.plcp_err),
  644. combined_plcp_delta, plcp_msec);
  645. /*
  646. * Reset the RF radio due to the high plcp
  647. * error rate
  648. */
  649. iwl_force_reset(priv, IWL_RF_RESET);
  650. }
  651. }
  652. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  653. set_bit(STATUS_STATISTICS, &priv->status);
  654. /* Reschedule the statistics timer to occur in
  655. * REG_RECALIB_PERIOD seconds to ensure we get a
  656. * thermal update even if the uCode doesn't give
  657. * us one */
  658. mod_timer(&priv->statistics_periodic, jiffies +
  659. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  660. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  661. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  662. iwl_rx_calc_noise(priv);
  663. queue_work(priv->workqueue, &priv->run_time_calib_work);
  664. }
  665. if (priv->cfg->ops->lib->temp_ops.temperature && change)
  666. priv->cfg->ops->lib->temp_ops.temperature(priv);
  667. }
  668. EXPORT_SYMBOL(iwl_rx_statistics);
  669. void iwl_reply_statistics(struct iwl_priv *priv,
  670. struct iwl_rx_mem_buffer *rxb)
  671. {
  672. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  673. if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
  674. #ifdef CONFIG_IWLWIFI_DEBUG
  675. memset(&priv->accum_statistics, 0,
  676. sizeof(struct iwl_notif_statistics));
  677. memset(&priv->delta_statistics, 0,
  678. sizeof(struct iwl_notif_statistics));
  679. memset(&priv->max_delta, 0,
  680. sizeof(struct iwl_notif_statistics));
  681. #endif
  682. IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
  683. }
  684. iwl_rx_statistics(priv, rxb);
  685. }
  686. EXPORT_SYMBOL(iwl_reply_statistics);
  687. /* Calc max signal level (dBm) among 3 possible receivers */
  688. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  689. struct iwl_rx_phy_res *rx_resp)
  690. {
  691. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  692. }
  693. #ifdef CONFIG_IWLWIFI_DEBUG
  694. /**
  695. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  696. *
  697. * You may hack this function to show different aspects of received frames,
  698. * including selective frame dumps.
  699. * group100 parameter selects whether to show 1 out of 100 good data frames.
  700. * All beacon and probe response frames are printed.
  701. */
  702. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  703. struct iwl_rx_phy_res *phy_res, u16 length,
  704. struct ieee80211_hdr *header, int group100)
  705. {
  706. u32 to_us;
  707. u32 print_summary = 0;
  708. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  709. u32 hundred = 0;
  710. u32 dataframe = 0;
  711. __le16 fc;
  712. u16 seq_ctl;
  713. u16 channel;
  714. u16 phy_flags;
  715. u32 rate_n_flags;
  716. u32 tsf_low;
  717. int rssi;
  718. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  719. return;
  720. /* MAC header */
  721. fc = header->frame_control;
  722. seq_ctl = le16_to_cpu(header->seq_ctrl);
  723. /* metadata */
  724. channel = le16_to_cpu(phy_res->channel);
  725. phy_flags = le16_to_cpu(phy_res->phy_flags);
  726. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  727. /* signal statistics */
  728. rssi = iwl_calc_rssi(priv, phy_res);
  729. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  730. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  731. /* if data frame is to us and all is good,
  732. * (optionally) print summary for only 1 out of every 100 */
  733. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  734. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  735. dataframe = 1;
  736. if (!group100)
  737. print_summary = 1; /* print each frame */
  738. else if (priv->framecnt_to_us < 100) {
  739. priv->framecnt_to_us++;
  740. print_summary = 0;
  741. } else {
  742. priv->framecnt_to_us = 0;
  743. print_summary = 1;
  744. hundred = 1;
  745. }
  746. } else {
  747. /* print summary for all other frames */
  748. print_summary = 1;
  749. }
  750. if (print_summary) {
  751. char *title;
  752. int rate_idx;
  753. u32 bitrate;
  754. if (hundred)
  755. title = "100Frames";
  756. else if (ieee80211_has_retry(fc))
  757. title = "Retry";
  758. else if (ieee80211_is_assoc_resp(fc))
  759. title = "AscRsp";
  760. else if (ieee80211_is_reassoc_resp(fc))
  761. title = "RasRsp";
  762. else if (ieee80211_is_probe_resp(fc)) {
  763. title = "PrbRsp";
  764. print_dump = 1; /* dump frame contents */
  765. } else if (ieee80211_is_beacon(fc)) {
  766. title = "Beacon";
  767. print_dump = 1; /* dump frame contents */
  768. } else if (ieee80211_is_atim(fc))
  769. title = "ATIM";
  770. else if (ieee80211_is_auth(fc))
  771. title = "Auth";
  772. else if (ieee80211_is_deauth(fc))
  773. title = "DeAuth";
  774. else if (ieee80211_is_disassoc(fc))
  775. title = "DisAssoc";
  776. else
  777. title = "Frame";
  778. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  779. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  780. bitrate = 0;
  781. WARN_ON_ONCE(1);
  782. } else {
  783. bitrate = iwl_rates[rate_idx].ieee / 2;
  784. }
  785. /* print frame summary.
  786. * MAC addresses show just the last byte (for brevity),
  787. * but you can hack it to show more, if you'd like to. */
  788. if (dataframe)
  789. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  790. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  791. title, le16_to_cpu(fc), header->addr1[5],
  792. length, rssi, channel, bitrate);
  793. else {
  794. /* src/dst addresses assume managed mode */
  795. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  796. "len=%u, rssi=%d, tim=%lu usec, "
  797. "phy=0x%02x, chnl=%d\n",
  798. title, le16_to_cpu(fc), header->addr1[5],
  799. header->addr3[5], length, rssi,
  800. tsf_low - priv->scan_start_tsf,
  801. phy_flags, channel);
  802. }
  803. }
  804. if (print_dump)
  805. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  806. }
  807. #endif
  808. /*
  809. * returns non-zero if packet should be dropped
  810. */
  811. int iwl_set_decrypted_flag(struct iwl_priv *priv,
  812. struct ieee80211_hdr *hdr,
  813. u32 decrypt_res,
  814. struct ieee80211_rx_status *stats)
  815. {
  816. u16 fc = le16_to_cpu(hdr->frame_control);
  817. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  818. return 0;
  819. if (!(fc & IEEE80211_FCTL_PROTECTED))
  820. return 0;
  821. IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res);
  822. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  823. case RX_RES_STATUS_SEC_TYPE_TKIP:
  824. /* The uCode has got a bad phase 1 Key, pushes the packet.
  825. * Decryption will be done in SW. */
  826. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  827. RX_RES_STATUS_BAD_KEY_TTAK)
  828. break;
  829. case RX_RES_STATUS_SEC_TYPE_WEP:
  830. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  831. RX_RES_STATUS_BAD_ICV_MIC) {
  832. /* bad ICV, the packet is destroyed since the
  833. * decryption is inplace, drop it */
  834. IWL_DEBUG_RX(priv, "Packet destroyed\n");
  835. return -1;
  836. }
  837. case RX_RES_STATUS_SEC_TYPE_CCMP:
  838. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  839. RX_RES_STATUS_DECRYPT_OK) {
  840. IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n");
  841. stats->flag |= RX_FLAG_DECRYPTED;
  842. }
  843. break;
  844. default:
  845. break;
  846. }
  847. return 0;
  848. }
  849. EXPORT_SYMBOL(iwl_set_decrypted_flag);
  850. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  851. {
  852. u32 decrypt_out = 0;
  853. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  854. RX_RES_STATUS_STATION_FOUND)
  855. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  856. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  857. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  858. /* packet was not encrypted */
  859. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  860. RX_RES_STATUS_SEC_TYPE_NONE)
  861. return decrypt_out;
  862. /* packet was encrypted with unknown alg */
  863. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  864. RX_RES_STATUS_SEC_TYPE_ERR)
  865. return decrypt_out;
  866. /* decryption was not done in HW */
  867. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  868. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  869. return decrypt_out;
  870. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  871. case RX_RES_STATUS_SEC_TYPE_CCMP:
  872. /* alg is CCM: check MIC only */
  873. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  874. /* Bad MIC */
  875. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  876. else
  877. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  878. break;
  879. case RX_RES_STATUS_SEC_TYPE_TKIP:
  880. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  881. /* Bad TTAK */
  882. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  883. break;
  884. }
  885. /* fall through if TTAK OK */
  886. default:
  887. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  888. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  889. else
  890. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  891. break;
  892. };
  893. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  894. decrypt_in, decrypt_out);
  895. return decrypt_out;
  896. }
  897. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  898. struct ieee80211_hdr *hdr,
  899. u16 len,
  900. u32 ampdu_status,
  901. struct iwl_rx_mem_buffer *rxb,
  902. struct ieee80211_rx_status *stats)
  903. {
  904. struct sk_buff *skb;
  905. int ret = 0;
  906. __le16 fc = hdr->frame_control;
  907. /* We only process data packets if the interface is open */
  908. if (unlikely(!priv->is_open)) {
  909. IWL_DEBUG_DROP_LIMIT(priv,
  910. "Dropping packet while interface is not open.\n");
  911. return;
  912. }
  913. /* In case of HW accelerated crypto and bad decryption, drop */
  914. if (!priv->cfg->mod_params->sw_crypto &&
  915. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  916. return;
  917. skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
  918. if (!skb) {
  919. IWL_ERR(priv, "alloc_skb failed\n");
  920. return;
  921. }
  922. skb_reserve(skb, IWL_LINK_HDR_MAX);
  923. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  924. /* mac80211 currently doesn't support paged SKB. Convert it to
  925. * linear SKB for management frame and data frame requires
  926. * software decryption or software defragementation. */
  927. if (ieee80211_is_mgmt(fc) ||
  928. ieee80211_has_protected(fc) ||
  929. ieee80211_has_morefrags(fc) ||
  930. le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
  931. ret = skb_linearize(skb);
  932. else
  933. ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
  934. 0 : -ENOMEM;
  935. if (ret) {
  936. kfree_skb(skb);
  937. goto out;
  938. }
  939. /*
  940. * XXX: We cannot touch the page and its virtual memory (hdr) after
  941. * here. It might have already been freed by the above skb change.
  942. */
  943. iwl_update_stats(priv, false, fc, len);
  944. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  945. ieee80211_rx(priv->hw, skb);
  946. out:
  947. priv->alloc_rxb_page--;
  948. rxb->page = NULL;
  949. }
  950. /* This is necessary only for a number of statistics, see the caller. */
  951. static int iwl_is_network_packet(struct iwl_priv *priv,
  952. struct ieee80211_hdr *header)
  953. {
  954. /* Filter incoming packets to determine if they are targeted toward
  955. * this network, discarding packets coming from ourselves */
  956. switch (priv->iw_mode) {
  957. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  958. /* packets to our IBSS update information */
  959. return !compare_ether_addr(header->addr3, priv->bssid);
  960. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  961. /* packets to our IBSS update information */
  962. return !compare_ether_addr(header->addr2, priv->bssid);
  963. default:
  964. return 1;
  965. }
  966. }
  967. /* Called for REPLY_RX (legacy ABG frames), or
  968. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  969. void iwl_rx_reply_rx(struct iwl_priv *priv,
  970. struct iwl_rx_mem_buffer *rxb)
  971. {
  972. struct ieee80211_hdr *header;
  973. struct ieee80211_rx_status rx_status;
  974. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  975. struct iwl_rx_phy_res *phy_res;
  976. __le32 rx_pkt_status;
  977. struct iwl4965_rx_mpdu_res_start *amsdu;
  978. u32 len;
  979. u32 ampdu_status;
  980. u32 rate_n_flags;
  981. /**
  982. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  983. * REPLY_RX: physical layer info is in this buffer
  984. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  985. * command and cached in priv->last_phy_res
  986. *
  987. * Here we set up local variables depending on which command is
  988. * received.
  989. */
  990. if (pkt->hdr.cmd == REPLY_RX) {
  991. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  992. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  993. + phy_res->cfg_phy_cnt);
  994. len = le16_to_cpu(phy_res->byte_count);
  995. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  996. phy_res->cfg_phy_cnt + len);
  997. ampdu_status = le32_to_cpu(rx_pkt_status);
  998. } else {
  999. if (!priv->last_phy_res[0]) {
  1000. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  1001. return;
  1002. }
  1003. phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  1004. amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  1005. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  1006. len = le16_to_cpu(amsdu->byte_count);
  1007. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  1008. ampdu_status = iwl_translate_rx_status(priv,
  1009. le32_to_cpu(rx_pkt_status));
  1010. }
  1011. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  1012. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  1013. phy_res->cfg_phy_cnt);
  1014. return;
  1015. }
  1016. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  1017. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  1018. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  1019. le32_to_cpu(rx_pkt_status));
  1020. return;
  1021. }
  1022. /* This will be used in several places later */
  1023. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  1024. /* rx_status carries information about the packet to mac80211 */
  1025. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  1026. rx_status.freq =
  1027. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  1028. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  1029. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  1030. rx_status.rate_idx =
  1031. iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  1032. rx_status.flag = 0;
  1033. /* TSF isn't reliable. In order to allow smooth user experience,
  1034. * this W/A doesn't propagate it to the mac80211 */
  1035. /*rx_status.flag |= RX_FLAG_TSFT;*/
  1036. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  1037. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  1038. rx_status.signal = iwl_calc_rssi(priv, phy_res);
  1039. /* Meaningful noise values are available only from beacon statistics,
  1040. * which are gathered only when associated, and indicate noise
  1041. * only for the associated network channel ...
  1042. * Ignore these noise values while scanning (other channels) */
  1043. if (iwl_is_associated(priv) &&
  1044. !test_bit(STATUS_SCANNING, &priv->status)) {
  1045. rx_status.noise = priv->last_rx_noise;
  1046. } else {
  1047. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1048. }
  1049. /* Reset beacon noise level if not associated. */
  1050. if (!iwl_is_associated(priv))
  1051. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  1052. #ifdef CONFIG_IWLWIFI_DEBUG
  1053. /* Set "1" to report good data frames in groups of 100 */
  1054. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  1055. iwl_dbg_report_frame(priv, phy_res, len, header, 1);
  1056. #endif
  1057. iwl_dbg_log_rx_data_frame(priv, len, header);
  1058. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, TSF %llu\n",
  1059. rx_status.signal, rx_status.noise,
  1060. (unsigned long long)rx_status.mactime);
  1061. /*
  1062. * "antenna number"
  1063. *
  1064. * It seems that the antenna field in the phy flags value
  1065. * is actually a bit field. This is undefined by radiotap,
  1066. * it wants an actual antenna number but I always get "7"
  1067. * for most legacy frames I receive indicating that the
  1068. * same frame was received on all three RX chains.
  1069. *
  1070. * I think this field should be removed in favor of a
  1071. * new 802.11n radiotap field "RX chains" that is defined
  1072. * as a bitmask.
  1073. */
  1074. rx_status.antenna =
  1075. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  1076. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  1077. /* set the preamble flag if appropriate */
  1078. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  1079. rx_status.flag |= RX_FLAG_SHORTPRE;
  1080. /* Set up the HT phy flags */
  1081. if (rate_n_flags & RATE_MCS_HT_MSK)
  1082. rx_status.flag |= RX_FLAG_HT;
  1083. if (rate_n_flags & RATE_MCS_HT40_MSK)
  1084. rx_status.flag |= RX_FLAG_40MHZ;
  1085. if (rate_n_flags & RATE_MCS_SGI_MSK)
  1086. rx_status.flag |= RX_FLAG_SHORT_GI;
  1087. if (iwl_is_network_packet(priv, header)) {
  1088. priv->last_rx_rssi = rx_status.signal;
  1089. priv->last_beacon_time = priv->ucode_beacon_time;
  1090. priv->last_tsf = le64_to_cpu(phy_res->timestamp);
  1091. }
  1092. iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  1093. rxb, &rx_status);
  1094. }
  1095. EXPORT_SYMBOL(iwl_rx_reply_rx);
  1096. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1097. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1098. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  1099. struct iwl_rx_mem_buffer *rxb)
  1100. {
  1101. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1102. priv->last_phy_res[0] = 1;
  1103. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  1104. sizeof(struct iwl_rx_phy_res));
  1105. }
  1106. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);