cx18-av-firmware.c 4.2 KB

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  1. /*
  2. * cx18 ADEC firmware functions
  3. *
  4. * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19. * 02110-1301, USA.
  20. */
  21. #include "cx18-driver.h"
  22. #include <linux/firmware.h>
  23. #define FWFILE "v4l-cx23418-dig.fw"
  24. int cx18_av_loadfw(struct cx18 *cx)
  25. {
  26. const struct firmware *fw = NULL;
  27. u32 size;
  28. u32 v;
  29. const u8 *ptr;
  30. int i;
  31. int retries = 0;
  32. if (request_firmware(&fw, FWFILE, &cx->dev->dev) != 0) {
  33. CX18_ERR("unable to open firmware %s\n", FWFILE);
  34. return -EINVAL;
  35. }
  36. /* The firmware load often has byte errors, so allow for several
  37. retries, both at byte level and at the firmware load level. */
  38. while (retries < 5) {
  39. cx18_av_write4(cx, CXADEC_CHIP_CTRL, 0x00010000);
  40. cx18_av_write(cx, CXADEC_STD_DET_CTL, 0xf6);
  41. /* Reset the Mako core (Register is undocumented.) */
  42. cx18_av_write4(cx, 0x8100, 0x00010000);
  43. /* Put the 8051 in reset and enable firmware upload */
  44. cx18_av_write4(cx, CXADEC_DL_CTL, 0x0F000000);
  45. ptr = fw->data;
  46. size = fw->size;
  47. for (i = 0; i < size; i++) {
  48. u32 dl_control = 0x0F000000 | i | ((u32)ptr[i] << 16);
  49. u32 value = 0;
  50. int retries;
  51. for (retries = 0; retries < 5; retries++) {
  52. cx18_av_write4(cx, CXADEC_DL_CTL, dl_control);
  53. udelay(10);
  54. value = cx18_av_read4(cx, CXADEC_DL_CTL);
  55. if (value == dl_control)
  56. break;
  57. /* Check if we can correct the byte by changing
  58. the address. We can only write the lower
  59. address byte of the address. */
  60. if ((value & 0x3F00) != (dl_control & 0x3F00)) {
  61. retries = 5;
  62. break;
  63. }
  64. }
  65. if (retries >= 5)
  66. break;
  67. }
  68. if (i == size)
  69. break;
  70. retries++;
  71. }
  72. if (retries >= 5) {
  73. CX18_ERR("unable to load firmware %s\n", FWFILE);
  74. release_firmware(fw);
  75. return -EIO;
  76. }
  77. cx18_av_write4(cx, CXADEC_DL_CTL, 0x13000000 | fw->size);
  78. /* Output to the 416 */
  79. cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x78000);
  80. /* Audio input control 1 set to Sony mode */
  81. /* Audio output input 2 is 0 for slave operation input */
  82. /* 0xC4000914[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
  83. /* 0xC4000914[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
  84. after WS transition for first bit of audio word. */
  85. cx18_av_write4(cx, CXADEC_I2S_IN_CTL, 0x000000A0);
  86. /* Audio output control 1 is set to Sony mode */
  87. /* Audio output control 2 is set to 1 for master mode */
  88. /* 0xC4000918[5]: 0 = left sample on WS=0, 1 = left sample on WS=1 */
  89. /* 0xC4000918[7]: 0 = Philips mode, 1 = Sony mode (1st SCK rising edge
  90. after WS transition for first bit of audio word. */
  91. /* 0xC4000918[8]: 0 = slave operation, 1 = master (SCK_OUT and WS_OUT
  92. are generated) */
  93. cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
  94. /* set alt I2s master clock to /16 and enable alt divider i2s
  95. passthrough */
  96. cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687);
  97. cx18_av_write4(cx, CXADEC_STD_DET_CTL, 0x000000F6);
  98. /* CxDevWrReg(CXADEC_STD_DET_CTL, 0x000000FF); */
  99. /* Set bit 0 in register 0x9CC to signify that this is MiniMe. */
  100. /* Register 0x09CC is defined by the Merlin firmware, and doesn't
  101. have a name in the spec. */
  102. cx18_av_write4(cx, 0x09CC, 1);
  103. #define CX18_AUDIO_ENABLE 0xc72014
  104. v = read_reg(CX18_AUDIO_ENABLE);
  105. /* If bit 11 is 1 */
  106. if (v & 0x800)
  107. write_reg(v & 0xFFFFFBFF, CX18_AUDIO_ENABLE); /* Clear bit 10 */
  108. /* Enable WW auto audio standard detection */
  109. v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
  110. v |= 0xFF; /* Auto by default */
  111. v |= 0x400; /* Stereo by default */
  112. v |= 0x14000000;
  113. cx18_av_write4(cx, CXADEC_STD_DET_CTL, v);
  114. release_firmware(fw);
  115. CX18_INFO("loaded %s firmware (%d bytes)\n", FWFILE, size);
  116. return 0;
  117. }