fw_common.c 24 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/firmware.h>
  31. #include <linux/export.h>
  32. #include "../wifi.h"
  33. #include "../pci.h"
  34. #include "../base.h"
  35. #include "../rtl8192ce/reg.h"
  36. #include "../rtl8192ce/def.h"
  37. #include "fw_common.h"
  38. static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  39. {
  40. struct rtl_priv *rtlpriv = rtl_priv(hw);
  41. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  42. if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) {
  43. u32 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  44. if (enable)
  45. value32 |= MCUFWDL_EN;
  46. else
  47. value32 &= ~MCUFWDL_EN;
  48. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  49. } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) {
  50. u8 tmp;
  51. if (enable) {
  52. tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  53. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
  54. tmp | 0x04);
  55. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  56. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
  57. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  58. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  59. } else {
  60. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  61. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  62. rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
  63. }
  64. }
  65. }
  66. static void rtl_block_fw_writeN(struct ieee80211_hw *hw, const u8 *buffer,
  67. u32 size)
  68. {
  69. struct rtl_priv *rtlpriv = rtl_priv(hw);
  70. u32 blockSize = REALTEK_USB_VENQT_MAX_BUF_SIZE - 20;
  71. u8 *bufferPtr = (u8 *) buffer;
  72. u32 i, offset, blockCount, remainSize;
  73. blockCount = size / blockSize;
  74. remainSize = size % blockSize;
  75. for (i = 0; i < blockCount; i++) {
  76. offset = i * blockSize;
  77. rtlpriv->io.writeN_sync(rtlpriv,
  78. (FW_8192C_START_ADDRESS + offset),
  79. (void *)(bufferPtr + offset),
  80. blockSize);
  81. }
  82. if (remainSize) {
  83. offset = blockCount * blockSize;
  84. rtlpriv->io.writeN_sync(rtlpriv,
  85. (FW_8192C_START_ADDRESS + offset),
  86. (void *)(bufferPtr + offset),
  87. remainSize);
  88. }
  89. }
  90. static void _rtl92c_fw_block_write(struct ieee80211_hw *hw,
  91. const u8 *buffer, u32 size)
  92. {
  93. struct rtl_priv *rtlpriv = rtl_priv(hw);
  94. u32 blockSize = sizeof(u32);
  95. u8 *bufferPtr = (u8 *) buffer;
  96. u32 *pu4BytePtr = (u32 *) buffer;
  97. u32 i, offset, blockCount, remainSize;
  98. u32 data;
  99. if (rtlpriv->io.writeN_sync) {
  100. rtl_block_fw_writeN(hw, buffer, size);
  101. return;
  102. }
  103. blockCount = size / blockSize;
  104. remainSize = size % blockSize;
  105. if (remainSize) {
  106. /* the last word is < 4 bytes - pad it with zeros */
  107. for (i = 0; i < 4 - remainSize; i++)
  108. *(bufferPtr + size + i) = 0;
  109. blockCount++;
  110. }
  111. for (i = 0; i < blockCount; i++) {
  112. offset = i * blockSize;
  113. /* for big-endian platforms, the firmware data need to be byte
  114. * swapped as it was read as a byte string and will be written
  115. * as 32-bit dwords and byte swapped when written
  116. */
  117. data = le32_to_cpu(*(__le32 *)(pu4BytePtr + i));
  118. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  119. data);
  120. }
  121. }
  122. static void _rtl92c_fw_page_write(struct ieee80211_hw *hw,
  123. u32 page, const u8 *buffer, u32 size)
  124. {
  125. struct rtl_priv *rtlpriv = rtl_priv(hw);
  126. u8 value8;
  127. u8 u8page = (u8) (page & 0x07);
  128. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  129. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  130. _rtl92c_fw_block_write(hw, buffer, size);
  131. }
  132. static void _rtl92c_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  133. {
  134. u32 fwlen = *pfwlen;
  135. u8 remain = (u8) (fwlen % 4);
  136. remain = (remain == 0) ? 0 : (4 - remain);
  137. while (remain > 0) {
  138. pfwbuf[fwlen] = 0;
  139. fwlen++;
  140. remain--;
  141. }
  142. *pfwlen = fwlen;
  143. }
  144. static void _rtl92c_write_fw(struct ieee80211_hw *hw,
  145. enum version_8192c version, u8 *buffer, u32 size)
  146. {
  147. struct rtl_priv *rtlpriv = rtl_priv(hw);
  148. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  149. u8 *bufferPtr = (u8 *) buffer;
  150. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes\n", size);
  151. if (IS_CHIP_VER_B(version)) {
  152. u32 pageNums, remainSize;
  153. u32 page, offset;
  154. if (IS_HARDWARE_TYPE_8192CE(rtlhal))
  155. _rtl92c_fill_dummy(bufferPtr, &size);
  156. pageNums = size / FW_8192C_PAGE_SIZE;
  157. remainSize = size % FW_8192C_PAGE_SIZE;
  158. if (pageNums > 4) {
  159. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  160. "Page numbers should not greater then 4\n");
  161. }
  162. for (page = 0; page < pageNums; page++) {
  163. offset = page * FW_8192C_PAGE_SIZE;
  164. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  165. FW_8192C_PAGE_SIZE);
  166. }
  167. if (remainSize) {
  168. offset = pageNums * FW_8192C_PAGE_SIZE;
  169. page = pageNums;
  170. _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
  171. remainSize);
  172. }
  173. } else {
  174. _rtl92c_fw_block_write(hw, buffer, size);
  175. }
  176. }
  177. static int _rtl92c_fw_free_to_go(struct ieee80211_hw *hw)
  178. {
  179. struct rtl_priv *rtlpriv = rtl_priv(hw);
  180. u32 counter = 0;
  181. u32 value32;
  182. do {
  183. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  184. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  185. (!(value32 & FWDL_ChkSum_rpt)));
  186. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  187. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  188. "chksum report faill ! REG_MCUFWDL:0x%08x\n", value32);
  189. return -EIO;
  190. }
  191. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  192. "Checksum report OK ! REG_MCUFWDL:0x%08x\n", value32);
  193. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  194. value32 |= MCUFWDL_RDY;
  195. value32 &= ~WINTINI_RDY;
  196. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  197. counter = 0;
  198. do {
  199. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  200. if (value32 & WINTINI_RDY) {
  201. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  202. "Polling FW ready success!! REG_MCUFWDL:0x%08x\n",
  203. value32);
  204. return 0;
  205. }
  206. mdelay(FW_8192C_POLLING_DELAY);
  207. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  208. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  209. "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", value32);
  210. return -EIO;
  211. }
  212. int rtl92c_download_fw(struct ieee80211_hw *hw)
  213. {
  214. struct rtl_priv *rtlpriv = rtl_priv(hw);
  215. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  216. struct rtl92c_firmware_header *pfwheader;
  217. u8 *pfwdata;
  218. u32 fwsize;
  219. enum version_8192c version = rtlhal->version;
  220. if (!rtlhal->pfirmware)
  221. return 1;
  222. pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
  223. pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
  224. pfwdata = (u8 *) rtlhal->pfirmware;
  225. fwsize = rtlhal->fwsize;
  226. if (IS_FW_HEADER_EXIST(pfwheader)) {
  227. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  228. "Firmware Version(%d), Signature(%#x),Size(%d)\n",
  229. le16_to_cpu(pfwheader->version),
  230. le16_to_cpu(pfwheader->signature),
  231. (uint)sizeof(struct rtl92c_firmware_header));
  232. pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
  233. fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
  234. }
  235. _rtl92c_enable_fw_download(hw, true);
  236. _rtl92c_write_fw(hw, version, pfwdata, fwsize);
  237. _rtl92c_enable_fw_download(hw, false);
  238. if (_rtl92c_fw_free_to_go(hw)) {
  239. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  240. "Firmware is not ready to run!\n");
  241. } else {
  242. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  243. "Firmware is ready to run!\n");
  244. }
  245. return 0;
  246. }
  247. EXPORT_SYMBOL(rtl92c_download_fw);
  248. static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  249. {
  250. struct rtl_priv *rtlpriv = rtl_priv(hw);
  251. u8 val_hmetfr, val_mcutst_1;
  252. bool result = false;
  253. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  254. val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
  255. if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
  256. result = true;
  257. return result;
  258. }
  259. static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
  260. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  261. {
  262. struct rtl_priv *rtlpriv = rtl_priv(hw);
  263. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  264. u8 boxnum;
  265. u16 box_reg = 0, box_extreg = 0;
  266. u8 u1b_tmp;
  267. bool isfw_read = false;
  268. bool bwrite_sucess = false;
  269. u8 wait_h2c_limmit = 100;
  270. u8 wait_writeh2c_limmit = 100;
  271. u8 boxcontent[4], boxextcontent[2];
  272. u32 h2c_waitcounter = 0;
  273. unsigned long flag;
  274. u8 idx;
  275. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");
  276. while (true) {
  277. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  278. if (rtlhal->h2c_setinprogress) {
  279. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  280. "H2C set in progress! Wait to set..element_id(%d)\n",
  281. element_id);
  282. while (rtlhal->h2c_setinprogress) {
  283. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  284. flag);
  285. h2c_waitcounter++;
  286. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  287. "Wait 100 us (%d times)...\n",
  288. h2c_waitcounter);
  289. udelay(100);
  290. if (h2c_waitcounter > 1000)
  291. return;
  292. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  293. flag);
  294. }
  295. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  296. } else {
  297. rtlhal->h2c_setinprogress = true;
  298. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  299. break;
  300. }
  301. }
  302. while (!bwrite_sucess) {
  303. wait_writeh2c_limmit--;
  304. if (wait_writeh2c_limmit == 0) {
  305. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  306. "Write H2C fail because no trigger for FW INT!\n");
  307. break;
  308. }
  309. boxnum = rtlhal->last_hmeboxnum;
  310. switch (boxnum) {
  311. case 0:
  312. box_reg = REG_HMEBOX_0;
  313. box_extreg = REG_HMEBOX_EXT_0;
  314. break;
  315. case 1:
  316. box_reg = REG_HMEBOX_1;
  317. box_extreg = REG_HMEBOX_EXT_1;
  318. break;
  319. case 2:
  320. box_reg = REG_HMEBOX_2;
  321. box_extreg = REG_HMEBOX_EXT_2;
  322. break;
  323. case 3:
  324. box_reg = REG_HMEBOX_3;
  325. box_extreg = REG_HMEBOX_EXT_3;
  326. break;
  327. default:
  328. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  329. "switch case not processed\n");
  330. break;
  331. }
  332. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  333. while (!isfw_read) {
  334. wait_h2c_limmit--;
  335. if (wait_h2c_limmit == 0) {
  336. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  337. "Waiting too long for FW read clear HMEBox(%d)!\n",
  338. boxnum);
  339. break;
  340. }
  341. udelay(10);
  342. isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
  343. u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
  344. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  345. "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n",
  346. boxnum, u1b_tmp);
  347. }
  348. if (!isfw_read) {
  349. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  350. "Write H2C register BOX[%d] fail!!!!! Fw do not read\n",
  351. boxnum);
  352. break;
  353. }
  354. memset(boxcontent, 0, sizeof(boxcontent));
  355. memset(boxextcontent, 0, sizeof(boxextcontent));
  356. boxcontent[0] = element_id;
  357. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  358. "Write element_id box_reg(%4x) = %2x\n",
  359. box_reg, element_id);
  360. switch (cmd_len) {
  361. case 1:
  362. boxcontent[0] &= ~(BIT(7));
  363. memcpy((u8 *) (boxcontent) + 1,
  364. p_cmdbuffer, 1);
  365. for (idx = 0; idx < 4; idx++) {
  366. rtl_write_byte(rtlpriv, box_reg + idx,
  367. boxcontent[idx]);
  368. }
  369. break;
  370. case 2:
  371. boxcontent[0] &= ~(BIT(7));
  372. memcpy((u8 *) (boxcontent) + 1,
  373. p_cmdbuffer, 2);
  374. for (idx = 0; idx < 4; idx++) {
  375. rtl_write_byte(rtlpriv, box_reg + idx,
  376. boxcontent[idx]);
  377. }
  378. break;
  379. case 3:
  380. boxcontent[0] &= ~(BIT(7));
  381. memcpy((u8 *) (boxcontent) + 1,
  382. p_cmdbuffer, 3);
  383. for (idx = 0; idx < 4; idx++) {
  384. rtl_write_byte(rtlpriv, box_reg + idx,
  385. boxcontent[idx]);
  386. }
  387. break;
  388. case 4:
  389. boxcontent[0] |= (BIT(7));
  390. memcpy((u8 *) (boxextcontent),
  391. p_cmdbuffer, 2);
  392. memcpy((u8 *) (boxcontent) + 1,
  393. p_cmdbuffer + 2, 2);
  394. for (idx = 0; idx < 2; idx++) {
  395. rtl_write_byte(rtlpriv, box_extreg + idx,
  396. boxextcontent[idx]);
  397. }
  398. for (idx = 0; idx < 4; idx++) {
  399. rtl_write_byte(rtlpriv, box_reg + idx,
  400. boxcontent[idx]);
  401. }
  402. break;
  403. case 5:
  404. boxcontent[0] |= (BIT(7));
  405. memcpy((u8 *) (boxextcontent),
  406. p_cmdbuffer, 2);
  407. memcpy((u8 *) (boxcontent) + 1,
  408. p_cmdbuffer + 2, 3);
  409. for (idx = 0; idx < 2; idx++) {
  410. rtl_write_byte(rtlpriv, box_extreg + idx,
  411. boxextcontent[idx]);
  412. }
  413. for (idx = 0; idx < 4; idx++) {
  414. rtl_write_byte(rtlpriv, box_reg + idx,
  415. boxcontent[idx]);
  416. }
  417. break;
  418. default:
  419. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  420. "switch case not processed\n");
  421. break;
  422. }
  423. bwrite_sucess = true;
  424. rtlhal->last_hmeboxnum = boxnum + 1;
  425. if (rtlhal->last_hmeboxnum == 4)
  426. rtlhal->last_hmeboxnum = 0;
  427. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
  428. "pHalData->last_hmeboxnum = %d\n",
  429. rtlhal->last_hmeboxnum);
  430. }
  431. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  432. rtlhal->h2c_setinprogress = false;
  433. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  434. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n");
  435. }
  436. void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
  437. u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
  438. {
  439. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  440. u32 tmp_cmdbuf[2];
  441. if (rtlhal->fw_ready == false) {
  442. RT_ASSERT(false, ("return H2C cmd because of Fw "
  443. "download fail!!!\n"));
  444. return;
  445. }
  446. memset(tmp_cmdbuf, 0, 8);
  447. memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
  448. _rtl92c_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  449. return;
  450. }
  451. EXPORT_SYMBOL(rtl92c_fill_h2c_cmd);
  452. void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
  453. {
  454. u8 u1b_tmp;
  455. u8 delay = 100;
  456. struct rtl_priv *rtlpriv = rtl_priv(hw);
  457. rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
  458. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  459. while (u1b_tmp & BIT(2)) {
  460. delay--;
  461. if (delay == 0) {
  462. RT_ASSERT(false, ("8051 reset fail.\n"));
  463. break;
  464. }
  465. udelay(50);
  466. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  467. }
  468. }
  469. EXPORT_SYMBOL(rtl92c_firmware_selfreset);
  470. void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  471. {
  472. struct rtl_priv *rtlpriv = rtl_priv(hw);
  473. u8 u1_h2c_set_pwrmode[3] = {0};
  474. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  475. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
  476. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
  477. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
  478. SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
  479. ppsc->reg_max_lps_awakeintvl);
  480. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  481. "rtl92c_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode",
  482. u1_h2c_set_pwrmode, 3);
  483. rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
  484. }
  485. EXPORT_SYMBOL(rtl92c_set_fw_pwrmode_cmd);
  486. static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
  487. struct sk_buff *skb)
  488. {
  489. struct rtl_priv *rtlpriv = rtl_priv(hw);
  490. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  491. struct rtl8192_tx_ring *ring;
  492. struct rtl_tx_desc *pdesc;
  493. unsigned long flags;
  494. struct sk_buff *pskb = NULL;
  495. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  496. pskb = __skb_dequeue(&ring->queue);
  497. if (pskb)
  498. kfree_skb(pskb);
  499. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  500. pdesc = &ring->desc[0];
  501. rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
  502. __skb_queue_tail(&ring->queue, skb);
  503. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  504. rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
  505. return true;
  506. }
  507. #define BEACON_PG 0 /*->1*/
  508. #define PSPOLL_PG 2
  509. #define NULL_PG 3
  510. #define PROBERSP_PG 4 /*->5*/
  511. #define TOTAL_RESERVED_PKT_LEN 768
  512. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  513. /* page 0 beacon */
  514. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  515. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  516. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  518. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  519. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  520. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  521. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  522. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  523. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  524. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  525. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  526. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  527. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  528. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  529. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  530. /* page 1 beacon */
  531. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  532. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  533. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  534. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  535. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  536. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  537. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  538. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  539. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  540. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  541. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  542. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  543. 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
  544. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  545. 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  546. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  547. /* page 2 ps-poll */
  548. 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
  549. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  550. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  551. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  552. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  553. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  554. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  555. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  556. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  557. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  558. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  559. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  560. 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  561. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  562. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  563. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  564. /* page 3 null */
  565. 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  566. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  567. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  568. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  569. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  570. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  571. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  572. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  573. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  574. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  575. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  576. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  577. 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
  578. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
  579. 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  580. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  581. /* page 4 probe_resp */
  582. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  583. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  584. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  585. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  586. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  587. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  588. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  589. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  590. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  591. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  592. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  593. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  594. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  595. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  596. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  597. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  598. /* page 5 probe_resp */
  599. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  600. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  601. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  602. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  603. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  604. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  605. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  606. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  607. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  608. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  609. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  610. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  611. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  612. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  613. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  614. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  615. };
  616. void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
  617. {
  618. struct rtl_priv *rtlpriv = rtl_priv(hw);
  619. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  620. struct sk_buff *skb = NULL;
  621. u32 totalpacketlen;
  622. bool rtstatus;
  623. u8 u1RsvdPageLoc[3] = {0};
  624. bool dlok = false;
  625. u8 *beacon;
  626. u8 *pspoll;
  627. u8 *nullfunc;
  628. u8 *probersp;
  629. /*---------------------------------------------------------
  630. (1) beacon
  631. ---------------------------------------------------------*/
  632. beacon = &reserved_page_packet[BEACON_PG * 128];
  633. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  634. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  635. /*-------------------------------------------------------
  636. (2) ps-poll
  637. --------------------------------------------------------*/
  638. pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  639. SET_80211_PS_POLL_AID(pspoll, (mac->assoc_id | 0xc000));
  640. SET_80211_PS_POLL_BSSID(pspoll, mac->bssid);
  641. SET_80211_PS_POLL_TA(pspoll, mac->mac_addr);
  642. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
  643. /*--------------------------------------------------------
  644. (3) null data
  645. ---------------------------------------------------------*/
  646. nullfunc = &reserved_page_packet[NULL_PG * 128];
  647. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  648. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  649. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  650. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
  651. /*---------------------------------------------------------
  652. (4) probe response
  653. ----------------------------------------------------------*/
  654. probersp = &reserved_page_packet[PROBERSP_PG * 128];
  655. SET_80211_HDR_ADDRESS1(probersp, mac->bssid);
  656. SET_80211_HDR_ADDRESS2(probersp, mac->mac_addr);
  657. SET_80211_HDR_ADDRESS3(probersp, mac->bssid);
  658. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
  659. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  660. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  661. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL",
  662. &reserved_page_packet[0], totalpacketlen);
  663. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  664. "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL",
  665. u1RsvdPageLoc, 3);
  666. skb = dev_alloc_skb(totalpacketlen);
  667. memcpy((u8 *) skb_put(skb, totalpacketlen),
  668. &reserved_page_packet, totalpacketlen);
  669. rtstatus = _rtl92c_cmd_send_packet(hw, skb);
  670. if (rtstatus)
  671. dlok = true;
  672. if (dlok) {
  673. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  674. "Set RSVD page location to Fw\n");
  675. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  676. "H2C_RSVDPAGE", u1RsvdPageLoc, 3);
  677. rtl92c_fill_h2c_cmd(hw, H2C_RSVDPAGE,
  678. sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
  679. } else
  680. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  681. "Set RSVD page location to Fw FAIL!!!!!!\n");
  682. }
  683. EXPORT_SYMBOL(rtl92c_set_fw_rsvdpagepkt);
  684. void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
  685. {
  686. u8 u1_joinbssrpt_parm[1] = {0};
  687. SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
  688. rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
  689. }
  690. EXPORT_SYMBOL(rtl92c_set_fw_joinbss_report_cmd);