skge.c 86 KB

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  1. /*
  2. * New driver for Marvell Yukon chipset and SysKonnect Gigabit
  3. * Ethernet adapters. Based on earlier sk98lin, e100 and
  4. * FreeBSD if_sk drivers.
  5. *
  6. * This driver intentionally does not support all the features
  7. * of the original driver such as link fail-over and link management because
  8. * those should be done at higher levels.
  9. *
  10. * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. */
  26. #include <linux/config.h>
  27. #include <linux/kernel.h>
  28. #include <linux/module.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/pci.h>
  34. #include <linux/if_vlan.h>
  35. #include <linux/ip.h>
  36. #include <linux/delay.h>
  37. #include <linux/crc32.h>
  38. #include <linux/dma-mapping.h>
  39. #include <asm/irq.h>
  40. #include "skge.h"
  41. #define DRV_NAME "skge"
  42. #define DRV_VERSION "0.8"
  43. #define PFX DRV_NAME " "
  44. #define DEFAULT_TX_RING_SIZE 128
  45. #define DEFAULT_RX_RING_SIZE 512
  46. #define MAX_TX_RING_SIZE 1024
  47. #define MAX_RX_RING_SIZE 4096
  48. #define RX_COPY_THRESHOLD 128
  49. #define RX_BUF_SIZE 1536
  50. #define PHY_RETRIES 1000
  51. #define ETH_JUMBO_MTU 9000
  52. #define TX_WATCHDOG (5 * HZ)
  53. #define NAPI_WEIGHT 64
  54. #define BLINK_MS 250
  55. MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
  56. MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
  57. MODULE_LICENSE("GPL");
  58. MODULE_VERSION(DRV_VERSION);
  59. static const u32 default_msg
  60. = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
  61. | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
  62. static int debug = -1; /* defaults above */
  63. module_param(debug, int, 0);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. static const struct pci_device_id skge_id_table[] = {
  66. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
  67. { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
  71. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
  73. { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
  76. { 0 }
  77. };
  78. MODULE_DEVICE_TABLE(pci, skge_id_table);
  79. static int skge_up(struct net_device *dev);
  80. static int skge_down(struct net_device *dev);
  81. static void skge_tx_clean(struct skge_port *skge);
  82. static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  83. static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
  84. static void genesis_get_stats(struct skge_port *skge, u64 *data);
  85. static void yukon_get_stats(struct skge_port *skge, u64 *data);
  86. static void yukon_init(struct skge_hw *hw, int port);
  87. static void yukon_reset(struct skge_hw *hw, int port);
  88. static void genesis_mac_init(struct skge_hw *hw, int port);
  89. static void genesis_reset(struct skge_hw *hw, int port);
  90. static void genesis_link_up(struct skge_port *skge);
  91. /* Avoid conditionals by using array */
  92. static const int txqaddr[] = { Q_XA1, Q_XA2 };
  93. static const int rxqaddr[] = { Q_R1, Q_R2 };
  94. static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
  95. static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
  96. static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
  97. /* Don't need to look at whole 16K.
  98. * last interesting register is descriptor poll timer.
  99. */
  100. #define SKGE_REGS_LEN (29*128)
  101. static int skge_get_regs_len(struct net_device *dev)
  102. {
  103. return SKGE_REGS_LEN;
  104. }
  105. /*
  106. * Returns copy of control register region
  107. * I/O region is divided into banks and certain regions are unreadable
  108. */
  109. static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  110. void *p)
  111. {
  112. const struct skge_port *skge = netdev_priv(dev);
  113. unsigned long offs;
  114. const void __iomem *io = skge->hw->regs;
  115. static const unsigned long bankmap
  116. = (1<<0) | (1<<2) | (1<<8) | (1<<9)
  117. | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
  118. | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
  119. | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
  120. regs->version = 1;
  121. for (offs = 0; offs < regs->len; offs += 128) {
  122. u32 len = min_t(u32, 128, regs->len - offs);
  123. if (bankmap & (1<<(offs/128)))
  124. memcpy_fromio(p + offs, io + offs, len);
  125. else
  126. memset(p + offs, 0, len);
  127. }
  128. }
  129. /* Wake on Lan only supported on Yukon chps with rev 1 or above */
  130. static int wol_supported(const struct skge_hw *hw)
  131. {
  132. return !((hw->chip_id == CHIP_ID_GENESIS ||
  133. (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
  134. }
  135. static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  136. {
  137. struct skge_port *skge = netdev_priv(dev);
  138. wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
  139. wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
  140. }
  141. static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  142. {
  143. struct skge_port *skge = netdev_priv(dev);
  144. struct skge_hw *hw = skge->hw;
  145. if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
  146. return -EOPNOTSUPP;
  147. if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
  148. return -EOPNOTSUPP;
  149. skge->wol = wol->wolopts == WAKE_MAGIC;
  150. if (skge->wol) {
  151. memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
  152. skge_write16(hw, WOL_CTRL_STAT,
  153. WOL_CTL_ENA_PME_ON_MAGIC_PKT |
  154. WOL_CTL_ENA_MAGIC_PKT_UNIT);
  155. } else
  156. skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
  157. return 0;
  158. }
  159. /* Determine supported/adverised modes based on hardware.
  160. * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
  161. */
  162. static u32 skge_supported_modes(const struct skge_hw *hw)
  163. {
  164. u32 supported;
  165. if (iscopper(hw)) {
  166. supported = SUPPORTED_10baseT_Half
  167. | SUPPORTED_10baseT_Full
  168. | SUPPORTED_100baseT_Half
  169. | SUPPORTED_100baseT_Full
  170. | SUPPORTED_1000baseT_Half
  171. | SUPPORTED_1000baseT_Full
  172. | SUPPORTED_Autoneg| SUPPORTED_TP;
  173. if (hw->chip_id == CHIP_ID_GENESIS)
  174. supported &= ~(SUPPORTED_10baseT_Half
  175. | SUPPORTED_10baseT_Full
  176. | SUPPORTED_100baseT_Half
  177. | SUPPORTED_100baseT_Full);
  178. else if (hw->chip_id == CHIP_ID_YUKON)
  179. supported &= ~SUPPORTED_1000baseT_Half;
  180. } else
  181. supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
  182. | SUPPORTED_Autoneg;
  183. return supported;
  184. }
  185. static int skge_get_settings(struct net_device *dev,
  186. struct ethtool_cmd *ecmd)
  187. {
  188. struct skge_port *skge = netdev_priv(dev);
  189. struct skge_hw *hw = skge->hw;
  190. ecmd->transceiver = XCVR_INTERNAL;
  191. ecmd->supported = skge_supported_modes(hw);
  192. if (iscopper(hw)) {
  193. ecmd->port = PORT_TP;
  194. ecmd->phy_address = hw->phy_addr;
  195. } else
  196. ecmd->port = PORT_FIBRE;
  197. ecmd->advertising = skge->advertising;
  198. ecmd->autoneg = skge->autoneg;
  199. ecmd->speed = skge->speed;
  200. ecmd->duplex = skge->duplex;
  201. return 0;
  202. }
  203. static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  204. {
  205. struct skge_port *skge = netdev_priv(dev);
  206. const struct skge_hw *hw = skge->hw;
  207. u32 supported = skge_supported_modes(hw);
  208. if (ecmd->autoneg == AUTONEG_ENABLE) {
  209. ecmd->advertising = supported;
  210. skge->duplex = -1;
  211. skge->speed = -1;
  212. } else {
  213. u32 setting;
  214. switch (ecmd->speed) {
  215. case SPEED_1000:
  216. if (ecmd->duplex == DUPLEX_FULL)
  217. setting = SUPPORTED_1000baseT_Full;
  218. else if (ecmd->duplex == DUPLEX_HALF)
  219. setting = SUPPORTED_1000baseT_Half;
  220. else
  221. return -EINVAL;
  222. break;
  223. case SPEED_100:
  224. if (ecmd->duplex == DUPLEX_FULL)
  225. setting = SUPPORTED_100baseT_Full;
  226. else if (ecmd->duplex == DUPLEX_HALF)
  227. setting = SUPPORTED_100baseT_Half;
  228. else
  229. return -EINVAL;
  230. break;
  231. case SPEED_10:
  232. if (ecmd->duplex == DUPLEX_FULL)
  233. setting = SUPPORTED_10baseT_Full;
  234. else if (ecmd->duplex == DUPLEX_HALF)
  235. setting = SUPPORTED_10baseT_Half;
  236. else
  237. return -EINVAL;
  238. break;
  239. default:
  240. return -EINVAL;
  241. }
  242. if ((setting & supported) == 0)
  243. return -EINVAL;
  244. skge->speed = ecmd->speed;
  245. skge->duplex = ecmd->duplex;
  246. }
  247. skge->autoneg = ecmd->autoneg;
  248. skge->advertising = ecmd->advertising;
  249. if (netif_running(dev)) {
  250. skge_down(dev);
  251. skge_up(dev);
  252. }
  253. return (0);
  254. }
  255. static void skge_get_drvinfo(struct net_device *dev,
  256. struct ethtool_drvinfo *info)
  257. {
  258. struct skge_port *skge = netdev_priv(dev);
  259. strcpy(info->driver, DRV_NAME);
  260. strcpy(info->version, DRV_VERSION);
  261. strcpy(info->fw_version, "N/A");
  262. strcpy(info->bus_info, pci_name(skge->hw->pdev));
  263. }
  264. static const struct skge_stat {
  265. char name[ETH_GSTRING_LEN];
  266. u16 xmac_offset;
  267. u16 gma_offset;
  268. } skge_stats[] = {
  269. { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
  270. { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
  271. { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
  272. { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
  273. { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
  274. { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
  275. { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
  276. { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
  277. { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
  278. { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
  279. { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
  280. { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
  281. { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
  282. { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
  283. { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
  284. { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
  285. { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  286. { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
  287. { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
  288. { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
  289. { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
  290. };
  291. static int skge_get_stats_count(struct net_device *dev)
  292. {
  293. return ARRAY_SIZE(skge_stats);
  294. }
  295. static void skge_get_ethtool_stats(struct net_device *dev,
  296. struct ethtool_stats *stats, u64 *data)
  297. {
  298. struct skge_port *skge = netdev_priv(dev);
  299. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  300. genesis_get_stats(skge, data);
  301. else
  302. yukon_get_stats(skge, data);
  303. }
  304. /* Use hardware MIB variables for critical path statistics and
  305. * transmit feedback not reported at interrupt.
  306. * Other errors are accounted for in interrupt handler.
  307. */
  308. static struct net_device_stats *skge_get_stats(struct net_device *dev)
  309. {
  310. struct skge_port *skge = netdev_priv(dev);
  311. u64 data[ARRAY_SIZE(skge_stats)];
  312. if (skge->hw->chip_id == CHIP_ID_GENESIS)
  313. genesis_get_stats(skge, data);
  314. else
  315. yukon_get_stats(skge, data);
  316. skge->net_stats.tx_bytes = data[0];
  317. skge->net_stats.rx_bytes = data[1];
  318. skge->net_stats.tx_packets = data[2] + data[4] + data[6];
  319. skge->net_stats.rx_packets = data[3] + data[5] + data[7];
  320. skge->net_stats.multicast = data[5] + data[7];
  321. skge->net_stats.collisions = data[10];
  322. skge->net_stats.tx_aborted_errors = data[12];
  323. return &skge->net_stats;
  324. }
  325. static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  326. {
  327. int i;
  328. switch (stringset) {
  329. case ETH_SS_STATS:
  330. for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
  331. memcpy(data + i * ETH_GSTRING_LEN,
  332. skge_stats[i].name, ETH_GSTRING_LEN);
  333. break;
  334. }
  335. }
  336. static void skge_get_ring_param(struct net_device *dev,
  337. struct ethtool_ringparam *p)
  338. {
  339. struct skge_port *skge = netdev_priv(dev);
  340. p->rx_max_pending = MAX_RX_RING_SIZE;
  341. p->tx_max_pending = MAX_TX_RING_SIZE;
  342. p->rx_mini_max_pending = 0;
  343. p->rx_jumbo_max_pending = 0;
  344. p->rx_pending = skge->rx_ring.count;
  345. p->tx_pending = skge->tx_ring.count;
  346. p->rx_mini_pending = 0;
  347. p->rx_jumbo_pending = 0;
  348. }
  349. static int skge_set_ring_param(struct net_device *dev,
  350. struct ethtool_ringparam *p)
  351. {
  352. struct skge_port *skge = netdev_priv(dev);
  353. if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
  354. p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
  355. return -EINVAL;
  356. skge->rx_ring.count = p->rx_pending;
  357. skge->tx_ring.count = p->tx_pending;
  358. if (netif_running(dev)) {
  359. skge_down(dev);
  360. skge_up(dev);
  361. }
  362. return 0;
  363. }
  364. static u32 skge_get_msglevel(struct net_device *netdev)
  365. {
  366. struct skge_port *skge = netdev_priv(netdev);
  367. return skge->msg_enable;
  368. }
  369. static void skge_set_msglevel(struct net_device *netdev, u32 value)
  370. {
  371. struct skge_port *skge = netdev_priv(netdev);
  372. skge->msg_enable = value;
  373. }
  374. static int skge_nway_reset(struct net_device *dev)
  375. {
  376. struct skge_port *skge = netdev_priv(dev);
  377. struct skge_hw *hw = skge->hw;
  378. int port = skge->port;
  379. if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
  380. return -EINVAL;
  381. spin_lock_bh(&hw->phy_lock);
  382. if (hw->chip_id == CHIP_ID_GENESIS) {
  383. genesis_reset(hw, port);
  384. genesis_mac_init(hw, port);
  385. } else {
  386. yukon_reset(hw, port);
  387. yukon_init(hw, port);
  388. }
  389. spin_unlock_bh(&hw->phy_lock);
  390. return 0;
  391. }
  392. static int skge_set_sg(struct net_device *dev, u32 data)
  393. {
  394. struct skge_port *skge = netdev_priv(dev);
  395. struct skge_hw *hw = skge->hw;
  396. if (hw->chip_id == CHIP_ID_GENESIS && data)
  397. return -EOPNOTSUPP;
  398. return ethtool_op_set_sg(dev, data);
  399. }
  400. static int skge_set_tx_csum(struct net_device *dev, u32 data)
  401. {
  402. struct skge_port *skge = netdev_priv(dev);
  403. struct skge_hw *hw = skge->hw;
  404. if (hw->chip_id == CHIP_ID_GENESIS && data)
  405. return -EOPNOTSUPP;
  406. return ethtool_op_set_tx_csum(dev, data);
  407. }
  408. static u32 skge_get_rx_csum(struct net_device *dev)
  409. {
  410. struct skge_port *skge = netdev_priv(dev);
  411. return skge->rx_csum;
  412. }
  413. /* Only Yukon supports checksum offload. */
  414. static int skge_set_rx_csum(struct net_device *dev, u32 data)
  415. {
  416. struct skge_port *skge = netdev_priv(dev);
  417. if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
  418. return -EOPNOTSUPP;
  419. skge->rx_csum = data;
  420. return 0;
  421. }
  422. static void skge_get_pauseparam(struct net_device *dev,
  423. struct ethtool_pauseparam *ecmd)
  424. {
  425. struct skge_port *skge = netdev_priv(dev);
  426. ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
  427. || (skge->flow_control == FLOW_MODE_SYMMETRIC);
  428. ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
  429. || (skge->flow_control == FLOW_MODE_SYMMETRIC);
  430. ecmd->autoneg = skge->autoneg;
  431. }
  432. static int skge_set_pauseparam(struct net_device *dev,
  433. struct ethtool_pauseparam *ecmd)
  434. {
  435. struct skge_port *skge = netdev_priv(dev);
  436. skge->autoneg = ecmd->autoneg;
  437. if (ecmd->rx_pause && ecmd->tx_pause)
  438. skge->flow_control = FLOW_MODE_SYMMETRIC;
  439. else if (ecmd->rx_pause && !ecmd->tx_pause)
  440. skge->flow_control = FLOW_MODE_REM_SEND;
  441. else if (!ecmd->rx_pause && ecmd->tx_pause)
  442. skge->flow_control = FLOW_MODE_LOC_SEND;
  443. else
  444. skge->flow_control = FLOW_MODE_NONE;
  445. if (netif_running(dev)) {
  446. skge_down(dev);
  447. skge_up(dev);
  448. }
  449. return 0;
  450. }
  451. /* Chip internal frequency for clock calculations */
  452. static inline u32 hwkhz(const struct skge_hw *hw)
  453. {
  454. if (hw->chip_id == CHIP_ID_GENESIS)
  455. return 53215; /* or: 53.125 MHz */
  456. else
  457. return 78215; /* or: 78.125 MHz */
  458. }
  459. /* Chip hz to microseconds */
  460. static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
  461. {
  462. return (ticks * 1000) / hwkhz(hw);
  463. }
  464. /* Microseconds to chip hz */
  465. static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
  466. {
  467. return hwkhz(hw) * usec / 1000;
  468. }
  469. static int skge_get_coalesce(struct net_device *dev,
  470. struct ethtool_coalesce *ecmd)
  471. {
  472. struct skge_port *skge = netdev_priv(dev);
  473. struct skge_hw *hw = skge->hw;
  474. int port = skge->port;
  475. ecmd->rx_coalesce_usecs = 0;
  476. ecmd->tx_coalesce_usecs = 0;
  477. if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
  478. u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
  479. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  480. if (msk & rxirqmask[port])
  481. ecmd->rx_coalesce_usecs = delay;
  482. if (msk & txirqmask[port])
  483. ecmd->tx_coalesce_usecs = delay;
  484. }
  485. return 0;
  486. }
  487. /* Note: interrupt timer is per board, but can turn on/off per port */
  488. static int skge_set_coalesce(struct net_device *dev,
  489. struct ethtool_coalesce *ecmd)
  490. {
  491. struct skge_port *skge = netdev_priv(dev);
  492. struct skge_hw *hw = skge->hw;
  493. int port = skge->port;
  494. u32 msk = skge_read32(hw, B2_IRQM_MSK);
  495. u32 delay = 25;
  496. if (ecmd->rx_coalesce_usecs == 0)
  497. msk &= ~rxirqmask[port];
  498. else if (ecmd->rx_coalesce_usecs < 25 ||
  499. ecmd->rx_coalesce_usecs > 33333)
  500. return -EINVAL;
  501. else {
  502. msk |= rxirqmask[port];
  503. delay = ecmd->rx_coalesce_usecs;
  504. }
  505. if (ecmd->tx_coalesce_usecs == 0)
  506. msk &= ~txirqmask[port];
  507. else if (ecmd->tx_coalesce_usecs < 25 ||
  508. ecmd->tx_coalesce_usecs > 33333)
  509. return -EINVAL;
  510. else {
  511. msk |= txirqmask[port];
  512. delay = min(delay, ecmd->rx_coalesce_usecs);
  513. }
  514. skge_write32(hw, B2_IRQM_MSK, msk);
  515. if (msk == 0)
  516. skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
  517. else {
  518. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
  519. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  520. }
  521. return 0;
  522. }
  523. enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
  524. static void skge_led(struct skge_port *skge, enum led_mode mode)
  525. {
  526. struct skge_hw *hw = skge->hw;
  527. int port = skge->port;
  528. spin_lock_bh(&hw->phy_lock);
  529. if (hw->chip_id == CHIP_ID_GENESIS) {
  530. switch (mode) {
  531. case LED_MODE_OFF:
  532. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
  533. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  534. skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
  535. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
  536. break;
  537. case LED_MODE_ON:
  538. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
  539. skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
  540. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  541. skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
  542. break;
  543. case LED_MODE_TST:
  544. skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
  545. skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
  546. skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
  547. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
  548. break;
  549. }
  550. } else {
  551. switch (mode) {
  552. case LED_MODE_OFF:
  553. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  554. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  555. PHY_M_LED_MO_DUP(MO_LED_OFF) |
  556. PHY_M_LED_MO_10(MO_LED_OFF) |
  557. PHY_M_LED_MO_100(MO_LED_OFF) |
  558. PHY_M_LED_MO_1000(MO_LED_OFF) |
  559. PHY_M_LED_MO_RX(MO_LED_OFF));
  560. break;
  561. case LED_MODE_ON:
  562. gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
  563. PHY_M_LED_PULS_DUR(PULS_170MS) |
  564. PHY_M_LED_BLINK_RT(BLINK_84MS) |
  565. PHY_M_LEDC_TX_CTRL |
  566. PHY_M_LEDC_DP_CTRL);
  567. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  568. PHY_M_LED_MO_RX(MO_LED_OFF) |
  569. (skge->speed == SPEED_100 ?
  570. PHY_M_LED_MO_100(MO_LED_ON) : 0));
  571. break;
  572. case LED_MODE_TST:
  573. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  574. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  575. PHY_M_LED_MO_DUP(MO_LED_ON) |
  576. PHY_M_LED_MO_10(MO_LED_ON) |
  577. PHY_M_LED_MO_100(MO_LED_ON) |
  578. PHY_M_LED_MO_1000(MO_LED_ON) |
  579. PHY_M_LED_MO_RX(MO_LED_ON));
  580. }
  581. }
  582. spin_unlock_bh(&hw->phy_lock);
  583. }
  584. /* blink LED's for finding board */
  585. static int skge_phys_id(struct net_device *dev, u32 data)
  586. {
  587. struct skge_port *skge = netdev_priv(dev);
  588. unsigned long ms;
  589. enum led_mode mode = LED_MODE_TST;
  590. if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
  591. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
  592. else
  593. ms = data * 1000;
  594. while (ms > 0) {
  595. skge_led(skge, mode);
  596. mode ^= LED_MODE_TST;
  597. if (msleep_interruptible(BLINK_MS))
  598. break;
  599. ms -= BLINK_MS;
  600. }
  601. /* back to regular LED state */
  602. skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
  603. return 0;
  604. }
  605. static struct ethtool_ops skge_ethtool_ops = {
  606. .get_settings = skge_get_settings,
  607. .set_settings = skge_set_settings,
  608. .get_drvinfo = skge_get_drvinfo,
  609. .get_regs_len = skge_get_regs_len,
  610. .get_regs = skge_get_regs,
  611. .get_wol = skge_get_wol,
  612. .set_wol = skge_set_wol,
  613. .get_msglevel = skge_get_msglevel,
  614. .set_msglevel = skge_set_msglevel,
  615. .nway_reset = skge_nway_reset,
  616. .get_link = ethtool_op_get_link,
  617. .get_ringparam = skge_get_ring_param,
  618. .set_ringparam = skge_set_ring_param,
  619. .get_pauseparam = skge_get_pauseparam,
  620. .set_pauseparam = skge_set_pauseparam,
  621. .get_coalesce = skge_get_coalesce,
  622. .set_coalesce = skge_set_coalesce,
  623. .get_sg = ethtool_op_get_sg,
  624. .set_sg = skge_set_sg,
  625. .get_tx_csum = ethtool_op_get_tx_csum,
  626. .set_tx_csum = skge_set_tx_csum,
  627. .get_rx_csum = skge_get_rx_csum,
  628. .set_rx_csum = skge_set_rx_csum,
  629. .get_strings = skge_get_strings,
  630. .phys_id = skge_phys_id,
  631. .get_stats_count = skge_get_stats_count,
  632. .get_ethtool_stats = skge_get_ethtool_stats,
  633. };
  634. /*
  635. * Allocate ring elements and chain them together
  636. * One-to-one association of board descriptors with ring elements
  637. */
  638. static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
  639. {
  640. struct skge_tx_desc *d;
  641. struct skge_element *e;
  642. int i;
  643. ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
  644. if (!ring->start)
  645. return -ENOMEM;
  646. for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
  647. e->desc = d;
  648. e->skb = NULL;
  649. if (i == ring->count - 1) {
  650. e->next = ring->start;
  651. d->next_offset = base;
  652. } else {
  653. e->next = e + 1;
  654. d->next_offset = base + (i+1) * sizeof(*d);
  655. }
  656. }
  657. ring->to_use = ring->to_clean = ring->start;
  658. return 0;
  659. }
  660. static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
  661. {
  662. struct sk_buff *skb = dev_alloc_skb(size);
  663. if (likely(skb)) {
  664. skb->dev = dev;
  665. skb_reserve(skb, NET_IP_ALIGN);
  666. }
  667. return skb;
  668. }
  669. /* Allocate and setup a new buffer for receiving */
  670. static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
  671. struct sk_buff *skb, unsigned int bufsize)
  672. {
  673. struct skge_rx_desc *rd = e->desc;
  674. u64 map;
  675. map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
  676. PCI_DMA_FROMDEVICE);
  677. rd->dma_lo = map;
  678. rd->dma_hi = map >> 32;
  679. e->skb = skb;
  680. rd->csum1_start = ETH_HLEN;
  681. rd->csum2_start = ETH_HLEN;
  682. rd->csum1 = 0;
  683. rd->csum2 = 0;
  684. wmb();
  685. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
  686. pci_unmap_addr_set(e, mapaddr, map);
  687. pci_unmap_len_set(e, maplen, bufsize);
  688. }
  689. /* Resume receiving using existing skb,
  690. * Note: DMA address is not changed by chip.
  691. * MTU not changed while receiver active.
  692. */
  693. static void skge_rx_reuse(struct skge_element *e, unsigned int size)
  694. {
  695. struct skge_rx_desc *rd = e->desc;
  696. rd->csum2 = 0;
  697. rd->csum2_start = ETH_HLEN;
  698. wmb();
  699. rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
  700. }
  701. /* Free all buffers in receive ring, assumes receiver stopped */
  702. static void skge_rx_clean(struct skge_port *skge)
  703. {
  704. struct skge_hw *hw = skge->hw;
  705. struct skge_ring *ring = &skge->rx_ring;
  706. struct skge_element *e;
  707. e = ring->start;
  708. do {
  709. struct skge_rx_desc *rd = e->desc;
  710. rd->control = 0;
  711. if (e->skb) {
  712. pci_unmap_single(hw->pdev,
  713. pci_unmap_addr(e, mapaddr),
  714. pci_unmap_len(e, maplen),
  715. PCI_DMA_FROMDEVICE);
  716. dev_kfree_skb(e->skb);
  717. e->skb = NULL;
  718. }
  719. } while ((e = e->next) != ring->start);
  720. }
  721. /* Allocate buffers for receive ring
  722. * For receive: to_clean is next received frame.
  723. */
  724. static int skge_rx_fill(struct skge_port *skge)
  725. {
  726. struct skge_ring *ring = &skge->rx_ring;
  727. struct skge_element *e;
  728. unsigned int bufsize = skge->rx_buf_size;
  729. e = ring->start;
  730. do {
  731. struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
  732. if (!skb)
  733. return -ENOMEM;
  734. skge_rx_setup(skge, e, skb, bufsize);
  735. } while ( (e = e->next) != ring->start);
  736. ring->to_clean = ring->start;
  737. return 0;
  738. }
  739. static void skge_link_up(struct skge_port *skge)
  740. {
  741. netif_carrier_on(skge->netdev);
  742. if (skge->tx_avail > MAX_SKB_FRAGS + 1)
  743. netif_wake_queue(skge->netdev);
  744. if (netif_msg_link(skge))
  745. printk(KERN_INFO PFX
  746. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  747. skge->netdev->name, skge->speed,
  748. skge->duplex == DUPLEX_FULL ? "full" : "half",
  749. (skge->flow_control == FLOW_MODE_NONE) ? "none" :
  750. (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
  751. (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
  752. (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
  753. "unknown");
  754. }
  755. static void skge_link_down(struct skge_port *skge)
  756. {
  757. netif_carrier_off(skge->netdev);
  758. netif_stop_queue(skge->netdev);
  759. if (netif_msg_link(skge))
  760. printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
  761. }
  762. static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
  763. {
  764. int i;
  765. u16 v;
  766. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  767. v = xm_read16(hw, port, XM_PHY_DATA);
  768. /* Need to wait for external PHY */
  769. for (i = 0; i < PHY_RETRIES; i++) {
  770. udelay(1);
  771. if (xm_read16(hw, port, XM_MMU_CMD)
  772. & XM_MMU_PHY_RDY)
  773. goto ready;
  774. }
  775. printk(KERN_WARNING PFX "%s: phy read timed out\n",
  776. hw->dev[port]->name);
  777. return 0;
  778. ready:
  779. v = xm_read16(hw, port, XM_PHY_DATA);
  780. return v;
  781. }
  782. static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  783. {
  784. int i;
  785. xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
  786. for (i = 0; i < PHY_RETRIES; i++) {
  787. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  788. goto ready;
  789. udelay(1);
  790. }
  791. printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
  792. hw->dev[port]->name);
  793. ready:
  794. xm_write16(hw, port, XM_PHY_DATA, val);
  795. for (i = 0; i < PHY_RETRIES; i++) {
  796. udelay(1);
  797. if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
  798. return;
  799. }
  800. printk(KERN_WARNING PFX "%s: phy write timed out\n",
  801. hw->dev[port]->name);
  802. }
  803. static void genesis_init(struct skge_hw *hw)
  804. {
  805. /* set blink source counter */
  806. skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
  807. skge_write8(hw, B2_BSC_CTRL, BSC_START);
  808. /* configure mac arbiter */
  809. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  810. /* configure mac arbiter timeout values */
  811. skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
  812. skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
  813. skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
  814. skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
  815. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  816. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  817. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  818. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  819. /* configure packet arbiter timeout */
  820. skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
  821. skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
  822. skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
  823. skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
  824. skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
  825. }
  826. static void genesis_reset(struct skge_hw *hw, int port)
  827. {
  828. const u8 zero[8] = { 0 };
  829. /* reset the statistics module */
  830. xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
  831. xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
  832. xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
  833. xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
  834. xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
  835. /* disable Broadcom PHY IRQ */
  836. xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
  837. xm_outhash(hw, port, XM_HSM, zero);
  838. }
  839. /* Convert mode to MII values */
  840. static const u16 phy_pause_map[] = {
  841. [FLOW_MODE_NONE] = 0,
  842. [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
  843. [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
  844. [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
  845. };
  846. /* Check status of Broadcom phy link */
  847. static void bcom_check_link(struct skge_hw *hw, int port)
  848. {
  849. struct net_device *dev = hw->dev[port];
  850. struct skge_port *skge = netdev_priv(dev);
  851. u16 status;
  852. /* read twice because of latch */
  853. (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
  854. status = xm_phy_read(hw, port, PHY_BCOM_STAT);
  855. pr_debug("bcom_check_link status=0x%x\n", status);
  856. if ((status & PHY_ST_LSYNC) == 0) {
  857. u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
  858. cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  859. xm_write16(hw, port, XM_MMU_CMD, cmd);
  860. /* dummy read to ensure writing */
  861. (void) xm_read16(hw, port, XM_MMU_CMD);
  862. if (netif_carrier_ok(dev))
  863. skge_link_down(skge);
  864. } else {
  865. if (skge->autoneg == AUTONEG_ENABLE &&
  866. (status & PHY_ST_AN_OVER)) {
  867. u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
  868. u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
  869. if (lpa & PHY_B_AN_RF) {
  870. printk(KERN_NOTICE PFX "%s: remote fault\n",
  871. dev->name);
  872. return;
  873. }
  874. /* Check Duplex mismatch */
  875. switch (aux & PHY_B_AS_AN_RES_MSK) {
  876. case PHY_B_RES_1000FD:
  877. skge->duplex = DUPLEX_FULL;
  878. break;
  879. case PHY_B_RES_1000HD:
  880. skge->duplex = DUPLEX_HALF;
  881. break;
  882. default:
  883. printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
  884. dev->name);
  885. return;
  886. }
  887. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  888. switch (aux & PHY_B_AS_PAUSE_MSK) {
  889. case PHY_B_AS_PAUSE_MSK:
  890. skge->flow_control = FLOW_MODE_SYMMETRIC;
  891. break;
  892. case PHY_B_AS_PRR:
  893. skge->flow_control = FLOW_MODE_REM_SEND;
  894. break;
  895. case PHY_B_AS_PRT:
  896. skge->flow_control = FLOW_MODE_LOC_SEND;
  897. break;
  898. default:
  899. skge->flow_control = FLOW_MODE_NONE;
  900. }
  901. skge->speed = SPEED_1000;
  902. }
  903. if (!netif_carrier_ok(dev))
  904. genesis_link_up(skge);
  905. }
  906. }
  907. /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
  908. * Phy on for 100 or 10Mbit operation
  909. */
  910. static void bcom_phy_init(struct skge_port *skge, int jumbo)
  911. {
  912. struct skge_hw *hw = skge->hw;
  913. int port = skge->port;
  914. int i;
  915. u16 id1, r, ext, ctl;
  916. /* magic workaround patterns for Broadcom */
  917. static const struct {
  918. u16 reg;
  919. u16 val;
  920. } A1hack[] = {
  921. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
  922. { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
  923. { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
  924. { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
  925. }, C0hack[] = {
  926. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
  927. { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
  928. };
  929. pr_debug("bcom_phy_init\n");
  930. /* read Id from external PHY (all have the same address) */
  931. id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
  932. /* Optimize MDIO transfer by suppressing preamble. */
  933. r = xm_read16(hw, port, XM_MMU_CMD);
  934. r |= XM_MMU_NO_PRE;
  935. xm_write16(hw, port, XM_MMU_CMD,r);
  936. switch (id1) {
  937. case PHY_BCOM_ID1_C0:
  938. /*
  939. * Workaround BCOM Errata for the C0 type.
  940. * Write magic patterns to reserved registers.
  941. */
  942. for (i = 0; i < ARRAY_SIZE(C0hack); i++)
  943. xm_phy_write(hw, port,
  944. C0hack[i].reg, C0hack[i].val);
  945. break;
  946. case PHY_BCOM_ID1_A1:
  947. /*
  948. * Workaround BCOM Errata for the A1 type.
  949. * Write magic patterns to reserved registers.
  950. */
  951. for (i = 0; i < ARRAY_SIZE(A1hack); i++)
  952. xm_phy_write(hw, port,
  953. A1hack[i].reg, A1hack[i].val);
  954. break;
  955. }
  956. /*
  957. * Workaround BCOM Errata (#10523) for all BCom PHYs.
  958. * Disable Power Management after reset.
  959. */
  960. r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
  961. r |= PHY_B_AC_DIS_PM;
  962. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
  963. /* Dummy read */
  964. xm_read16(hw, port, XM_ISRC);
  965. ext = PHY_B_PEC_EN_LTR; /* enable tx led */
  966. ctl = PHY_CT_SP1000; /* always 1000mbit */
  967. if (skge->autoneg == AUTONEG_ENABLE) {
  968. /*
  969. * Workaround BCOM Errata #1 for the C5 type.
  970. * 1000Base-T Link Acquisition Failure in Slave Mode
  971. * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
  972. */
  973. u16 adv = PHY_B_1000C_RD;
  974. if (skge->advertising & ADVERTISED_1000baseT_Half)
  975. adv |= PHY_B_1000C_AHD;
  976. if (skge->advertising & ADVERTISED_1000baseT_Full)
  977. adv |= PHY_B_1000C_AFD;
  978. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
  979. ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  980. } else {
  981. if (skge->duplex == DUPLEX_FULL)
  982. ctl |= PHY_CT_DUP_MD;
  983. /* Force to slave */
  984. xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
  985. }
  986. /* Set autonegotiation pause parameters */
  987. xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
  988. phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
  989. /* Handle Jumbo frames */
  990. if (jumbo) {
  991. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  992. PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
  993. ext |= PHY_B_PEC_HIGH_LA;
  994. }
  995. xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
  996. xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
  997. /* Use link status change interrrupt */
  998. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  999. bcom_check_link(hw, port);
  1000. }
  1001. static void genesis_mac_init(struct skge_hw *hw, int port)
  1002. {
  1003. struct net_device *dev = hw->dev[port];
  1004. struct skge_port *skge = netdev_priv(dev);
  1005. int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
  1006. int i;
  1007. u32 r;
  1008. const u8 zero[6] = { 0 };
  1009. /* Clear MIB counters */
  1010. xm_write16(hw, port, XM_STAT_CMD,
  1011. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1012. /* Clear two times according to Errata #3 */
  1013. xm_write16(hw, port, XM_STAT_CMD,
  1014. XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  1015. /* Unreset the XMAC. */
  1016. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1017. /*
  1018. * Perform additional initialization for external PHYs,
  1019. * namely for the 1000baseTX cards that use the XMAC's
  1020. * GMII mode.
  1021. */
  1022. /* Take external Phy out of reset */
  1023. r = skge_read32(hw, B2_GP_IO);
  1024. if (port == 0)
  1025. r |= GP_DIR_0|GP_IO_0;
  1026. else
  1027. r |= GP_DIR_2|GP_IO_2;
  1028. skge_write32(hw, B2_GP_IO, r);
  1029. skge_read32(hw, B2_GP_IO);
  1030. /* Enable GMII interfac */
  1031. xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
  1032. bcom_phy_init(skge, jumbo);
  1033. /* Set Station Address */
  1034. xm_outaddr(hw, port, XM_SA, dev->dev_addr);
  1035. /* We don't use match addresses so clear */
  1036. for (i = 1; i < 16; i++)
  1037. xm_outaddr(hw, port, XM_EXM(i), zero);
  1038. /* configure Rx High Water Mark (XM_RX_HI_WM) */
  1039. xm_write16(hw, port, XM_RX_HI_WM, 1450);
  1040. /* We don't need the FCS appended to the packet. */
  1041. r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
  1042. if (jumbo)
  1043. r |= XM_RX_BIG_PK_OK;
  1044. if (skge->duplex == DUPLEX_HALF) {
  1045. /*
  1046. * If in manual half duplex mode the other side might be in
  1047. * full duplex mode, so ignore if a carrier extension is not seen
  1048. * on frames received
  1049. */
  1050. r |= XM_RX_DIS_CEXT;
  1051. }
  1052. xm_write16(hw, port, XM_RX_CMD, r);
  1053. /* We want short frames padded to 60 bytes. */
  1054. xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
  1055. /*
  1056. * Bump up the transmit threshold. This helps hold off transmit
  1057. * underruns when we're blasting traffic from both ports at once.
  1058. */
  1059. xm_write16(hw, port, XM_TX_THR, 512);
  1060. /*
  1061. * Enable the reception of all error frames. This is is
  1062. * a necessary evil due to the design of the XMAC. The
  1063. * XMAC's receive FIFO is only 8K in size, however jumbo
  1064. * frames can be up to 9000 bytes in length. When bad
  1065. * frame filtering is enabled, the XMAC's RX FIFO operates
  1066. * in 'store and forward' mode. For this to work, the
  1067. * entire frame has to fit into the FIFO, but that means
  1068. * that jumbo frames larger than 8192 bytes will be
  1069. * truncated. Disabling all bad frame filtering causes
  1070. * the RX FIFO to operate in streaming mode, in which
  1071. * case the XMAC will start transfering frames out of the
  1072. * RX FIFO as soon as the FIFO threshold is reached.
  1073. */
  1074. xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
  1075. /*
  1076. * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
  1077. * - Enable all bits excepting 'Octets Rx OK Low CntOv'
  1078. * and 'Octets Rx OK Hi Cnt Ov'.
  1079. */
  1080. xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
  1081. /*
  1082. * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
  1083. * - Enable all bits excepting 'Octets Tx OK Low CntOv'
  1084. * and 'Octets Tx OK Hi Cnt Ov'.
  1085. */
  1086. xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
  1087. /* Configure MAC arbiter */
  1088. skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
  1089. /* configure timeout values */
  1090. skge_write8(hw, B3_MA_TOINI_RX1, 72);
  1091. skge_write8(hw, B3_MA_TOINI_RX2, 72);
  1092. skge_write8(hw, B3_MA_TOINI_TX1, 72);
  1093. skge_write8(hw, B3_MA_TOINI_TX2, 72);
  1094. skge_write8(hw, B3_MA_RCINI_RX1, 0);
  1095. skge_write8(hw, B3_MA_RCINI_RX2, 0);
  1096. skge_write8(hw, B3_MA_RCINI_TX1, 0);
  1097. skge_write8(hw, B3_MA_RCINI_TX2, 0);
  1098. /* Configure Rx MAC FIFO */
  1099. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
  1100. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
  1101. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
  1102. /* Configure Tx MAC FIFO */
  1103. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
  1104. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
  1105. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
  1106. if (jumbo) {
  1107. /* Enable frame flushing if jumbo frames used */
  1108. skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
  1109. } else {
  1110. /* enable timeout timers if normal frames */
  1111. skge_write16(hw, B3_PA_CTRL,
  1112. (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
  1113. }
  1114. }
  1115. static void genesis_stop(struct skge_port *skge)
  1116. {
  1117. struct skge_hw *hw = skge->hw;
  1118. int port = skge->port;
  1119. u32 reg;
  1120. /* Clear Tx packet arbiter timeout IRQ */
  1121. skge_write16(hw, B3_PA_CTRL,
  1122. port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
  1123. /*
  1124. * If the transfer stucks at the MAC the STOP command will not
  1125. * terminate if we don't flush the XMAC's transmit FIFO !
  1126. */
  1127. xm_write32(hw, port, XM_MODE,
  1128. xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
  1129. /* Reset the MAC */
  1130. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
  1131. /* For external PHYs there must be special handling */
  1132. reg = skge_read32(hw, B2_GP_IO);
  1133. if (port == 0) {
  1134. reg |= GP_DIR_0;
  1135. reg &= ~GP_IO_0;
  1136. } else {
  1137. reg |= GP_DIR_2;
  1138. reg &= ~GP_IO_2;
  1139. }
  1140. skge_write32(hw, B2_GP_IO, reg);
  1141. skge_read32(hw, B2_GP_IO);
  1142. xm_write16(hw, port, XM_MMU_CMD,
  1143. xm_read16(hw, port, XM_MMU_CMD)
  1144. & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
  1145. xm_read16(hw, port, XM_MMU_CMD);
  1146. }
  1147. static void genesis_get_stats(struct skge_port *skge, u64 *data)
  1148. {
  1149. struct skge_hw *hw = skge->hw;
  1150. int port = skge->port;
  1151. int i;
  1152. unsigned long timeout = jiffies + HZ;
  1153. xm_write16(hw, port,
  1154. XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
  1155. /* wait for update to complete */
  1156. while (xm_read16(hw, port, XM_STAT_CMD)
  1157. & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
  1158. if (time_after(jiffies, timeout))
  1159. break;
  1160. udelay(10);
  1161. }
  1162. /* special case for 64 bit octet counter */
  1163. data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
  1164. | xm_read32(hw, port, XM_TXO_OK_LO);
  1165. data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
  1166. | xm_read32(hw, port, XM_RXO_OK_LO);
  1167. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1168. data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
  1169. }
  1170. static void genesis_mac_intr(struct skge_hw *hw, int port)
  1171. {
  1172. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1173. u16 status = xm_read16(hw, port, XM_ISRC);
  1174. if (netif_msg_intr(skge))
  1175. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1176. skge->netdev->name, status);
  1177. if (status & XM_IS_TXF_UR) {
  1178. xm_write32(hw, port, XM_MODE, XM_MD_FTF);
  1179. ++skge->net_stats.tx_fifo_errors;
  1180. }
  1181. if (status & XM_IS_RXF_OV) {
  1182. xm_write32(hw, port, XM_MODE, XM_MD_FRF);
  1183. ++skge->net_stats.rx_fifo_errors;
  1184. }
  1185. }
  1186. static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
  1187. {
  1188. int i;
  1189. gma_write16(hw, port, GM_SMI_DATA, val);
  1190. gma_write16(hw, port, GM_SMI_CTRL,
  1191. GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
  1192. for (i = 0; i < PHY_RETRIES; i++) {
  1193. udelay(1);
  1194. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  1195. break;
  1196. }
  1197. }
  1198. static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
  1199. {
  1200. int i;
  1201. gma_write16(hw, port, GM_SMI_CTRL,
  1202. GM_SMI_CT_PHY_AD(hw->phy_addr)
  1203. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  1204. for (i = 0; i < PHY_RETRIES; i++) {
  1205. udelay(1);
  1206. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
  1207. goto ready;
  1208. }
  1209. printk(KERN_WARNING PFX "%s: phy read timeout\n",
  1210. hw->dev[port]->name);
  1211. return 0;
  1212. ready:
  1213. return gma_read16(hw, port, GM_SMI_DATA);
  1214. }
  1215. static void genesis_link_up(struct skge_port *skge)
  1216. {
  1217. struct skge_hw *hw = skge->hw;
  1218. int port = skge->port;
  1219. u16 cmd;
  1220. u32 mode, msk;
  1221. pr_debug("genesis_link_up\n");
  1222. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1223. /*
  1224. * enabling pause frame reception is required for 1000BT
  1225. * because the XMAC is not reset if the link is going down
  1226. */
  1227. if (skge->flow_control == FLOW_MODE_NONE ||
  1228. skge->flow_control == FLOW_MODE_LOC_SEND)
  1229. /* Disable Pause Frame Reception */
  1230. cmd |= XM_MMU_IGN_PF;
  1231. else
  1232. /* Enable Pause Frame Reception */
  1233. cmd &= ~XM_MMU_IGN_PF;
  1234. xm_write16(hw, port, XM_MMU_CMD, cmd);
  1235. mode = xm_read32(hw, port, XM_MODE);
  1236. if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
  1237. skge->flow_control == FLOW_MODE_LOC_SEND) {
  1238. /*
  1239. * Configure Pause Frame Generation
  1240. * Use internal and external Pause Frame Generation.
  1241. * Sending pause frames is edge triggered.
  1242. * Send a Pause frame with the maximum pause time if
  1243. * internal oder external FIFO full condition occurs.
  1244. * Send a zero pause time frame to re-start transmission.
  1245. */
  1246. /* XM_PAUSE_DA = '010000C28001' (default) */
  1247. /* XM_MAC_PTIME = 0xffff (maximum) */
  1248. /* remember this value is defined in big endian (!) */
  1249. xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
  1250. mode |= XM_PAUSE_MODE;
  1251. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
  1252. } else {
  1253. /*
  1254. * disable pause frame generation is required for 1000BT
  1255. * because the XMAC is not reset if the link is going down
  1256. */
  1257. /* Disable Pause Mode in Mode Register */
  1258. mode &= ~XM_PAUSE_MODE;
  1259. skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
  1260. }
  1261. xm_write32(hw, port, XM_MODE, mode);
  1262. msk = XM_DEF_MSK;
  1263. /* disable GP0 interrupt bit for external Phy */
  1264. msk |= XM_IS_INP_ASS;
  1265. xm_write16(hw, port, XM_IMSK, msk);
  1266. xm_read16(hw, port, XM_ISRC);
  1267. /* get MMU Command Reg. */
  1268. cmd = xm_read16(hw, port, XM_MMU_CMD);
  1269. if (skge->duplex == DUPLEX_FULL)
  1270. cmd |= XM_MMU_GMII_FD;
  1271. /*
  1272. * Workaround BCOM Errata (#10523) for all BCom Phys
  1273. * Enable Power Management after link up
  1274. */
  1275. xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
  1276. xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
  1277. & ~PHY_B_AC_DIS_PM);
  1278. xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  1279. /* enable Rx/Tx */
  1280. xm_write16(hw, port, XM_MMU_CMD,
  1281. cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  1282. skge_link_up(skge);
  1283. }
  1284. static inline void bcom_phy_intr(struct skge_port *skge)
  1285. {
  1286. struct skge_hw *hw = skge->hw;
  1287. int port = skge->port;
  1288. u16 isrc;
  1289. isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
  1290. if (netif_msg_intr(skge))
  1291. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
  1292. skge->netdev->name, isrc);
  1293. if (isrc & PHY_B_IS_PSE)
  1294. printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
  1295. hw->dev[port]->name);
  1296. /* Workaround BCom Errata:
  1297. * enable and disable loopback mode if "NO HCD" occurs.
  1298. */
  1299. if (isrc & PHY_B_IS_NO_HDCL) {
  1300. u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
  1301. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1302. ctrl | PHY_CT_LOOP);
  1303. xm_phy_write(hw, port, PHY_BCOM_CTRL,
  1304. ctrl & ~PHY_CT_LOOP);
  1305. }
  1306. if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
  1307. bcom_check_link(hw, port);
  1308. }
  1309. /* Marvell Phy Initailization */
  1310. static void yukon_init(struct skge_hw *hw, int port)
  1311. {
  1312. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1313. u16 ctrl, ct1000, adv;
  1314. pr_debug("yukon_init\n");
  1315. if (skge->autoneg == AUTONEG_ENABLE) {
  1316. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  1317. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  1318. PHY_M_EC_MAC_S_MSK);
  1319. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  1320. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  1321. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  1322. }
  1323. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  1324. if (skge->autoneg == AUTONEG_DISABLE)
  1325. ctrl &= ~PHY_CT_ANE;
  1326. ctrl |= PHY_CT_RESET;
  1327. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1328. ctrl = 0;
  1329. ct1000 = 0;
  1330. adv = PHY_AN_CSMA;
  1331. if (skge->autoneg == AUTONEG_ENABLE) {
  1332. if (iscopper(hw)) {
  1333. if (skge->advertising & ADVERTISED_1000baseT_Full)
  1334. ct1000 |= PHY_M_1000C_AFD;
  1335. if (skge->advertising & ADVERTISED_1000baseT_Half)
  1336. ct1000 |= PHY_M_1000C_AHD;
  1337. if (skge->advertising & ADVERTISED_100baseT_Full)
  1338. adv |= PHY_M_AN_100_FD;
  1339. if (skge->advertising & ADVERTISED_100baseT_Half)
  1340. adv |= PHY_M_AN_100_HD;
  1341. if (skge->advertising & ADVERTISED_10baseT_Full)
  1342. adv |= PHY_M_AN_10_FD;
  1343. if (skge->advertising & ADVERTISED_10baseT_Half)
  1344. adv |= PHY_M_AN_10_HD;
  1345. } else /* special defines for FIBER (88E1011S only) */
  1346. adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
  1347. /* Set Flow-control capabilities */
  1348. adv |= phy_pause_map[skge->flow_control];
  1349. /* Restart Auto-negotiation */
  1350. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1351. } else {
  1352. /* forced speed/duplex settings */
  1353. ct1000 = PHY_M_1000C_MSE;
  1354. if (skge->duplex == DUPLEX_FULL)
  1355. ctrl |= PHY_CT_DUP_MD;
  1356. switch (skge->speed) {
  1357. case SPEED_1000:
  1358. ctrl |= PHY_CT_SP1000;
  1359. break;
  1360. case SPEED_100:
  1361. ctrl |= PHY_CT_SP100;
  1362. break;
  1363. }
  1364. ctrl |= PHY_CT_RESET;
  1365. }
  1366. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  1367. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  1368. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  1369. /* Enable phy interrupt on autonegotiation complete (or link up) */
  1370. if (skge->autoneg == AUTONEG_ENABLE)
  1371. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
  1372. else
  1373. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1374. }
  1375. static void yukon_reset(struct skge_hw *hw, int port)
  1376. {
  1377. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
  1378. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  1379. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  1380. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  1381. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  1382. gma_write16(hw, port, GM_RX_CTRL,
  1383. gma_read16(hw, port, GM_RX_CTRL)
  1384. | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1385. }
  1386. static void yukon_mac_init(struct skge_hw *hw, int port)
  1387. {
  1388. struct skge_port *skge = netdev_priv(hw->dev[port]);
  1389. int i;
  1390. u32 reg;
  1391. const u8 *addr = hw->dev[port]->dev_addr;
  1392. /* WA code for COMA mode -- set PHY reset */
  1393. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1394. hw->chip_rev >= CHIP_REV_YU_LITE_A3)
  1395. skge_write32(hw, B2_GP_IO,
  1396. (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
  1397. /* hard reset */
  1398. skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1399. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1400. /* WA code for COMA mode -- clear PHY reset */
  1401. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1402. hw->chip_rev >= CHIP_REV_YU_LITE_A3)
  1403. skge_write32(hw, B2_GP_IO,
  1404. (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
  1405. & ~GP_IO_9);
  1406. /* Set hardware config mode */
  1407. reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
  1408. GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
  1409. reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
  1410. /* Clear GMC reset */
  1411. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
  1412. skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
  1413. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
  1414. if (skge->autoneg == AUTONEG_DISABLE) {
  1415. reg = GM_GPCR_AU_ALL_DIS;
  1416. gma_write16(hw, port, GM_GP_CTRL,
  1417. gma_read16(hw, port, GM_GP_CTRL) | reg);
  1418. switch (skge->speed) {
  1419. case SPEED_1000:
  1420. reg |= GM_GPCR_SPEED_1000;
  1421. /* fallthru */
  1422. case SPEED_100:
  1423. reg |= GM_GPCR_SPEED_100;
  1424. }
  1425. if (skge->duplex == DUPLEX_FULL)
  1426. reg |= GM_GPCR_DUP_FULL;
  1427. } else
  1428. reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
  1429. switch (skge->flow_control) {
  1430. case FLOW_MODE_NONE:
  1431. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1432. reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1433. break;
  1434. case FLOW_MODE_LOC_SEND:
  1435. /* disable Rx flow-control */
  1436. reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
  1437. }
  1438. gma_write16(hw, port, GM_GP_CTRL, reg);
  1439. skge_read16(hw, GMAC_IRQ_SRC);
  1440. yukon_init(hw, port);
  1441. /* MIB clear */
  1442. reg = gma_read16(hw, port, GM_PHY_ADDR);
  1443. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  1444. for (i = 0; i < GM_MIB_CNT_SIZE; i++)
  1445. gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
  1446. gma_write16(hw, port, GM_PHY_ADDR, reg);
  1447. /* transmit control */
  1448. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  1449. /* receive control reg: unicast + multicast + no FCS */
  1450. gma_write16(hw, port, GM_RX_CTRL,
  1451. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  1452. /* transmit flow control */
  1453. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  1454. /* transmit parameter */
  1455. gma_write16(hw, port, GM_TX_PARAM,
  1456. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  1457. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  1458. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
  1459. /* serial mode register */
  1460. reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1461. if (hw->dev[port]->mtu > 1500)
  1462. reg |= GM_SMOD_JUMBO_ENA;
  1463. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  1464. /* physical address: used for pause frames */
  1465. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  1466. /* virtual address for data */
  1467. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  1468. /* enable interrupt mask for counter overflows */
  1469. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  1470. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  1471. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  1472. /* Initialize Mac Fifo */
  1473. /* Configure Rx MAC FIFO */
  1474. skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
  1475. reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  1476. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1477. hw->chip_rev >= CHIP_REV_YU_LITE_A3)
  1478. reg &= ~GMF_RX_F_FL_ON;
  1479. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  1480. skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
  1481. skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
  1482. /* Configure Tx MAC FIFO */
  1483. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  1484. skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  1485. }
  1486. static void yukon_stop(struct skge_port *skge)
  1487. {
  1488. struct skge_hw *hw = skge->hw;
  1489. int port = skge->port;
  1490. if (hw->chip_id == CHIP_ID_YUKON_LITE &&
  1491. hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
  1492. skge_write32(hw, B2_GP_IO,
  1493. skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
  1494. }
  1495. gma_write16(hw, port, GM_GP_CTRL,
  1496. gma_read16(hw, port, GM_GP_CTRL)
  1497. & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
  1498. gma_read16(hw, port, GM_GP_CTRL);
  1499. /* set GPHY Control reset */
  1500. skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1501. skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1502. }
  1503. static void yukon_get_stats(struct skge_port *skge, u64 *data)
  1504. {
  1505. struct skge_hw *hw = skge->hw;
  1506. int port = skge->port;
  1507. int i;
  1508. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  1509. | gma_read32(hw, port, GM_TXO_OK_LO);
  1510. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  1511. | gma_read32(hw, port, GM_RXO_OK_LO);
  1512. for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
  1513. data[i] = gma_read32(hw, port,
  1514. skge_stats[i].gma_offset);
  1515. }
  1516. static void yukon_mac_intr(struct skge_hw *hw, int port)
  1517. {
  1518. struct net_device *dev = hw->dev[port];
  1519. struct skge_port *skge = netdev_priv(dev);
  1520. u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1521. if (netif_msg_intr(skge))
  1522. printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
  1523. dev->name, status);
  1524. if (status & GM_IS_RX_FF_OR) {
  1525. ++skge->net_stats.rx_fifo_errors;
  1526. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1527. }
  1528. if (status & GM_IS_TX_FF_UR) {
  1529. ++skge->net_stats.tx_fifo_errors;
  1530. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1531. }
  1532. }
  1533. static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
  1534. {
  1535. switch (aux & PHY_M_PS_SPEED_MSK) {
  1536. case PHY_M_PS_SPEED_1000:
  1537. return SPEED_1000;
  1538. case PHY_M_PS_SPEED_100:
  1539. return SPEED_100;
  1540. default:
  1541. return SPEED_10;
  1542. }
  1543. }
  1544. static void yukon_link_up(struct skge_port *skge)
  1545. {
  1546. struct skge_hw *hw = skge->hw;
  1547. int port = skge->port;
  1548. u16 reg;
  1549. pr_debug("yukon_link_up\n");
  1550. /* Enable Transmit FIFO Underrun */
  1551. skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
  1552. reg = gma_read16(hw, port, GM_GP_CTRL);
  1553. if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
  1554. reg |= GM_GPCR_DUP_FULL;
  1555. /* enable Rx/Tx */
  1556. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1557. gma_write16(hw, port, GM_GP_CTRL, reg);
  1558. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
  1559. skge_link_up(skge);
  1560. }
  1561. static void yukon_link_down(struct skge_port *skge)
  1562. {
  1563. struct skge_hw *hw = skge->hw;
  1564. int port = skge->port;
  1565. u16 ctrl;
  1566. pr_debug("yukon_link_down\n");
  1567. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1568. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1569. ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1570. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1571. if (skge->flow_control == FLOW_MODE_REM_SEND) {
  1572. /* restore Asymmetric Pause bit */
  1573. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
  1574. gm_phy_read(hw, port,
  1575. PHY_MARV_AUNE_ADV)
  1576. | PHY_M_AN_ASP);
  1577. }
  1578. yukon_reset(hw, port);
  1579. skge_link_down(skge);
  1580. yukon_init(hw, port);
  1581. }
  1582. static void yukon_phy_intr(struct skge_port *skge)
  1583. {
  1584. struct skge_hw *hw = skge->hw;
  1585. int port = skge->port;
  1586. const char *reason = NULL;
  1587. u16 istatus, phystat;
  1588. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1589. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1590. if (netif_msg_intr(skge))
  1591. printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1592. skge->netdev->name, istatus, phystat);
  1593. if (istatus & PHY_M_IS_AN_COMPL) {
  1594. if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
  1595. & PHY_M_AN_RF) {
  1596. reason = "remote fault";
  1597. goto failed;
  1598. }
  1599. if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
  1600. reason = "master/slave fault";
  1601. goto failed;
  1602. }
  1603. if (!(phystat & PHY_M_PS_SPDUP_RES)) {
  1604. reason = "speed/duplex";
  1605. goto failed;
  1606. }
  1607. skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
  1608. ? DUPLEX_FULL : DUPLEX_HALF;
  1609. skge->speed = yukon_speed(hw, phystat);
  1610. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  1611. switch (phystat & PHY_M_PS_PAUSE_MSK) {
  1612. case PHY_M_PS_PAUSE_MSK:
  1613. skge->flow_control = FLOW_MODE_SYMMETRIC;
  1614. break;
  1615. case PHY_M_PS_RX_P_EN:
  1616. skge->flow_control = FLOW_MODE_REM_SEND;
  1617. break;
  1618. case PHY_M_PS_TX_P_EN:
  1619. skge->flow_control = FLOW_MODE_LOC_SEND;
  1620. break;
  1621. default:
  1622. skge->flow_control = FLOW_MODE_NONE;
  1623. }
  1624. if (skge->flow_control == FLOW_MODE_NONE ||
  1625. (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
  1626. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1627. else
  1628. skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1629. yukon_link_up(skge);
  1630. return;
  1631. }
  1632. if (istatus & PHY_M_IS_LSP_CHANGE)
  1633. skge->speed = yukon_speed(hw, phystat);
  1634. if (istatus & PHY_M_IS_DUP_CHANGE)
  1635. skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1636. if (istatus & PHY_M_IS_LST_CHANGE) {
  1637. if (phystat & PHY_M_PS_LINK_UP)
  1638. yukon_link_up(skge);
  1639. else
  1640. yukon_link_down(skge);
  1641. }
  1642. return;
  1643. failed:
  1644. printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
  1645. skge->netdev->name, reason);
  1646. /* XXX restart autonegotiation? */
  1647. }
  1648. static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
  1649. {
  1650. u32 end;
  1651. start /= 8;
  1652. len /= 8;
  1653. end = start + len - 1;
  1654. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  1655. skge_write32(hw, RB_ADDR(q, RB_START), start);
  1656. skge_write32(hw, RB_ADDR(q, RB_WP), start);
  1657. skge_write32(hw, RB_ADDR(q, RB_RP), start);
  1658. skge_write32(hw, RB_ADDR(q, RB_END), end);
  1659. if (q == Q_R1 || q == Q_R2) {
  1660. /* Set thresholds on receive queue's */
  1661. skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
  1662. start + (2*len)/3);
  1663. skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
  1664. start + (len/3));
  1665. } else {
  1666. /* Enable store & forward on Tx queue's because
  1667. * Tx FIFO is only 4K on Genesis and 1K on Yukon
  1668. */
  1669. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  1670. }
  1671. skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  1672. }
  1673. /* Setup Bus Memory Interface */
  1674. static void skge_qset(struct skge_port *skge, u16 q,
  1675. const struct skge_element *e)
  1676. {
  1677. struct skge_hw *hw = skge->hw;
  1678. u32 watermark = 0x600;
  1679. u64 base = skge->dma + (e->desc - skge->mem);
  1680. /* optimization to reduce window on 32bit/33mhz */
  1681. if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
  1682. watermark /= 2;
  1683. skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
  1684. skge_write32(hw, Q_ADDR(q, Q_F), watermark);
  1685. skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
  1686. skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
  1687. }
  1688. static int skge_up(struct net_device *dev)
  1689. {
  1690. struct skge_port *skge = netdev_priv(dev);
  1691. struct skge_hw *hw = skge->hw;
  1692. int port = skge->port;
  1693. u32 chunk, ram_addr;
  1694. size_t rx_size, tx_size;
  1695. int err;
  1696. if (netif_msg_ifup(skge))
  1697. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  1698. if (dev->mtu > RX_BUF_SIZE)
  1699. skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
  1700. else
  1701. skge->rx_buf_size = RX_BUF_SIZE;
  1702. rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
  1703. tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
  1704. skge->mem_size = tx_size + rx_size;
  1705. skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
  1706. if (!skge->mem)
  1707. return -ENOMEM;
  1708. memset(skge->mem, 0, skge->mem_size);
  1709. if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
  1710. goto free_pci_mem;
  1711. err = skge_rx_fill(skge);
  1712. if (err)
  1713. goto free_rx_ring;
  1714. if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
  1715. skge->dma + rx_size)))
  1716. goto free_rx_ring;
  1717. skge->tx_avail = skge->tx_ring.count - 1;
  1718. /* Enable IRQ from port */
  1719. hw->intr_mask |= portirqmask[port];
  1720. skge_write32(hw, B0_IMSK, hw->intr_mask);
  1721. /* Initialze MAC */
  1722. spin_lock_bh(&hw->phy_lock);
  1723. if (hw->chip_id == CHIP_ID_GENESIS)
  1724. genesis_mac_init(hw, port);
  1725. else
  1726. yukon_mac_init(hw, port);
  1727. spin_unlock_bh(&hw->phy_lock);
  1728. /* Configure RAMbuffers */
  1729. chunk = hw->ram_size / ((hw->ports + 1)*2);
  1730. ram_addr = hw->ram_offset + 2 * chunk * port;
  1731. skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
  1732. skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
  1733. BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
  1734. skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
  1735. skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
  1736. /* Start receiver BMU */
  1737. wmb();
  1738. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
  1739. skge_led(skge, LED_MODE_ON);
  1740. pr_debug("skge_up completed\n");
  1741. return 0;
  1742. free_rx_ring:
  1743. skge_rx_clean(skge);
  1744. kfree(skge->rx_ring.start);
  1745. free_pci_mem:
  1746. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  1747. return err;
  1748. }
  1749. static int skge_down(struct net_device *dev)
  1750. {
  1751. struct skge_port *skge = netdev_priv(dev);
  1752. struct skge_hw *hw = skge->hw;
  1753. int port = skge->port;
  1754. if (netif_msg_ifdown(skge))
  1755. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  1756. netif_stop_queue(dev);
  1757. /* Stop transmitter */
  1758. skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
  1759. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1760. RB_RST_SET|RB_DIS_OP_MD);
  1761. if (hw->chip_id == CHIP_ID_GENESIS)
  1762. genesis_stop(skge);
  1763. else
  1764. yukon_stop(skge);
  1765. /* Disable Force Sync bit and Enable Alloc bit */
  1766. skge_write8(hw, SK_REG(port, TXA_CTRL),
  1767. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1768. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1769. skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1770. skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1771. /* Reset PCI FIFO */
  1772. skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
  1773. skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1774. /* Reset the RAM Buffer async Tx queue */
  1775. skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
  1776. /* stop receiver */
  1777. skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
  1778. skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
  1779. RB_RST_SET|RB_DIS_OP_MD);
  1780. skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
  1781. if (hw->chip_id == CHIP_ID_GENESIS) {
  1782. skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
  1783. skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
  1784. } else {
  1785. skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1786. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1787. }
  1788. skge_led(skge, LED_MODE_OFF);
  1789. skge_tx_clean(skge);
  1790. skge_rx_clean(skge);
  1791. kfree(skge->rx_ring.start);
  1792. kfree(skge->tx_ring.start);
  1793. pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
  1794. return 0;
  1795. }
  1796. static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  1797. {
  1798. struct skge_port *skge = netdev_priv(dev);
  1799. struct skge_hw *hw = skge->hw;
  1800. struct skge_ring *ring = &skge->tx_ring;
  1801. struct skge_element *e;
  1802. struct skge_tx_desc *td;
  1803. int i;
  1804. u32 control, len;
  1805. u64 map;
  1806. unsigned long flags;
  1807. skb = skb_padto(skb, ETH_ZLEN);
  1808. if (!skb)
  1809. return NETDEV_TX_OK;
  1810. local_irq_save(flags);
  1811. if (!spin_trylock(&skge->tx_lock)) {
  1812. /* Collision - tell upper layer to requeue */
  1813. local_irq_restore(flags);
  1814. return NETDEV_TX_LOCKED;
  1815. }
  1816. if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
  1817. netif_stop_queue(dev);
  1818. spin_unlock_irqrestore(&skge->tx_lock, flags);
  1819. printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
  1820. dev->name);
  1821. return NETDEV_TX_BUSY;
  1822. }
  1823. e = ring->to_use;
  1824. td = e->desc;
  1825. e->skb = skb;
  1826. len = skb_headlen(skb);
  1827. map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1828. pci_unmap_addr_set(e, mapaddr, map);
  1829. pci_unmap_len_set(e, maplen, len);
  1830. td->dma_lo = map;
  1831. td->dma_hi = map >> 32;
  1832. if (skb->ip_summed == CHECKSUM_HW) {
  1833. const struct iphdr *ip
  1834. = (const struct iphdr *) (skb->data + ETH_HLEN);
  1835. int offset = skb->h.raw - skb->data;
  1836. /* This seems backwards, but it is what the sk98lin
  1837. * does. Looks like hardware is wrong?
  1838. */
  1839. if (ip->protocol == IPPROTO_UDP
  1840. && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
  1841. control = BMU_TCP_CHECK;
  1842. else
  1843. control = BMU_UDP_CHECK;
  1844. td->csum_offs = 0;
  1845. td->csum_start = offset;
  1846. td->csum_write = offset + skb->csum;
  1847. } else
  1848. control = BMU_CHECK;
  1849. if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
  1850. control |= BMU_EOF| BMU_IRQ_EOF;
  1851. else {
  1852. struct skge_tx_desc *tf = td;
  1853. control |= BMU_STFWD;
  1854. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1855. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1856. map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  1857. frag->size, PCI_DMA_TODEVICE);
  1858. e = e->next;
  1859. e->skb = NULL;
  1860. tf = e->desc;
  1861. tf->dma_lo = map;
  1862. tf->dma_hi = (u64) map >> 32;
  1863. pci_unmap_addr_set(e, mapaddr, map);
  1864. pci_unmap_len_set(e, maplen, frag->size);
  1865. tf->control = BMU_OWN | BMU_SW | control | frag->size;
  1866. }
  1867. tf->control |= BMU_EOF | BMU_IRQ_EOF;
  1868. }
  1869. /* Make sure all the descriptors written */
  1870. wmb();
  1871. td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
  1872. wmb();
  1873. skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
  1874. if (netif_msg_tx_queued(skge))
  1875. printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
  1876. dev->name, e - ring->start, skb->len);
  1877. ring->to_use = e->next;
  1878. skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
  1879. if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
  1880. pr_debug("%s: transmit queue full\n", dev->name);
  1881. netif_stop_queue(dev);
  1882. }
  1883. dev->trans_start = jiffies;
  1884. spin_unlock_irqrestore(&skge->tx_lock, flags);
  1885. return NETDEV_TX_OK;
  1886. }
  1887. static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
  1888. {
  1889. /* This ring element can be skb or fragment */
  1890. if (e->skb) {
  1891. pci_unmap_single(hw->pdev,
  1892. pci_unmap_addr(e, mapaddr),
  1893. pci_unmap_len(e, maplen),
  1894. PCI_DMA_TODEVICE);
  1895. dev_kfree_skb_any(e->skb);
  1896. e->skb = NULL;
  1897. } else {
  1898. pci_unmap_page(hw->pdev,
  1899. pci_unmap_addr(e, mapaddr),
  1900. pci_unmap_len(e, maplen),
  1901. PCI_DMA_TODEVICE);
  1902. }
  1903. }
  1904. static void skge_tx_clean(struct skge_port *skge)
  1905. {
  1906. struct skge_ring *ring = &skge->tx_ring;
  1907. struct skge_element *e;
  1908. unsigned long flags;
  1909. spin_lock_irqsave(&skge->tx_lock, flags);
  1910. for (e = ring->to_clean; e != ring->to_use; e = e->next) {
  1911. ++skge->tx_avail;
  1912. skge_tx_free(skge->hw, e);
  1913. }
  1914. ring->to_clean = e;
  1915. spin_unlock_irqrestore(&skge->tx_lock, flags);
  1916. }
  1917. static void skge_tx_timeout(struct net_device *dev)
  1918. {
  1919. struct skge_port *skge = netdev_priv(dev);
  1920. if (netif_msg_timer(skge))
  1921. printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
  1922. skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
  1923. skge_tx_clean(skge);
  1924. }
  1925. static int skge_change_mtu(struct net_device *dev, int new_mtu)
  1926. {
  1927. int err = 0;
  1928. int running = netif_running(dev);
  1929. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  1930. return -EINVAL;
  1931. if (running)
  1932. skge_down(dev);
  1933. dev->mtu = new_mtu;
  1934. if (running)
  1935. skge_up(dev);
  1936. return err;
  1937. }
  1938. static void genesis_set_multicast(struct net_device *dev)
  1939. {
  1940. struct skge_port *skge = netdev_priv(dev);
  1941. struct skge_hw *hw = skge->hw;
  1942. int port = skge->port;
  1943. int i, count = dev->mc_count;
  1944. struct dev_mc_list *list = dev->mc_list;
  1945. u32 mode;
  1946. u8 filter[8];
  1947. pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
  1948. mode = xm_read32(hw, port, XM_MODE);
  1949. mode |= XM_MD_ENA_HASH;
  1950. if (dev->flags & IFF_PROMISC)
  1951. mode |= XM_MD_ENA_PROM;
  1952. else
  1953. mode &= ~XM_MD_ENA_PROM;
  1954. if (dev->flags & IFF_ALLMULTI)
  1955. memset(filter, 0xff, sizeof(filter));
  1956. else {
  1957. memset(filter, 0, sizeof(filter));
  1958. for (i = 0; list && i < count; i++, list = list->next) {
  1959. u32 crc, bit;
  1960. crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
  1961. bit = ~crc & 0x3f;
  1962. filter[bit/8] |= 1 << (bit%8);
  1963. }
  1964. }
  1965. xm_write32(hw, port, XM_MODE, mode);
  1966. xm_outhash(hw, port, XM_HSM, filter);
  1967. }
  1968. static void yukon_set_multicast(struct net_device *dev)
  1969. {
  1970. struct skge_port *skge = netdev_priv(dev);
  1971. struct skge_hw *hw = skge->hw;
  1972. int port = skge->port;
  1973. struct dev_mc_list *list = dev->mc_list;
  1974. u16 reg;
  1975. u8 filter[8];
  1976. memset(filter, 0, sizeof(filter));
  1977. reg = gma_read16(hw, port, GM_RX_CTRL);
  1978. reg |= GM_RXCR_UCF_ENA;
  1979. if (dev->flags & IFF_PROMISC) /* promiscious */
  1980. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1981. else if (dev->flags & IFF_ALLMULTI) /* all multicast */
  1982. memset(filter, 0xff, sizeof(filter));
  1983. else if (dev->mc_count == 0) /* no multicast */
  1984. reg &= ~GM_RXCR_MCF_ENA;
  1985. else {
  1986. int i;
  1987. reg |= GM_RXCR_MCF_ENA;
  1988. for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
  1989. u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
  1990. filter[bit/8] |= 1 << (bit%8);
  1991. }
  1992. }
  1993. gma_write16(hw, port, GM_MC_ADDR_H1,
  1994. (u16)filter[0] | ((u16)filter[1] << 8));
  1995. gma_write16(hw, port, GM_MC_ADDR_H2,
  1996. (u16)filter[2] | ((u16)filter[3] << 8));
  1997. gma_write16(hw, port, GM_MC_ADDR_H3,
  1998. (u16)filter[4] | ((u16)filter[5] << 8));
  1999. gma_write16(hw, port, GM_MC_ADDR_H4,
  2000. (u16)filter[6] | ((u16)filter[7] << 8));
  2001. gma_write16(hw, port, GM_RX_CTRL, reg);
  2002. }
  2003. static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
  2004. {
  2005. if (hw->chip_id == CHIP_ID_GENESIS)
  2006. return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
  2007. else
  2008. return (status & GMR_FS_ANY_ERR) ||
  2009. (status & GMR_FS_RX_OK) == 0;
  2010. }
  2011. static void skge_rx_error(struct skge_port *skge, int slot,
  2012. u32 control, u32 status)
  2013. {
  2014. if (netif_msg_rx_err(skge))
  2015. printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
  2016. skge->netdev->name, slot, control, status);
  2017. if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
  2018. skge->net_stats.rx_length_errors++;
  2019. else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
  2020. if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
  2021. skge->net_stats.rx_length_errors++;
  2022. if (status & XMR_FS_FRA_ERR)
  2023. skge->net_stats.rx_frame_errors++;
  2024. if (status & XMR_FS_FCS_ERR)
  2025. skge->net_stats.rx_crc_errors++;
  2026. } else {
  2027. if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
  2028. skge->net_stats.rx_length_errors++;
  2029. if (status & GMR_FS_FRAGMENT)
  2030. skge->net_stats.rx_frame_errors++;
  2031. if (status & GMR_FS_CRC_ERR)
  2032. skge->net_stats.rx_crc_errors++;
  2033. }
  2034. }
  2035. /* Get receive buffer from descriptor.
  2036. * Handles copy of small buffers and reallocation failures
  2037. */
  2038. static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
  2039. struct skge_element *e,
  2040. unsigned int len)
  2041. {
  2042. struct sk_buff *nskb, *skb;
  2043. if (len < RX_COPY_THRESHOLD) {
  2044. nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
  2045. if (unlikely(!nskb))
  2046. return NULL;
  2047. pci_dma_sync_single_for_cpu(skge->hw->pdev,
  2048. pci_unmap_addr(e, mapaddr),
  2049. len, PCI_DMA_FROMDEVICE);
  2050. memcpy(nskb->data, e->skb->data, len);
  2051. pci_dma_sync_single_for_device(skge->hw->pdev,
  2052. pci_unmap_addr(e, mapaddr),
  2053. len, PCI_DMA_FROMDEVICE);
  2054. if (skge->rx_csum) {
  2055. struct skge_rx_desc *rd = e->desc;
  2056. nskb->csum = le16_to_cpu(rd->csum2);
  2057. nskb->ip_summed = CHECKSUM_HW;
  2058. }
  2059. skge_rx_reuse(e, skge->rx_buf_size);
  2060. return nskb;
  2061. } else {
  2062. nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
  2063. if (unlikely(!nskb))
  2064. return NULL;
  2065. pci_unmap_single(skge->hw->pdev,
  2066. pci_unmap_addr(e, mapaddr),
  2067. pci_unmap_len(e, maplen),
  2068. PCI_DMA_FROMDEVICE);
  2069. skb = e->skb;
  2070. if (skge->rx_csum) {
  2071. struct skge_rx_desc *rd = e->desc;
  2072. skb->csum = le16_to_cpu(rd->csum2);
  2073. skb->ip_summed = CHECKSUM_HW;
  2074. }
  2075. skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
  2076. return skb;
  2077. }
  2078. }
  2079. static int skge_poll(struct net_device *dev, int *budget)
  2080. {
  2081. struct skge_port *skge = netdev_priv(dev);
  2082. struct skge_hw *hw = skge->hw;
  2083. struct skge_ring *ring = &skge->rx_ring;
  2084. struct skge_element *e;
  2085. unsigned int to_do = min(dev->quota, *budget);
  2086. unsigned int work_done = 0;
  2087. pr_debug("skge_poll\n");
  2088. for (e = ring->to_clean; work_done < to_do; e = e->next) {
  2089. struct skge_rx_desc *rd = e->desc;
  2090. struct sk_buff *skb;
  2091. u32 control, len, status;
  2092. rmb();
  2093. control = rd->control;
  2094. if (control & BMU_OWN)
  2095. break;
  2096. len = control & BMU_BBC;
  2097. status = rd->status;
  2098. if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
  2099. || bad_phy_status(hw, status))) {
  2100. skge_rx_error(skge, e - ring->start, control, status);
  2101. skge_rx_reuse(e, skge->rx_buf_size);
  2102. continue;
  2103. }
  2104. if (netif_msg_rx_status(skge))
  2105. printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
  2106. dev->name, e - ring->start, rd->status, len);
  2107. skb = skge_rx_get(skge, e, len);
  2108. if (likely(skb)) {
  2109. skb_put(skb, len);
  2110. skb->protocol = eth_type_trans(skb, dev);
  2111. dev->last_rx = jiffies;
  2112. netif_receive_skb(skb);
  2113. ++work_done;
  2114. } else
  2115. skge_rx_reuse(e, skge->rx_buf_size);
  2116. }
  2117. ring->to_clean = e;
  2118. /* restart receiver */
  2119. wmb();
  2120. skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
  2121. CSR_START | CSR_IRQ_CL_F);
  2122. *budget -= work_done;
  2123. dev->quota -= work_done;
  2124. if (work_done >= to_do)
  2125. return 1; /* not done */
  2126. local_irq_disable();
  2127. __netif_rx_complete(dev);
  2128. hw->intr_mask |= portirqmask[skge->port];
  2129. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2130. local_irq_enable();
  2131. return 0;
  2132. }
  2133. static inline void skge_tx_intr(struct net_device *dev)
  2134. {
  2135. struct skge_port *skge = netdev_priv(dev);
  2136. struct skge_hw *hw = skge->hw;
  2137. struct skge_ring *ring = &skge->tx_ring;
  2138. struct skge_element *e;
  2139. spin_lock(&skge->tx_lock);
  2140. for (e = ring->to_clean; e != ring->to_use; e = e->next) {
  2141. struct skge_tx_desc *td = e->desc;
  2142. u32 control;
  2143. rmb();
  2144. control = td->control;
  2145. if (control & BMU_OWN)
  2146. break;
  2147. if (unlikely(netif_msg_tx_done(skge)))
  2148. printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
  2149. dev->name, e - ring->start, td->status);
  2150. skge_tx_free(hw, e);
  2151. e->skb = NULL;
  2152. ++skge->tx_avail;
  2153. }
  2154. ring->to_clean = e;
  2155. skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
  2156. if (skge->tx_avail > MAX_SKB_FRAGS + 1)
  2157. netif_wake_queue(dev);
  2158. spin_unlock(&skge->tx_lock);
  2159. }
  2160. /* Parity errors seem to happen when Genesis is connected to a switch
  2161. * with no other ports present. Heartbeat error??
  2162. */
  2163. static void skge_mac_parity(struct skge_hw *hw, int port)
  2164. {
  2165. struct net_device *dev = hw->dev[port];
  2166. if (dev) {
  2167. struct skge_port *skge = netdev_priv(dev);
  2168. ++skge->net_stats.tx_heartbeat_errors;
  2169. }
  2170. if (hw->chip_id == CHIP_ID_GENESIS)
  2171. skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
  2172. MFF_CLR_PERR);
  2173. else
  2174. /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
  2175. skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
  2176. (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
  2177. ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
  2178. }
  2179. static void skge_pci_clear(struct skge_hw *hw)
  2180. {
  2181. u16 status;
  2182. pci_read_config_word(hw->pdev, PCI_STATUS, &status);
  2183. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  2184. pci_write_config_word(hw->pdev, PCI_STATUS,
  2185. status | PCI_STATUS_ERROR_BITS);
  2186. skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  2187. }
  2188. static void skge_mac_intr(struct skge_hw *hw, int port)
  2189. {
  2190. if (hw->chip_id == CHIP_ID_GENESIS)
  2191. genesis_mac_intr(hw, port);
  2192. else
  2193. yukon_mac_intr(hw, port);
  2194. }
  2195. /* Handle device specific framing and timeout interrupts */
  2196. static void skge_error_irq(struct skge_hw *hw)
  2197. {
  2198. u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2199. if (hw->chip_id == CHIP_ID_GENESIS) {
  2200. /* clear xmac errors */
  2201. if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
  2202. skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
  2203. if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
  2204. skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
  2205. } else {
  2206. /* Timestamp (unused) overflow */
  2207. if (hwstatus & IS_IRQ_TIST_OV)
  2208. skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  2209. if (hwstatus & IS_IRQ_SENSOR) {
  2210. /* no sensors on 32-bit Yukon */
  2211. if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
  2212. printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
  2213. skge_write32(hw, B0_HWE_IMSK,
  2214. IS_ERR_MSK & ~IS_IRQ_SENSOR);
  2215. } else
  2216. printk(KERN_WARNING PFX "sensor interrupt\n");
  2217. }
  2218. }
  2219. if (hwstatus & IS_RAM_RD_PAR) {
  2220. printk(KERN_ERR PFX "Ram read data parity error\n");
  2221. skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
  2222. }
  2223. if (hwstatus & IS_RAM_WR_PAR) {
  2224. printk(KERN_ERR PFX "Ram write data parity error\n");
  2225. skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
  2226. }
  2227. if (hwstatus & IS_M1_PAR_ERR)
  2228. skge_mac_parity(hw, 0);
  2229. if (hwstatus & IS_M2_PAR_ERR)
  2230. skge_mac_parity(hw, 1);
  2231. if (hwstatus & IS_R1_PAR_ERR)
  2232. skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
  2233. if (hwstatus & IS_R2_PAR_ERR)
  2234. skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
  2235. if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
  2236. printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
  2237. hwstatus);
  2238. skge_pci_clear(hw);
  2239. hwstatus = skge_read32(hw, B0_HWE_ISRC);
  2240. if (hwstatus & IS_IRQ_STAT) {
  2241. printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
  2242. hwstatus);
  2243. hw->intr_mask &= ~IS_HW_ERR;
  2244. }
  2245. }
  2246. }
  2247. /*
  2248. * Interrrupt from PHY are handled in tasklet (soft irq)
  2249. * because accessing phy registers requires spin wait which might
  2250. * cause excess interrupt latency.
  2251. */
  2252. static void skge_extirq(unsigned long data)
  2253. {
  2254. struct skge_hw *hw = (struct skge_hw *) data;
  2255. int port;
  2256. spin_lock(&hw->phy_lock);
  2257. for (port = 0; port < 2; port++) {
  2258. struct net_device *dev = hw->dev[port];
  2259. if (dev && netif_running(dev)) {
  2260. struct skge_port *skge = netdev_priv(dev);
  2261. if (hw->chip_id != CHIP_ID_GENESIS)
  2262. yukon_phy_intr(skge);
  2263. else
  2264. bcom_phy_intr(skge);
  2265. }
  2266. }
  2267. spin_unlock(&hw->phy_lock);
  2268. local_irq_disable();
  2269. hw->intr_mask |= IS_EXT_REG;
  2270. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2271. local_irq_enable();
  2272. }
  2273. static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
  2274. {
  2275. struct skge_hw *hw = dev_id;
  2276. u32 status = skge_read32(hw, B0_SP_ISRC);
  2277. if (status == 0 || status == ~0) /* hotplug or shared irq */
  2278. return IRQ_NONE;
  2279. status &= hw->intr_mask;
  2280. if (status & IS_R1_F) {
  2281. hw->intr_mask &= ~IS_R1_F;
  2282. netif_rx_schedule(hw->dev[0]);
  2283. }
  2284. if (status & IS_R2_F) {
  2285. hw->intr_mask &= ~IS_R2_F;
  2286. netif_rx_schedule(hw->dev[1]);
  2287. }
  2288. if (status & IS_XA1_F)
  2289. skge_tx_intr(hw->dev[0]);
  2290. if (status & IS_XA2_F)
  2291. skge_tx_intr(hw->dev[1]);
  2292. if (status & IS_PA_TO_RX1) {
  2293. struct skge_port *skge = netdev_priv(hw->dev[0]);
  2294. ++skge->net_stats.rx_over_errors;
  2295. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
  2296. }
  2297. if (status & IS_PA_TO_RX2) {
  2298. struct skge_port *skge = netdev_priv(hw->dev[1]);
  2299. ++skge->net_stats.rx_over_errors;
  2300. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
  2301. }
  2302. if (status & IS_PA_TO_TX1)
  2303. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
  2304. if (status & IS_PA_TO_TX2)
  2305. skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
  2306. if (status & IS_MAC1)
  2307. skge_mac_intr(hw, 0);
  2308. if (status & IS_MAC2)
  2309. skge_mac_intr(hw, 1);
  2310. if (status & IS_HW_ERR)
  2311. skge_error_irq(hw);
  2312. if (status & IS_EXT_REG) {
  2313. hw->intr_mask &= ~IS_EXT_REG;
  2314. tasklet_schedule(&hw->ext_tasklet);
  2315. }
  2316. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2317. return IRQ_HANDLED;
  2318. }
  2319. #ifdef CONFIG_NET_POLL_CONTROLLER
  2320. static void skge_netpoll(struct net_device *dev)
  2321. {
  2322. struct skge_port *skge = netdev_priv(dev);
  2323. disable_irq(dev->irq);
  2324. skge_intr(dev->irq, skge->hw, NULL);
  2325. enable_irq(dev->irq);
  2326. }
  2327. #endif
  2328. static int skge_set_mac_address(struct net_device *dev, void *p)
  2329. {
  2330. struct skge_port *skge = netdev_priv(dev);
  2331. struct sockaddr *addr = p;
  2332. int err = 0;
  2333. if (!is_valid_ether_addr(addr->sa_data))
  2334. return -EADDRNOTAVAIL;
  2335. skge_down(dev);
  2336. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2337. memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
  2338. dev->dev_addr, ETH_ALEN);
  2339. memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
  2340. dev->dev_addr, ETH_ALEN);
  2341. if (dev->flags & IFF_UP)
  2342. err = skge_up(dev);
  2343. return err;
  2344. }
  2345. static const struct {
  2346. u8 id;
  2347. const char *name;
  2348. } skge_chips[] = {
  2349. { CHIP_ID_GENESIS, "Genesis" },
  2350. { CHIP_ID_YUKON, "Yukon" },
  2351. { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
  2352. { CHIP_ID_YUKON_LP, "Yukon-LP"},
  2353. };
  2354. static const char *skge_board_name(const struct skge_hw *hw)
  2355. {
  2356. int i;
  2357. static char buf[16];
  2358. for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
  2359. if (skge_chips[i].id == hw->chip_id)
  2360. return skge_chips[i].name;
  2361. snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
  2362. return buf;
  2363. }
  2364. /*
  2365. * Setup the board data structure, but don't bring up
  2366. * the port(s)
  2367. */
  2368. static int skge_reset(struct skge_hw *hw)
  2369. {
  2370. u16 ctst;
  2371. u8 t8, mac_cfg;
  2372. int i;
  2373. ctst = skge_read16(hw, B0_CTST);
  2374. /* do a SW reset */
  2375. skge_write8(hw, B0_CTST, CS_RST_SET);
  2376. skge_write8(hw, B0_CTST, CS_RST_CLR);
  2377. /* clear PCI errors, if any */
  2378. skge_pci_clear(hw);
  2379. skge_write8(hw, B0_CTST, CS_MRST_CLR);
  2380. /* restore CLK_RUN bits (for Yukon-Lite) */
  2381. skge_write16(hw, B0_CTST,
  2382. ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
  2383. hw->chip_id = skge_read8(hw, B2_CHIP_ID);
  2384. hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
  2385. hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
  2386. switch (hw->chip_id) {
  2387. case CHIP_ID_GENESIS:
  2388. switch (hw->phy_type) {
  2389. case SK_PHY_BCOM:
  2390. hw->phy_addr = PHY_ADDR_BCOM;
  2391. break;
  2392. default:
  2393. printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
  2394. pci_name(hw->pdev), hw->phy_type);
  2395. return -EOPNOTSUPP;
  2396. }
  2397. break;
  2398. case CHIP_ID_YUKON:
  2399. case CHIP_ID_YUKON_LITE:
  2400. case CHIP_ID_YUKON_LP:
  2401. if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
  2402. hw->phy_type = SK_PHY_MARV_COPPER;
  2403. hw->phy_addr = PHY_ADDR_MARV;
  2404. if (!iscopper(hw))
  2405. hw->phy_type = SK_PHY_MARV_FIBER;
  2406. break;
  2407. default:
  2408. printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
  2409. pci_name(hw->pdev), hw->chip_id);
  2410. return -EOPNOTSUPP;
  2411. }
  2412. mac_cfg = skge_read8(hw, B2_MAC_CFG);
  2413. hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
  2414. hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
  2415. /* read the adapters RAM size */
  2416. t8 = skge_read8(hw, B2_E_0);
  2417. if (hw->chip_id == CHIP_ID_GENESIS) {
  2418. if (t8 == 3) {
  2419. /* special case: 4 x 64k x 36, offset = 0x80000 */
  2420. hw->ram_size = 0x100000;
  2421. hw->ram_offset = 0x80000;
  2422. } else
  2423. hw->ram_size = t8 * 512;
  2424. }
  2425. else if (t8 == 0)
  2426. hw->ram_size = 0x20000;
  2427. else
  2428. hw->ram_size = t8 * 4096;
  2429. if (hw->chip_id == CHIP_ID_GENESIS)
  2430. genesis_init(hw);
  2431. else {
  2432. /* switch power to VCC (WA for VAUX problem) */
  2433. skge_write8(hw, B0_POWER_CTRL,
  2434. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  2435. for (i = 0; i < hw->ports; i++) {
  2436. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  2437. skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  2438. }
  2439. }
  2440. /* turn off hardware timer (unused) */
  2441. skge_write8(hw, B2_TI_CTRL, TIM_STOP);
  2442. skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  2443. skge_write8(hw, B0_LED, LED_STAT_ON);
  2444. /* enable the Tx Arbiters */
  2445. for (i = 0; i < hw->ports; i++)
  2446. skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  2447. /* Initialize ram interface */
  2448. skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
  2449. skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
  2450. skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
  2451. skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
  2452. skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
  2453. skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
  2454. skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
  2455. skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
  2456. skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
  2457. skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
  2458. skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
  2459. skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
  2460. skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
  2461. skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
  2462. /* Set interrupt moderation for Transmit only
  2463. * Receive interrupts avoided by NAPI
  2464. */
  2465. skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
  2466. skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
  2467. skge_write32(hw, B2_IRQM_CTRL, TIM_START);
  2468. hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
  2469. skge_write32(hw, B0_IMSK, hw->intr_mask);
  2470. if (hw->chip_id != CHIP_ID_GENESIS)
  2471. skge_write8(hw, GMAC_IRQ_MSK, 0);
  2472. spin_lock_bh(&hw->phy_lock);
  2473. for (i = 0; i < hw->ports; i++) {
  2474. if (hw->chip_id == CHIP_ID_GENESIS)
  2475. genesis_reset(hw, i);
  2476. else
  2477. yukon_reset(hw, i);
  2478. }
  2479. spin_unlock_bh(&hw->phy_lock);
  2480. return 0;
  2481. }
  2482. /* Initialize network device */
  2483. static struct net_device *skge_devinit(struct skge_hw *hw, int port,
  2484. int highmem)
  2485. {
  2486. struct skge_port *skge;
  2487. struct net_device *dev = alloc_etherdev(sizeof(*skge));
  2488. if (!dev) {
  2489. printk(KERN_ERR "skge etherdev alloc failed");
  2490. return NULL;
  2491. }
  2492. SET_MODULE_OWNER(dev);
  2493. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  2494. dev->open = skge_up;
  2495. dev->stop = skge_down;
  2496. dev->hard_start_xmit = skge_xmit_frame;
  2497. dev->get_stats = skge_get_stats;
  2498. if (hw->chip_id == CHIP_ID_GENESIS)
  2499. dev->set_multicast_list = genesis_set_multicast;
  2500. else
  2501. dev->set_multicast_list = yukon_set_multicast;
  2502. dev->set_mac_address = skge_set_mac_address;
  2503. dev->change_mtu = skge_change_mtu;
  2504. SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
  2505. dev->tx_timeout = skge_tx_timeout;
  2506. dev->watchdog_timeo = TX_WATCHDOG;
  2507. dev->poll = skge_poll;
  2508. dev->weight = NAPI_WEIGHT;
  2509. #ifdef CONFIG_NET_POLL_CONTROLLER
  2510. dev->poll_controller = skge_netpoll;
  2511. #endif
  2512. dev->irq = hw->pdev->irq;
  2513. dev->features = NETIF_F_LLTX;
  2514. if (highmem)
  2515. dev->features |= NETIF_F_HIGHDMA;
  2516. skge = netdev_priv(dev);
  2517. skge->netdev = dev;
  2518. skge->hw = hw;
  2519. skge->msg_enable = netif_msg_init(debug, default_msg);
  2520. skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
  2521. skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
  2522. /* Auto speed and flow control */
  2523. skge->autoneg = AUTONEG_ENABLE;
  2524. skge->flow_control = FLOW_MODE_SYMMETRIC;
  2525. skge->duplex = -1;
  2526. skge->speed = -1;
  2527. skge->advertising = skge_supported_modes(hw);
  2528. hw->dev[port] = dev;
  2529. skge->port = port;
  2530. spin_lock_init(&skge->tx_lock);
  2531. if (hw->chip_id != CHIP_ID_GENESIS) {
  2532. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  2533. skge->rx_csum = 1;
  2534. }
  2535. /* read the mac address */
  2536. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
  2537. /* device is off until link detection */
  2538. netif_carrier_off(dev);
  2539. netif_stop_queue(dev);
  2540. return dev;
  2541. }
  2542. static void __devinit skge_show_addr(struct net_device *dev)
  2543. {
  2544. const struct skge_port *skge = netdev_priv(dev);
  2545. if (netif_msg_probe(skge))
  2546. printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  2547. dev->name,
  2548. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  2549. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  2550. }
  2551. static int __devinit skge_probe(struct pci_dev *pdev,
  2552. const struct pci_device_id *ent)
  2553. {
  2554. struct net_device *dev, *dev1;
  2555. struct skge_hw *hw;
  2556. int err, using_dac = 0;
  2557. if ((err = pci_enable_device(pdev))) {
  2558. printk(KERN_ERR PFX "%s cannot enable PCI device\n",
  2559. pci_name(pdev));
  2560. goto err_out;
  2561. }
  2562. if ((err = pci_request_regions(pdev, DRV_NAME))) {
  2563. printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
  2564. pci_name(pdev));
  2565. goto err_out_disable_pdev;
  2566. }
  2567. pci_set_master(pdev);
  2568. if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
  2569. using_dac = 1;
  2570. else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
  2571. printk(KERN_ERR PFX "%s no usable DMA configuration\n",
  2572. pci_name(pdev));
  2573. goto err_out_free_regions;
  2574. }
  2575. #ifdef __BIG_ENDIAN
  2576. /* byte swap decriptors in hardware */
  2577. {
  2578. u32 reg;
  2579. pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
  2580. reg |= PCI_REV_DESC;
  2581. pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
  2582. }
  2583. #endif
  2584. err = -ENOMEM;
  2585. hw = kmalloc(sizeof(*hw), GFP_KERNEL);
  2586. if (!hw) {
  2587. printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
  2588. pci_name(pdev));
  2589. goto err_out_free_regions;
  2590. }
  2591. memset(hw, 0, sizeof(*hw));
  2592. hw->pdev = pdev;
  2593. spin_lock_init(&hw->phy_lock);
  2594. tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
  2595. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  2596. if (!hw->regs) {
  2597. printk(KERN_ERR PFX "%s: cannot map device registers\n",
  2598. pci_name(pdev));
  2599. goto err_out_free_hw;
  2600. }
  2601. if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
  2602. printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
  2603. pci_name(pdev), pdev->irq);
  2604. goto err_out_iounmap;
  2605. }
  2606. pci_set_drvdata(pdev, hw);
  2607. err = skge_reset(hw);
  2608. if (err)
  2609. goto err_out_free_irq;
  2610. printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
  2611. pci_resource_start(pdev, 0), pdev->irq,
  2612. skge_board_name(hw), hw->chip_rev);
  2613. if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
  2614. goto err_out_led_off;
  2615. if ((err = register_netdev(dev))) {
  2616. printk(KERN_ERR PFX "%s: cannot register net device\n",
  2617. pci_name(pdev));
  2618. goto err_out_free_netdev;
  2619. }
  2620. skge_show_addr(dev);
  2621. if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
  2622. if (register_netdev(dev1) == 0)
  2623. skge_show_addr(dev1);
  2624. else {
  2625. /* Failure to register second port need not be fatal */
  2626. printk(KERN_WARNING PFX "register of second port failed\n");
  2627. hw->dev[1] = NULL;
  2628. free_netdev(dev1);
  2629. }
  2630. }
  2631. return 0;
  2632. err_out_free_netdev:
  2633. free_netdev(dev);
  2634. err_out_led_off:
  2635. skge_write16(hw, B0_LED, LED_STAT_OFF);
  2636. err_out_free_irq:
  2637. free_irq(pdev->irq, hw);
  2638. err_out_iounmap:
  2639. iounmap(hw->regs);
  2640. err_out_free_hw:
  2641. kfree(hw);
  2642. err_out_free_regions:
  2643. pci_release_regions(pdev);
  2644. err_out_disable_pdev:
  2645. pci_disable_device(pdev);
  2646. pci_set_drvdata(pdev, NULL);
  2647. err_out:
  2648. return err;
  2649. }
  2650. static void __devexit skge_remove(struct pci_dev *pdev)
  2651. {
  2652. struct skge_hw *hw = pci_get_drvdata(pdev);
  2653. struct net_device *dev0, *dev1;
  2654. if (!hw)
  2655. return;
  2656. if ((dev1 = hw->dev[1]))
  2657. unregister_netdev(dev1);
  2658. dev0 = hw->dev[0];
  2659. unregister_netdev(dev0);
  2660. tasklet_kill(&hw->ext_tasklet);
  2661. free_irq(pdev->irq, hw);
  2662. pci_release_regions(pdev);
  2663. pci_disable_device(pdev);
  2664. if (dev1)
  2665. free_netdev(dev1);
  2666. free_netdev(dev0);
  2667. skge_write16(hw, B0_LED, LED_STAT_OFF);
  2668. iounmap(hw->regs);
  2669. kfree(hw);
  2670. pci_set_drvdata(pdev, NULL);
  2671. }
  2672. #ifdef CONFIG_PM
  2673. static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
  2674. {
  2675. struct skge_hw *hw = pci_get_drvdata(pdev);
  2676. int i, wol = 0;
  2677. for (i = 0; i < 2; i++) {
  2678. struct net_device *dev = hw->dev[i];
  2679. if (dev) {
  2680. struct skge_port *skge = netdev_priv(dev);
  2681. if (netif_running(dev)) {
  2682. netif_carrier_off(dev);
  2683. skge_down(dev);
  2684. }
  2685. netif_device_detach(dev);
  2686. wol |= skge->wol;
  2687. }
  2688. }
  2689. pci_save_state(pdev);
  2690. pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
  2691. pci_disable_device(pdev);
  2692. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2693. return 0;
  2694. }
  2695. static int skge_resume(struct pci_dev *pdev)
  2696. {
  2697. struct skge_hw *hw = pci_get_drvdata(pdev);
  2698. int i;
  2699. pci_set_power_state(pdev, PCI_D0);
  2700. pci_restore_state(pdev);
  2701. pci_enable_wake(pdev, PCI_D0, 0);
  2702. skge_reset(hw);
  2703. for (i = 0; i < 2; i++) {
  2704. struct net_device *dev = hw->dev[i];
  2705. if (dev) {
  2706. netif_device_attach(dev);
  2707. if (netif_running(dev))
  2708. skge_up(dev);
  2709. }
  2710. }
  2711. return 0;
  2712. }
  2713. #endif
  2714. static struct pci_driver skge_driver = {
  2715. .name = DRV_NAME,
  2716. .id_table = skge_id_table,
  2717. .probe = skge_probe,
  2718. .remove = __devexit_p(skge_remove),
  2719. #ifdef CONFIG_PM
  2720. .suspend = skge_suspend,
  2721. .resume = skge_resume,
  2722. #endif
  2723. };
  2724. static int __init skge_init_module(void)
  2725. {
  2726. return pci_module_init(&skge_driver);
  2727. }
  2728. static void __exit skge_cleanup_module(void)
  2729. {
  2730. pci_unregister_driver(&skge_driver);
  2731. }
  2732. module_init(skge_init_module);
  2733. module_exit(skge_cleanup_module);