octeon-feature.h 6.9 KB

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  1. /***********************license start***************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: support@caviumnetworks.com
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2008 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. ***********************license end**************************************/
  27. /*
  28. * File defining checks for different Octeon features.
  29. */
  30. #ifndef __OCTEON_FEATURE_H__
  31. #define __OCTEON_FEATURE_H__
  32. #include <asm/octeon/cvmx-mio-defs.h>
  33. #include <asm/octeon/cvmx-rnm-defs.h>
  34. enum octeon_feature {
  35. /* CN68XX uses port kinds for packet interface */
  36. OCTEON_FEATURE_PKND,
  37. /* CN68XX has different fields in word0 - word2 */
  38. OCTEON_FEATURE_CN68XX_WQE,
  39. /*
  40. * Octeon models in the CN5XXX family and higher support
  41. * atomic add instructions to memory (saa/saad).
  42. */
  43. OCTEON_FEATURE_SAAD,
  44. /* Does this Octeon support the ZIP offload engine? */
  45. OCTEON_FEATURE_ZIP,
  46. /* Does this Octeon support crypto acceleration using COP2? */
  47. OCTEON_FEATURE_CRYPTO,
  48. OCTEON_FEATURE_DORM_CRYPTO,
  49. /* Does this Octeon support PCI express? */
  50. OCTEON_FEATURE_PCIE,
  51. /* Does this Octeon support SRIOs */
  52. OCTEON_FEATURE_SRIO,
  53. /* Does this Octeon support Interlaken */
  54. OCTEON_FEATURE_ILK,
  55. /* Some Octeon models support internal memory for storing
  56. * cryptographic keys */
  57. OCTEON_FEATURE_KEY_MEMORY,
  58. /* Octeon has a LED controller for banks of external LEDs */
  59. OCTEON_FEATURE_LED_CONTROLLER,
  60. /* Octeon has a trace buffer */
  61. OCTEON_FEATURE_TRA,
  62. /* Octeon has a management port */
  63. OCTEON_FEATURE_MGMT_PORT,
  64. /* Octeon has a raid unit */
  65. OCTEON_FEATURE_RAID,
  66. /* Octeon has a builtin USB */
  67. OCTEON_FEATURE_USB,
  68. /* Octeon IPD can run without using work queue entries */
  69. OCTEON_FEATURE_NO_WPTR,
  70. /* Octeon has DFA state machines */
  71. OCTEON_FEATURE_DFA,
  72. /* Octeon MDIO block supports clause 45 transactions for 10
  73. * Gig support */
  74. OCTEON_FEATURE_MDIO_CLAUSE_45,
  75. /*
  76. * CN52XX and CN56XX used a block named NPEI for PCIe
  77. * access. Newer chips replaced this with SLI+DPI.
  78. */
  79. OCTEON_FEATURE_NPEI,
  80. OCTEON_FEATURE_HFA,
  81. OCTEON_FEATURE_DFM,
  82. OCTEON_FEATURE_CIU2,
  83. OCTEON_MAX_FEATURE
  84. };
  85. static inline int cvmx_fuse_read(int fuse);
  86. /**
  87. * Determine if the current Octeon supports a specific feature. These
  88. * checks have been optimized to be fairly quick, but they should still
  89. * be kept out of fast path code.
  90. *
  91. * @feature: Feature to check for. This should always be a constant so the
  92. * compiler can remove the switch statement through optimization.
  93. *
  94. * Returns Non zero if the feature exists. Zero if the feature does not
  95. * exist.
  96. */
  97. static inline int octeon_has_feature(enum octeon_feature feature)
  98. {
  99. switch (feature) {
  100. case OCTEON_FEATURE_SAAD:
  101. return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
  102. case OCTEON_FEATURE_ZIP:
  103. if (OCTEON_IS_MODEL(OCTEON_CN30XX)
  104. || OCTEON_IS_MODEL(OCTEON_CN50XX)
  105. || OCTEON_IS_MODEL(OCTEON_CN52XX))
  106. return 0;
  107. else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
  108. return 1;
  109. else
  110. return !cvmx_fuse_read(121);
  111. case OCTEON_FEATURE_CRYPTO:
  112. if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
  113. union cvmx_mio_fus_dat2 fus_2;
  114. fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
  115. if (fus_2.s.nocrypto || fus_2.s.nomul) {
  116. return 0;
  117. } else if (!fus_2.s.dorm_crypto) {
  118. return 1;
  119. } else {
  120. union cvmx_rnm_ctl_status st;
  121. st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
  122. return st.s.eer_val;
  123. }
  124. } else {
  125. return !cvmx_fuse_read(90);
  126. }
  127. case OCTEON_FEATURE_DORM_CRYPTO:
  128. if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
  129. union cvmx_mio_fus_dat2 fus_2;
  130. fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
  131. return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
  132. } else {
  133. return 0;
  134. }
  135. case OCTEON_FEATURE_PCIE:
  136. return OCTEON_IS_MODEL(OCTEON_CN56XX)
  137. || OCTEON_IS_MODEL(OCTEON_CN52XX)
  138. || OCTEON_IS_MODEL(OCTEON_CN6XXX);
  139. case OCTEON_FEATURE_SRIO:
  140. return OCTEON_IS_MODEL(OCTEON_CN63XX)
  141. || OCTEON_IS_MODEL(OCTEON_CN66XX);
  142. case OCTEON_FEATURE_ILK:
  143. return (OCTEON_IS_MODEL(OCTEON_CN68XX));
  144. case OCTEON_FEATURE_KEY_MEMORY:
  145. return OCTEON_IS_MODEL(OCTEON_CN38XX)
  146. || OCTEON_IS_MODEL(OCTEON_CN58XX)
  147. || OCTEON_IS_MODEL(OCTEON_CN56XX)
  148. || OCTEON_IS_MODEL(OCTEON_CN6XXX);
  149. case OCTEON_FEATURE_LED_CONTROLLER:
  150. return OCTEON_IS_MODEL(OCTEON_CN38XX)
  151. || OCTEON_IS_MODEL(OCTEON_CN58XX)
  152. || OCTEON_IS_MODEL(OCTEON_CN56XX);
  153. case OCTEON_FEATURE_TRA:
  154. return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
  155. || OCTEON_IS_MODEL(OCTEON_CN50XX));
  156. case OCTEON_FEATURE_MGMT_PORT:
  157. return OCTEON_IS_MODEL(OCTEON_CN56XX)
  158. || OCTEON_IS_MODEL(OCTEON_CN52XX)
  159. || OCTEON_IS_MODEL(OCTEON_CN6XXX);
  160. case OCTEON_FEATURE_RAID:
  161. return OCTEON_IS_MODEL(OCTEON_CN56XX)
  162. || OCTEON_IS_MODEL(OCTEON_CN52XX)
  163. || OCTEON_IS_MODEL(OCTEON_CN6XXX);
  164. case OCTEON_FEATURE_USB:
  165. return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
  166. || OCTEON_IS_MODEL(OCTEON_CN58XX));
  167. case OCTEON_FEATURE_NO_WPTR:
  168. return (OCTEON_IS_MODEL(OCTEON_CN56XX)
  169. || OCTEON_IS_MODEL(OCTEON_CN52XX)
  170. || OCTEON_IS_MODEL(OCTEON_CN6XXX))
  171. && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
  172. && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
  173. case OCTEON_FEATURE_DFA:
  174. if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
  175. && !OCTEON_IS_MODEL(OCTEON_CN31XX)
  176. && !OCTEON_IS_MODEL(OCTEON_CN58XX))
  177. return 0;
  178. else if (OCTEON_IS_MODEL(OCTEON_CN3020))
  179. return 0;
  180. else
  181. return !cvmx_fuse_read(120);
  182. case OCTEON_FEATURE_HFA:
  183. if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
  184. return 0;
  185. else
  186. return !cvmx_fuse_read(90);
  187. case OCTEON_FEATURE_DFM:
  188. if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
  189. || OCTEON_IS_MODEL(OCTEON_CN66XX)))
  190. return 0;
  191. else
  192. return !cvmx_fuse_read(90);
  193. case OCTEON_FEATURE_MDIO_CLAUSE_45:
  194. return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
  195. || OCTEON_IS_MODEL(OCTEON_CN58XX)
  196. || OCTEON_IS_MODEL(OCTEON_CN50XX));
  197. case OCTEON_FEATURE_NPEI:
  198. return OCTEON_IS_MODEL(OCTEON_CN56XX)
  199. || OCTEON_IS_MODEL(OCTEON_CN52XX);
  200. case OCTEON_FEATURE_PKND:
  201. return OCTEON_IS_MODEL(OCTEON_CN68XX);
  202. case OCTEON_FEATURE_CN68XX_WQE:
  203. return OCTEON_IS_MODEL(OCTEON_CN68XX);
  204. case OCTEON_FEATURE_CIU2:
  205. return OCTEON_IS_MODEL(OCTEON_CN68XX);
  206. default:
  207. break;
  208. }
  209. return 0;
  210. }
  211. #endif /* __OCTEON_FEATURE_H__ */