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m523xsim.h

m523xsim.h 7.0 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *	m523xsim.h -- ColdFire 523x System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *	(C) Copyright 2003-2005, Greg Ungerer <gerg@snapgear.com>
    7. 

  7.  */
    8. 

  8. 

  9. /****************************************************************************/
    10. 

  10. #ifndef	m523xsim_h
    11. 

  11. #define	m523xsim_h
    12. 

  12. /****************************************************************************/
    13. 

  13. 

  14. #define	CPU_NAME		"COLDFIRE(m523x)"
    15. 

  15. #define	CPU_INSTR_PER_JIFFY	3
    16. 

  16. #define	MCF_BUSCLK		(MCF_CLK / 2)
    17. 

  17. 

  18. #include <asm/m52xxacr.h>
    19. 

  19. 

  20. /*
    21. 

  21.  *	Define the 523x SIM register set addresses.
    22. 

  22.  */
    23. 

  23. #define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */
    24. 

  24. #define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */
    25. 

  25. 

  26. #define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */
    27. 

  27. #define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */
    28. 

  28. #define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
    29. 

  29. #define	MCFINTC_IMRL		0x0c		/* Interrupt mask 1-31 */
    30. 

  30. #define	MCFINTC_INTFRCH		0x10		/* Interrupt force 32-63 */
    31. 

  31. #define	MCFINTC_INTFRCL		0x14		/* Interrupt force 1-31 */
    32. 

  32. #define	MCFINTC_IRLR		0x18		/* */
    33. 

  33. #define	MCFINTC_IACKL		0x19		/* */
    34. 

  34. #define	MCFINTC_ICR0		0x40		/* Base ICR register */
    35. 

  35. 

  36. #define	MCFINT_VECBASE		64		/* Vector base number */
    37. 

  37. #define	MCFINT_UART0		13		/* Interrupt number for UART0 */
    38. 

  38. #define	MCFINT_UART1		14		/* Interrupt number for UART1 */
    39. 

  39. #define	MCFINT_UART2		15		/* Interrupt number for UART2 */
    40. 

  40. #define MCFINT_QSPI		18		/* Interrupt number for QSPI */
    41. 

  41. #define	MCFINT_FECRX0		23		/* Interrupt number for FEC */
    42. 

  42. #define	MCFINT_FECTX0		27		/* Interrupt number for FEC */
    43. 

  43. #define	MCFINT_FECENTC0		29		/* Interrupt number for FEC */
    44. 

  44. #define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */
    45. 

  45. 

  46. #define	MCF_IRQ_UART0	        (MCFINT_VECBASE + MCFINT_UART0)
    47. 

  47. #define	MCF_IRQ_UART1	        (MCFINT_VECBASE + MCFINT_UART1)
    48. 

  48. #define	MCF_IRQ_UART2	        (MCFINT_VECBASE + MCFINT_UART2)
    49. 

  49. 

  50. #define	MCF_IRQ_FECRX0		(MCFINT_VECBASE + MCFINT_FECRX0)
    51. 

  51. #define	MCF_IRQ_FECTX0		(MCFINT_VECBASE + MCFINT_FECTX0)
    52. 

  52. #define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)
    53. 

  53. 

  54. #define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)
    55. 

  55. 

  56. /*
    57. 

  57.  *	SDRAM configuration registers.
    58. 

  58.  */
    59. 

  59. #define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */
    60. 

  60. #define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */
    61. 

  61. #define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */
    62. 

  62. #define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */
    63. 

  63. #define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */
    64. 

  64. 

  65. /*
    66. 

  66.  *  Reset Control Unit (relative to IPSBAR).
    67. 

  67.  */
    68. 

  68. #define	MCF_RCR			(MCF_IPSBAR + 0x110000)
    69. 

  69. #define	MCF_RSR			(MCF_IPSBAR + 0x110001)
    70. 

  70. 

  71. #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
    72. 

  72. #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
    73. 

  73. 

  74. /*
    75. 

  75.  *  UART module.
    76. 

  76.  */
    77. 

  77. #define MCFUART_BASE0		(MCF_IPSBAR + 0x200)
    78. 

  78. #define MCFUART_BASE1		(MCF_IPSBAR + 0x240)
    79. 

  79. #define MCFUART_BASE2		(MCF_IPSBAR + 0x280)
    80. 

  80. 

  81. /*
    82. 

  82.  *  FEC ethernet module.
    83. 

  83.  */
    84. 

  84. #define	MCFFEC_BASE0		(MCF_IPSBAR + 0x1000)
    85. 

  85. #define	MCFFEC_SIZE0		0x800
    86. 

  86. 

  87. /*
    88. 

  88.  *  QSPI module.
    89. 

  89.  */
    90. 

  90. #define	MCFQSPI_BASE		(MCF_IPSBAR + 0x340)
    91. 

  91. #define	MCFQSPI_SIZE		0x40
    92. 

  92. 

  93. #define	MCFQSPI_CS0		91
    94. 

  94. #define	MCFQSPI_CS1		92
    95. 

  95. #define	MCFQSPI_CS2		103
    96. 

  96. #define	MCFQSPI_CS3		99
    97. 

  97. 

  98. /*
    99. 

  99.  *  GPIO module.
    100. 

  100.  */
    101. 

  101. #define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)
    102. 

  102. #define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)
    103. 

  103. #define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
    104. 

  104. #define MCFGPIO_PODR_BUSCTL	(MCF_IPSBAR + 0x100003)
    105. 

  105. #define MCFGPIO_PODR_BS		(MCF_IPSBAR + 0x100004)
    106. 

  106. #define MCFGPIO_PODR_CS		(MCF_IPSBAR + 0x100005)
    107. 

  107. #define MCFGPIO_PODR_SDRAM	(MCF_IPSBAR + 0x100006)
    108. 

  108. #define MCFGPIO_PODR_FECI2C	(MCF_IPSBAR + 0x100007)
    109. 

  109. #define MCFGPIO_PODR_UARTH	(MCF_IPSBAR + 0x100008)
    110. 

  110. #define MCFGPIO_PODR_UARTL	(MCF_IPSBAR + 0x100009)
    111. 

  111. #define MCFGPIO_PODR_QSPI	(MCF_IPSBAR + 0x10000A)
    112. 

  112. #define MCFGPIO_PODR_TIMER	(MCF_IPSBAR + 0x10000B)
    113. 

  113. #define MCFGPIO_PODR_ETPU	(MCF_IPSBAR + 0x10000C)
    114. 

  114. 

  115. #define MCFGPIO_PDDR_ADDR	(MCF_IPSBAR + 0x100010)
    116. 

  116. #define MCFGPIO_PDDR_DATAH	(MCF_IPSBAR + 0x100011)
    117. 

  117. #define MCFGPIO_PDDR_DATAL	(MCF_IPSBAR + 0x100012)
    118. 

  118. #define MCFGPIO_PDDR_BUSCTL	(MCF_IPSBAR + 0x100013)
    119. 

  119. #define MCFGPIO_PDDR_BS		(MCF_IPSBAR + 0x100014)
    120. 

  120. #define MCFGPIO_PDDR_CS		(MCF_IPSBAR + 0x100015)
    121. 

  121. #define MCFGPIO_PDDR_SDRAM	(MCF_IPSBAR + 0x100016)
    122. 

  122. #define MCFGPIO_PDDR_FECI2C	(MCF_IPSBAR + 0x100017)
    123. 

  123. #define MCFGPIO_PDDR_UARTH	(MCF_IPSBAR + 0x100018)
    124. 

  124. #define MCFGPIO_PDDR_UARTL	(MCF_IPSBAR + 0x100019)
    125. 

  125. #define MCFGPIO_PDDR_QSPI	(MCF_IPSBAR + 0x10001A)
    126. 

  126. #define MCFGPIO_PDDR_TIMER	(MCF_IPSBAR + 0x10001B)
    127. 

  127. #define MCFGPIO_PDDR_ETPU	(MCF_IPSBAR + 0x10001C)
    128. 

  128. 

  129. #define MCFGPIO_PPDSDR_ADDR	(MCF_IPSBAR + 0x100020)
    130. 

  130. #define MCFGPIO_PPDSDR_DATAH	(MCF_IPSBAR + 0x100021)
    131. 

  131. #define MCFGPIO_PPDSDR_DATAL	(MCF_IPSBAR + 0x100022)
    132. 

  132. #define MCFGPIO_PPDSDR_BUSCTL	(MCF_IPSBAR + 0x100023)
    133. 

  133. #define MCFGPIO_PPDSDR_BS	(MCF_IPSBAR + 0x100024)
    134. 

  134. #define MCFGPIO_PPDSDR_CS	(MCF_IPSBAR + 0x100025)
    135. 

  135. #define MCFGPIO_PPDSDR_SDRAM	(MCF_IPSBAR + 0x100026)
    136. 

  136. #define MCFGPIO_PPDSDR_FECI2C	(MCF_IPSBAR + 0x100027)
    137. 

  137. #define MCFGPIO_PPDSDR_UARTH	(MCF_IPSBAR + 0x100028)
    138. 

  138. #define MCFGPIO_PPDSDR_UARTL	(MCF_IPSBAR + 0x100029)
    139. 

  139. #define MCFGPIO_PPDSDR_QSPI	(MCF_IPSBAR + 0x10002A)
    140. 

  140. #define MCFGPIO_PPDSDR_TIMER	(MCF_IPSBAR + 0x10002B)
    141. 

  141. #define MCFGPIO_PPDSDR_ETPU	(MCF_IPSBAR + 0x10002C)
    142. 

  142. 

  143. #define MCFGPIO_PCLRR_ADDR	(MCF_IPSBAR + 0x100030)
    144. 

  144. #define MCFGPIO_PCLRR_DATAH	(MCF_IPSBAR + 0x100031)
    145. 

  145. #define MCFGPIO_PCLRR_DATAL	(MCF_IPSBAR + 0x100032)
    146. 

  146. #define MCFGPIO_PCLRR_BUSCTL	(MCF_IPSBAR + 0x100033)
    147. 

  147. #define MCFGPIO_PCLRR_BS	(MCF_IPSBAR + 0x100034)
    148. 

  148. #define MCFGPIO_PCLRR_CS	(MCF_IPSBAR + 0x100035)
    149. 

  149. #define MCFGPIO_PCLRR_SDRAM	(MCF_IPSBAR + 0x100036)
    150. 

  150. #define MCFGPIO_PCLRR_FECI2C	(MCF_IPSBAR + 0x100037)
    151. 

  151. #define MCFGPIO_PCLRR_UARTH	(MCF_IPSBAR + 0x100038)
    152. 

  152. #define MCFGPIO_PCLRR_UARTL	(MCF_IPSBAR + 0x100039)
    153. 

  153. #define MCFGPIO_PCLRR_QSPI	(MCF_IPSBAR + 0x10003A)
    154. 

  154. #define MCFGPIO_PCLRR_TIMER	(MCF_IPSBAR + 0x10003B)
    155. 

  155. #define MCFGPIO_PCLRR_ETPU	(MCF_IPSBAR + 0x10003C)
    156. 

  156. 

  157. /*
    158. 

  158.  * PIT timer base addresses.
    159. 

  159.  */
    160. 

  160. #define	MCFPIT_BASE1		(MCF_IPSBAR + 0x150000)
    161. 

  161. #define	MCFPIT_BASE2		(MCF_IPSBAR + 0x160000)
    162. 

  162. #define	MCFPIT_BASE3		(MCF_IPSBAR + 0x170000)
    163. 

  163. #define	MCFPIT_BASE4		(MCF_IPSBAR + 0x180000)
    164. 

  164. 

  165. /*
    166. 

  166.  * EPort
    167. 

  167.  */
    168. 

  168. #define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x130000)
    169. 

  169. #define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)
    170. 

  170. #define MCFEPORT_EPIER		(MCF_IPSBAR + 0x130003)
    171. 

  171. #define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)
    172. 

  172. #define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)
    173. 

  173. #define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)
    174. 

  174. 

  175. /*
    176. 

  176.  * Generic GPIO support
    177. 

  177.  */
    178. 

  178. #define MCFGPIO_PODR			MCFGPIO_PODR_ADDR
    179. 

  179. #define MCFGPIO_PDDR			MCFGPIO_PDDR_ADDR
    180. 

  180. #define MCFGPIO_PPDR			MCFGPIO_PPDSDR_ADDR
    181. 

  181. #define MCFGPIO_SETR			MCFGPIO_PPDSDR_ADDR
    182. 

  182. #define MCFGPIO_CLRR			MCFGPIO_PCLRR_ADDR
    183. 

  183. 

  184. #define MCFGPIO_PIN_MAX			107
    185. 

  185. #define MCFGPIO_IRQ_MAX			8
    186. 

  186. #define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE
    187. 

  187. 

  188. /*
    189. 

  189.  * Pin Assignment
    190. 

  190. */
    191. 

  191. #define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)
    192. 

  192. #define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)
    193. 

  193. 

  194. /*
    195. 

  195.  * DMA unit base addresses.
    196. 

  196.  */
    197. 

  197. #define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)
    198. 

  198. #define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)
    199. 

  199. #define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)
    200. 

  200. #define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)
    201. 

  201. 

  202. /****************************************************************************/
    203. 

  203. #endif	/* m523xsim_h */
    204.