vexpress-v2p-ca15-tc1.dts 3.2 KB

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  1. /*
  2. * ARM Ltd. Versatile Express
  3. *
  4. * CoreTile Express A15x2 (version with Test Chip 1)
  5. * Cortex-A15 MPCore (V2P-CA15)
  6. *
  7. * HBI-0237A
  8. */
  9. /dts-v1/;
  10. / {
  11. model = "V2P-CA15";
  12. arm,hbi = <0x237>;
  13. compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. chosen { };
  18. aliases {
  19. serial0 = &v2m_serial0;
  20. serial1 = &v2m_serial1;
  21. serial2 = &v2m_serial2;
  22. serial3 = &v2m_serial3;
  23. i2c0 = &v2m_i2c_dvi;
  24. i2c1 = &v2m_i2c_pcie;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a15";
  32. reg = <0>;
  33. };
  34. cpu@1 {
  35. device_type = "cpu";
  36. compatible = "arm,cortex-a15";
  37. reg = <1>;
  38. };
  39. };
  40. memory@80000000 {
  41. device_type = "memory";
  42. reg = <0x80000000 0x40000000>;
  43. };
  44. hdlcd@2b000000 {
  45. compatible = "arm,hdlcd";
  46. reg = <0x2b000000 0x1000>;
  47. interrupts = <0 85 4>;
  48. };
  49. memory-controller@2b0a0000 {
  50. compatible = "arm,pl341", "arm,primecell";
  51. reg = <0x2b0a0000 0x1000>;
  52. };
  53. wdt@2b060000 {
  54. compatible = "arm,sp805", "arm,primecell";
  55. reg = <0x2b060000 0x1000>;
  56. interrupts = <98>;
  57. };
  58. gic: interrupt-controller@2c001000 {
  59. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  60. #interrupt-cells = <3>;
  61. #address-cells = <0>;
  62. interrupt-controller;
  63. reg = <0x2c001000 0x1000>,
  64. <0x2c002000 0x100>;
  65. };
  66. memory-controller@7ffd0000 {
  67. compatible = "arm,pl354", "arm,primecell";
  68. reg = <0x7ffd0000 0x1000>;
  69. interrupts = <0 86 4>,
  70. <0 87 4>;
  71. };
  72. dma@7ffb0000 {
  73. compatible = "arm,pl330", "arm,primecell";
  74. reg = <0x7ffb0000 0x1000>;
  75. interrupts = <0 92 4>,
  76. <0 88 4>,
  77. <0 89 4>,
  78. <0 90 4>,
  79. <0 91 4>;
  80. };
  81. pmu {
  82. compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
  83. interrupts = <0 68 4>,
  84. <0 69 4>;
  85. };
  86. motherboard {
  87. ranges = <0 0 0x08000000 0x04000000>,
  88. <1 0 0x14000000 0x04000000>,
  89. <2 0 0x18000000 0x04000000>,
  90. <3 0 0x1c000000 0x04000000>,
  91. <4 0 0x0c000000 0x04000000>,
  92. <5 0 0x10000000 0x04000000>;
  93. interrupt-map-mask = <0 0 63>;
  94. interrupt-map = <0 0 0 &gic 0 0 4>,
  95. <0 0 1 &gic 0 1 4>,
  96. <0 0 2 &gic 0 2 4>,
  97. <0 0 3 &gic 0 3 4>,
  98. <0 0 4 &gic 0 4 4>,
  99. <0 0 5 &gic 0 5 4>,
  100. <0 0 6 &gic 0 6 4>,
  101. <0 0 7 &gic 0 7 4>,
  102. <0 0 8 &gic 0 8 4>,
  103. <0 0 9 &gic 0 9 4>,
  104. <0 0 10 &gic 0 10 4>,
  105. <0 0 11 &gic 0 11 4>,
  106. <0 0 12 &gic 0 12 4>,
  107. <0 0 13 &gic 0 13 4>,
  108. <0 0 14 &gic 0 14 4>,
  109. <0 0 15 &gic 0 15 4>,
  110. <0 0 16 &gic 0 16 4>,
  111. <0 0 17 &gic 0 17 4>,
  112. <0 0 18 &gic 0 18 4>,
  113. <0 0 19 &gic 0 19 4>,
  114. <0 0 20 &gic 0 20 4>,
  115. <0 0 21 &gic 0 21 4>,
  116. <0 0 22 &gic 0 22 4>,
  117. <0 0 23 &gic 0 23 4>,
  118. <0 0 24 &gic 0 24 4>,
  119. <0 0 25 &gic 0 25 4>,
  120. <0 0 26 &gic 0 26 4>,
  121. <0 0 27 &gic 0 27 4>,
  122. <0 0 28 &gic 0 28 4>,
  123. <0 0 29 &gic 0 29 4>,
  124. <0 0 30 &gic 0 30 4>,
  125. <0 0 31 &gic 0 31 4>,
  126. <0 0 32 &gic 0 32 4>,
  127. <0 0 33 &gic 0 33 4>,
  128. <0 0 34 &gic 0 34 4>,
  129. <0 0 35 &gic 0 35 4>,
  130. <0 0 36 &gic 0 36 4>,
  131. <0 0 37 &gic 0 37 4>,
  132. <0 0 38 &gic 0 38 4>,
  133. <0 0 39 &gic 0 39 4>,
  134. <0 0 40 &gic 0 40 4>,
  135. <0 0 41 &gic 0 41 4>,
  136. <0 0 42 &gic 0 42 4>;
  137. };
  138. };
  139. /include/ "vexpress-v2m-rs1.dtsi"