em28xx-core.c 18 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include "em28xx.h"
  25. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  26. static unsigned int core_debug;
  27. module_param(core_debug,int,0644);
  28. MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
  29. #define em28xx_coredbg(fmt, arg...) do {\
  30. if (core_debug) \
  31. printk(KERN_INFO "%s %s :"fmt, \
  32. dev->name, __func__ , ##arg); } while (0)
  33. static unsigned int reg_debug;
  34. module_param(reg_debug,int,0644);
  35. MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
  36. #define em28xx_regdbg(fmt, arg...) do {\
  37. if (reg_debug) \
  38. printk(KERN_INFO "%s %s :"fmt, \
  39. dev->name, __func__ , ##arg); } while (0)
  40. static int alt = EM28XX_PINOUT;
  41. module_param(alt, int, 0644);
  42. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  43. /* FIXME */
  44. #define em28xx_isocdbg(fmt, arg...) do {\
  45. if (core_debug) \
  46. printk(KERN_INFO "%s %s :"fmt, \
  47. dev->name, __func__ , ##arg); } while (0)
  48. /*
  49. * em28xx_read_reg_req()
  50. * reads data from the usb device specifying bRequest
  51. */
  52. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  53. char *buf, int len)
  54. {
  55. int ret, byte;
  56. if (dev->state & DEV_DISCONNECTED)
  57. return -ENODEV;
  58. if (len > URB_MAX_CTRL_SIZE)
  59. return -EINVAL;
  60. em28xx_regdbg("req=%02x, reg=%02x ", req, reg);
  61. mutex_lock(&dev->ctrl_urb_lock);
  62. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  63. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  64. 0x0000, reg, dev->urb_buf, len, HZ);
  65. if (ret < 0) {
  66. if (reg_debug)
  67. printk(" failed!\n");
  68. mutex_unlock(&dev->ctrl_urb_lock);
  69. return ret;
  70. }
  71. if (len)
  72. memcpy(buf, dev->urb_buf, len);
  73. mutex_unlock(&dev->ctrl_urb_lock);
  74. if (reg_debug) {
  75. printk("%02x values: ", ret);
  76. for (byte = 0; byte < len; byte++)
  77. printk(" %02x", (unsigned char)buf[byte]);
  78. printk("\n");
  79. }
  80. return ret;
  81. }
  82. /*
  83. * em28xx_read_reg_req()
  84. * reads data from the usb device specifying bRequest
  85. */
  86. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  87. {
  88. u8 val;
  89. int ret;
  90. if (dev->state & DEV_DISCONNECTED)
  91. return(-ENODEV);
  92. em28xx_regdbg("req=%02x, reg=%02x:", req, reg);
  93. mutex_lock(&dev->ctrl_urb_lock);
  94. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  95. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  96. 0x0000, reg, dev->urb_buf, 1, HZ);
  97. val = dev->urb_buf[0];
  98. mutex_unlock(&dev->ctrl_urb_lock);
  99. if (ret < 0) {
  100. printk(" failed!\n");
  101. return ret;
  102. }
  103. if (reg_debug)
  104. printk("%02x\n", (unsigned char) val);
  105. return val;
  106. }
  107. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  108. {
  109. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  110. }
  111. /*
  112. * em28xx_write_regs_req()
  113. * sends data to the usb device, specifying bRequest
  114. */
  115. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  116. int len)
  117. {
  118. int ret;
  119. if (dev->state & DEV_DISCONNECTED)
  120. return -ENODEV;
  121. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  122. return -EINVAL;
  123. em28xx_regdbg("req=%02x reg=%02x:", req, reg);
  124. if (reg_debug) {
  125. int i;
  126. for (i = 0; i < len; ++i)
  127. printk(" %02x", (unsigned char)buf[i]);
  128. printk("\n");
  129. }
  130. mutex_lock(&dev->ctrl_urb_lock);
  131. memcpy(dev->urb_buf, buf, len);
  132. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req,
  133. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  134. 0x0000, reg, dev->urb_buf, len, HZ);
  135. mutex_unlock(&dev->ctrl_urb_lock);
  136. if (dev->wait_after_write)
  137. msleep(dev->wait_after_write);
  138. return ret;
  139. }
  140. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  141. {
  142. int rc;
  143. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  144. /* Stores GPO/GPIO values at the cache, if changed
  145. Only write values should be stored, since input on a GPIO
  146. register will return the input bits.
  147. Not sure what happens on reading GPO register.
  148. */
  149. if (rc >= 0) {
  150. if (reg == EM2880_R04_GPO)
  151. dev->reg_gpo = buf[0];
  152. else if (reg == EM28XX_R08_GPIO)
  153. dev->reg_gpio = buf[0];
  154. }
  155. return rc;
  156. }
  157. /*
  158. * em28xx_write_reg_bits()
  159. * sets only some bits (specified by bitmask) of a register, by first reading
  160. * the actual value
  161. */
  162. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  163. u8 bitmask)
  164. {
  165. int oldval;
  166. u8 newval;
  167. /* Uses cache for gpo/gpio registers */
  168. if (reg == EM2880_R04_GPO)
  169. oldval = dev->reg_gpo;
  170. else if (reg == EM28XX_R08_GPIO)
  171. oldval = dev->reg_gpio;
  172. else
  173. oldval = em28xx_read_reg(dev, reg);
  174. if (oldval < 0)
  175. return oldval;
  176. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  177. return em28xx_write_regs(dev, reg, &newval, 1);
  178. }
  179. /*
  180. * em28xx_write_ac97()
  181. * write a 16 bit value to the specified AC97 address (LSB first!)
  182. */
  183. static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u8 *val)
  184. {
  185. int ret, i;
  186. u8 addr = reg & 0x7f;
  187. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, val, 2);
  188. if (ret < 0)
  189. return ret;
  190. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  191. if (ret < 0)
  192. return ret;
  193. /* Wait up to 50 ms for AC97 command to complete */
  194. for (i = 0; i < 10; i++) {
  195. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  196. if (ret < 0)
  197. return ret;
  198. if (!(ret & 0x01))
  199. return 0;
  200. msleep(5);
  201. }
  202. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  203. return 0;
  204. }
  205. static int em28xx_set_audio_source(struct em28xx *dev)
  206. {
  207. static char *enable = "\x08\x08";
  208. static char *disable = "\x08\x88";
  209. char *video = enable, *line = disable;
  210. int ret;
  211. u8 input;
  212. if (dev->is_em2800) {
  213. if (dev->ctl_ainput)
  214. input = EM2800_AUDIO_SRC_LINE;
  215. else
  216. input = EM2800_AUDIO_SRC_TUNER;
  217. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  218. if (ret < 0)
  219. return ret;
  220. }
  221. if (dev->has_msp34xx)
  222. input = EM28XX_AUDIO_SRC_TUNER;
  223. else {
  224. switch (dev->ctl_ainput) {
  225. case EM28XX_AMUX_VIDEO:
  226. input = EM28XX_AUDIO_SRC_TUNER;
  227. break;
  228. case EM28XX_AMUX_LINE_IN:
  229. input = EM28XX_AUDIO_SRC_LINE;
  230. video = disable;
  231. line = enable;
  232. break;
  233. case EM28XX_AMUX_AC97_VIDEO:
  234. input = EM28XX_AUDIO_SRC_LINE;
  235. break;
  236. case EM28XX_AMUX_AC97_LINE_IN:
  237. input = EM28XX_AUDIO_SRC_LINE;
  238. video = disable;
  239. line = enable;
  240. break;
  241. }
  242. }
  243. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  244. if (ret < 0)
  245. return ret;
  246. msleep(5);
  247. /* Sets AC97 mixer registers
  248. This is seems to be needed, even for non-ac97 configs
  249. */
  250. ret = em28xx_write_ac97(dev, EM28XX_R14_VIDEO_AC97, video);
  251. if (ret < 0)
  252. return ret;
  253. ret = em28xx_write_ac97(dev, EM28XX_R10_LINE_IN_AC97, line);
  254. return ret;
  255. }
  256. int em28xx_audio_analog_set(struct em28xx *dev)
  257. {
  258. int ret;
  259. char s[2] = { 0x00, 0x00 };
  260. u8 xclk = 0x07;
  261. s[0] |= 0x1f - dev->volume;
  262. s[1] |= 0x1f - dev->volume;
  263. /* Mute */
  264. s[1] |= 0x80;
  265. ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
  266. if (ret < 0)
  267. return ret;
  268. if (dev->has_12mhz_i2s)
  269. xclk |= 0x20;
  270. if (!dev->mute)
  271. xclk |= 0x80;
  272. ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7);
  273. if (ret < 0)
  274. return ret;
  275. msleep(10);
  276. /* Selects the proper audio input */
  277. ret = em28xx_set_audio_source(dev);
  278. /* Unmute device */
  279. if (!dev->mute)
  280. s[1] &= ~0x80;
  281. ret = em28xx_write_ac97(dev, EM28XX_R02_MASTER_AC97, s);
  282. return ret;
  283. }
  284. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  285. int em28xx_colorlevels_set_default(struct em28xx *dev)
  286. {
  287. em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1); /* contrast */
  288. em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1); /* brightness */
  289. em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1); /* saturation */
  290. em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1);
  291. em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1);
  292. em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1);
  293. em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1);
  294. em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1);
  295. em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1);
  296. em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1);
  297. em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1);
  298. em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1);
  299. return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1);
  300. }
  301. int em28xx_capture_start(struct em28xx *dev, int start)
  302. {
  303. int rc;
  304. /* FIXME: which is the best order? */
  305. /* video registers are sampled by VREF */
  306. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  307. start ? 0x10 : 0x00, 0x10);
  308. if (rc < 0)
  309. return rc;
  310. if (!start) {
  311. /* disable video capture */
  312. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1);
  313. return rc;
  314. }
  315. /* enable video capture */
  316. rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  317. if (dev->mode == EM28XX_ANALOG_MODE)
  318. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1);
  319. else
  320. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1);
  321. msleep(6);
  322. return rc;
  323. }
  324. int em28xx_outfmt_set_yuv422(struct em28xx *dev)
  325. {
  326. em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1);
  327. em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1);
  328. return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1);
  329. }
  330. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  331. u8 ymin, u8 ymax)
  332. {
  333. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  334. xmin, ymin, xmax, ymax);
  335. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  336. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  337. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  338. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  339. }
  340. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  341. u16 width, u16 height)
  342. {
  343. u8 cwidth = width;
  344. u8 cheight = height;
  345. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  346. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  347. (width | (overflow & 2) << 7),
  348. (height | (overflow & 1) << 8));
  349. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  350. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  351. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  352. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  353. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  354. }
  355. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  356. {
  357. u8 mode;
  358. /* the em2800 scaler only supports scaling down to 50% */
  359. if (dev->is_em2800)
  360. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  361. else {
  362. u8 buf[2];
  363. buf[0] = h;
  364. buf[1] = h >> 8;
  365. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  366. buf[0] = v;
  367. buf[1] = v >> 8;
  368. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  369. /* it seems that both H and V scalers must be active
  370. to work correctly */
  371. mode = (h || v)? 0x30: 0x00;
  372. }
  373. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  374. }
  375. /* FIXME: this only function read values from dev */
  376. int em28xx_resolution_set(struct em28xx *dev)
  377. {
  378. int width, height;
  379. width = norm_maxw(dev);
  380. height = norm_maxh(dev) >> 1;
  381. em28xx_outfmt_set_yuv422(dev);
  382. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  383. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  384. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  385. }
  386. int em28xx_set_alternate(struct em28xx *dev)
  387. {
  388. int errCode, prev_alt = dev->alt;
  389. int i;
  390. unsigned int min_pkt_size = dev->width * 2 + 4;
  391. /* When image size is bigger than a certain value,
  392. the frame size should be increased, otherwise, only
  393. green screen will be received.
  394. */
  395. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  396. min_pkt_size *= 2;
  397. for (i = 0; i < dev->num_alt; i++) {
  398. /* stop when the selected alt setting offers enough bandwidth */
  399. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  400. dev->alt = i;
  401. break;
  402. /* otherwise make sure that we end up with the maximum bandwidth
  403. because the min_pkt_size equation might be wrong...
  404. */
  405. } else if (dev->alt_max_pkt_size[i] >
  406. dev->alt_max_pkt_size[dev->alt])
  407. dev->alt = i;
  408. }
  409. if (dev->alt != prev_alt) {
  410. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  411. min_pkt_size, dev->alt);
  412. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  413. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  414. dev->alt, dev->max_pkt_size);
  415. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  416. if (errCode < 0) {
  417. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  418. dev->alt, errCode);
  419. return errCode;
  420. }
  421. }
  422. return 0;
  423. }
  424. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  425. {
  426. int rc = 0;
  427. if (!gpio)
  428. return rc;
  429. dev->em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  430. if (dev->mode == EM28XX_ANALOG_MODE)
  431. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x67", 1);
  432. else
  433. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x37", 1);
  434. msleep(6);
  435. /* Send GPIO reset sequences specified at board entry */
  436. while (gpio->sleep >= 0) {
  437. if (gpio->reg >= 0) {
  438. rc = em28xx_write_reg_bits(dev,
  439. gpio->reg,
  440. gpio->val,
  441. gpio->mask);
  442. if (rc < 0)
  443. return rc;
  444. }
  445. if (gpio->sleep > 0)
  446. msleep(gpio->sleep);
  447. gpio++;
  448. }
  449. return rc;
  450. }
  451. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  452. {
  453. if (dev->mode == set_mode)
  454. return 0;
  455. if (set_mode == EM28XX_MODE_UNDEFINED) {
  456. dev->mode = set_mode;
  457. return 0;
  458. }
  459. dev->mode = set_mode;
  460. if (dev->mode == EM28XX_DIGITAL_MODE)
  461. return em28xx_gpio_set(dev, dev->digital_gpio);
  462. else
  463. return em28xx_gpio_set(dev, dev->analog_gpio);
  464. }
  465. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  466. /* ------------------------------------------------------------------
  467. URB control
  468. ------------------------------------------------------------------*/
  469. /*
  470. * IRQ callback, called by URB callback
  471. */
  472. static void em28xx_irq_callback(struct urb *urb)
  473. {
  474. struct em28xx_dmaqueue *dma_q = urb->context;
  475. struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
  476. int rc, i;
  477. /* Copy data from URB */
  478. spin_lock(&dev->slock);
  479. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  480. spin_unlock(&dev->slock);
  481. /* Reset urb buffers */
  482. for (i = 0; i < urb->number_of_packets; i++) {
  483. urb->iso_frame_desc[i].status = 0;
  484. urb->iso_frame_desc[i].actual_length = 0;
  485. }
  486. urb->status = 0;
  487. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  488. if (urb->status) {
  489. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  490. urb->status);
  491. }
  492. }
  493. /*
  494. * Stop and Deallocate URBs
  495. */
  496. void em28xx_uninit_isoc(struct em28xx *dev)
  497. {
  498. struct urb *urb;
  499. int i;
  500. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  501. dev->isoc_ctl.nfields = -1;
  502. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  503. urb = dev->isoc_ctl.urb[i];
  504. if (urb) {
  505. usb_kill_urb(urb);
  506. usb_unlink_urb(urb);
  507. if (dev->isoc_ctl.transfer_buffer[i]) {
  508. usb_buffer_free(dev->udev,
  509. urb->transfer_buffer_length,
  510. dev->isoc_ctl.transfer_buffer[i],
  511. urb->transfer_dma);
  512. }
  513. usb_free_urb(urb);
  514. dev->isoc_ctl.urb[i] = NULL;
  515. }
  516. dev->isoc_ctl.transfer_buffer[i] = NULL;
  517. }
  518. kfree(dev->isoc_ctl.urb);
  519. kfree(dev->isoc_ctl.transfer_buffer);
  520. dev->isoc_ctl.urb = NULL;
  521. dev->isoc_ctl.transfer_buffer = NULL;
  522. dev->isoc_ctl.num_bufs = 0;
  523. em28xx_capture_start(dev, 0);
  524. }
  525. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  526. /*
  527. * Allocate URBs and start IRQ
  528. */
  529. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  530. int num_bufs, int max_pkt_size,
  531. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  532. {
  533. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  534. int i;
  535. int sb_size, pipe;
  536. struct urb *urb;
  537. int j, k;
  538. int rc;
  539. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  540. /* De-allocates all pending stuff */
  541. em28xx_uninit_isoc(dev);
  542. dev->isoc_ctl.isoc_copy = isoc_copy;
  543. dev->isoc_ctl.num_bufs = num_bufs;
  544. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  545. if (!dev->isoc_ctl.urb) {
  546. em28xx_errdev("cannot alloc memory for usb buffers\n");
  547. return -ENOMEM;
  548. }
  549. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  550. GFP_KERNEL);
  551. if (!dev->isoc_ctl.transfer_buffer) {
  552. em28xx_errdev("cannot allocate memory for usbtransfer\n");
  553. kfree(dev->isoc_ctl.urb);
  554. return -ENOMEM;
  555. }
  556. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  557. dev->isoc_ctl.buf = NULL;
  558. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  559. /* allocate urbs and transfer buffers */
  560. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  561. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  562. if (!urb) {
  563. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  564. em28xx_uninit_isoc(dev);
  565. return -ENOMEM;
  566. }
  567. dev->isoc_ctl.urb[i] = urb;
  568. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  569. sb_size, GFP_KERNEL, &urb->transfer_dma);
  570. if (!dev->isoc_ctl.transfer_buffer[i]) {
  571. em28xx_err("unable to allocate %i bytes for transfer"
  572. " buffer %i%s\n",
  573. sb_size, i,
  574. in_interrupt()?" while in int":"");
  575. em28xx_uninit_isoc(dev);
  576. return -ENOMEM;
  577. }
  578. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  579. /* FIXME: this is a hack - should be
  580. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  581. should also be using 'desc.bInterval'
  582. */
  583. pipe = usb_rcvisocpipe(dev->udev,
  584. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  585. usb_fill_int_urb(urb, dev->udev, pipe,
  586. dev->isoc_ctl.transfer_buffer[i], sb_size,
  587. em28xx_irq_callback, dma_q, 1);
  588. urb->number_of_packets = max_packets;
  589. urb->transfer_flags = URB_ISO_ASAP;
  590. k = 0;
  591. for (j = 0; j < max_packets; j++) {
  592. urb->iso_frame_desc[j].offset = k;
  593. urb->iso_frame_desc[j].length =
  594. dev->isoc_ctl.max_pkt_size;
  595. k += dev->isoc_ctl.max_pkt_size;
  596. }
  597. }
  598. init_waitqueue_head(&dma_q->wq);
  599. em28xx_capture_start(dev, 1);
  600. /* submit urbs and enables IRQ */
  601. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  602. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  603. if (rc) {
  604. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  605. rc);
  606. em28xx_uninit_isoc(dev);
  607. return rc;
  608. }
  609. }
  610. return 0;
  611. }
  612. EXPORT_SYMBOL_GPL(em28xx_init_isoc);